board/amcc/bamboo/bamboo.c

   1 /*
   2  * (C) Copyright 2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <spd_sdram.h>
  27 #include <ppc440.h>
  28 #include "bamboo.h"
  29
  30 void ext_bus_cntlr_init(void);
  31 void configure_ppc440ep_pins(void);
  32
  33 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
  34 #if 0
  35 {          /* GPIO   Alternate1       Alternate2        Alternate3 */
  36     {
  37         /* GPIO Core 0 */
  38         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0  -> EBC_ADDR(7)      DMA_REQ(2) */
  39         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1  -> EBC_ADDR(6)      DMA_ACK(2) */
  40         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2  -> EBC_ADDR(5)      DMA_EOT/TC(2) */
  41         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3  -> EBC_ADDR(4)      DMA_REQ(3) */
  42         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4  -> EBC_ADDR(3)      DMA_ACK(3) */
  43         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  44         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6  -> EBC_CS_N(1) */
  45         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7  -> EBC_CS_N(2) */
  46         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8  -> EBC_CS_N(3) */
  47         { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9  -> EBC_CS_N(4) */
  48         { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  49         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  50         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  51         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  52         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  53         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  54         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  55         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  56         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  57         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  58         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  59         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  60         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  61         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  62         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  63         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  64         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->                  USB2D_RXVALID */
  65         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ      USB2D_RXERROR */
  66         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->                  USB2D_TXVALID */
  67         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA     USB2D_PAD_SUSPNDM */
  68         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK      USB2D_XCVRSELECT */
  69         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
  70     },
  71     {
  72         /* GPIO Core 1 */
  73         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0  -> USB2D_OPMODE0 */
  74         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1  -> USB2D_OPMODE1 */
  75         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2  -> UART0_DCD_N      UART1_DSR_CTS_N   UART2_SOUT */
  76         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3  -> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
  77         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4  -> UART0_8PIN_CTS_N                   UART3_SIN */
  78         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5  -> UART0_RTS_N */
  79         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6  -> UART0_DTR_N      UART1_SOUT */
  80         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7  -> UART0_RI_N       UART1_SIN */
  81         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8  -> UIC_IRQ(0) */
  82         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9  -> UIC_IRQ(1) */
  83         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  84         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  85         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)       DMA_ACK(1) */
  86         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)       DMA_EOT/TC(1) */
  87         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)       DMA_REQ(0) */
  88         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)       DMA_ACK(0) */
  89         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)       DMA_EOT/TC(0) */
  90         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  91         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
  92         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
  93         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
  94         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
  95         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
  96         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \     Can be unselected thru TraceSelect Bit */
  97         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /        in PowerPC440EP Chip */
  98         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
  99         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
 100         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
 101         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
 102         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
 103         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
 104         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
 105     }
 106 };
 107 #endif
 108
 109 /*----------------------------------------------------------------------------+
 110   | EBC Devices Characteristics
 111   |   Peripheral Bank Access Parameters       -   EBC0_BnAP
 112   |   Peripheral Bank Configuration Register  -   EBC0_BnCR
 113   +----------------------------------------------------------------------------*/
 114 /* Small Flash */
 115 #define EBC0_BNAP_SMALL_FLASH                           \
 116         EBC0_BNAP_BME_DISABLED                  |       \
 117         EBC0_BNAP_TWT_ENCODE(6)                 |       \
 118         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 119         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 120         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 121         EBC0_BNAP_WBF_ENCODE(3)                 |       \
 122         EBC0_BNAP_TH_ENCODE(1)                  |       \
 123         EBC0_BNAP_RE_ENABLED                    |       \
 124         EBC0_BNAP_SOR_DELAYED                   |       \
 125         EBC0_BNAP_BEM_WRITEONLY                 |       \
 126         EBC0_BNAP_PEN_DISABLED
 127
 128 #define EBC0_BNCR_SMALL_FLASH_CS0                       \
 129         EBC0_BNCR_BAS_ENCODE(0xFFF00000)        |       \
 130         EBC0_BNCR_BS_1MB                        |       \
 131         EBC0_BNCR_BU_RW                         |       \
 132         EBC0_BNCR_BW_8BIT
 133
 134 #define EBC0_BNCR_SMALL_FLASH_CS4                       \
 135         EBC0_BNCR_BAS_ENCODE(0x87800000)        |       \
 136         EBC0_BNCR_BS_8MB                        |       \
 137         EBC0_BNCR_BU_RW                         |       \
 138         EBC0_BNCR_BW_16BIT
 139
 140 /* Large Flash or SRAM */
 141 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM                   \
 142         EBC0_BNAP_BME_DISABLED                  |       \
 143         EBC0_BNAP_TWT_ENCODE(8)                 |       \
 144         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 145         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 146         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 147         EBC0_BNAP_WBF_ENCODE(1)                 |       \
 148         EBC0_BNAP_TH_ENCODE(2)                  |       \
 149         EBC0_BNAP_SOR_DELAYED                   |       \
 150         EBC0_BNAP_BEM_RW                        |       \
 151         EBC0_BNAP_PEN_DISABLED
 152
 153 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0               \
 154         EBC0_BNCR_BAS_ENCODE(0xFF800000)        |       \
 155         EBC0_BNCR_BS_8MB                        |       \
 156         EBC0_BNCR_BU_RW                         |       \
 157         EBC0_BNCR_BW_16BIT
 158
 159
 160 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4               \
 161         EBC0_BNCR_BAS_ENCODE(0x87800000)        |       \
 162         EBC0_BNCR_BS_8MB                        |       \
 163         EBC0_BNCR_BU_RW                         |       \
 164         EBC0_BNCR_BW_16BIT
 165
 166 /* NVRAM - FPGA */
 167 #define EBC0_BNAP_NVRAM_FPGA                            \
 168         EBC0_BNAP_BME_DISABLED                  |       \
 169         EBC0_BNAP_TWT_ENCODE(9)                 |       \
 170         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 171         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 172         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 173         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 174         EBC0_BNAP_TH_ENCODE(2)                  |       \
 175         EBC0_BNAP_RE_ENABLED                    |       \
 176         EBC0_BNAP_SOR_DELAYED                   |       \
 177         EBC0_BNAP_BEM_WRITEONLY                 |       \
 178         EBC0_BNAP_PEN_DISABLED
 179
 180 #define EBC0_BNCR_NVRAM_FPGA_CS5                        \
 181         EBC0_BNCR_BAS_ENCODE(0x80000000)        |       \
 182         EBC0_BNCR_BS_1MB                        |       \
 183         EBC0_BNCR_BU_RW                         |       \
 184         EBC0_BNCR_BW_8BIT
 185
 186 /* Nand Flash */
 187 #define EBC0_BNAP_NAND_FLASH                            \
 188         EBC0_BNAP_BME_DISABLED                  |       \
 189         EBC0_BNAP_TWT_ENCODE(3)                 |       \
 190         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 191         EBC0_BNAP_OEN_ENCODE(0)                 |       \
 192         EBC0_BNAP_WBN_ENCODE(0)                 |       \
 193         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 194         EBC0_BNAP_TH_ENCODE(1)                  |       \
 195         EBC0_BNAP_RE_ENABLED                    |       \
 196         EBC0_BNAP_SOR_NOT_DELAYED               |       \
 197         EBC0_BNAP_BEM_RW                        |       \
 198         EBC0_BNAP_PEN_DISABLED
 199
 200
 201 #define EBC0_BNCR_NAND_FLASH_CS0        0xB8400000
 202
 203 /* NAND0 */
 204 #define EBC0_BNCR_NAND_FLASH_CS1                        \
 205         EBC0_BNCR_BAS_ENCODE(0x90000000)        |       \
 206         EBC0_BNCR_BS_1MB                        |       \
 207         EBC0_BNCR_BU_RW                         |       \
 208         EBC0_BNCR_BW_32BIT
 209 /* NAND1 - Bank2 */
 210 #define EBC0_BNCR_NAND_FLASH_CS2                        \
 211         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 212         EBC0_BNCR_BS_1MB                        |       \
 213         EBC0_BNCR_BU_RW                         |       \
 214         EBC0_BNCR_BW_32BIT
 215
 216 /* NAND1 - Bank3 */
 217 #define EBC0_BNCR_NAND_FLASH_CS3                        \
 218         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 219         EBC0_BNCR_BS_1MB                        |       \
 220         EBC0_BNCR_BU_RW                         |       \
 221         EBC0_BNCR_BW_32BIT
 222
 223 int board_early_init_f(void)
 224 {
 225         ext_bus_cntlr_init();
 226
 227         /*--------------------------------------------------------------------
 228          * Setup the interrupt controller polarities, triggers, etc.
 229          *-------------------------------------------------------------------*/
 230         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 231         mtdcr(uic0er, 0x00000000);      /* disable all */
 232         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
 233         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 234         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 235         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 236         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 237
 238         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 239         mtdcr(uic1er, 0x00000000);      /* disable all */
 240         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 241         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 242         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 243         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 244         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 245
 246         /*--------------------------------------------------------------------
 247          * Setup the GPIO pins
 248          *-------------------------------------------------------------------*/
 249         out32(GPIO0_OSRL,  0x00000400);
 250         out32(GPIO0_OSRH,  0x00000000);
 251         out32(GPIO0_TSRL,  0x00000400);
 252         out32(GPIO0_TSRH,  0x00000000);
 253         out32(GPIO0_ISR1L, 0x00000000);
 254         out32(GPIO0_ISR1H, 0x00000000);
 255         out32(GPIO0_ISR2L, 0x00000000);
 256         out32(GPIO0_ISR2H, 0x00000000);
 257         out32(GPIO0_ISR3L, 0x00000000);
 258         out32(GPIO0_ISR3H, 0x00000000);
 259
 260         out32(GPIO1_OSRL,  0x0C380000);
 261         out32(GPIO1_OSRH,  0x00000000);
 262         out32(GPIO1_TSRL,  0x0C380000);
 263         out32(GPIO1_TSRH,  0x00000000);
 264         out32(GPIO1_ISR1L, 0x0FC30000);
 265         out32(GPIO1_ISR1H, 0x00000000);
 266         out32(GPIO1_ISR2L, 0x0C010000);
 267         out32(GPIO1_ISR2H, 0x00000000);
 268         out32(GPIO1_ISR3L, 0x01400000);
 269         out32(GPIO1_ISR3H, 0x00000000);
 270
 271         configure_ppc440ep_pins();
 272
 273         return 0;
 274 }
 275
 276 int checkboard(void)
 277 {
 278         sys_info_t sysinfo;
 279         unsigned char *s = getenv("serial#");
 280
 281         get_sys_info(&sysinfo);
 282
 283         printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
 284         if (s != NULL) {
 285                 puts(", serial# ");
 286                 puts(s);
 287         }
 288         putc('\n');
 289
 290         printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 291         printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 292         printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 293         printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 294         printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 295
 296         return (0);
 297 }
 298
 299 /*************************************************************************
 300  *
 301  * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
 302  *
 303  * Fixed memory is composed of :
 304  *      MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
 305  *      13 row add bits, 10 column add bits (but 12 row used only).
 306  *      ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
 307  *      12 row add bits, 10 column add bits.
 308  *      Prepare a subset (only the used ones) of SPD data
 309  *
 310  *      Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
 311  *      the corresponding bank is divided by 2 due to number of Row addresses
 312  *      12 in the ECC module
 313  *
 314  *  Assumes:    64 MB, ECC, non-registered
 315  *              PLB @ 133 MHz
 316  *
 317  ************************************************************************/
 318 void fixed_sdram_init(void)
 319 {
 320         /*
 321          * clear this first, if the DDR is enabled by a debugger
 322          * then you can not make changes.
 323          */
 324         mtsdram(mem_cfg0, 0x00000000);  /* Disable EEC */
 325
 326         /*--------------------------------------------------------------------
 327          * Setup for board-specific specific mem
 328          *------------------------------------------------------------------*/
 329         /*
 330          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 331          */
 332         mtsdram(mem_b0cr, 0x00082001);
 333         mtsdram(mem_b1cr, 0x00000000);
 334         mtsdram(mem_b2cr, 0x00000000);
 335         mtsdram(mem_b3cr, 0x00000000);
 336 }
 337
 338 long int initdram (int board_type)
 339 {
 340         long dram_size = 0;
 341
 342         /*
 343          * First init bank0 (onboard sdram) and then configure the DIMM-slots
 344          */
 345         fixed_sdram_init();
 346         dram_size = spd_sdram (0);
 347
 348         return dram_size;
 349 }
 350
 351 #if defined(CFG_DRAM_TEST)
 352 int testdram(void)
 353 {
 354         unsigned long *mem = (unsigned long *)0;
 355         const unsigned long kend = (1024 / sizeof(unsigned long));
 356         unsigned long k, n;
 357
 358         mtmsr(0);
 359
 360         for (k = 0; k < CFG_KBYTES_SDRAM;
 361              ++k, mem += (1024 / sizeof(unsigned long))) {
 362                 if ((k & 1023) == 0) {
 363                         printf("%3d MB\r", k / 1024);
 364                 }
 365
 366                 memset(mem, 0xaaaaaaaa, 1024);
 367                 for (n = 0; n < kend; ++n) {
 368                         if (mem[n] != 0xaaaaaaaa) {
 369                                 printf("SDRAM test fails at: %08x\n",
 370                                        (uint) & mem[n]);
 371                                 return 1;
 372                         }
 373                 }
 374
 375                 memset(mem, 0x55555555, 1024);
 376                 for (n = 0; n < kend; ++n) {
 377                         if (mem[n] != 0x55555555) {
 378                                 printf("SDRAM test fails at: %08x\n",
 379                                        (uint) & mem[n]);
 380                                 return 1;
 381                         }
 382                 }
 383         }
 384         printf("SDRAM test passes\n");
 385         return 0;
 386 }
 387 #endif
 388
 389 /*************************************************************************
 390  *  pci_pre_init
 391  *
 392  *  This routine is called just prior to registering the hose and gives
 393  *  the board the opportunity to check things. Returning a value of zero
 394  *  indicates that things are bad & PCI initialization should be aborted.
 395  *
 396  *      Different boards may wish to customize the pci controller structure
 397  *      (add regions, override default access routines, etc) or perform
 398  *      certain pre-initialization actions.
 399  *
 400  ************************************************************************/
 401 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 402 int pci_pre_init(struct pci_controller *hose)
 403 {
 404         unsigned long strap;
 405         unsigned long addr;
 406
 407         /*--------------------------------------------------------------------------+
 408          *      Bamboo is always configured as the host & requires the
 409          *      PCI arbiter to be enabled.
 410          *--------------------------------------------------------------------------*/
 411         mfsdr(sdr_sdstp1, strap);
 412         if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
 413                 printf("PCI: SDR0_STRP1[PAE] not set.\n");
 414                 printf("PCI: Configuration aborted.\n");
 415                 return 0;
 416         }
 417
 418         /*-------------------------------------------------------------------------+
 419           | Set priority for all PLB3 devices to 0.
 420           | Set PLB3 arbiter to fair mode.
 421           +-------------------------------------------------------------------------*/
 422         mfsdr(sdr_amp1, addr);
 423         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 424         addr = mfdcr(plb3_acr);
 425         mtdcr(plb3_acr, addr | 0x80000000);
 426
 427         /*-------------------------------------------------------------------------+
 428           | Set priority for all PLB4 devices to 0.
 429           +-------------------------------------------------------------------------*/
 430         mfsdr(sdr_amp0, addr);
 431         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 432         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 433         mtdcr(plb4_acr, addr);
 434
 435         /*-------------------------------------------------------------------------+
 436           | Set Nebula PLB4 arbiter to fair mode.
 437           +-------------------------------------------------------------------------*/
 438         /* Segment0 */
 439         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 440         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 441         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 442         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 443         mtdcr(plb0_acr, addr);
 444
 445         /* Segment1 */
 446         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 447         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 448         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 449         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 450         mtdcr(plb1_acr, addr);
 451
 452         return 1;
 453 }
 454 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 455
 456 /*************************************************************************
 457  *  pci_target_init
 458  *
 459  *      The bootstrap configuration provides default settings for the pci
 460  *      inbound map (PIM). But the bootstrap config choices are limited and
 461  *      may not be sufficient for a given board.
 462  *
 463  ************************************************************************/
 464 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 465 void pci_target_init(struct pci_controller *hose)
 466 {
 467         /*--------------------------------------------------------------------------+
 468          * Set up Direct MMIO registers
 469          *--------------------------------------------------------------------------*/
 470         /*--------------------------------------------------------------------------+
 471           | PowerPC440 EP PCI Master configuration.
 472           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 473           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 474           |   Use byte reversed out routines to handle endianess.
 475           | Make this region non-prefetchable.
 476           +--------------------------------------------------------------------------*/
 477         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 478         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 479         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 480         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 481         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 482
 483         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 484         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 485         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 486         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 487         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 488
 489         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 490         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 491         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 492         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 493
 494         /*--------------------------------------------------------------------------+
 495          * Set up Configuration registers
 496          *--------------------------------------------------------------------------*/
 497
 498         /* Program the board's subsystem id/vendor id */
 499         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 500                               CFG_PCI_SUBSYS_VENDORID);
 501         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 502
 503         /* Configure command register as bus master */
 504         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 505
 506         /* 240nS PCI clock */
 507         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 508
 509         /* No error reporting */
 510         pci_write_config_word(0, PCI_ERREN, 0);
 511
 512         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 513
 514 }
 515 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 516
 517 /*************************************************************************
 518  *  pci_master_init
 519  *
 520  ************************************************************************/
 521 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 522 void pci_master_init(struct pci_controller *hose)
 523 {
 524         unsigned short temp_short;
 525
 526         /*--------------------------------------------------------------------------+
 527           | Write the PowerPC440 EP PCI Configuration regs.
 528           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 529           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 530           +--------------------------------------------------------------------------*/
 531         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 532         pci_write_config_word(0, PCI_COMMAND,
 533                               temp_short | PCI_COMMAND_MASTER |
 534                               PCI_COMMAND_MEMORY);
 535 }
 536 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 537
 538 /*************************************************************************
 539  *  is_pci_host
 540  *
 541  *      This routine is called to determine if a pci scan should be
 542  *      performed. With various hardware environments (especially cPCI and
 543  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 544  *      bit in the strap register, or generic host/adapter assumptions.
 545  *
 546  *      Rather than hard-code a bad assumption in the general 440 code, the
 547  *      440 pci code requires the board to decide at runtime.
 548  *
 549  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 550  *
 551  *
 552  ************************************************************************/
 553 #if defined(CONFIG_PCI)
 554 int is_pci_host(struct pci_controller *hose)
 555 {
 556         /* Bamboo is always configured as host. */
 557         return (1);
 558 }
 559 #endif                          /* defined(CONFIG_PCI) */
 560
 561 /*----------------------------------------------------------------------------+
 562   | is_powerpc440ep_pass1.
 563   +----------------------------------------------------------------------------*/
 564 int is_powerpc440ep_pass1(void)
 565 {
 566         unsigned long pvr;
 567
 568         pvr = get_pvr();
 569
 570         if (pvr == PVR_POWERPC_440EP_PASS1)
 571                 return TRUE;
 572         else if (pvr == PVR_POWERPC_440EP_PASS2)
 573                 return FALSE;
 574         else {
 575                 printf("brdutil error 3\n");
 576                 for (;;)
 577                         ;
 578         }
 579
 580         return(FALSE);
 581 }
 582
 583 /*----------------------------------------------------------------------------+
 584   | is_nand_selected.
 585   +----------------------------------------------------------------------------*/
 586 int is_nand_selected(void)
 587 {
 588         return FALSE; /* test-only */
 589 }
 590
 591 /*----------------------------------------------------------------------------+
 592   | config_on_ebc_cs4_is_small_flash => from EPLD
 593   +----------------------------------------------------------------------------*/
 594 unsigned char config_on_ebc_cs4_is_small_flash(void)
 595 {
 596         /* Not implemented yet => returns constant value */
 597         return TRUE;
 598 }
 599
 600 /*----------------------------------------------------------------------------+
 601   | Ext_bus_cntlr_init.
 602   | Initialize the external bus controller
 603   +----------------------------------------------------------------------------*/
 604 void ext_bus_cntlr_init(void)
 605 {
 606         unsigned long sdr0_pstrp0, sdr0_sdstp1;
 607         unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
 608         int           computed_boot_device = BOOT_DEVICE_UNKNOWN;
 609         unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
 610         unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
 611         unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
 612         unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
 613         unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
 614
 615
 616         /*-------------------------------------------------------------------------+
 617           |
 618           |  PART 1 : Initialize EBC Bank 5
 619           |  ==============================
 620           | Bank5 is always associated to the NVRAM/EPLD.
 621           | It has to be initialized prior to other banks settings computation since
 622           | some board registers values may be needed
 623           |
 624           +-------------------------------------------------------------------------*/
 625         /* NVRAM - FPGA */
 626         mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
 627         mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
 628
 629         /*-------------------------------------------------------------------------+
 630           |
 631           |  PART 2 : Determine which boot device was selected
 632           |  =========================================
 633           |
 634           |  Read Pin Strap Register in PPC440EP
 635           |  In case of boot from IIC, read Serial Device Strap Register1
 636           |
 637           |  Result can either be :
 638           |   - Boot from EBC 8bits    => SMALL FLASH
 639           |   - Boot from EBC 16bits   => Large Flash or SRAM
 640           |   - Boot from NAND Flash
 641           |   - Boot from PCI
 642           |
 643           +-------------------------------------------------------------------------*/
 644         /* Read Pin Strap Register in PPC440EP */
 645         mfsdr(sdr_pstrp0, sdr0_pstrp0);
 646         bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
 647
 648         /*-------------------------------------------------------------------------+
 649           |  PPC440EP Pass1
 650           +-------------------------------------------------------------------------*/
 651         if (is_powerpc440ep_pass1() == TRUE) {
 652                 switch(bootstrap_settings) {
 653                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 654                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 655                         /* Boot from Small Flash */
 656                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 657                         break;
 658                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 659                         /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
 660                         /* Boot from PCI */
 661                         computed_boot_device = BOOT_FROM_PCI;
 662                         break;
 663
 664                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 665                         /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
 666                         /* Boot from Nand Flash */
 667                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 668                         break;
 669
 670                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 671                         /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
 672                         /* Boot from Small Flash */
 673                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 674                         break;
 675
 676                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 677                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 678                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 679                         /* Read Serial Device Strap Register1 in PPC440EP */
 680                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 681                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 682                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 683
 684                         switch(boot_selection) {
 685                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 686                                 switch(ebc_boot_size) {
 687                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 688                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 689                                         break;
 690                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 691                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 692                                         break;
 693                                 }
 694                                 break;
 695
 696                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 697                                 computed_boot_device = BOOT_FROM_PCI;
 698                                 break;
 699
 700                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 701                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 702                                 break;
 703                         }
 704                         break;
 705                 }
 706         }
 707
 708         /*-------------------------------------------------------------------------+
 709           |  PPC440EP Pass2
 710           +-------------------------------------------------------------------------*/
 711         else {
 712                 switch(bootstrap_settings) {
 713                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 714                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 715                         /* Boot from Small Flash */
 716                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 717                         break;
 718                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 719                         /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
 720                         /* Boot from PCI */
 721                         computed_boot_device = BOOT_FROM_PCI;
 722                         break;
 723
 724                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 725                         /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
 726                         /* Boot from Nand Flash */
 727                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 728                         break;
 729
 730                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 731                         /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
 732                         /* Boot from Large Flash or SRAM */
 733                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 734                         break;
 735
 736                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
 737                         /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
 738                         /* Boot from Large Flash or SRAM */
 739                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 740                         break;
 741
 742                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
 743                         /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
 744                         /* Boot from PCI */
 745                         computed_boot_device = BOOT_FROM_PCI;
 746                         break;
 747
 748                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 749                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 750                         /* Default Strap Settings 5-7 */
 751                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 752                         /* Read Serial Device Strap Register1 in PPC440EP */
 753                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 754                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 755                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 756
 757                         switch(boot_selection) {
 758                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 759                                 switch(ebc_boot_size) {
 760                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 761                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 762                                         break;
 763                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 764                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 765                                         break;
 766                                 }
 767                                 break;
 768
 769                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 770                                 computed_boot_device = BOOT_FROM_PCI;
 771                                 break;
 772
 773                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 774                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 775                                 break;
 776                         }
 777                         break;
 778                 }
 779         }
 780
 781         /*-------------------------------------------------------------------------+
 782           |
 783           |  PART 3 : Compute EBC settings depending on selected boot device
 784           |  ======   ======================================================
 785           |
 786           | Resulting EBC init will be among following configurations :
 787           |
 788           |  - Boot from EBC 8bits => boot from SMALL FLASH selected
 789           |            EBC-CS0     = Small Flash
 790           |            EBC-CS1,2,3 = NAND Flash or
 791           |                         Exp.Slot depending on Soft Config
 792           |            EBC-CS4     = SRAM/Large Flash or
 793           |                         Large Flash/SRAM depending on jumpers
 794           |            EBC-CS5     = NVRAM / EPLD
 795           |
 796           |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
 797           |            EBC-CS0     = SRAM/Large Flash or
 798           |                          Large Flash/SRAM depending on jumpers
 799           |            EBC-CS1,2,3 = NAND Flash or
 800           |                          Exp.Slot depending on Software Configuration
 801           |            EBC-CS4     = Small Flash
 802           |            EBC-CS5     = NVRAM / EPLD
 803           |
 804           |  - Boot from NAND Flash
 805           |            EBC-CS0     = NAND Flash0
 806           |            EBC-CS1,2,3 = NAND Flash1
 807           |            EBC-CS4     = SRAM/Large Flash or
 808           |                          Large Flash/SRAM depending on jumpers
 809           |            EBC-CS5     = NVRAM / EPLD
 810           |
 811           |    - Boot from PCI
 812           |            EBC-CS0     = ...
 813           |            EBC-CS1,2,3 = NAND Flash or
 814           |                          Exp.Slot depending on Software Configuration
 815           |            EBC-CS4     = SRAM/Large Flash or
 816           |                          Large Flash/SRAM or
 817           |                          Small Flash depending on jumpers
 818           |            EBC-CS5     = NVRAM / EPLD
 819           |
 820           +-------------------------------------------------------------------------*/
 821
 822         switch(computed_boot_device) {
 823                 /*------------------------------------------------------------------------- */
 824         case BOOT_FROM_SMALL_FLASH:
 825                 /*------------------------------------------------------------------------- */
 826                 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
 827                 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
 828                 if ((is_nand_selected()) == TRUE) {
 829                         /* NAND Flash */
 830                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 831                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 832                         /*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
 833                           ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
 834                           ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
 835                           ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
 836                         ebc0_cs2_bnap_value = 0;
 837                         ebc0_cs2_bncr_value = 0;
 838                         ebc0_cs3_bnap_value = 0;
 839                         ebc0_cs3_bncr_value = 0;
 840                 } else {
 841                         /* Expansion Slot */
 842                         ebc0_cs1_bnap_value = 0;
 843                         ebc0_cs1_bncr_value = 0;
 844                         ebc0_cs2_bnap_value = 0;
 845                         ebc0_cs2_bncr_value = 0;
 846                         ebc0_cs3_bnap_value = 0;
 847                         ebc0_cs3_bncr_value = 0;
 848                 }
 849                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 850                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 851
 852                 break;
 853
 854                 /*------------------------------------------------------------------------- */
 855         case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 856                 /*------------------------------------------------------------------------- */
 857                 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 858                 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
 859                 if ((is_nand_selected()) == TRUE) {
 860                         /* NAND Flash */
 861                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 862                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 863                         ebc0_cs2_bnap_value = 0;
 864                         ebc0_cs2_bncr_value = 0;
 865                         ebc0_cs3_bnap_value = 0;
 866                         ebc0_cs3_bncr_value = 0;
 867                 } else {
 868                         /* Expansion Slot */
 869                         ebc0_cs1_bnap_value = 0;
 870                         ebc0_cs1_bncr_value = 0;
 871                         ebc0_cs2_bnap_value = 0;
 872                         ebc0_cs2_bncr_value = 0;
 873                         ebc0_cs3_bnap_value = 0;
 874                         ebc0_cs3_bncr_value = 0;
 875                 }
 876                 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 877                 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 878
 879                 break;
 880
 881                 /*------------------------------------------------------------------------- */
 882         case BOOT_FROM_NAND_FLASH0:
 883                 /*------------------------------------------------------------------------- */
 884                 ebc0_cs0_bnap_value = 0;
 885                 ebc0_cs0_bncr_value = 0;
 886
 887                 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 888                 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 889                 ebc0_cs2_bnap_value = 0;
 890                 ebc0_cs2_bncr_value = 0;
 891                 ebc0_cs3_bnap_value = 0;
 892                 ebc0_cs3_bncr_value = 0;
 893
 894                 /* Large Flash or SRAM */
 895                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 896                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 897
 898                 break;
 899
 900                 /*------------------------------------------------------------------------- */
 901         case BOOT_FROM_PCI:
 902                 /*------------------------------------------------------------------------- */
 903                 ebc0_cs0_bnap_value = 0;
 904                 ebc0_cs0_bncr_value = 0;
 905
 906                 if ((is_nand_selected()) == TRUE) {
 907                         /* NAND Flash */
 908                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 909                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 910                         ebc0_cs2_bnap_value = 0;
 911                         ebc0_cs2_bncr_value = 0;
 912                         ebc0_cs3_bnap_value = 0;
 913                         ebc0_cs3_bncr_value = 0;
 914                 } else {
 915                         /* Expansion Slot */
 916                         ebc0_cs1_bnap_value = 0;
 917                         ebc0_cs1_bncr_value = 0;
 918                         ebc0_cs2_bnap_value = 0;
 919                         ebc0_cs2_bncr_value = 0;
 920                         ebc0_cs3_bnap_value = 0;
 921                         ebc0_cs3_bncr_value = 0;
 922                 }
 923
 924                 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
 925                         /* Small Flash */
 926                         ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 927                         ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 928                 } else {
 929                         /* Large Flash or SRAM */
 930                         ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 931                         ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 932                 }
 933
 934                 break;
 935
 936                 /*------------------------------------------------------------------------- */
 937         case BOOT_DEVICE_UNKNOWN:
 938                 /*------------------------------------------------------------------------- */
 939                 /* Error */
 940                 break;
 941
 942         }
 943
 944
 945         /*-------------------------------------------------------------------------+
 946           | Initialize EBC CONFIG
 947           +-------------------------------------------------------------------------*/
 948         mtdcr(ebccfga, xbcfg);
 949         mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN        |
 950               EBC0_CFG_PTD_ENABLED        |
 951               EBC0_CFG_RTC_2048PERCLK     |
 952               EBC0_CFG_EMPL_LOW           |
 953               EBC0_CFG_EMPH_LOW           |
 954               EBC0_CFG_CSTC_DRIVEN        |
 955               EBC0_CFG_BPF_ONEDW          |
 956               EBC0_CFG_EMS_8BIT           |
 957               EBC0_CFG_PME_DISABLED       |
 958               EBC0_CFG_PMT_ENCODE(0)      );
 959
 960         /*-------------------------------------------------------------------------+
 961           | Initialize EBC Bank 0-4
 962           +-------------------------------------------------------------------------*/
 963         /* EBC Bank0 */
 964         mtebc(pb0ap, ebc0_cs0_bnap_value);
 965         mtebc(pb0cr, ebc0_cs0_bncr_value);
 966         /* EBC Bank1 */
 967         mtebc(pb1ap, ebc0_cs1_bnap_value);
 968         mtebc(pb1cr, ebc0_cs1_bncr_value);
 969         /* EBC Bank2 */
 970         mtebc(pb2ap, ebc0_cs2_bnap_value);
 971         mtebc(pb2cr, ebc0_cs2_bncr_value);
 972         /* EBC Bank3 */
 973         mtebc(pb3ap, ebc0_cs3_bnap_value);
 974         mtebc(pb3cr, ebc0_cs3_bncr_value);
 975         /* EBC Bank4 */
 976         mtebc(pb4ap, ebc0_cs4_bnap_value);
 977         mtebc(pb4cr, ebc0_cs4_bncr_value);
 978
 979         return;
 980 }
 981
 982
 983 /*----------------------------------------------------------------------------+
 984   | get_uart_configuration.
 985   +----------------------------------------------------------------------------*/
 986 uart_config_nb_t get_uart_configuration(void)
 987 {
 988         return (L4); /* test-only */
 989 }
 990
 991 /*----------------------------------------------------------------------------+
 992   | set_phy_configuration_through_fpga => to EPLD
 993   +----------------------------------------------------------------------------*/
 994 void set_phy_configuration_through_fpga(zmii_config_t config)
 995 {
 996
 997         unsigned long fpga_selection_reg;
 998
 999         fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1000
1001         switch(config)
1002         {
1003         case ZMII_CONFIGURATION_IS_MII:
1004                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1005                 break;
1006         case ZMII_CONFIGURATION_IS_RMII:
1007                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1008                 break;
1009         case ZMII_CONFIGURATION_IS_SMII:
1010                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1011                 break;
1012         case ZMII_CONFIGURATION_UNKNOWN:
1013         default:
1014                 break;
1015         }
1016         out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1017
1018 }
1019
1020 /*----------------------------------------------------------------------------+
1021   | scp_selection_in_fpga.
1022   +----------------------------------------------------------------------------*/
1023 void scp_selection_in_fpga(void)
1024 {
1025         unsigned long fpga_selection_2_reg;
1026
1027         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1028         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1029         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1030 }
1031
1032 /*----------------------------------------------------------------------------+
1033   | iic1_selection_in_fpga.
1034   +----------------------------------------------------------------------------*/
1035 void iic1_selection_in_fpga(void)
1036 {
1037         unsigned long fpga_selection_2_reg;
1038
1039         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1040         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1041         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1042 }
1043
1044 /*----------------------------------------------------------------------------+
1045   | dma_a_b_selection_in_fpga.
1046   +----------------------------------------------------------------------------*/
1047 void dma_a_b_selection_in_fpga(void)
1048 {
1049         unsigned long fpga_selection_2_reg;
1050
1051         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1052         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1053 }
1054
1055 /*----------------------------------------------------------------------------+
1056   | dma_a_b_unselect_in_fpga.
1057   +----------------------------------------------------------------------------*/
1058 void dma_a_b_unselect_in_fpga(void)
1059 {
1060         unsigned long fpga_selection_2_reg;
1061
1062         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1063         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1064 }
1065
1066 /*----------------------------------------------------------------------------+
1067   | dma_c_d_selection_in_fpga.
1068   +----------------------------------------------------------------------------*/
1069 void dma_c_d_selection_in_fpga(void)
1070 {
1071         unsigned long fpga_selection_2_reg;
1072
1073         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1074         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1075 }
1076
1077 /*----------------------------------------------------------------------------+
1078   | dma_c_d_unselect_in_fpga.
1079   +----------------------------------------------------------------------------*/
1080 void dma_c_d_unselect_in_fpga(void)
1081 {
1082         unsigned long fpga_selection_2_reg;
1083
1084         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1085         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1086 }
1087
1088 /*----------------------------------------------------------------------------+
1089   | usb2_device_selection_in_fpga.
1090   +----------------------------------------------------------------------------*/
1091 void usb2_device_selection_in_fpga(void)
1092 {
1093         unsigned long fpga_selection_1_reg;
1094
1095         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1096         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1097 }
1098
1099 /*----------------------------------------------------------------------------+
1100   | usb2_device_reset_through_fpga.
1101   +----------------------------------------------------------------------------*/
1102 void usb2_device_reset_through_fpga(void)
1103 {
1104         /* Perform soft Reset pulse */
1105         unsigned long fpga_reset_reg;
1106         int i;
1107
1108         fpga_reset_reg = in8(FPGA_RESET_REG);
1109         out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1110         for (i=0; i<500; i++)
1111                 udelay(1000);
1112         out8(FPGA_RESET_REG,fpga_reset_reg);
1113 }
1114
1115 /*----------------------------------------------------------------------------+
1116   | usb2_host_selection_in_fpga.
1117   +----------------------------------------------------------------------------*/
1118 void usb2_host_selection_in_fpga(void)
1119 {
1120         unsigned long fpga_selection_1_reg;
1121
1122         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1123         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1124 }
1125
1126 /*----------------------------------------------------------------------------+
1127   | ndfc_selection_in_fpga.
1128   +----------------------------------------------------------------------------*/
1129 void ndfc_selection_in_fpga(void)
1130 {
1131         unsigned long fpga_selection_1_reg;
1132
1133         fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1134         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1135         /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */
1136         /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
1137         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1138 }
1139
1140 /*----------------------------------------------------------------------------+
1141   | uart_selection_in_fpga.
1142   +----------------------------------------------------------------------------*/
1143 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1144 {
1145         /* FPGA register */
1146         unsigned char   fpga_selection_3_reg;
1147
1148         /* Read FPGA Reagister */
1149         fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1150
1151         switch (uart_config)
1152         {
1153         case L1:
1154                 /* ----------------------------------------------------------------------- */
1155                 /* L1 configuration:    UART0 = 8 pins */
1156                 /* ----------------------------------------------------------------------- */
1157                 /* Configure FPGA */
1158                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1159                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1160                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1161
1162                 break;
1163
1164         case L2:
1165                 /* ----------------------------------------------------------------------- */
1166                 /* L2 configuration:    UART0 = 4 pins */
1167                 /*                      UART1 = 4 pins */
1168                 /* ----------------------------------------------------------------------- */
1169                 /* Configure FPGA */
1170                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1171                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1172                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1173
1174                 break;
1175
1176         case L3:
1177                 /* ----------------------------------------------------------------------- */
1178                 /* L3 configuration:    UART0 = 4 pins */
1179                 /*                      UART1 = 2 pins */
1180                 /*                      UART2 = 2 pins */
1181                 /* ----------------------------------------------------------------------- */
1182                 /* Configure FPGA */
1183                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1184                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1185                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1186                 break;
1187
1188         case L4:
1189                 /* Configure FPGA */
1190                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1191                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1192                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1193
1194                 break;
1195
1196         default:
1197                 /* Unsupported UART configuration number */
1198                 for (;;)
1199                         ;
1200                 break;
1201
1202         }
1203 }
1204
1205
1206 /*----------------------------------------------------------------------------+
1207   | init_default_gpio
1208   +----------------------------------------------------------------------------*/
1209 void init_default_gpio(void)
1210 {
1211         int i;
1212
1213         /* Init GPIO0 */
1214         for(i=0; i<GPIO_MAX; i++)
1215         {
1216                 gpio_tab[GPIO0][i].add    = GPIO0_BASE;
1217                 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1218                 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1219         }
1220
1221         /* Init GPIO1 */
1222         for(i=0; i<GPIO_MAX; i++)
1223         {
1224                 gpio_tab[GPIO1][i].add    = GPIO1_BASE;
1225                 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1226                 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1227         }
1228
1229         /* EBC_CS_N(5) - GPIO0_10 */
1230         gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
1231         gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
1232
1233         /* EBC_CS_N(4) - GPIO0_9 */
1234         gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
1235         gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
1236 }
1237
1238 /*----------------------------------------------------------------------------+
1239   | update_uart_ios
1240   +------------------------------------------------------------------------------
1241   |
1242   | Set UART Configuration in PowerPC440EP
1243   |
1244   | +---------------------------------------------------------------------+
1245   | | Configuartion   |   Connector   | Nb of pins | Pins   | Associated  |
1246   | |    Number       |   Port Name   |  available | naming |   CORE      |
1247   | +-----------------+---------------+------------+--------+-------------+
1248   | |     L1          |   Port_A      |     8      | UART   | UART core 0 |
1249   | +-----------------+---------------+------------+--------+-------------+
1250   | |     L2          |   Port_A      |     4      | UART1  | UART core 0 |
1251   | |    (L2D)        |   Port_B      |     4      | UART2  | UART core 1 |
1252   | +-----------------+---------------+------------+--------+-------------+
1253   | |     L3          |   Port_A      |     4      | UART1  | UART core 0 |
1254   | |    (L3D)        |   Port_B      |     2      | UART2  | UART core 1 |
1255   | |                 |   Port_C      |     2      | UART3  | UART core 2 |
1256   | +-----------------+---------------+------------+--------+-------------+
1257   | |                 |   Port_A      |     2      | UART1  | UART core 0 |
1258   | |     L4          |   Port_B      |     2      | UART2  | UART core 1 |
1259   | |    (L4D)        |   Port_C      |     2      | UART3  | UART core 2 |
1260   | |                 |   Port_D      |     2      | UART4  | UART core 3 |
1261   | +-----------------+---------------+------------+--------+-------------+
1262   |
1263   |  Involved GPIOs
1264   |
1265   | +------------------------------------------------------------------------------+
1266   | |  GPIO   |   Aternate 1     | I/O |  Alternate 2    | I/O | Alternate 3 | I/O |
1267   | +---------+------------------+-----+-----------------+-----+-------------+-----+
1268   | | GPIO1_2 | UART0_DCD_N      |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |  O  |
1269   | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |  I  |
1270   | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA              |  NA | UART3_SIN   |  I  |
1271   | | GPIO1_5 | UART0_RTS_N      |  O  | NA              |  NA | UART3_SOUT  |  O  |
1272   | | GPIO1_6 | UART0_DTR_N      |  O  | UART1_SOUT      |  O  | NA          |  NA |
1273   | | GPIO1_7 | UART0_RI_N       |  I  | UART1_SIN       |  I  | NA          |  NA |
1274   | +------------------------------------------------------------------------------+
1275   |
1276   |
1277   +----------------------------------------------------------------------------*/
1278
1279 void update_uart_ios(uart_config_nb_t uart_config)
1280 {
1281         switch (uart_config)
1282         {
1283         case L1:
1284                 /* ----------------------------------------------------------------------- */
1285                 /* L1 configuration:    UART0 = 8 pins */
1286                 /* ----------------------------------------------------------------------- */
1287                 /* Update GPIO Configuration Table */
1288                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1289                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1290
1291                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1292                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1293
1294                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1295                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1296
1297                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1298                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1299
1300                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1301                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1302
1303                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1304                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1305
1306                 break;
1307
1308         case L2:
1309                 /* ----------------------------------------------------------------------- */
1310                 /* L2 configuration:    UART0 = 4 pins */
1311                 /*                      UART1 = 4 pins */
1312                 /* ----------------------------------------------------------------------- */
1313                 /* Update GPIO Configuration Table */
1314                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1315                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1316
1317                 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1318                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1319
1320                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1321                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1322
1323                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1324                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1325
1326                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1327                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1328
1329                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1330                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1331
1332                 break;
1333
1334         case L3:
1335                 /* ----------------------------------------------------------------------- */
1336                 /* L3 configuration:    UART0 = 4 pins */
1337                 /*                      UART1 = 2 pins */
1338                 /*                      UART2 = 2 pins */
1339                 /* ----------------------------------------------------------------------- */
1340                 /* Update GPIO Configuration Table */
1341                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1342                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1343
1344                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1345                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1346
1347                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1348                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1349
1350                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1351                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1352
1353                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1354                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1355
1356                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1357                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1358
1359                 break;
1360
1361         case L4:
1362                 /* ----------------------------------------------------------------------- */
1363                 /* L4 configuration:    UART0 = 2 pins */
1364                 /*                      UART1 = 2 pins */
1365                 /*                      UART2 = 2 pins */
1366                 /*                      UART3 = 2 pins */
1367                 /* ----------------------------------------------------------------------- */
1368                 /* Update GPIO Configuration Table */
1369                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1370                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1371
1372                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1373                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1374
1375                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1376                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1377
1378                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1379                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1380
1381                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1382                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1383
1384                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1385                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1386
1387                 break;
1388
1389         default:
1390                 /* Unsupported UART configuration number */
1391                 printf("ERROR - Unsupported UART configuration number.\n\n");
1392                 for (;;)
1393                         ;
1394                 break;
1395
1396         }
1397
1398         /* Set input Selection Register on Alt_Receive for UART Input Core */
1399         out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1400         out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1401         out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1402 }
1403
1404 /*----------------------------------------------------------------------------+
1405   | update_ndfc_ios(void).
1406   +----------------------------------------------------------------------------*/
1407 void update_ndfc_ios(void)
1408 {
1409         /* Update GPIO Configuration Table */
1410         gpio_tab[GPIO0][6].in_out = GPIO_OUT;       /* EBC_CS_N(1) */
1411         gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1412
1413 #if 0
1414         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(2) */
1415         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1416
1417         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(3) */
1418         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1419 #endif
1420 }
1421
1422 /*----------------------------------------------------------------------------+
1423   | update_zii_ios(void).
1424   +----------------------------------------------------------------------------*/
1425 void update_zii_ios(void)
1426 {
1427         /* Update GPIO Configuration Table */
1428         gpio_tab[GPIO0][12].in_out = GPIO_IN;       /* ZII_p0Rxd(0) */
1429         gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1430
1431         gpio_tab[GPIO0][13].in_out = GPIO_IN;       /* ZII_p0Rxd(1) */
1432         gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1433
1434         gpio_tab[GPIO0][14].in_out = GPIO_IN;       /* ZII_p0Rxd(2) */
1435         gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1436
1437         gpio_tab[GPIO0][15].in_out = GPIO_IN;       /* ZII_p0Rxd(3) */
1438         gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1439
1440         gpio_tab[GPIO0][16].in_out = GPIO_OUT;      /* ZII_p0Txd(0) */
1441         gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1442
1443         gpio_tab[GPIO0][17].in_out = GPIO_OUT;      /* ZII_p0Txd(1) */
1444         gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1445
1446         gpio_tab[GPIO0][18].in_out = GPIO_OUT;      /* ZII_p0Txd(2) */
1447         gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1448
1449         gpio_tab[GPIO0][19].in_out = GPIO_OUT;      /* ZII_p0Txd(3) */
1450         gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1451
1452         gpio_tab[GPIO0][20].in_out = GPIO_IN;       /* ZII_p0Rx_er */
1453         gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1454
1455         gpio_tab[GPIO0][21].in_out = GPIO_IN;       /* ZII_p0Rx_dv */
1456         gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1457
1458         gpio_tab[GPIO0][22].in_out = GPIO_IN;       /* ZII_p0Crs */
1459         gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1460
1461         gpio_tab[GPIO0][23].in_out = GPIO_OUT;      /* ZII_p0Tx_er */
1462         gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1463
1464         gpio_tab[GPIO0][24].in_out = GPIO_OUT;      /* ZII_p0Tx_en */
1465         gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1466
1467         gpio_tab[GPIO0][25].in_out = GPIO_IN;       /* ZII_p0Col */
1468         gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1469
1470 }
1471
1472 /*----------------------------------------------------------------------------+
1473   | update_uic_0_3_irq_ios().
1474   +----------------------------------------------------------------------------*/
1475 void update_uic_0_3_irq_ios(void)
1476 {
1477         gpio_tab[GPIO1][8].in_out = GPIO_IN;        /* UIC_IRQ(0) */
1478         gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1479
1480         gpio_tab[GPIO1][9].in_out = GPIO_IN;        /* UIC_IRQ(1) */
1481         gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1482
1483         gpio_tab[GPIO1][10].in_out = GPIO_IN;       /* UIC_IRQ(2) */
1484         gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1485
1486         gpio_tab[GPIO1][11].in_out = GPIO_IN;       /* UIC_IRQ(3) */
1487         gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1488 }
1489
1490 /*----------------------------------------------------------------------------+
1491   | update_uic_4_9_irq_ios().
1492   +----------------------------------------------------------------------------*/
1493 void update_uic_4_9_irq_ios(void)
1494 {
1495         gpio_tab[GPIO1][12].in_out = GPIO_IN;       /* UIC_IRQ(4) */
1496         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1497
1498         gpio_tab[GPIO1][13].in_out = GPIO_IN;       /* UIC_IRQ(6) */
1499         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1500
1501         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* UIC_IRQ(7) */
1502         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1503
1504         gpio_tab[GPIO1][15].in_out = GPIO_IN;       /* UIC_IRQ(8) */
1505         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1506
1507         gpio_tab[GPIO1][16].in_out = GPIO_IN;       /* UIC_IRQ(9) */
1508         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1509 }
1510
1511 /*----------------------------------------------------------------------------+
1512   | update_dma_a_b_ios().
1513   +----------------------------------------------------------------------------*/
1514 void update_dma_a_b_ios(void)
1515 {
1516         gpio_tab[GPIO1][12].in_out = GPIO_OUT;      /* DMA_ACK(1) */
1517         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1518
1519         gpio_tab[GPIO1][13].in_out = GPIO_BI;       /* DMA_EOT/TC(1) */
1520         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1521
1522         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* DMA_REQ(0) */
1523         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1524
1525         gpio_tab[GPIO1][15].in_out = GPIO_OUT;      /* DMA_ACK(0) */
1526         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1527
1528         gpio_tab[GPIO1][16].in_out = GPIO_BI;       /* DMA_EOT/TC(0) */
1529         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1530 }
1531
1532 /*----------------------------------------------------------------------------+
1533   | update_dma_c_d_ios().
1534   +----------------------------------------------------------------------------*/
1535 void update_dma_c_d_ios(void)
1536 {
1537         gpio_tab[GPIO0][0].in_out = GPIO_IN;        /* DMA_REQ(2) */
1538         gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1539
1540         gpio_tab[GPIO0][1].in_out = GPIO_OUT;       /* DMA_ACK(2) */
1541         gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1542
1543         gpio_tab[GPIO0][2].in_out = GPIO_BI;        /* DMA_EOT/TC(2) */
1544         gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1545
1546         gpio_tab[GPIO0][3].in_out = GPIO_IN;        /* DMA_REQ(3) */
1547         gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1548
1549         gpio_tab[GPIO0][4].in_out = GPIO_OUT;       /* DMA_ACK(3) */
1550         gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1551
1552         gpio_tab[GPIO0][5].in_out = GPIO_BI;        /* DMA_EOT/TC(3) */
1553         gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1554
1555 }
1556
1557 /*----------------------------------------------------------------------------+
1558   | update_ebc_master_ios().
1559   +----------------------------------------------------------------------------*/
1560 void update_ebc_master_ios(void)
1561 {
1562         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* EXT_EBC_REQ */
1563         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1564
1565         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1566         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1567
1568         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* EBC_EXT_ACK */
1569         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1570
1571         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* EBC_EXR_BUSREQ */
1572         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1573 }
1574
1575 /*----------------------------------------------------------------------------+
1576   | update_usb2_device_ios().
1577   +----------------------------------------------------------------------------*/
1578 void update_usb2_device_ios(void)
1579 {
1580         gpio_tab[GPIO0][26].in_out = GPIO_IN;       /* USB2D_RXVALID */
1581         gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1582
1583         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* USB2D_RXERROR */
1584         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1585
1586         gpio_tab[GPIO0][28].in_out = GPIO_OUT;      /* USB2D_TXVALID */
1587         gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1588
1589         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* USB2D_PAD_SUSPNDM */
1590         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1591
1592         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* USB2D_XCVRSELECT */
1593         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1594
1595         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* USB2D_TERMSELECT */
1596         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1597
1598         gpio_tab[GPIO1][0].in_out = GPIO_OUT;       /* USB2D_OPMODE0 */
1599         gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1600
1601         gpio_tab[GPIO1][1].in_out = GPIO_OUT;       /* USB2D_OPMODE1 */
1602         gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1603
1604 }
1605
1606 /*----------------------------------------------------------------------------+
1607   | update_pci_patch_ios().
1608   +----------------------------------------------------------------------------*/
1609 void update_pci_patch_ios(void)
1610 {
1611         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1612         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1613 }
1614
1615 /*----------------------------------------------------------------------------+
1616   |   set_chip_gpio_configuration(unsigned char gpio_core)
1617   |   Put the core impacted by clock modification and sharing in reset.
1618   |   Config the select registers to resolve the sharing depending of the config.
1619   |   Configure the GPIO registers.
1620   |
1621   +----------------------------------------------------------------------------*/
1622 void set_chip_gpio_configuration(unsigned char gpio_core)
1623 {
1624         unsigned char i=0, j=0, reg_offset = 0;
1625         unsigned long gpio_reg, gpio_core_add;
1626
1627         /* GPIO config of the GPIOs 0 to 31 */
1628         for (i=0; i<GPIO_MAX; i++, j++)
1629         {
1630                 if (i == GPIO_MAX/2)
1631                 {
1632                         reg_offset = 4;
1633                         j = i-16;
1634                 }
1635
1636                 gpio_core_add = gpio_tab[gpio_core][i].add;
1637
1638                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1639                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1640                 {
1641                         switch (gpio_tab[gpio_core][i].alt_nb)
1642                         {
1643                         case GPIO_SEL:
1644                                 break;
1645
1646                         case GPIO_ALT1:
1647                                 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1648                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1649                                 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1650                                 break;
1651
1652                         case GPIO_ALT2:
1653                                 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1654                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1655                                 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1656                                 break;
1657
1658                         case GPIO_ALT3:
1659                                 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1660                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1661                                 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1662                                 break;
1663                         }
1664                 }
1665                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1666                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1667                 {
1668
1669                         switch (gpio_tab[gpio_core][i].alt_nb)
1670                         {
1671                         case GPIO_SEL:
1672                                 break;
1673                         case GPIO_ALT1:
1674                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1675                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1676                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1677                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1678                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1679                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1680                                 break;
1681                         case GPIO_ALT2:
1682                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1683                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1684                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1685                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1686                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1687                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1688                                 break;
1689                         case GPIO_ALT3:
1690                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1691                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1692                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1693                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1694                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1695                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1696                                 break;
1697                         }
1698                 }
1699         }
1700 }
1701
1702 /*----------------------------------------------------------------------------+
1703   | force_bup_core_selection.
1704   +----------------------------------------------------------------------------*/
1705 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1706 {
1707         /* Pointer invalid */
1708         if (core_select_P == NULL)
1709         {
1710                 printf("Configuration invalid pointer 1\n");
1711                 for (;;)
1712                         ;
1713         }
1714
1715         /* L4 Selection */
1716         *(core_select_P+UART_CORE0)            = CORE_SELECTED;
1717         *(core_select_P+UART_CORE1)            = CORE_SELECTED;
1718         *(core_select_P+UART_CORE2)            = CORE_SELECTED;
1719         *(core_select_P+UART_CORE3)            = CORE_SELECTED;
1720
1721         /* RMII Selection */
1722         *(core_select_P+RMII_SEL)               = CORE_SELECTED;
1723
1724         /* External Interrupt 0-9 selection */
1725         *(core_select_P+UIC_0_3)                = CORE_SELECTED;
1726         *(core_select_P+UIC_4_9)                = CORE_SELECTED;
1727
1728         *(core_select_P+SCP_CORE)            = CORE_SELECTED;
1729         *(core_select_P+DMA_CHANNEL_CD)            = CORE_SELECTED;
1730         *(core_select_P+PACKET_REJ_FUNC_AVAIL)            = CORE_SELECTED;
1731         *(core_select_P+USB1_DEVICE)            = CORE_SELECTED;
1732
1733         *config_val_P = CONFIG_IS_VALID;
1734
1735 }
1736
1737 /*----------------------------------------------------------------------------+
1738   | configure_ppc440ep_pins.
1739   +----------------------------------------------------------------------------*/
1740 void configure_ppc440ep_pins(void)
1741 {
1742         uart_config_nb_t uart_configuration;
1743         config_validity_t config_val = CONFIG_IS_INVALID;
1744
1745         /* Create Core Selection Table */
1746         core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1747                 {
1748                         CORE_NOT_SELECTED,      /* IIC_CORE, */
1749                         CORE_NOT_SELECTED,      /* SPC_CORE, */
1750                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_AB, */
1751                         CORE_NOT_SELECTED,      /* UIC_4_9, */
1752                         CORE_NOT_SELECTED,      /* USB2_HOST, */
1753                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_CD, */
1754                         CORE_NOT_SELECTED,      /* USB2_DEVICE, */
1755                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_AVAIL, */
1756                         CORE_NOT_SELECTED,      /* USB1_DEVICE, */
1757                         CORE_NOT_SELECTED,      /* EBC_MASTER, */
1758                         CORE_NOT_SELECTED,      /* NAND_FLASH, */
1759                         CORE_NOT_SELECTED,      /* UART_CORE0, */
1760                         CORE_NOT_SELECTED,      /* UART_CORE1, */
1761                         CORE_NOT_SELECTED,      /* UART_CORE2, */
1762                         CORE_NOT_SELECTED,      /* UART_CORE3, */
1763                         CORE_NOT_SELECTED,      /* MII_SEL, */
1764                         CORE_NOT_SELECTED,      /* RMII_SEL, */
1765                         CORE_NOT_SELECTED,      /* SMII_SEL, */
1766                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_EN */
1767                         CORE_NOT_SELECTED,      /* UIC_0_3 */
1768                         CORE_NOT_SELECTED,      /* USB1_HOST */
1769                         CORE_NOT_SELECTED       /* PCI_PATCH */
1770                 };
1771
1772
1773         /* Table Default Initialisation + FPGA Access */
1774         init_default_gpio();
1775         set_chip_gpio_configuration(GPIO0);
1776         set_chip_gpio_configuration(GPIO1);
1777
1778         /* Update Table */
1779         force_bup_core_selection(ppc440ep_core_selection, &config_val);
1780 #if 0 /* test-only */
1781         /* If we are running PIBS 1, force known configuration */
1782         update_core_selection_table(ppc440ep_core_selection, &config_val);
1783 #endif
1784
1785         /*----------------------------------------------------------------------------+
1786           | SDR + ios table update + fpga initialization
1787           +----------------------------------------------------------------------------*/
1788         unsigned long sdr0_pfc1     = 0;
1789         unsigned long sdr0_usb0     = 0;
1790         unsigned long sdr0_mfr      = 0;
1791
1792         /* PCI Always selected */
1793
1794         /* I2C Selection */
1795         if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1796         {
1797                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1798                 iic1_selection_in_fpga();
1799         }
1800
1801         /* SCP Selection */
1802         if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1803         {
1804                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1805                 scp_selection_in_fpga();
1806         }
1807
1808         /* UIC 0:3 Selection */
1809         if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1810         {
1811                 update_uic_0_3_irq_ios();
1812                 dma_a_b_unselect_in_fpga();
1813         }
1814
1815         /* UIC 4:9 Selection */
1816         if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1817         {
1818                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1819                 update_uic_4_9_irq_ios();
1820         }
1821
1822         /* DMA AB Selection */
1823         if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1824         {
1825                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1826                 update_dma_a_b_ios();
1827                 dma_a_b_selection_in_fpga();
1828         }
1829
1830         /* DMA CD Selection */
1831         if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1832         {
1833                 update_dma_c_d_ios();
1834                 dma_c_d_selection_in_fpga();
1835         }
1836
1837         /* EBC Master Selection */
1838         if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1839         {
1840                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1841                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1842                 update_ebc_master_ios();
1843         }
1844
1845         /* PCI Patch Enable */
1846         if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1847         {
1848                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1849                 update_pci_patch_ios();
1850         }
1851
1852         /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1853         if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1854         {
1855                 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1856                 printf("Invalid configuration => USB2 Host selected\n");
1857                 for (;;)
1858                         ;
1859                 /*usb2_host_selection_in_fpga(); */
1860         }
1861
1862         /* USB2.0 Device Selection */
1863         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1864         {
1865                 update_usb2_device_ios();
1866                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1867                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1868
1869                 mfsdr(sdr_usb0, sdr0_usb0);
1870                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1871                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1872                 mtsdr(sdr_usb0, sdr0_usb0);
1873
1874                 usb2_device_selection_in_fpga();
1875         }
1876
1877         /* USB1.1 Device Selection */
1878         if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1879         {
1880                 mfsdr(sdr_usb0, sdr0_usb0);
1881                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1882                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1883                 mtsdr(sdr_usb0, sdr0_usb0);
1884         }
1885
1886         /* USB1.1 Host Selection */
1887         if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1888         {
1889                 mfsdr(sdr_usb0, sdr0_usb0);
1890                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1891                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1892                 mtsdr(sdr_usb0, sdr0_usb0);
1893         }
1894
1895         /* NAND Flash Selection */
1896         if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1897         {
1898                 update_ndfc_ios();
1899
1900                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
1901                       SDR0_CUST0_NDFC_ENABLE    |
1902                       SDR0_CUST0_NDFC_BW_8_BIT  |
1903                       SDR0_CUST0_NDFC_ARE_MASK  |
1904                       SDR0_CUST0_CHIPSELGAT_EN1 );
1905                 /*SDR0_CUST0_CHIPSELGAT_EN2 ); */
1906                 /*SDR0_CUST0_CHIPSELGAT_EN3 ); */
1907
1908                 ndfc_selection_in_fpga();
1909         }
1910         else
1911         {
1912                 /* Set Mux on EMAC */
1913                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
1914         }
1915
1916         /* MII Selection */
1917         if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1918         {
1919                 update_zii_ios();
1920                 mfsdr(sdr_mfr, sdr0_mfr);
1921                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
1922                 mtsdr(sdr_mfr, sdr0_mfr);
1923
1924                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1925         }
1926
1927         /* RMII Selection */
1928         if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1929         {
1930                 update_zii_ios();
1931                 mfsdr(sdr_mfr, sdr0_mfr);
1932                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1933                 mtsdr(sdr_mfr, sdr0_mfr);
1934
1935                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1936         }
1937
1938         /* SMII Selection */
1939         if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1940         {
1941                 update_zii_ios();
1942                 mfsdr(sdr_mfr, sdr0_mfr);
1943                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
1944                 mtsdr(sdr_mfr, sdr0_mfr);
1945
1946                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1947         }
1948
1949         /* UART Selection */
1950         uart_configuration = get_uart_configuration();
1951         switch (uart_configuration)
1952         {
1953         case L1:         /* L1 Selection */
1954                 /* UART0 8 pins Only */
1955                 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
1956                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;   /* Chip Pb */
1957                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1958                 break;
1959         case L2:         /* L2 Selection */
1960                 /* UART0 and UART1 4 pins */
1961                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1962                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1963                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1964                 break;
1965         case L3:         /* L3 Selection */
1966                 /* UART0 4 pins, UART1 and UART2 2 pins */
1967                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1968                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1969                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1970                 break;
1971         case L4:         /* L4 Selection */
1972                 /* UART0, UART1, UART2 and UART3 2 pins */
1973                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1974                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1975                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1976                 break;
1977         }
1978         update_uart_ios(uart_configuration);
1979
1980         /* UART Selection in all cases */
1981         uart_selection_in_fpga(uart_configuration);
1982
1983         /* Packet Reject Function Available */
1984         if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
1985         {
1986                 /* Set UPR Bit in SDR0_PFC1 Register */
1987                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
1988         }
1989
1990         /* Packet Reject Function Enable */
1991         if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
1992         {
1993                 mfsdr(sdr_mfr, sdr0_mfr);
1994                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
1995                 mtsdr(sdr_mfr, sdr0_mfr);
1996         }
1997
1998         /* Perform effective access to hardware */
1999         mtsdr(sdr_pfc1, sdr0_pfc1);
2000         set_chip_gpio_configuration(GPIO0);
2001         set_chip_gpio_configuration(GPIO1);
2002
2003         /* USB2.0 Device Reset must be done after GPIO setting */
2004         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2005                 usb2_device_reset_through_fpga();
2006
2007 }