2 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3 * Copyright (C) 2012 Renesas Solutions Corp.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
14 #define MODEMR (0xFFCC0020)
15 #define MODEMR_MASK (0x6)
16 #define MODEMR_533MHZ (0x2)
20 u32 r = readl(MODEMR);
21 if ((r & MODEMR_MASK) & MODEMR_533MHZ)
22 puts("CPU Clock: 533MHz\n");
24 puts("CPU Clock: 400MHz\n");
26 puts("BOARD: Alpha Project. AP-SH4A-4A\n");
30 #define MSTPSR1 (0xFFC80044)
31 #define MSTPCR1 (0xFFC80034)
32 #define MSTPSR1_GETHER (1 << 14)
35 #define ET0_ETXD0 (0x4 << 3)
36 #define ET0_GTX_CLK_A (0x4 << 6)
37 #define ET0_ETXD1_A (0x4 << 9)
38 #define ET0_ETXD2_A (0x4 << 12)
39 #define ET0_ETXD3_A (0x4 << 15)
40 #define ET0_ETXD4 (0x3 << 18)
41 #define ET0_ETXD5_A (0x5 << 21)
42 #define ET0_ETXD6_A (0x5 << 24)
43 #define ET0_ETXD7 (0x4 << 27)
44 #define IPSR3_ETH_ENABLE \
45 (ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
46 ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
49 #define ET0_ERXD7 (0x4)
50 #define ET0_RX_DV (0x4 << 3)
51 #define ET0_RX_ER (0x4 << 6)
52 #define ET0_CRS (0x4 << 9)
53 #define ET0_COL (0x4 << 12)
54 #define ET0_MDC (0x4 << 15)
55 #define ET0_MDIO_A (0x3 << 18)
56 #define ET0_LINK_A (0x3 << 20)
57 #define ET0_PHY_INT_A (0x3 << 24)
59 #define IPSR4_ETH_ENABLE \
60 (ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
61 ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
64 #define ET0_ERXD0 (0x4 << 20)
65 #define ET0_ERXD1 (0x4 << 23)
66 #define ET0_ERXD2_A (0x3 << 26)
67 #define ET0_ERXD3_A (0x3 << 28)
68 #define IPSR8_ETH_ENABLE \
69 (ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
72 #define RX4_D (0x1 << 22)
73 #define TX4_D (0x1 << 23)
74 #define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
77 #define ET0_ERXD4 (0x4 << 4)
78 #define ET0_ERXD5 (0x4 << 7)
79 #define ET0_ERXD6 (0x3 << 10)
80 #define ET0_TX_EN (0x2 << 19)
81 #define ET0_TX_ER (0x2 << 21)
82 #define ET0_TX_CLK_A (0x4 << 23)
83 #define ET0_RX_CLK_A (0x3 << 26)
84 #define IPSR11_ETH_ENABLE \
85 (ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
86 ET0_TX_CLK_A | ET0_RX_CLK_A)
88 #define GPSR1_INIT (0xFFFF7FFF)
89 #define GPSR2_INIT (0x4005FEFF)
90 #define GPSR3_INIT (0x2EFFFFFF)
91 #define GPSR4_INIT (0xC7000000)
97 /* Set IPSR register */
99 data |= IPSR3_ETH_ENABLE;
104 data |= IPSR4_ETH_ENABLE;
109 data |= IPSR8_ETH_ENABLE;
113 data = readl(IPSR10);
114 data |= IPSR10_SCIF_ENABLE;
116 writel(data, IPSR10);
118 data = readl(IPSR11);
119 data |= IPSR11_ETH_ENABLE;
121 writel(data, IPSR11);
145 data = MODESEL2_INIT;
147 writel(data, MODESEL2);
149 #if defined(CONFIG_SH_ETHER)
150 u32 r = readl(MSTPSR1);
151 if (r & MSTPSR1_GETHER)
152 writel((r & ~MSTPSR1_GETHER), MSTPCR1);
157 int board_late_init(void)
159 printf("Cannot use I2C to get MAC address\n");