3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
5 * (C) Copyright 2001-2004
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <linux/byteorder/swab.h>
31 flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
33 /* Board support for 1 or 2 flash devices */
34 #define FLASH_PORT_WIDTH8
36 typedef unsigned char FLASH_PORT_WIDTH;
37 typedef volatile unsigned char FLASH_PORT_WIDTHV;
41 /* Intel-compatible flash ID */
42 #define INTEL_COMPAT 0x89
43 #define INTEL_ALT 0xB0
45 /* Intel-compatible flash commands */
46 #define INTEL_PROGRAM 0x10
47 #define INTEL_ERASE 0x20
48 #define INTEL_CLEAR 0x50
49 #define INTEL_LOCKBIT 0x60
50 #define INTEL_PROTECT 0x01
51 #define INTEL_STATUS 0x70
52 #define INTEL_READID 0x90
53 #define INTEL_CONFIRM 0xD0
54 #define INTEL_RESET 0xFF
56 /* Intel-compatible flash status bits */
57 #define INTEL_FINISHED 0x80
60 #define FPW FLASH_PORT_WIDTH
61 #define FPWV FLASH_PORT_WIDTHV
63 #define FLASH_CYCLE1 0x0555
64 #define FLASH_CYCLE2 0x02aa
68 /*-----------------------------------------------------------------------
71 static ulong flash_get_size (FPW * addr, flash_info_t * info);
72 static int write_data (flash_info_t * info, ulong dest, FPW data);
73 static int write_data_block (flash_info_t * info, ulong src, ulong dest);
74 static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
75 static void flash_get_offsets (ulong base, flash_info_t * info);
76 void inline spin_wheel (void);
78 /*-----------------------------------------------------------------------
81 unsigned long flash_init (void)
87 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
88 memset (&flash_info[i], 0, sizeof (flash_info_t));
92 flash_get_size ((FPW *) CFG_FLASH1_BASE,
94 flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]);
97 flash_get_size ((FPW *) CFG_FLASH1_BASE,
99 fsize = CFG_FLASH1_BASE + flash_info[i - 1].size;
100 flash_get_offsets (fsize, &flash_info[i]);
103 flash_get_size ((FPW *) CFG_FLASH0_BASE,
105 flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]);
108 flash_get_size ((FPW *) CFG_FLASH0_BASE,
110 fsize = CFG_FLASH0_BASE + flash_info[i - 1].size;
111 flash_get_offsets (fsize, &flash_info[i]);
114 panic ("configured to many flash banks!\n");
117 size += flash_info[i].size;
120 /* Protect monitor and environment sectors
122 #if defined (CFG_AMD_BOOT)
123 flash_protect (FLAG_PROTECT_SET,
125 CFG_MONITOR_BASE + monitor_flash_len - 1,
127 flash_protect (FLAG_PROTECT_SET,
129 CFG_INTEL_BASE + monitor_flash_len - 1,
132 flash_protect (FLAG_PROTECT_SET,
134 CFG_MONITOR_BASE + monitor_flash_len - 1,
136 flash_protect (FLAG_PROTECT_SET,
138 CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
141 flash_protect (FLAG_PROTECT_SET,
143 CFG_ENV1_ADDR + CFG_ENV1_SIZE - 1, &flash_info[1]);
144 flash_protect (FLAG_PROTECT_SET,
146 CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[3]);
151 /*-----------------------------------------------------------------------
153 static void flash_get_offsets (ulong base, flash_info_t * info)
157 if (info->flash_id == FLASH_UNKNOWN)
160 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
161 for (i = 0; i < info->sector_count; i++) {
162 info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
163 info->protect[i] = 0;
167 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
168 for (i = 0; i < info->sector_count; i++) {
169 info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
170 info->protect[i] = 0;
175 /*-----------------------------------------------------------------------
177 void flash_print_info (flash_info_t * info)
181 if (info->flash_id == FLASH_UNKNOWN) {
182 printf ("missing or unknown FLASH type\n");
186 switch (info->flash_id & FLASH_VENDMASK) {
187 case FLASH_MAN_INTEL:
194 printf ("Unknown Vendor ");
198 switch (info->flash_id & FLASH_TYPEMASK) {
199 case FLASH_28F128J3A:
200 printf ("28F128J3A\n");
204 printf ("AMD29F040B\n");
208 printf ("Unknown Chip Type\n");
212 printf (" Size: %ld MB in %d Sectors\n",
213 info->size >> 20, info->sector_count);
215 printf (" Sector Start Addresses:");
216 for (i = 0; i < info->sector_count; ++i) {
220 info->start[i], info->protect[i] ? " (RO)" : " ");
227 * The following code cannot be run from FLASH!
229 static ulong flash_get_size (FPW * addr, flash_info_t * info)
234 /* Write auto select command: read Manufacturer ID */
235 /* Write auto select command sequence and test FLASH answer */
236 addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
238 addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
240 addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
245 switch (addr[0] & 0xff) {
247 case (uchar) AMD_MANUFACT:
248 info->flash_id = FLASH_MAN_AMD;
252 case (uchar) INTEL_MANUFACT:
253 info->flash_id = FLASH_MAN_INTEL;
258 printf ("unknown\n");
259 info->flash_id = FLASH_UNKNOWN;
260 info->sector_count = 0;
262 addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
263 return (0); /* no or unknown flash */
268 case (FPW) INTEL_ID_28F128J3A:
269 info->flash_id += FLASH_28F128J3A;
270 info->sector_count = 64;
271 info->size = 0x00800000; /* => 16 MB */
274 case (FPW) AMD_ID_LV040B:
275 info->flash_id += FLASH_AM040;
277 info->sector_count = 7;
278 info->size = 0x00070000; /* => 448 KB */
281 /* for Environment settings */
282 info->sector_count = 1;
283 info->size = PHYS_AMD_SECT_SIZE; /* => 64 KB */
289 info->flash_id = FLASH_UNKNOWN;
293 if (info->sector_count > CFG_MAX_FLASH_SECT) {
294 printf ("** ERROR: sector count %d > max (%d) **\n",
295 info->sector_count, CFG_MAX_FLASH_SECT);
296 info->sector_count = CFG_MAX_FLASH_SECT;
299 if (value == (FPW) INTEL_ID_28F128J3A)
300 addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
302 addr[0] = (FPW) 0x00F000F0; /* restore read mode */
308 /*-----------------------------------------------------------------------
310 int flash_erase (flash_info_t * info, int s_first, int s_last)
312 int flag, prot, sect;
313 ulong type, start, last;
314 int rcode = 0, intel = 0;
316 if ((s_first < 0) || (s_first > s_last)) {
317 if (info->flash_id == FLASH_UNKNOWN)
318 printf ("- missing\n");
320 printf ("- no sectors to erase\n");
324 type = (info->flash_id & FLASH_VENDMASK);
325 if ((type != FLASH_MAN_INTEL)) {
326 type = (info->flash_id & FLASH_VENDMASK);
327 if ((type != FLASH_MAN_AMD)) {
328 printf ("Can't erase unknown flash type %08lx - aborted\n",
334 if (type == FLASH_MAN_INTEL)
338 for (sect = s_first; sect <= s_last; ++sect) {
339 if (info->protect[sect]) {
345 printf ("- Warning: %d protected sectors will not be erased!\n", prot);
350 start = get_timer (0);
353 /* Disable interrupts which might cause a timeout here */
354 flag = disable_interrupts ();
356 /* Start erase on unprotected sectors */
357 for (sect = s_first; sect <= s_last; sect++) {
358 if (info->protect[sect] == 0) { /* not protected */
359 FPWV *addr = (FPWV *) (info->start[sect]);
362 printf ("Erasing sector %2d ... ", sect);
364 /* arm simple, non interrupt dependent timer */
365 start = get_timer (0);
368 *addr = (FPW) 0x00500050; /* clear status register */
369 *addr = (FPW) 0x00200020; /* erase setup */
370 *addr = (FPW) 0x00D000D0; /* erase confirm */
372 FPWV *base; /* first address in bank */
374 base = (FPWV *) (CFG_AMD_BASE);
375 base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
376 base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
377 base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
378 base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
379 base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
380 *addr = (FPW) 0x00300030; /* erase sector */
384 *addr) & (FPW) 0x00800080) !=
386 if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
387 printf ("Timeout\n");
389 *addr = (FPW) 0x00B000B0; /* suspend erase */
390 *addr = (FPW) 0x00FF00FF; /* reset to read mode */
392 *addr = (FPW) 0x00F000F0; /* reset to read mode */
400 *addr = (FPW) 0x00500050; /* clear status register cmd. */
401 *addr = (FPW) 0x00FF00FF; /* resest to read mode */
403 *addr = (FPW) 0x00F000F0; /* reset to read mode */
411 /*-----------------------------------------------------------------------
412 * Copy memory to flash, returns:
415 * 2 - Flash not erased
416 * 4 - Flash not identified
419 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
421 if (info->flash_id == FLASH_UNKNOWN) {
425 switch (info->flash_id & FLASH_VENDMASK) {
428 FPW data = 0; /* 16 or 32 bit word, matches flash bus width */
429 int bytes; /* number of bytes to program in current word */
430 int left; /* number of bytes left to program */
433 for (left = cnt, res = 0;
434 left > 0 && res == 0;
435 addr += sizeof (data), left -=
436 sizeof (data) - bytes) {
438 bytes = addr & (sizeof (data) - 1);
439 addr &= ~(sizeof (data) - 1);
441 /* combine source and destination data so can program
442 * an entire word of 16 or 32 bits
444 for (i = 0; i < sizeof (data); i++) {
446 if (i < bytes || i - bytes >= left)
447 data += *((uchar *) addr + i);
452 res = write_word_amd (info, (FPWV *) addr,
456 } /* case FLASH_MAN_AMD */
458 case FLASH_MAN_INTEL:
462 int count, i, l, rc, port_width;
464 /* get lower word aligned address */
469 * handle unaligned start bytes
471 if ((l = addr - wp) != 0) {
473 for (i = 0, cp = wp; i < l; ++i, ++cp) {
474 data = (data << 8) | (*(uchar *) cp);
477 for (; i < port_width && cnt > 0; ++i) {
478 data = (data << 8) | *src++;
483 for (; cnt == 0 && i < port_width; ++i, ++cp)
484 data = (data << 8) | (*(uchar *) cp);
487 write_data (info, wp, SWAP (data))) != 0)
492 if (cnt > WR_BLOCK) {
494 * handle word aligned part
497 while (cnt >= WR_BLOCK) {
500 write_data_block (info,
509 if (count++ > 0x800) {
516 if (cnt < WR_BLOCK) {
518 * handle word aligned part
521 while (cnt >= port_width) {
523 for (i = 0; i < port_width; ++i)
524 data = (data << 8) | *src++;
527 write_data (info, wp,
533 if (count++ > 0x800) {
544 * handle unaligned tail bytes
547 for (i = 0, cp = wp; i < port_width && cnt > 0;
549 data = (data << 8) | *src++;
553 for (; i < port_width; ++i, ++cp)
554 data = (data << 8) | (*(uchar *) cp);
556 return (write_data (info, wp, SWAP (data)));
557 } /* case FLASH_MAN_INTEL */
563 /*-----------------------------------------------------------------------
564 * Write a word or halfword to Flash, returns:
567 * 2 - Flash not erased
569 static int write_data (flash_info_t * info, ulong dest, FPW data)
571 FPWV *addr = (FPWV *) dest;
575 /* Check if Flash is (sufficiently) erased */
576 if ((*addr & data) != data) {
577 printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
580 /* Disable interrupts which might cause a timeout here */
581 flag = disable_interrupts ();
583 *addr = (FPW) 0x00400040; /* write setup */
586 /* arm simple, non interrupt dependent timer */
587 start = get_timer (0);
589 /* wait while polling the status register */
590 while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
591 if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
592 *addr = (FPW) 0x00FF00FF; /* restore read mode */
597 *addr = (FPW) 0x00FF00FF; /* restore read mode */
602 /*-----------------------------------------------------------------------
603 * Write a word or halfword to Flash, returns:
606 * 2 - Flash not erased
608 static int write_data_block (flash_info_t * info, ulong src, ulong dest)
610 FPWV *srcaddr = (FPWV *) src;
611 FPWV *dstaddr = (FPWV *) dest;
615 /* Check if Flash is (sufficiently) erased */
616 for (i = 0; i < WR_BLOCK; i++)
617 if ((*dstaddr++ & 0xff) != 0xff) {
618 printf ("not erased at %08lx (%lx)\n",
619 (ulong) dstaddr, *dstaddr);
623 dstaddr = (FPWV *) dest;
625 /* Disable interrupts which might cause a timeout here */
626 flag = disable_interrupts ();
628 *dstaddr = (FPW) 0x00e800e8; /* write block setup */
630 /* arm simple, non interrupt dependent timer */
631 start = get_timer (0);
633 /* wait while polling the status register */
634 while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
635 if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
636 *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
641 *dstaddr = (FPW) 0x001f001f; /* write 32 to buffer */
642 for (i = 0; i < WR_BLOCK; i++)
643 *dstaddr++ = *srcaddr++;
646 *dstaddr = (FPW) 0x00d000d0; /* write 32 to buffer */
648 /* arm simple, non interrupt dependent timer */
649 start = get_timer (0);
651 /* wait while polling the status register */
652 while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
653 if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
654 *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
659 *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
664 /*-----------------------------------------------------------------------
665 * Write a word to Flash for AMD FLASH
666 * A word is 16 or 32 bits, whichever the bus width of the flash bank
667 * (not an individual chip) is.
672 * 2 - Flash not erased
674 static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
678 int res = 0; /* result, assume success */
679 FPWV *base; /* first address in flash bank */
681 /* Check if Flash is (sufficiently) erased */
682 if ((*dest & data) != data) {
686 base = (FPWV *) (CFG_AMD_BASE);
688 /* Disable interrupts which might cause a timeout here */
689 flag = disable_interrupts ();
691 base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
692 base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
693 base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
695 *dest = data; /* start programming the data */
697 /* re-enable interrupts if necessary */
699 enable_interrupts ();
701 start = get_timer (0);
703 /* data polling for D7 */
705 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
706 if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
707 *dest = (FPW) 0x00F000F0; /* reset bank */
715 void inline spin_wheel (void)
718 static char w[] = "\\/-";
720 printf ("\010%c", w[p]);
721 (++p == 3) ? (p = 0) : 0;
724 /*-----------------------------------------------------------------------
725 * Set/Clear sector's lock bit, returns:
727 * 1 - Error (timeout, voltage problems, etc.)
729 int flash_real_protect (flash_info_t * info, long sector, int prot)
734 FPWV *addr = (FPWV *) (info->start[sector]);
735 int flag = disable_interrupts ();
738 * 29F040B AMD flash does not support software protection/unprotection,
739 * the only way to protect the AMD flash is marked it as prot bit.
740 * This flash only support hardware protection, by supply or not supply
743 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
744 info->protect[sector] = prot;
749 *addr = INTEL_CLEAR; /* Clear status register */
750 if (prot) { /* Set sector lock bit */
751 *addr = INTEL_LOCKBIT; /* Sector lock bit */
752 *addr = INTEL_PROTECT; /* set */
753 } else { /* Clear sector lock bit */
754 *addr = INTEL_LOCKBIT; /* All sectors lock bits */
755 *addr = INTEL_CONFIRM; /* clear */
758 start = get_timer (0);
760 while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
761 if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
762 printf ("Flash lock bit operation timed out\n");
768 if (*addr != INTEL_OK) {
769 printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
770 (uint) addr, (uint) * addr);
775 info->protect[sector] = prot;
778 * Clear lock bit command clears all sectors lock bits, so
779 * we have to restore lock bits of protected sectors.
782 for (i = 0; i < info->sector_count; i++) {
783 if (info->protect[i]) {
784 start = get_timer (0);
785 addr = (FPWV *) (info->start[i]);
786 *addr = INTEL_LOCKBIT; /* Sector lock bit */
787 *addr = INTEL_PROTECT; /* set */
788 while ((*addr & INTEL_FINISHED) !=
790 if (get_timer (start) >
791 CFG_FLASH_UNLOCK_TOUT) {
792 printf ("Flash lock bit operation timed out\n");
802 enable_interrupts ();
804 *addr = INTEL_RESET; /* Reset to read array mode */