board/advantech/imx8qm_rom7720_a1/spl.c

   1 // SPDX-License-Identifier:     GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <dm.h>
   7 #include <image.h>
   8 #include <init.h>
   9 #include <spl.h>
  10 #include <fsl_esdhc.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sci/sci.h>
  16 #include <asm/arch/imx8-pins.h>
  17 #include <asm/arch/iomux.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define ESDHC_PAD_CTRL  ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  22                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  23                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  24                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  25
  26 #define ESDHC_CLK_PAD_CTRL      ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  27                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  28                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  29                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  30
  31 #define ENET_INPUT_PAD_CTRL     ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
  32                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  33                 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  34                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  35
  36 #define ENET_NORMAL_PAD_CTRL    ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  37                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  38                 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  39                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  40
  41 #define FSPI_PAD_CTRL   ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  42                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  43                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  44                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  45
  46 #define GPIO_PAD_CTRL   ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  47                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  48                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  49                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  50
  51 #define I2C_PAD_CTRL    ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  52                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  53                 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
  54                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  55
  56 #define UART_PAD_CTRL   ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  57                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  58                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  59                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  60 #ifdef CONFIG_FSL_ESDHC
  61
  62 #define USDHC1_CD_GPIO  IMX_GPIO_NR(5, 22)
  63 #define USDHC2_CD_GPIO  IMX_GPIO_NR(4, 12)
  64
  65 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  66         {USDHC1_BASE_ADDR, 0, 8},
  67         {USDHC2_BASE_ADDR, 0, 4},
  68         {USDHC3_BASE_ADDR, 0, 4},
  69 };
  70
  71 static iomux_cfg_t emmc0[] = {
  72         SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
  73         SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  74         SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  75         SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  76         SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  77         SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  78         SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  79         SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  80         SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  81         SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  82         SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  83         SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  84 };
  85
  86 static iomux_cfg_t usdhc2_sd[] = {
  87         SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
  88         SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  89         SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  90         SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  91         SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  92         SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  93         SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  94         SC_P_USDHC2_WP   | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  95         SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  96 };
  97
  98 int board_mmc_init(bd_t *bis)
  99 {
 100         int i, ret;
 101
 102         /*
 103          * According to the board_mmc_init() the following map is done:
 104          * (U-Boot device node)    (Physical Port)
 105          * mmc0                    USDHC1
 106          * mmc1                    USDHC2
 107          * mmc2                    USDHC3
 108          */
 109         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 110                 switch (i) {
 111                 case 0:
 112                         ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
 113                         if (ret != SC_ERR_NONE)
 114                                 return ret;
 115
 116                         imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
 117                         init_clk_usdhc(0);
 118                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 119                         break;
 120                 case 1:
 121                         ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
 122                         if (ret != SC_ERR_NONE)
 123                                 return ret;
 124                         ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
 125                         if (ret != SC_ERR_NONE)
 126                                 return ret;
 127
 128                         imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
 129                         init_clk_usdhc(2);
 130                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 131                         gpio_request(USDHC2_CD_GPIO, "sd2_cd");
 132                         gpio_direction_input(USDHC2_CD_GPIO);
 133                         break;
 134                 default:
 135                         printf("Warning: you configured more USDHC controllers"
 136                                 "(%d) than supported by the board\n", i + 1);
 137                         return 0;
 138                 }
 139                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 140                 if (ret) {
 141                         printf("Warning: failed to initialize mmc dev %d\n", i);
 142                         return ret;
 143                 }
 144         }
 145
 146         return 0;
 147 }
 148
 149 int board_mmc_getcd(struct mmc *mmc)
 150 {
 151         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 152         int ret = 0;
 153
 154         switch (cfg->esdhc_base) {
 155         case USDHC1_BASE_ADDR:
 156                 ret = 1;
 157                 break;
 158         case USDHC2_BASE_ADDR:
 159                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 160                 break;
 161         case USDHC3_BASE_ADDR:
 162                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 163                 break;
 164         }
 165
 166         return ret;
 167 }
 168
 169 #endif /* CONFIG_FSL_ESDHC */
 170
 171 void spl_board_init(void)
 172 {
 173 #if defined(CONFIG_SPL_SPI_SUPPORT)
 174         if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
 175                 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
 176                         puts("Warning: failed to initialize FSPI0\n");
 177                 }
 178         }
 179 #endif
 180
 181         puts("Normal Boot\n");
 182 }
 183
 184 void spl_board_prepare_for_boot(void)
 185 {
 186 #if defined(CONFIG_SPL_SPI_SUPPORT)
 187         if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
 188                 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
 189                         puts("Warning: failed to turn off FSPI0\n");
 190                 }
 191         }
 192 #endif
 193 }
 194
 195 #ifdef CONFIG_SPL_LOAD_FIT
 196 int board_fit_config_name_match(const char *name)
 197 {
 198         /* Just empty function now - can't decide what to choose */
 199         debug("%s: %s\n", __func__, name);
 200
 201         return 0;
 202 }
 203 #endif
 204
 205 void board_init_f(ulong dummy)
 206 {
 207         /* Clear global data */
 208         memset((void *)gd, 0, sizeof(gd_t));
 209
 210         arch_cpu_init();
 211
 212         board_early_init_f();
 213
 214         timer_init();
 215
 216         preloader_console_init();
 217
 218         /* Clear the BSS. */
 219         memset(__bss_start, 0, __bss_end - __bss_start);
 220
 221         board_init_r(NULL, 0);
 222 }