board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  * Copyright 2022 Linaro
   5  */
   6
   7 #include <common.h>
   8 #include <dwc3-uboot.h>
   9 #include <efi.h>
  10 #include <efi_loader.h>
  11 #include <errno.h>
  12 #include <miiphy.h>
  13 #include <netdev.h>
  14 #include <spl.h>
  15 #include <usb.h>
  16 #include <asm/io.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm-generic/gpio.h>
  19 #include <asm/arch/imx8mp_pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/mach-imx/gpio.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/mach-imx/dma.h>
  25 #include <linux/delay.h>
  26 #include <linux/kernel.h>
  27 #include <power/pmic.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define WDOG_PAD_CTRL   (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
  32
  33 static const iomux_v3_cfg_t wdog_pads[] = {
  34         MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  35 };
  36
  37 #ifdef CONFIG_NAND_MXS
  38 static void setup_gpmi_nand(void)
  39 {
  40         init_nand_clk();
  41 }
  42 #endif
  43
  44 #if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
  45 struct efi_fw_image fw_images[] = {
  46 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
  47         {
  48                 .image_type_id = IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID,
  49                 .fw_name = u"IMX8MP-RSB3720-FIT",
  50                 .image_index = 1,
  51         },
  52 #elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
  53         {
  54                 .image_type_id = IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID,
  55                 .fw_name = u"IMX8MP-RSB3720-FIT",
  56                 .image_index = 1,
  57         },
  58 #endif
  59 };
  60
  61 struct efi_capsule_update_info update_info = {
  62         .dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1",
  63         .images = fw_images,
  64 };
  65
  66 u8 num_image_type_guids = ARRAY_SIZE(fw_images);
  67 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
  68
  69
  70 int board_early_init_f(void)
  71 {
  72         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  73
  74         imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  75
  76         set_wdog_reset(wdog);
  77
  78         init_uart_clk(2);
  79
  80         return 0;
  81 }
  82
  83 #ifdef CONFIG_OF_BOARD_SETUP
  84 int ft_board_setup(void *blob, struct bd_info *bd)
  85 {
  86         return 0;
  87 }
  88 #endif
  89
  90 #ifdef CONFIG_FEC_MXC
  91 #define FEC_RST_PAD IMX_GPIO_NR(4, 2)
  92 static const iomux_v3_cfg_t fec1_rst_pads[] = {
  93         MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  94 };
  95
  96 static void setup_iomux_fec(void)
  97 {
  98         imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  99                                          ARRAY_SIZE(fec1_rst_pads));
 100
 101         gpio_request(FEC_RST_PAD, "fec1_rst");
 102         gpio_direction_output(FEC_RST_PAD, 0);
 103         mdelay(15);
 104         gpio_direction_output(FEC_RST_PAD, 1);
 105         mdelay(100);
 106 }
 107
 108 static int setup_fec(void)
 109 {
 110         struct iomuxc_gpr_base_regs *gpr =
 111                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 112
 113         setup_iomux_fec();
 114
 115         /* Enable RGMII TX clk output */
 116         setbits_le32(&gpr->gpr[1], BIT(22));
 117
 118         return 0;
 119 }
 120 #endif /* CONFIG_FEC_MXC */
 121
 122 #ifdef CONFIG_DWC_ETH_QOS
 123 #define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
 124 static const iomux_v3_cfg_t eqos_rst_pads[] = {
 125         MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 126 };
 127
 128 static void setup_iomux_eqos(void)
 129 {
 130         imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
 131                                          ARRAY_SIZE(eqos_rst_pads));
 132
 133         gpio_request(EQOS_RST_PAD, "eqos_rst");
 134         gpio_direction_output(EQOS_RST_PAD, 0);
 135         mdelay(15);
 136         gpio_direction_output(EQOS_RST_PAD, 1);
 137         mdelay(100);
 138 }
 139
 140 static int setup_eqos(void)
 141 {
 142         struct iomuxc_gpr_base_regs *gpr =
 143                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 144
 145         setup_iomux_eqos();
 146
 147         /* set INTF as RGMII, enable RGMII TXC clock */
 148         clrsetbits_le32(&gpr->gpr[1],
 149                         IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
 150         setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
 151
 152         return set_clk_eqos(ENET_125MHZ);
 153 }
 154 #endif /* CONFIG_DWC_ETH_QOS */
 155
 156 int board_phy_config(struct phy_device *phydev)
 157 {
 158         if (IS_ENABLED(CONFIG_FEC_MXC) || IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
 159                 /* enable rgmii rxc skew and phy mode select to RGMII copper */
 160                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 161                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 162
 163                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
 164                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
 165                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 166                 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 167
 168                 if (phydev->drv->config)
 169                         phydev->drv->config(phydev);
 170         }
 171
 172         return 0;
 173 }
 174
 175 #define DISPMIX                         13
 176 #define MIPI                            15
 177
 178 #define WDOG_TRIG IMX_GPIO_NR(4, 20)
 179
 180 static iomux_v3_cfg_t wdt_trig[] = {
 181         MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 182 };
 183
 184 static void setup_iomux_wdt(void)
 185 {
 186         imx_iomux_v3_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig));
 187         gpio_request(WDOG_TRIG, "wdt_trig");
 188         gpio_direction_output(WDOG_TRIG, 1);
 189 }
 190
 191 int board_init(void)
 192 {
 193 #ifdef CONFIG_FEC_MXC
 194         setup_fec();
 195 #endif
 196
 197 #ifdef CONFIG_DWC_ETH_QOS
 198         /* clock, pin, gpr */
 199         setup_eqos();
 200 #endif
 201
 202 #ifdef CONFIG_NAND_MXS
 203         setup_gpmi_nand();
 204 #endif
 205
 206         setup_iomux_wdt();
 207
 208         return 0;
 209 }
 210
 211 int board_late_init(void)
 212 {
 213         if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
 214                 env_set("board_name", "RSB3720A1");
 215                 env_set("board_rev", "iMX8MP");
 216         }
 217
 218         return 0;
 219 }
 220
 221 #ifdef CONFIG_SPL_MMC_SUPPORT
 222 #define UBOOT_RAW_SECTOR_OFFSET 0x40
 223 unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
 224 {
 225         u32 boot_dev = spl_boot_device();
 226
 227         switch (boot_dev) {
 228         case BOOT_DEVICE_MMC2:
 229                 return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
 230         default:
 231                 return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
 232         }
 233 }
 234 #endif /* CONFIG_SPL_MMC_SUPPORT */