2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
11 * Copyright 2012 Stefan Roese <sr@denx.de>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
27 #include <linux/compiler.h>
28 #include <asm/processor.h>
32 #include "is46r16320d.h"
34 #include "mt46v16m16-75.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 #if !defined(CONFIG_SYS_RAMBOOT) && \
40 (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
41 static void sdram_start(int hi_addr)
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
44 long control = SDRAM_CONTROL | hi_addr_bit;
46 /* unlock mode register */
47 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
49 /* precharge all banks */
50 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
53 /* set mode register: extended mode */
54 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
56 /* set mode register: reset DLL */
57 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
60 /* precharge all banks */
61 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
64 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
66 /* set mode register */
67 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
69 /* normal operation */
70 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
73 * Wait a short while for the DLL to lock before accessing
81 * ATTENTION: Although partially referenced initdram does NOT make real use
82 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
83 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
85 phys_size_t initdram(int board_type)
90 #if !defined(CONFIG_SYS_RAMBOOT) && \
91 (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
94 /* setup SDRAM chip selects */
95 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
96 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
98 /* setup config registers */
99 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
100 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
104 out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
107 /* find RAM size using SDRAM CS0 only */
109 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
111 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
119 /* memory smaller than 1MB is impossible */
120 if (dramsize < (1 << 20))
123 /* set SDRAM CS0 size according to the amount of RAM found */
125 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
126 0x13 + __builtin_ffs(dramsize >> 20) - 1);
128 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
130 #else /* CONFIG_SYS_RAMBOOT */
132 /* retrieve size of memory connected to SDRAM CS0 */
133 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
134 if (dramsize >= 0x13)
135 dramsize = (1 << (dramsize - 0x13)) << 20;
139 /* retrieve size of memory connected to SDRAM CS1 */
140 dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
141 if (dramsize2 >= 0x13)
142 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
146 #endif /* CONFIG_SYS_RAMBOOT */
149 * On MPC5200B we need to set the special configuration delay in the
150 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
151 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
153 * "The SDelay should be written to a value of 0x00000004. It is
154 * required to account for changes caused by normal wafer processing
159 if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
160 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
162 return dramsize + dramsize2;
165 static void get_revisions(int *failsavelevel, int *digiboardversion,
168 struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
171 /* read digitalboard-version from TMR[2..4] */
173 val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
174 val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
175 val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
176 *digiboardversion = val;
179 * A4M2K only supports digiboardversion. No failsavelevel and
182 #if !defined(CONFIG_A4M2K)
184 * Figure out failsavelevel
187 *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
189 if (*digiboardversion == 0) {
190 *failsavelevel = 1; /* digiboard-version ok */
192 /* read fpga-version from TMR[5..7] */
194 val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
195 val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
196 val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
199 if (*fpgaversion == 1)
200 *failsavelevel = 2; /* fpga-version ok */
206 * This function is called from the SPL U-Boot version for
207 * early init stuff, that needs to be done for OS (e.g. Linux)
208 * booting. Doing it later in the real U-Boot would not work
209 * in case that the SPL U-Boot boots Linux directly.
211 void spl_board_init(void)
213 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
214 struct mpc5xxx_mmap_ctl *mm =
215 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
217 #if defined(CONFIG_A4M2K)
218 /* enable CS3 and CS5 (FPGA) */
219 setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
221 int digiboardversion;
226 get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
228 val = in_be32(&mm->ipbi_ws_ctrl);
230 /* first clear bits 19..21 (CS3...5) */
231 val &= ~((1 << 19) | (1 << 20) | (1 << 21));
232 if (failsavelevel == 2) {
234 val |= (1 << 19) | (1 << 21);
237 if (failsavelevel >= 1) {
238 /* at least digiboard-version ok */
242 /* And write new value back to register */
243 out_be32(&mm->ipbi_ws_ctrl, val);
247 * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG)
248 * as all 3 config versions (failsave level) have the same setup.
252 * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
255 * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
256 * set bit 0(msb) to 1
258 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
260 #if defined(CONFIG_A4M2K)
261 /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
263 /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
264 gpio->simple_ddr |= 1 << (31 - 15);
265 gpio->simple_ddr |= 1 << (31 - 14);
266 gpio->simple_ddr |= 1 << (31 - 13);
267 gpio->simple_ddr |= 1 << (31 - 12);
269 /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
270 gpio->simple_gpioe |= 1 << (31 - 15);
271 gpio->simple_gpioe |= 1 << (31 - 14);
272 gpio->simple_gpioe |= 1 << (31 - 13);
273 gpio->simple_gpioe |= 1 << (31 - 12);
275 /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
277 /* set PSC2[0..2] (STSLED[0..2]) direction to output */
278 gpio->simple_ddr |= 1 << (31 - 27);
279 gpio->simple_ddr |= 1 << (31 - 26);
280 gpio->simple_ddr |= 1 << (31 - 25);
282 /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
283 gpio->simple_gpioe |= 1 << (31 - 27);
284 gpio->simple_gpioe |= 1 << (31 - 26);
285 gpio->simple_gpioe |= 1 << (31 - 25);
287 /* Setup PSC6[2] as MRST2 self reset GPIO output */
289 /* set PSC6[2]/IRDA_TX (MRST2) direction to output */
290 gpio->simple_ddr |= 1 << (31 - 3);
292 /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
293 gpio->simple_ode |= 1 << (31 - 3);
295 /* set PSC6[2]/IRDA_TX (MRST2) output as default high */
296 gpio->simple_dvo |= 1 << (31 - 3);
298 /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
299 gpio->simple_gpioe |= 1 << (31 - 3);
301 /* Setup PSC6[3] as HARNSSCD harness code GPIO input */
303 /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
304 gpio->simple_ddr |= 0 << (31 - 2);
306 /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
307 gpio->simple_gpioe |= 1 << (31 - 2);
309 /* setup GPIOs for status-leds if needed - see ticket #57 */
310 if (failsavelevel > 0) {
311 /* digiboard-version is OK */
312 /* LED is LOW ACTIVE - so deactivate by set output to 1 */
313 gpio->simple_dvo |= 1 << (31 - 12);
314 gpio->simple_dvo |= 1 << (31 - 13);
315 /* set GPIO direction to output */
316 gpio->simple_ddr |= 1 << (31 - 12);
317 gpio->simple_ddr |= 1 << (31 - 13);
318 /* open drain config is set to "normal output" at reset */
319 /* gpio->simple_ode &=~ ( 1 << (31-12) ); */
320 /* gpio->simple_ode &=~ ( 1 << (31-13) ); */
322 gpio->simple_gpioe |= 1 << (31 - 12);
323 gpio->simple_gpioe |= 1 << (31 - 13);
326 /* setup fpga irq - see ticket #65 */
327 if (failsavelevel > 1) {
329 * The main irq initialisation is done in interrupts.c
332 struct mpc5xxx_intr *intr =
333 (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
335 setbits_be32(&intr->ctrl, 0x08C01801);
338 * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
339 * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
347 int digiboardversion;
351 get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
354 puts("Board: A4M2K\n");
355 printf(" digiboard IO version %u\n", digiboardversion);
357 puts("Board: A3M071\n");
358 printf("Rev: failsave level %u\n", failsavelevel);
359 printf(" digiboard IO version %u\n", digiboardversion);
360 if (failsavelevel > 0) /* only if fpga-version red */
361 printf(" fpga IO version %u\n", fpgaversion);
367 /* miscellaneous platform dependent initialisations */
368 int misc_init_r(void)
370 /* adjust flash start and offset to detected values */
371 gd->bd->bi_flashstart = flash_info[0].start[0];
372 gd->bd->bi_flashoffset = 0;
375 out_be32((void *)MPC5XXX_BOOTCS_START,
376 START_REG(gd->bd->bi_flashstart));
377 out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
378 out_be32((void *)MPC5XXX_BOOTCS_STOP,
379 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
380 out_be32((void *)MPC5XXX_CS0_STOP,
381 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
386 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
387 void ft_board_setup(void *blob, bd_t * bd)
389 ft_cpu_setup(blob, bd);
391 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
393 #ifdef CONFIG_SPL_OS_BOOT
395 * A3M071 specific implementation of spl_start_uboot()
398 * 0 if booting into OS is selected (default)
399 * 1 if booting into U-Boot is selected
401 int spl_start_uboot(void)
406 getenv_f("boot_os", s, sizeof(s));
407 if ((s != NULL) && (strcmp(s, "yes") == 0))
414 #if defined(CONFIG_HW_WATCHDOG)
415 static int watchdog_toggle;
417 void hw_watchdog_reset(void)
422 * Check if watchdog is enabled via user command
424 if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
425 /* Set direction to output */
426 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
429 * Toggle watchdog output
431 val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
432 CONFIG_WDOG_GPIO_PIN);
434 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
435 CONFIG_WDOG_GPIO_PIN);
437 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
438 CONFIG_WDOG_GPIO_PIN);
443 int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
448 if (strncmp(argv[1], "on", 2) == 0)
450 else if (strncmp(argv[1], "off", 3) == 0)
457 printf("Usage: wdogtoggle %s\n", cmdtp->usage);
462 wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
463 "toggle GPIO pin to service watchdog",
464 "[on/off] - Switch watchdog toggling via GPIO pin on/off"