board/Synology/ds109/ds109.c

   1 /*
   2  * Copyright (C) 2009-2012
   3  * Wojciech Dubowik <wojciech.dubowik@neratec.com>
   4  * Luka Perkov <luka@openwrt.org>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <miiphy.h>
  11 #include <asm/setup.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/soc.h>
  14 #include <asm/arch/mpp.h>
  15 #include "ds109.h"
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 int board_early_init_f(void)
  20 {
  21         /*
  22          * default gpio configuration
  23          * There are maximum 64 gpios controlled through 2 sets of registers
  24          * the below configuration configures mainly initial LED status
  25          */
  26         mvebu_config_gpio(DS109_OE_VAL_LOW,
  27                           DS109_OE_VAL_HIGH,
  28                           DS109_OE_LOW, DS109_OE_HIGH);
  29
  30         /* Multi-Purpose Pins Functionality configuration */
  31         static const u32 kwmpp_config[] = {
  32                 MPP0_SPI_SCn,           /* SPI Flash */
  33                 MPP1_SPI_MOSI,
  34                 MPP2_SPI_SCK,
  35                 MPP3_SPI_MISO,
  36                 MPP4_GPIO,
  37                 MPP5_GPO,
  38                 MPP6_SYSRST_OUTn,       /* Reset signal */
  39                 MPP7_GPO,
  40                 MPP8_TW_SDA,            /* I2C */
  41                 MPP9_TW_SCK,            /* I2C */
  42                 MPP10_UART0_TXD,
  43                 MPP11_UART0_RXD,
  44                 MPP12_GPO,
  45                 MPP13_UART1_TXD,
  46                 MPP14_UART1_RXD,
  47                 MPP15_GPIO,
  48                 MPP16_GPIO,
  49                 MPP17_GPIO,
  50                 MPP18_GPO,
  51                 MPP19_GPO,
  52                 MPP20_SATA1_ACTn,
  53                 MPP21_SATA0_ACTn,
  54                 MPP22_GPIO,             /* HDD2 FAIL LED */
  55                 MPP23_GPIO,             /* HDD1 FAIL LED */
  56                 MPP24_GPIO,
  57                 MPP25_GPIO,
  58                 MPP26_GPIO,
  59                 MPP27_GPIO,
  60                 MPP28_GPIO,
  61                 MPP29_GPIO,
  62                 MPP30_GPIO,
  63                 MPP31_GPIO,             /* HDD2 */
  64                 MPP32_GPIO,             /* FAN A */
  65                 MPP33_GPIO,             /* FAN B */
  66                 MPP34_GPIO,             /* FAN C */
  67                 MPP35_GPIO,             /* FAN SENSE */
  68                 MPP36_GPIO,
  69                 MPP37_GPIO,
  70                 MPP38_GPIO,
  71                 MPP39_GPIO,
  72                 MPP40_GPIO,
  73                 MPP41_GPIO,
  74                 MPP42_GPIO,
  75                 MPP43_GPIO,
  76                 MPP44_GPIO,
  77                 MPP45_GPIO,
  78                 MPP46_GPIO,
  79                 MPP47_GPIO,
  80                 MPP48_GPIO,
  81                 MPP49_GPIO,
  82                 0
  83         };
  84         kirkwood_mpp_conf(kwmpp_config, NULL);
  85         return 0;
  86 }
  87
  88 int board_init(void)
  89 {
  90         /* address of boot parameters */
  91         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  92
  93         return 0;
  94 }
  95
  96 /* Synology reset uses UART */
  97 #include <ns16550.h>
  98 #define SOFTWARE_SHUTDOWN   0x31
  99 #define SOFTWARE_REBOOT     0x43
 100 #define CONFIG_SYS_NS16550_COM2         KW_UART1_BASE
 101 void reset_misc(void)
 102 {
 103         int b_d;
 104         printf("Synology reset...");
 105         udelay(50000);
 106
 107         b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
 108                 CONFIG_SYS_NS16550_CLK, 9600);
 109         NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
 110         NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
 111 }
 112
 113 /* Support old kernels */
 114 void setup_board_tags(struct tag **in_params)
 115 {
 116         unsigned int boardId;
 117         struct tag *params;
 118         struct tag_mv_uboot *t;
 119         int i;
 120
 121         printf("Synology board tags...");
 122         params = *in_params;
 123         t = (struct tag_mv_uboot *)&params->u;
 124
 125         t->uboot_version = VER_NUM;
 126
 127         boardId = SYNO_DS109_ID;
 128         t->uboot_version |= boardId;
 129
 130         t->tclk = CONFIG_SYS_TCLK;
 131         t->sysclk = CONFIG_SYS_TCLK*2;
 132
 133         t->isusbhost = 1;
 134         for (i = 0; i < 4; i++) {
 135                 memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
 136                 t->mtu[i] = 0;
 137         }
 138
 139         params->hdr.tag = ATAG_MV_UBOOT;
 140         params->hdr.size = tag_size(tag_mv_uboot);
 141         params = tag_next(params);
 142         *in_params = params;
 143 }
 144
 145 #ifdef CONFIG_RESET_PHY_R
 146 /* Configure and enable MV88E1116 PHY */
 147 void reset_phy(void)
 148 {
 149         u16 reg;
 150         u16 devadr;
 151         char *name = "egiga0";
 152
 153         if (miiphy_set_current_dev(name))
 154                 return;
 155
 156         /* command to read PHY dev address */
 157         if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
 158                 printf("Error: 88E1116 could not read PHY dev address\n");
 159                 return;
 160         }
 161
 162         /*
 163          * Enable RGMII delay on Tx and Rx for CPU port
 164          * Ref: sec 4.7.2 of chip datasheet
 165          */
 166         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 167         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 168         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 169         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 170         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 171
 172         /* reset the phy */
 173         miiphy_reset(name, devadr);
 174
 175         printf("88E1116 Initialized on %s\n", name);
 176 }
 177 #endif /* CONFIG_RESET_PHY_R */