1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
5 * Based on sheevaplug.c originally written by
6 * Prafulla Wadaskar <prafulla@marvell.com>
8 * Marvell Semiconductor <www.marvell.com>
14 #include <asm/mach-types.h>
15 #include <asm/arch/soc.h>
16 #include <asm/arch/mpp.h>
17 #include <asm/arch/cpu.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 int board_early_init_f(void)
25 * default gpio configuration
27 mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
28 NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
30 /* Multi-Purpose Pins Functionality configuration */
31 static const u32 kwmpp_config[] = {
70 kirkwood_mpp_conf(kwmpp_config, NULL);
77 * arch number of board
79 gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
81 /* adress of boot parameters */
82 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
87 #ifdef CONFIG_RESET_PHY_R
88 /* Configure and enable MV88E1116 PHY */
93 char *name = "egiga0";
95 if (miiphy_set_current_dev(name))
98 /* command to read PHY dev address */
99 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
100 printf("Err..%s could not read PHY dev address\n", __func__);
105 * Enable RGMII delay on Tx and Rx for CPU port
106 * Ref: sec 4.7.2 of chip datasheet
108 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
109 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
110 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
111 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
112 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
115 miiphy_reset(name, devadr);
117 printf("88E1116 Initialized on %s\n", name);
119 #endif /* CONFIG_RESET_PHY_R */