3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <asm/arch/mpp.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 int board_early_init_f(void)
22 * default gpio configuration
23 * There are maximum 64 gpios controlled through 2 sets of registers
24 * the below configuration configures mainly initial LED status
26 mvebu_config_gpio(RD6281A_OE_VAL_LOW,
28 RD6281A_OE_LOW, RD6281A_OE_HIGH);
30 /* Multi-Purpose Pins Functionality configuration */
31 static const u32 kwmpp_config[] = {
84 kirkwood_mpp_conf(kwmpp_config, NULL);
91 * arch number of board
93 gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
95 /* adress of boot parameters */
96 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
101 void mv_phy_88e1116_init(char *name)
106 if (miiphy_set_current_dev(name))
109 /* command to read PHY dev address */
110 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
111 printf("Err..%s could not read PHY dev address\n",
117 * Enable RGMII delay on Tx and Rx for CPU port
118 * Ref: sec 4.7.2 of chip datasheet
120 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
121 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
122 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
123 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
124 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
127 if (miiphy_read (name, devadr, MII_BMCR, ®) != 0) {
128 printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
131 if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
132 printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
136 printf("88E1116 Initialized on %s\n", name);
139 /* Configure and enable Switch and PHY */
142 /* configure and initialize switch */
143 struct mv88e61xx_config swcfg = {
145 .vlancfg = MV88E61XX_VLANCFG_ROUTER,
146 .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
147 .led_init = MV88E61XX_LED_INIT_EN,
148 .portstate = MV88E61XX_PORTSTT_FORWARDING,
150 .ports_enabled = 0x3f,
153 mv88e61xx_switch_initialize(&swcfg);
155 /* configure and initialize PHY */
156 mv_phy_88e1116_init("egiga1");