board/Marvell/octeon_ebb7304/board_ddr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2020 Marvell International Ltd.
   4  *
   5  * https://spdx.org/licenses
   6  */
   7
   8 #ifndef __BOARD_DDR_H__
   9 #define __BOARD_DDR_H__
  10
  11 #define OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION0                       \
  12         { {0x1050, 0x0}, {NULL, NULL} }, { {0x1051, 0x0}, {NULL, NULL} }
  13 #define OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION1                       \
  14         { {0x1052, 0x0}, {NULL, NULL} }, { {0x1053, 0x0}, {NULL, NULL} }
  15
  16 #define OCTEON_EBB7304_BOARD_EEPROM_TWSI_ADDR   0x56
  17
  18 /*
  19  * Local copy of these parameters to allow for customization for this
  20  * board design.  The generic version resides in lib_octeon_shared.h.
  21  */
  22
  23 /* LMC0_MODEREG_PARAMS1 */
  24 #define OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_1SLOT              \
  25         {                                                       \
  26                 .cn78xx = {                                     \
  27                         .pasr_00        = 0,                    \
  28                         .asr_00         = 0,                    \
  29                         .srt_00         = 0,                    \
  30                         .rtt_wr_00      = ddr4_rttwr_80ohm & 3, \
  31                         .rtt_wr_00_ext  = (ddr4_rttwr_80ohm >> 2) & 1,  \
  32                         .dic_00         = ddr4_dic_34ohm,       \
  33                         .rtt_nom_00     = 0,                    \
  34                         .pasr_01        = 0,                    \
  35                         .asr_01         = 0,                    \
  36                         .srt_01         = 0,                    \
  37                         .rtt_wr_01      = 0,                    \
  38                         .dic_01         = ddr4_dic_34ohm,       \
  39                         .rtt_nom_01     = 0,                    \
  40                         .pasr_10        = 0,                    \
  41                         .asr_10         = 0,                    \
  42                         .srt_10         = 0,                    \
  43                         .rtt_wr_10      = 0,                    \
  44                         .dic_10         = ddr4_dic_34ohm,       \
  45                         .rtt_nom_10     = 0,                    \
  46                         .pasr_11        = 0,                    \
  47                         .asr_11         = 0,                    \
  48                         .srt_11         = 0,                    \
  49                         .rtt_wr_11      = 0,                    \
  50                         .dic_11         = ddr4_dic_34ohm,       \
  51                         .rtt_nom_11     = 0,                    \
  52                 }                                               \
  53         }
  54
  55 #define OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_2SLOT      \
  56         {                                                       \
  57                 .cn78xx = {                                     \
  58                         .pasr_00        = 0,                    \
  59                         .asr_00         = 0,                    \
  60                         .srt_00         = 0,                    \
  61                         .rtt_wr_00      = ddr4_rttwr_80ohm & 3, \
  62                         .rtt_wr_00_ext  = (ddr4_rttwr_80ohm >> 2) & 1,  \
  63                         .dic_00         = ddr4_dic_34ohm,       \
  64                         .rtt_nom_00     = 0,                    \
  65                         .pasr_01        = 0,                    \
  66                         .asr_01         = 0,                    \
  67                         .srt_01         = 0,                    \
  68                         .rtt_wr_01      = 0,                    \
  69                         .dic_01         = ddr4_dic_34ohm,       \
  70                         .rtt_nom_01     = 0,                    \
  71                         .pasr_10        = 0,                    \
  72                         .asr_10         = 0,                    \
  73                         .srt_10         = 0,                    \
  74                         .rtt_wr_10      = ddr4_rttwr_80ohm & 3, \
  75                         .rtt_wr_10_ext  = (ddr4_rttwr_80ohm >> 2) & 1,  \
  76                         .dic_10         = ddr4_dic_34ohm,       \
  77                         .rtt_nom_10     = 0,                    \
  78                         .pasr_11        = 0,                    \
  79                         .asr_11         = 0,                    \
  80                         .srt_11         = 0,                    \
  81                         .rtt_wr_11      = 0,                    \
  82                         .dic_11         = ddr4_dic_34ohm,       \
  83                         .rtt_nom_11     = 0                     \
  84                 }                                               \
  85         }
  86
  87 #define OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_1SLOT              \
  88         {                                                       \
  89                 .cn78xx = {                                     \
  90                         .pasr_00        = 0,                    \
  91                         .asr_00         = 0,                    \
  92                         .srt_00         = 0,                    \
  93                         .rtt_wr_00      = ddr4_rttwr_240ohm,    \
  94                         .dic_00         = ddr4_dic_34ohm,       \
  95                         .rtt_nom_00     = 0,                    \
  96                         .pasr_01        = 0,                    \
  97                         .asr_01         = 0,                    \
  98                         .srt_01         = 0,                    \
  99                         .rtt_wr_01      = ddr4_rttwr_240ohm,    \
 100                         .dic_01         = ddr4_dic_34ohm,       \
 101                         .rtt_nom_01     = 0,                    \
 102                         .pasr_10        = 0,                    \
 103                         .asr_10         = 0,                    \
 104                         .srt_10         = 0,                    \
 105                         .dic_10         = ddr4_dic_34ohm,       \
 106                         .rtt_nom_10     = 0,                    \
 107                         .pasr_11        = 0,                    \
 108                         .asr_11         = 0,                    \
 109                         .srt_11         = 0,                    \
 110                         .rtt_wr_11      = 0,                    \
 111                         .dic_11         = ddr4_dic_34ohm,       \
 112                         .rtt_nom_11     = 0,                    \
 113                 }                                               \
 114         }
 115
 116 #define OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_2SLOT              \
 117         {                                                       \
 118                 .cn78xx = {                                     \
 119                         .pasr_00        = 0,                    \
 120                         .asr_00         = 0,                    \
 121                         .srt_00         = 0,                    \
 122                         .rtt_wr_00      = ddr4_rttwr_240ohm,    \
 123                         .dic_00         = ddr4_dic_34ohm,       \
 124                         .rtt_nom_00     = ddr4_rttnom_120ohm,   \
 125                         .pasr_01        = 0,                    \
 126                         .asr_01         = 0,                    \
 127                         .srt_01         = 0,                    \
 128                         .rtt_wr_01      = ddr4_rttwr_240ohm,    \
 129                         .dic_01         = ddr4_dic_34ohm,       \
 130                         .rtt_nom_01     = ddr4_rttnom_120ohm,   \
 131                         .pasr_10        = 0,                    \
 132                         .asr_10         = 0,                    \
 133                         .srt_10         = 0,                    \
 134                         .rtt_wr_10      = ddr4_rttwr_240ohm,    \
 135                         .dic_10         = ddr4_dic_34ohm,       \
 136                         .rtt_nom_10     = ddr4_rttnom_120ohm,   \
 137                         .pasr_11        = 0,                    \
 138                         .asr_11         = 0,                    \
 139                         .srt_11         = 0,                    \
 140                         .rtt_wr_11      = ddr4_rttwr_240ohm,    \
 141                         .dic_11         = ddr4_dic_34ohm,       \
 142                         .rtt_nom_11     = ddr4_rttnom_120ohm,   \
 143                 }                                               \
 144         }
 145
 146 #define OCTEON_EBB7304_MODEREG_PARAMS1_4RANK_1SLOT              \
 147         {                                                       \
 148                 .cn78xx = {                                     \
 149                         .pasr_00        = 0,                    \
 150                         .asr_00         = 0,                    \
 151                         .srt_00         = 0,                    \
 152                         .rtt_wr_00      = rttwr_60ohm,          \
 153                         .dic_00         = dic_34ohm,            \
 154                         .rtt_nom_00     = rttnom_20ohm,         \
 155                         .pasr_01        = 0,                    \
 156                         .asr_01         = 0,                    \
 157                         .srt_01         = 0,                    \
 158                         .rtt_wr_01      = rttwr_60ohm,          \
 159                         .dic_01         = dic_34ohm,            \
 160                         .rtt_nom_01     = rttnom_none,          \
 161                         .pasr_10        = 0,                    \
 162                         .asr_10         = 0,                    \
 163                         .srt_10         = 0,                    \
 164                         .rtt_wr_10      = rttwr_60ohm,          \
 165                         .dic_10         = dic_34ohm,            \
 166                         .rtt_nom_10     = rttnom_20ohm,         \
 167                         .pasr_11        = 0,                    \
 168                         .asr_11         = 0,                    \
 169                         .srt_11         = 0,                    \
 170                         .rtt_wr_11      = rttwr_60ohm,          \
 171                         .dic_11         = dic_34ohm,            \
 172                         .rtt_nom_11     = rttnom_none,          \
 173                 }                                               \
 174         }
 175
 176 #define OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_1SLOT      \
 177 {                                                       \
 178         .cn78xx = {                                     \
 179                 .rtt_park_00    = ddr4_rttpark_60ohm,   \
 180                 .vref_value_00  = 0x22,                 \
 181                 .vref_range_00  = 0,                    \
 182                 .rtt_park_01    = 0,                    \
 183                 .vref_value_01  = 0,                    \
 184                 .vref_range_01  = 0,                    \
 185                 .rtt_park_10    = 0,                    \
 186                 .vref_value_10  = 0,                    \
 187                 .vref_range_10  = 0,                    \
 188                 .rtt_park_11    = 0,                    \
 189                 .vref_value_11  = 0,                    \
 190                 .vref_range_11  = 0                     \
 191         }                                               \
 192 }
 193
 194 /* FIX */
 195 #define OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_2SLOT      \
 196 {                                                       \
 197         .cn78xx = {                                     \
 198                 .rtt_park_00    = ddr4_rttpark_48ohm,   \
 199                 .vref_value_00  = 0x1f,                 \
 200                 .vref_range_00  = 0,                    \
 201                 .rtt_park_01    = 0,                    \
 202                 .vref_value_01  = 0,                    \
 203                 .vref_range_01  = 0,                    \
 204                 .rtt_park_10    = ddr4_rttpark_48ohm,   \
 205                 .vref_value_10  = 0x1f,                 \
 206                 .vref_range_10  = 0,                    \
 207                 .rtt_park_11    = 0,                    \
 208                 .vref_value_11  = 0,                    \
 209                 .vref_range_11  = 0                     \
 210         }                                               \
 211 }
 212
 213 #define OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_1SLOT      \
 214 {                                                       \
 215         .cn78xx = {                                     \
 216                 .rtt_park_00    = ddr4_rttpark_120ohm,  \
 217                 .vref_value_00  = 0x19,                 \
 218                 .vref_range_00  = 0,                    \
 219                 .rtt_park_01    = ddr4_rttpark_120ohm,  \
 220                 .vref_value_01  = 0x19,                 \
 221                 .vref_range_01  = 0,                    \
 222                 .rtt_park_10    = 0,                    \
 223                 .vref_value_10  = 0,                    \
 224                 .vref_range_10  = 0,                    \
 225                 .rtt_park_11    = 0,                    \
 226                 .vref_value_11  = 0,                    \
 227                 .vref_range_11  = 0                     \
 228         }                                               \
 229 }
 230
 231 #define OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_2SLOT      \
 232 {                                                       \
 233         .cn78xx = {                                     \
 234                 .rtt_park_00    = ddr4_rttpark_60ohm,   \
 235                 .vref_value_00  = 0x19,                 \
 236                 .vref_range_00  = 0,                    \
 237                 .rtt_park_01    = ddr4_rttpark_60ohm,   \
 238                 .vref_value_01  = 0x19,                 \
 239                 .vref_range_01  = 0,                    \
 240                 .rtt_park_10    = ddr4_rttpark_60ohm,   \
 241                 .vref_value_10  = 0x19,                 \
 242                 .vref_range_10  = 0,                    \
 243                 .rtt_park_11    = ddr4_rttpark_60ohm,   \
 244                 .vref_value_11  = 0x19,                 \
 245                 .vref_range_11  = 0                     \
 246         }                                               \
 247 }
 248
 249 #define OCTEON_EBB7304_MODEREG_PARAMS2_4RANK_1SLOT      \
 250 {                                                       \
 251         .cn78xx = {                                     \
 252                 .rtt_park_00    = ddr4_rttpark_80ohm,   \
 253                 .vref_value_00  = 0x1f,                 \
 254                 .vref_range_00  = 0,                    \
 255                 .rtt_park_01    = ddr4_rttpark_80ohm,   \
 256                 .vref_value_01  = 0x1f,                 \
 257                 .vref_range_01  = 0,                    \
 258                 .rtt_park_10    = 0,                    \
 259                 .vref_value_10  = 0,                    \
 260                 .vref_range_10  = 0,                    \
 261                 .rtt_park_11    = 0,                    \
 262                 .vref_value_11  = 0,                    \
 263                 .vref_range_11  = 0                     \
 264         }                                               \
 265 }
 266
 267 #define OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION              \
 268         /*   1 */                                                       \
 269         {                                                               \
 270                 ddr4_dqx_driver_34_ohm,                                 \
 271                 0x00000000ULL,                                          \
 272                 OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_1SLOT,             \
 273                 OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_1SLOT,             \
 274                 ddr4_rodt_ctl_48_ohm,                                   \
 275                 0x00000000ULL,                                          \
 276                 0                                                       \
 277         },                                                              \
 278         /*   2 */                                                       \
 279         {                                                               \
 280                 ddr4_dqx_driver_34_ohm,                                 \
 281                 0x00000000ULL,                                          \
 282                 OCTEON_EBB7304_MODEREG_PARAMS1_1RANK_2SLOT,             \
 283                 OCTEON_EBB7304_MODEREG_PARAMS2_1RANK_2SLOT,             \
 284                 ddr4_rodt_ctl_80_ohm,                                   \
 285                 0x00000000ULL,                                          \
 286                 0                                                       \
 287         }
 288
 289 #define OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION              \
 290         /*   1 */                                                       \
 291         {                                                               \
 292                 ddr4_dqx_driver_34_ohm,                                 \
 293                 0x00000000ULL,                                          \
 294                 OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_1SLOT,             \
 295                 OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_1SLOT,             \
 296                 ddr4_rodt_ctl_80_ohm,                                   \
 297                 0x00000000ULL,                                          \
 298                 0                                                       \
 299         },                                                              \
 300         /*   2 */                                                       \
 301         {                                                               \
 302                 ddr4_dqx_driver_34_ohm,                                 \
 303                 0x0c0c0303ULL,                                          \
 304                 OCTEON_EBB7304_MODEREG_PARAMS1_2RANK_2SLOT,             \
 305                 OCTEON_EBB7304_MODEREG_PARAMS2_2RANK_2SLOT,             \
 306                 ddr4_rodt_ctl_48_ohm,                                   \
 307                 0x04080102ULL,                                          \
 308                 0                                                       \
 309         }
 310
 311 #define OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION              \
 312         /*   1 */                                                       \
 313         {                                                               \
 314                 ddr4_dqx_driver_34_ohm,                                 \
 315                 0x01030203ULL,                                          \
 316                 OCTEON_EBB7304_MODEREG_PARAMS1_4RANK_1SLOT,             \
 317                 OCTEON_EBB7304_MODEREG_PARAMS2_4RANK_1SLOT,             \
 318                 ddr4_rodt_ctl_48_ohm,                                   \
 319                 0x01010202ULL,                                          \
 320                 0                                                       \
 321         }
 322
 323 /*
 324  * Construct a static initializer for the ddr_configuration_t variable that
 325  * holds (almost) all of the information required for DDR initialization.
 326  */
 327
 328 /*
 329  * The parameters below make up the custom_lmc_config data structure.
 330  * This structure is used to customize the way that the LMC DRAM
 331  * Controller is configured for a particular board design.
 332  *
 333  * Refer to the file lib_octeon_board_table_entry.h for a description
 334  * of the custom board settings.  It is usually kept in the following
 335  * location... arch/mips/include/asm/arch-octeon/
 336  *
 337  */
 338
 339 #define OCTEON_EBB7304_DDR_CONFIGURATION                                \
 340 /* Interface 0 */                                                       \
 341 {                                                                       \
 342         .custom_lmc_config = {                                          \
 343                 .min_rtt_nom_idx                = 1,                    \
 344                 .max_rtt_nom_idx                = 7,                    \
 345                 .min_rodt_ctl                   = 1,                    \
 346                 .max_rodt_ctl                   = 7,                    \
 347                 .ck_ctl                         = ddr4_driver_34_ohm,   \
 348                 .cmd_ctl                        = ddr4_driver_34_ohm,   \
 349                 .ctl_ctl                        = ddr4_driver_34_ohm,   \
 350                 .min_cas_latency                = 0,                    \
 351                 .offset_en                      = 1,                    \
 352                 .offset_udimm                   = 2,                    \
 353                 .offset_rdimm                   = 2,                    \
 354                 .ddr_rtt_nom_auto               = 0,                    \
 355                 .ddr_rodt_ctl_auto              = 0,                    \
 356                 .rlevel_comp_offset_udimm       = 0,                    \
 357                 .rlevel_comp_offset_rdimm       = 0,                    \
 358                 .rlevel_compute                 = 0,                    \
 359                 .ddr2t_udimm                    = 1,                    \
 360                 .ddr2t_rdimm                    = 1,                    \
 361                 .maximum_adjacent_rlevel_delay_increment = 2,           \
 362                 .fprch2                         = 2,                    \
 363                 .dll_write_offset               = NULL,                 \
 364                 .dll_read_offset                = NULL,                 \
 365                 .parity                         = 0                     \
 366         },                                                              \
 367         .dimm_config_table = {                                          \
 368                 OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION0,              \
 369                 DIMM_CONFIG_TERMINATOR                                  \
 370         },                                                              \
 371         .unbuffered = {                                                 \
 372                 .ddr_board_delay                = 0,                    \
 373                 .lmc_delay_clk                  = 0,                    \
 374                 .lmc_delay_cmd                  = 0,                    \
 375                 .lmc_delay_dq                   = 0                     \
 376         },                                                              \
 377         .registered = {                                                 \
 378                 .ddr_board_delay                = 0,                    \
 379                 .lmc_delay_clk                  = 0,                    \
 380                 .lmc_delay_cmd                  = 0,                    \
 381                 .lmc_delay_dq                   = 0                     \
 382         },                                                              \
 383         .odt_1rank_config = {                                           \
 384                 OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION      \
 385         },                                                              \
 386         .odt_2rank_config = {                                           \
 387                 OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION      \
 388         },                                                              \
 389         .odt_4rank_config = {                                           \
 390                 OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION      \
 391         }                                                               \
 392 },                                                                      \
 393 /* Interface 1 */                                                       \
 394 {                                                                       \
 395         .custom_lmc_config = {                                          \
 396                 .min_rtt_nom_idx                = 1,                    \
 397                 .max_rtt_nom_idx                = 7,                    \
 398                 .min_rodt_ctl                   = 1,                    \
 399                 .max_rodt_ctl                   = 7,                    \
 400                 .ck_ctl                         = ddr4_driver_34_ohm,   \
 401                 .cmd_ctl                        = ddr4_driver_34_ohm,   \
 402                 .ctl_ctl                        = ddr4_driver_34_ohm,   \
 403                 .min_cas_latency                = 0,                    \
 404                 .offset_en                      = 1,                    \
 405                 .offset_udimm                   = 2,                    \
 406                 .offset_rdimm                   = 2,                    \
 407                 .ddr_rtt_nom_auto               = 0,                    \
 408                 .ddr_rodt_ctl_auto              = 0,                    \
 409                 .rlevel_comp_offset_udimm       = 0,                    \
 410                 .rlevel_comp_offset_rdimm       = 0,                    \
 411                 .rlevel_compute                 = 0,                    \
 412                 .ddr2t_udimm                    = 1,                    \
 413                 .ddr2t_rdimm                    = 1,                    \
 414                 .maximum_adjacent_rlevel_delay_increment = 2,           \
 415                 .fprch2                         = 2,                    \
 416                 .dll_write_offset               = NULL,                 \
 417                 .dll_read_offset                = NULL,                 \
 418                 .parity                         = 0                     \
 419         },                                                              \
 420         .dimm_config_table = {                                          \
 421                 OCTEON_EBB7304_DRAM_SOCKET_CONFIGURATION1,              \
 422                 DIMM_CONFIG_TERMINATOR                                  \
 423         },                                                              \
 424         .unbuffered = {                                                 \
 425                 .ddr_board_delay                = 0,                    \
 426                 .lmc_delay_clk                  = 0,                    \
 427                 .lmc_delay_cmd                  = 0,                    \
 428                 .lmc_delay_dq                   = 0                     \
 429         },                                                              \
 430         .registered = {                                                 \
 431                 .ddr_board_delay                = 0,                    \
 432                 .lmc_delay_clk                  = 0,                    \
 433                 .lmc_delay_cmd                  = 0,                    \
 434                 .lmc_delay_dq                   = 0                     \
 435         },                                                              \
 436         .odt_1rank_config = {                                           \
 437                 OCTEON_EBB7304_CN78XX_DRAM_ODT_1RANK_CONFIGURATION      \
 438         },                                                              \
 439         .odt_2rank_config = {                                           \
 440                 OCTEON_EBB7304_CN78XX_DRAM_ODT_2RANK_CONFIGURATION      \
 441         },                                                              \
 442         .odt_4rank_config = {                                           \
 443                 OCTEON_EBB7304_CN78XX_DRAM_ODT_4RANK_CONFIGURATION      \
 444         }                                                               \
 445 },
 446
 447 #endif /* __BOARD_DDR_H__ */