1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
8 #include <dm/device-internal.h>
10 #include <env_internal.h>
16 #include <asm/global_data.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <linux/delay.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 /* IO expander I2C device */
25 #define I2C_IO_EXP_ADDR 0x22
26 #define I2C_IO_CFG_REG_0 0x6
27 #define I2C_IO_DATA_OUT_REG_0 0x2
28 #define I2C_IO_REG_0_SATA_OFF 2
29 #define I2C_IO_REG_0_USB_H_OFF 1
31 /* The pin control values are the same for DB and Espressobin */
32 #define PINCTRL_NB_REG_VALUE 0x000173fa
33 #define PINCTRL_SB_REG_VALUE 0x00007a23
35 /* Ethernet switch registers */
36 /* SMI addresses for multi-chip mode */
37 #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
38 #define MVEBU_SW_G2_SMI_ADDR (28)
41 #define MVEBU_SW_SMI_DATA_REG (1)
42 #define MVEBU_SW_SMI_CMD_REG (0)
43 #define SW_SMI_CMD_REG_ADDR_OFF 0
44 #define SW_SMI_CMD_DEV_ADDR_OFF 5
45 #define SW_SMI_CMD_SMI_OP_OFF 10
46 #define SW_SMI_CMD_SMI_MODE_OFF 12
47 #define SW_SMI_CMD_SMI_BUSY_OFF 15
49 /* Single-chip mode */
50 /* Switch Port Registers */
51 #define MVEBU_SW_LINK_CTRL_REG (1)
52 #define MVEBU_SW_PORT_CTRL_REG (4)
53 #define MVEBU_SW_PORT_BASE_VLAN (6)
55 /* Global 2 Registers */
56 #define MVEBU_G2_SMI_PHY_CMD_REG (24)
57 #define MVEBU_G2_SMI_PHY_DATA_REG (25)
60 * Memory Controller Registers
62 * Assembled based on public information:
63 * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/v2020.11.26/wtmi/main.c#L332-336
64 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
66 * And checked against the written register values for the various topologies:
67 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/master/a3700/mv_ddr_tim.h
69 #define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
70 #define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
71 #define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
72 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
73 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
75 int board_early_init_f(void)
82 /* adress of boot parameters */
83 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
88 #ifdef CONFIG_BOARD_LATE_INIT
89 int board_late_init(void)
91 char *ptr = &default_environment[0];
99 if (!of_machine_is_compatible("globalscale,espressobin"))
103 * Find free space for new variables in default_environment[] array.
104 * Free space is after the last variable, each variable is termined
105 * by nul byte and after the last variable is additional nul byte.
106 * Move ptr to the position where new variable can be filled.
108 while (*ptr != '\0') {
109 do { ptr++; } while (*ptr != '\0');
114 * Ensure that 'env default -a' does not erase permanent MAC addresses
115 * stored in env variables: $ethaddr, $eth1addr, $eth2addr and $eth3addr
118 mac = env_get("ethaddr");
119 if (mac && strlen(mac) <= 17)
120 ptr += sprintf(ptr, "ethaddr=%s", mac) + 1;
122 for (i = 1; i <= 3; i++) {
123 sprintf(eth, "eth%daddr", i);
125 if (mac && strlen(mac) <= 17)
126 ptr += sprintf(ptr, "%s=%s", eth, mac) + 1;
129 /* If the memory controller has been configured for DDR4, we're running on v7 */
130 ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
131 & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
133 /* eMMC is mmc dev num 1 */
134 mmc_dev = find_mmc_device(1);
135 emmc = (mmc_dev && mmc_get_op_cond(mmc_dev, true) == 0);
137 /* if eMMC is not present then remove it from DM */
138 if (!emmc && mmc_dev) {
140 device_remove(dev, DM_REMOVE_NORMAL);
142 if (of_live_active())
143 ofnode_set_enabled(dev_ofnode(dev), false);
146 /* Ensure that 'env default -a' set correct value to $fdtfile */
148 strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7-emmc.dtb");
150 strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7.dtb");
152 strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-emmc.dtb");
154 strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb");
155 ptr += strlen(ptr) + 1;
158 * After the last variable (which is nul term string) append another nul
159 * byte which terminates the list. So everything after ptr is ignored.
167 /* Board specific AHCI / SATA enable code */
168 int board_ahci_enable(void)
174 /* Only DB requres this configuration */
175 if (!of_machine_is_compatible("marvell,armada-3720-db"))
178 /* Configure IO exander PCA9555: 7bit address 0x22 */
179 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
181 printf("Cannot find PCA9555: %d\n", ret);
185 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
187 printf("Failed to read IO expander value via I2C\n");
192 * Enable SATA power via IO expander connected via I2C by setting
193 * the corresponding bit to output mode to enable power for SATA
195 buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
196 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
198 printf("Failed to set IO expander via I2C\n");
205 /* Board specific xHCI enable code */
206 int board_xhci_enable(fdt_addr_t base)
212 /* Only DB requres this configuration */
213 if (!of_machine_is_compatible("marvell,armada-3720-db"))
216 /* Configure IO exander PCA9555: 7bit address 0x22 */
217 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
219 printf("Cannot find PCA9555: %d\n", ret);
223 printf("Enable USB VBUS\n");
226 * Read configuration (direction) and set VBUS pin as output
227 * (reset pin = output)
229 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
231 printf("Failed to read IO expander value via I2C\n");
234 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
235 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
237 printf("Failed to set IO expander via I2C\n");
241 /* Read VBUS output value and disable it */
242 ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
244 printf("Failed to read IO expander value via I2C\n");
247 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
248 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
250 printf("Failed to set IO expander via I2C\n");
255 * Required delay for configuration to settle - must wait for
256 * power on port is disabled in case VBUS signal was high,
257 * required 3 seconds delay to let VBUS signal fully settle down
261 /* Enable VBUS power: Set output value of VBUS pin as enabled */
262 buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
263 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
265 printf("Failed to set IO expander via I2C\n");
269 mdelay(500); /* required delay to let output value settle */
274 #ifdef CONFIG_LAST_STAGE_INIT
275 /* Helper function for accessing switch devices in multi-chip connection mode */
276 static int mii_multi_chip_mode_write(struct udevice *bus, int dev_smi_addr,
277 int smi_addr, int reg, u16 value)
281 if (dm_mdio_write(bus, dev_smi_addr, MDIO_DEVAD_NONE,
282 MVEBU_SW_SMI_DATA_REG, value) != 0) {
283 printf("Error writing to the PHY addr=%02x reg=%02x\n",
288 smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
289 (1 << SW_SMI_CMD_SMI_MODE_OFF) |
290 (1 << SW_SMI_CMD_SMI_OP_OFF) |
291 (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
292 (reg << SW_SMI_CMD_REG_ADDR_OFF);
293 if (dm_mdio_write(bus, dev_smi_addr, MDIO_DEVAD_NONE,
294 MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
295 printf("Error writing to the PHY addr=%02x reg=%02x\n",
303 /* Bring-up board-specific network stuff */
304 int last_stage_init(void)
309 if (!of_machine_is_compatible("globalscale,espressobin"))
312 node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
313 if (!ofnode_valid(node) ||
314 uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
316 printf("Cannot find MDIO bus\n");
321 * FIXME: remove this code once Topaz driver gets available
322 * A3720 Community Board Only
323 * Configure Topaz switch (88E6341)
324 * Restrict output to ports 1,2,3 only from port 0 (CPU)
325 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
327 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
328 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
329 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
330 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
331 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
332 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
334 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
335 MVEBU_SW_PORT_CTRL_REG, 0x7f);
336 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
337 MVEBU_SW_PORT_CTRL_REG, 0x7f);
338 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
339 MVEBU_SW_PORT_CTRL_REG, 0x7f);
340 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
341 MVEBU_SW_PORT_CTRL_REG, 0x7f);
343 /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
344 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
345 MVEBU_SW_LINK_CTRL_REG, 0xe002);
347 /* Power up PHY 1, 2, 3 (through Global 2 registers) */
348 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
349 MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
350 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
351 MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
352 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
353 MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
354 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
355 MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
361 #ifdef CONFIG_OF_BOARD_SETUP
362 int ft_board_setup(void *blob, struct bd_info *bd)
364 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
370 /* Fill SPI MTD partitions for Linux kernel on Espressobin */
371 if (!of_machine_is_compatible("globalscale,espressobin"))
374 spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
378 /* Do not touch partitions if they are already defined */
379 if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
382 parts_off = fdt_add_subnode(blob, spi_off, "partitions");
384 printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
388 ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
390 printf("Can't set compatible property: %s\n", fdt_strerror(ret));
394 ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
396 printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
400 ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
402 printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
406 /* Add u-boot-env partition */
408 part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
410 printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
414 ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
416 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
420 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
422 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
426 ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
428 printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
432 /* Add firmware partition */
434 part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
436 printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
440 ret = fdt_setprop_u32(blob, part_off, "reg", 0);
442 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
446 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
448 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
452 ret = fdt_setprop_string(blob, part_off, "label", "firmware");
454 printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));