1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <linux/delay.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 /* IO expander I2C device */
20 #define I2C_IO_EXP_ADDR 0x22
21 #define I2C_IO_CFG_REG_0 0x6
22 #define I2C_IO_DATA_OUT_REG_0 0x2
23 #define I2C_IO_REG_0_SATA_OFF 2
24 #define I2C_IO_REG_0_USB_H_OFF 1
26 /* The pin control values are the same for DB and Espressobin */
27 #define PINCTRL_NB_REG_VALUE 0x000173fa
28 #define PINCTRL_SB_REG_VALUE 0x00007a23
30 /* Ethernet switch registers */
31 /* SMI addresses for multi-chip mode */
32 #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
33 #define MVEBU_SW_G2_SMI_ADDR (28)
36 #define MVEBU_SW_SMI_DATA_REG (1)
37 #define MVEBU_SW_SMI_CMD_REG (0)
38 #define SW_SMI_CMD_REG_ADDR_OFF 0
39 #define SW_SMI_CMD_DEV_ADDR_OFF 5
40 #define SW_SMI_CMD_SMI_OP_OFF 10
41 #define SW_SMI_CMD_SMI_MODE_OFF 12
42 #define SW_SMI_CMD_SMI_BUSY_OFF 15
44 /* Single-chip mode */
45 /* Switch Port Registers */
46 #define MVEBU_SW_LINK_CTRL_REG (1)
47 #define MVEBU_SW_PORT_CTRL_REG (4)
48 #define MVEBU_SW_PORT_BASE_VLAN (6)
50 /* Global 2 Registers */
51 #define MVEBU_G2_SMI_PHY_CMD_REG (24)
52 #define MVEBU_G2_SMI_PHY_DATA_REG (25)
55 * Memory Controller Registers
57 * Assembled based on public information:
58 * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
59 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
61 * And checked against the written register values for the various topologies:
62 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
64 #define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
65 #define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
66 #define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
67 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
68 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
70 int board_early_init_f(void)
77 /* adress of boot parameters */
78 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
83 #ifdef CONFIG_BOARD_LATE_INIT
84 int board_late_init(void)
88 if (env_get("fdtfile"))
91 if (!of_machine_is_compatible("globalscale,espressobin"))
94 /* If the memory controller has been configured for DDR4, we're running on v7 */
95 ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
96 & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
98 emmc = of_machine_is_compatible("globalscale,espressobin-emmc");
101 env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
103 env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
105 env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
107 env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
113 /* Board specific AHCI / SATA enable code */
114 int board_ahci_enable(void)
120 /* Only DB requres this configuration */
121 if (!of_machine_is_compatible("marvell,armada-3720-db"))
124 /* Configure IO exander PCA9555: 7bit address 0x22 */
125 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
127 printf("Cannot find PCA9555: %d\n", ret);
131 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
133 printf("Failed to read IO expander value via I2C\n");
138 * Enable SATA power via IO expander connected via I2C by setting
139 * the corresponding bit to output mode to enable power for SATA
141 buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
142 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
144 printf("Failed to set IO expander via I2C\n");
151 /* Board specific xHCI enable code */
152 int board_xhci_enable(fdt_addr_t base)
158 /* Only DB requres this configuration */
159 if (!of_machine_is_compatible("marvell,armada-3720-db"))
162 /* Configure IO exander PCA9555: 7bit address 0x22 */
163 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
165 printf("Cannot find PCA9555: %d\n", ret);
169 printf("Enable USB VBUS\n");
172 * Read configuration (direction) and set VBUS pin as output
173 * (reset pin = output)
175 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
177 printf("Failed to read IO expander value via I2C\n");
180 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
181 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
183 printf("Failed to set IO expander via I2C\n");
187 /* Read VBUS output value and disable it */
188 ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
190 printf("Failed to read IO expander value via I2C\n");
193 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
194 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
196 printf("Failed to set IO expander via I2C\n");
201 * Required delay for configuration to settle - must wait for
202 * power on port is disabled in case VBUS signal was high,
203 * required 3 seconds delay to let VBUS signal fully settle down
207 /* Enable VBUS power: Set output value of VBUS pin as enabled */
208 buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
209 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
211 printf("Failed to set IO expander via I2C\n");
215 mdelay(500); /* required delay to let output value settle */
220 /* Helper function for accessing switch devices in multi-chip connection mode */
221 static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
222 int smi_addr, int reg, u16 value)
226 if (bus->write(bus, dev_smi_addr, 0,
227 MVEBU_SW_SMI_DATA_REG, value) != 0) {
228 printf("Error writing to the PHY addr=%02x reg=%02x\n",
233 smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
234 (1 << SW_SMI_CMD_SMI_MODE_OFF) |
235 (1 << SW_SMI_CMD_SMI_OP_OFF) |
236 (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
237 (reg << SW_SMI_CMD_REG_ADDR_OFF);
238 if (bus->write(bus, dev_smi_addr, 0,
239 MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
240 printf("Error writing to the PHY addr=%02x reg=%02x\n",
248 /* Bring-up board-specific network stuff */
249 int board_network_enable(struct mii_dev *bus)
251 if (!of_machine_is_compatible("globalscale,espressobin"))
255 * FIXME: remove this code once Topaz driver gets available
256 * A3720 Community Board Only
257 * Configure Topaz switch (88E6341)
258 * Restrict output to ports 1,2,3 only from port 0 (CPU)
259 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
261 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
262 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
263 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
264 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
265 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
266 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
268 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
269 MVEBU_SW_PORT_CTRL_REG, 0x7f);
270 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
271 MVEBU_SW_PORT_CTRL_REG, 0x7f);
272 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
273 MVEBU_SW_PORT_CTRL_REG, 0x7f);
274 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
275 MVEBU_SW_PORT_CTRL_REG, 0x7f);
277 /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
278 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
279 MVEBU_SW_LINK_CTRL_REG, 0xe002);
281 /* Power up PHY 1, 2, 3 (through Global 2 registers) */
282 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
283 MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
284 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
285 MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
286 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
287 MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
288 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
289 MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
294 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
295 int ft_board_setup(void *blob, struct bd_info *bd)
302 /* Fill SPI MTD partitions for Linux kernel on Espressobin */
303 if (!of_machine_is_compatible("globalscale,espressobin"))
306 spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
310 /* Do not touch partitions if they are already defined */
311 if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
314 parts_off = fdt_add_subnode(blob, spi_off, "partitions");
316 printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
320 ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
322 printf("Can't set compatible property: %s\n", fdt_strerror(ret));
326 ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
328 printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
332 ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
334 printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
338 /* Add u-boot-env partition */
340 part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
342 printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
346 ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
348 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
352 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
354 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
358 ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
360 printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
364 /* Add firmware partition */
366 part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
368 printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
372 ret = fdt_setprop_u32(blob, part_off, "reg", 0);
374 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
378 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
380 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
384 ret = fdt_setprop_string(blob, part_off, "label", "firmware");
386 printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));