2 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 /* IO expander I2C device */
18 #define I2C_IO_EXP_ADDR 0x22
19 #define I2C_IO_CFG_REG_0 0x6
20 #define I2C_IO_DATA_OUT_REG_0 0x2
21 #define I2C_IO_REG_0_SATA_OFF 2
22 #define I2C_IO_REG_0_USB_H_OFF 1
24 #define PINCTRL_NB_REG_VALUE 0x000173fa
25 #define PINCTRL_SB_REG_VALUE 0x00007a23
27 /* Ethernet switch registers */
28 /* SMI addresses for multi-chip mode */
29 #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
30 #define MVEBU_SW_G2_SMI_ADDR (28)
33 #define MVEBU_SW_SMI_DATA_REG (1)
34 #define MVEBU_SW_SMI_CMD_REG (0)
35 #define SW_SMI_CMD_REG_ADDR_OFF 0
36 #define SW_SMI_CMD_DEV_ADDR_OFF 5
37 #define SW_SMI_CMD_SMI_OP_OFF 10
38 #define SW_SMI_CMD_SMI_MODE_OFF 12
39 #define SW_SMI_CMD_SMI_BUSY_OFF 15
41 /* Single-chip mode */
42 /* Switch Port Registers */
43 #define MVEBU_SW_LINK_CTRL_REG (1)
44 #define MVEBU_SW_PORT_CTRL_REG (4)
46 /* Global 2 Registers */
47 #define MVEBU_G2_SMI_PHY_CMD_REG (24)
48 #define MVEBU_G2_SMI_PHY_DATA_REG (25)
50 int board_early_init_f(void)
52 const void *blob = gd->fdt_blob;
53 const char *bank_name;
54 const char *compat = "marvell,armada-3700-pinctl";
59 * Temporary WA for setting correct pin control values
60 * until the real pin control driver is awailable.
62 off = fdt_node_offset_by_compatible(blob, -1, compat);
63 while (off != -FDT_ERR_NOTFOUND) {
64 bank_name = fdt_getprop(blob, off, "bank-name", &len);
65 addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
66 blob, off, "reg", 0, NULL, true);
67 if (!strncmp(bank_name, "armada-3700-nb", len))
68 writel(PINCTRL_NB_REG_VALUE, addr);
69 else if (!strncmp(bank_name, "armada-3700-sb", len))
70 writel(PINCTRL_SB_REG_VALUE, addr);
72 off = fdt_node_offset_by_compatible(blob, off, compat);
80 /* adress of boot parameters */
81 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
86 /* Board specific AHCI / SATA enable code */
87 int board_ahci_enable(void)
93 /* Configure IO exander PCA9555: 7bit address 0x22 */
94 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
96 printf("Cannot find PCA9555: %d\n", ret);
100 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
102 printf("Failed to read IO expander value via I2C\n");
107 * Enable SATA power via IO expander connected via I2C by setting
108 * the corresponding bit to output mode to enable power for SATA
110 buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
111 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
113 printf("Failed to set IO expander via I2C\n");
120 /* Board specific xHCI enable code */
121 int board_xhci_enable(void)
127 /* Configure IO exander PCA9555: 7bit address 0x22 */
128 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
130 printf("Cannot find PCA9555: %d\n", ret);
134 printf("Enable USB VBUS\n");
137 * Read configuration (direction) and set VBUS pin as output
138 * (reset pin = output)
140 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
142 printf("Failed to read IO expander value via I2C\n");
145 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
146 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
148 printf("Failed to set IO expander via I2C\n");
152 /* Read VBUS output value and disable it */
153 ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
155 printf("Failed to read IO expander value via I2C\n");
158 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
159 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
161 printf("Failed to set IO expander via I2C\n");
166 * Required delay for configuration to settle - must wait for
167 * power on port is disabled in case VBUS signal was high,
168 * required 3 seconds delay to let VBUS signal fully settle down
172 /* Enable VBUS power: Set output value of VBUS pin as enabled */
173 buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
174 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
176 printf("Failed to set IO expander via I2C\n");
180 mdelay(500); /* required delay to let output value settle */
185 /* Helper function for accessing switch devices in multi-chip connection mode */
186 static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
187 int smi_addr, int reg, u16 value)
191 if (bus->write(bus, dev_smi_addr, 0,
192 MVEBU_SW_SMI_DATA_REG, value) != 0) {
193 printf("Error writing to the PHY addr=%02x reg=%02x\n",
198 smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
199 (1 << SW_SMI_CMD_SMI_MODE_OFF) |
200 (1 << SW_SMI_CMD_SMI_OP_OFF) |
201 (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
202 (reg << SW_SMI_CMD_REG_ADDR_OFF);
203 if (bus->write(bus, dev_smi_addr, 0,
204 MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
205 printf("Error writing to the PHY addr=%02x reg=%02x\n",
213 /* Bring-up board-specific network stuff */
214 int board_network_enable(struct mii_dev *bus)
216 if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
220 * FIXME: remove this code once Topaz driver gets available
221 * A3720 Community Board Only
222 * Configure Topaz switch (88E6341)
223 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
225 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
226 MVEBU_SW_PORT_CTRL_REG, 0x7f);
227 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
228 MVEBU_SW_PORT_CTRL_REG, 0x7f);
229 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
230 MVEBU_SW_PORT_CTRL_REG, 0x7f);
231 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
232 MVEBU_SW_PORT_CTRL_REG, 0x7f);
234 /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
235 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
236 MVEBU_SW_LINK_CTRL_REG, 0xe002);
238 /* Power up PHY 1, 2, 3 (through Global 2 registers) */
239 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
240 MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
241 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
242 MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
243 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
244 MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
245 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
246 MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);