1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
8 #include <dm/device-internal.h>
14 #include <asm/global_data.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <linux/delay.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* IO expander I2C device */
23 #define I2C_IO_EXP_ADDR 0x22
24 #define I2C_IO_CFG_REG_0 0x6
25 #define I2C_IO_DATA_OUT_REG_0 0x2
26 #define I2C_IO_REG_0_SATA_OFF 2
27 #define I2C_IO_REG_0_USB_H_OFF 1
29 /* The pin control values are the same for DB and Espressobin */
30 #define PINCTRL_NB_REG_VALUE 0x000173fa
31 #define PINCTRL_SB_REG_VALUE 0x00007a23
33 /* Ethernet switch registers */
34 /* SMI addresses for multi-chip mode */
35 #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
36 #define MVEBU_SW_G2_SMI_ADDR (28)
39 #define MVEBU_SW_SMI_DATA_REG (1)
40 #define MVEBU_SW_SMI_CMD_REG (0)
41 #define SW_SMI_CMD_REG_ADDR_OFF 0
42 #define SW_SMI_CMD_DEV_ADDR_OFF 5
43 #define SW_SMI_CMD_SMI_OP_OFF 10
44 #define SW_SMI_CMD_SMI_MODE_OFF 12
45 #define SW_SMI_CMD_SMI_BUSY_OFF 15
47 /* Single-chip mode */
48 /* Switch Port Registers */
49 #define MVEBU_SW_LINK_CTRL_REG (1)
50 #define MVEBU_SW_PORT_CTRL_REG (4)
51 #define MVEBU_SW_PORT_BASE_VLAN (6)
53 /* Global 2 Registers */
54 #define MVEBU_G2_SMI_PHY_CMD_REG (24)
55 #define MVEBU_G2_SMI_PHY_DATA_REG (25)
58 * Memory Controller Registers
60 * Assembled based on public information:
61 * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
62 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
64 * And checked against the written register values for the various topologies:
65 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
67 #define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
68 #define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
69 #define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
70 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
71 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
73 int board_early_init_f(void)
80 /* adress of boot parameters */
81 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
86 #ifdef CONFIG_BOARD_LATE_INIT
87 int board_late_init(void)
93 if (!of_machine_is_compatible("globalscale,espressobin"))
96 /* If the memory controller has been configured for DDR4, we're running on v7 */
97 ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
98 & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
100 /* eMMC is mmc dev num 1 */
101 mmc_dev = find_mmc_device(1);
102 emmc = (mmc_dev && mmc_init(mmc_dev) == 0);
104 /* if eMMC is not present then remove it from DM */
105 if (!emmc && mmc_dev) {
107 device_remove(dev, DM_REMOVE_NORMAL);
111 if (env_get("fdtfile"))
115 env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
117 env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
119 env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
121 env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
127 /* Board specific AHCI / SATA enable code */
128 int board_ahci_enable(void)
134 /* Only DB requres this configuration */
135 if (!of_machine_is_compatible("marvell,armada-3720-db"))
138 /* Configure IO exander PCA9555: 7bit address 0x22 */
139 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
141 printf("Cannot find PCA9555: %d\n", ret);
145 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
147 printf("Failed to read IO expander value via I2C\n");
152 * Enable SATA power via IO expander connected via I2C by setting
153 * the corresponding bit to output mode to enable power for SATA
155 buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
156 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
158 printf("Failed to set IO expander via I2C\n");
165 /* Board specific xHCI enable code */
166 int board_xhci_enable(fdt_addr_t base)
172 /* Only DB requres this configuration */
173 if (!of_machine_is_compatible("marvell,armada-3720-db"))
176 /* Configure IO exander PCA9555: 7bit address 0x22 */
177 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
179 printf("Cannot find PCA9555: %d\n", ret);
183 printf("Enable USB VBUS\n");
186 * Read configuration (direction) and set VBUS pin as output
187 * (reset pin = output)
189 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
191 printf("Failed to read IO expander value via I2C\n");
194 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
195 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
197 printf("Failed to set IO expander via I2C\n");
201 /* Read VBUS output value and disable it */
202 ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
204 printf("Failed to read IO expander value via I2C\n");
207 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
208 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
210 printf("Failed to set IO expander via I2C\n");
215 * Required delay for configuration to settle - must wait for
216 * power on port is disabled in case VBUS signal was high,
217 * required 3 seconds delay to let VBUS signal fully settle down
221 /* Enable VBUS power: Set output value of VBUS pin as enabled */
222 buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
223 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
225 printf("Failed to set IO expander via I2C\n");
229 mdelay(500); /* required delay to let output value settle */
234 /* Helper function for accessing switch devices in multi-chip connection mode */
235 static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
236 int smi_addr, int reg, u16 value)
240 if (bus->write(bus, dev_smi_addr, 0,
241 MVEBU_SW_SMI_DATA_REG, value) != 0) {
242 printf("Error writing to the PHY addr=%02x reg=%02x\n",
247 smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
248 (1 << SW_SMI_CMD_SMI_MODE_OFF) |
249 (1 << SW_SMI_CMD_SMI_OP_OFF) |
250 (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
251 (reg << SW_SMI_CMD_REG_ADDR_OFF);
252 if (bus->write(bus, dev_smi_addr, 0,
253 MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
254 printf("Error writing to the PHY addr=%02x reg=%02x\n",
262 /* Bring-up board-specific network stuff */
263 int board_network_enable(struct mii_dev *bus)
265 if (!of_machine_is_compatible("globalscale,espressobin"))
269 * FIXME: remove this code once Topaz driver gets available
270 * A3720 Community Board Only
271 * Configure Topaz switch (88E6341)
272 * Restrict output to ports 1,2,3 only from port 0 (CPU)
273 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
275 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
276 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
277 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
278 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
279 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
280 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
282 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
283 MVEBU_SW_PORT_CTRL_REG, 0x7f);
284 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
285 MVEBU_SW_PORT_CTRL_REG, 0x7f);
286 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
287 MVEBU_SW_PORT_CTRL_REG, 0x7f);
288 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
289 MVEBU_SW_PORT_CTRL_REG, 0x7f);
291 /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
292 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
293 MVEBU_SW_LINK_CTRL_REG, 0xe002);
295 /* Power up PHY 1, 2, 3 (through Global 2 registers) */
296 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
297 MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
298 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
299 MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
300 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
301 MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
302 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
303 MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
308 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
309 int ft_board_setup(void *blob, struct bd_info *bd)
316 /* Fill SPI MTD partitions for Linux kernel on Espressobin */
317 if (!of_machine_is_compatible("globalscale,espressobin"))
320 spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
324 /* Do not touch partitions if they are already defined */
325 if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
328 parts_off = fdt_add_subnode(blob, spi_off, "partitions");
330 printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
334 ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
336 printf("Can't set compatible property: %s\n", fdt_strerror(ret));
340 ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
342 printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
346 ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
348 printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
352 /* Add u-boot-env partition */
354 part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
356 printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
360 ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
362 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
366 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
368 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
372 ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
374 printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
378 /* Add firmware partition */
380 part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
382 printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
386 ret = fdt_setprop_u32(blob, part_off, "reg", 0);
388 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
392 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
394 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
398 ret = fdt_setprop_string(blob, part_off, "label", "firmware");
400 printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));