1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
8 #include <dm/device-internal.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/soc.h>
17 #include <linux/delay.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 /* IO expander I2C device */
22 #define I2C_IO_EXP_ADDR 0x22
23 #define I2C_IO_CFG_REG_0 0x6
24 #define I2C_IO_DATA_OUT_REG_0 0x2
25 #define I2C_IO_REG_0_SATA_OFF 2
26 #define I2C_IO_REG_0_USB_H_OFF 1
28 /* The pin control values are the same for DB and Espressobin */
29 #define PINCTRL_NB_REG_VALUE 0x000173fa
30 #define PINCTRL_SB_REG_VALUE 0x00007a23
32 /* Ethernet switch registers */
33 /* SMI addresses for multi-chip mode */
34 #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
35 #define MVEBU_SW_G2_SMI_ADDR (28)
38 #define MVEBU_SW_SMI_DATA_REG (1)
39 #define MVEBU_SW_SMI_CMD_REG (0)
40 #define SW_SMI_CMD_REG_ADDR_OFF 0
41 #define SW_SMI_CMD_DEV_ADDR_OFF 5
42 #define SW_SMI_CMD_SMI_OP_OFF 10
43 #define SW_SMI_CMD_SMI_MODE_OFF 12
44 #define SW_SMI_CMD_SMI_BUSY_OFF 15
46 /* Single-chip mode */
47 /* Switch Port Registers */
48 #define MVEBU_SW_LINK_CTRL_REG (1)
49 #define MVEBU_SW_PORT_CTRL_REG (4)
50 #define MVEBU_SW_PORT_BASE_VLAN (6)
52 /* Global 2 Registers */
53 #define MVEBU_G2_SMI_PHY_CMD_REG (24)
54 #define MVEBU_G2_SMI_PHY_DATA_REG (25)
57 * Memory Controller Registers
59 * Assembled based on public information:
60 * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
61 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
63 * And checked against the written register values for the various topologies:
64 * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
66 #define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
67 #define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
68 #define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
69 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
70 #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
72 int board_early_init_f(void)
79 /* adress of boot parameters */
80 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
85 #ifdef CONFIG_BOARD_LATE_INIT
86 int board_late_init(void)
92 if (!of_machine_is_compatible("globalscale,espressobin"))
95 /* If the memory controller has been configured for DDR4, we're running on v7 */
96 ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
97 & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
99 /* eMMC is mmc dev num 1 */
100 mmc_dev = find_mmc_device(1);
101 emmc = (mmc_dev && mmc_init(mmc_dev) == 0);
103 /* if eMMC is not present then remove it from DM */
104 if (!emmc && mmc_dev) {
106 device_remove(dev, DM_REMOVE_NORMAL);
110 if (env_get("fdtfile"))
114 env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
116 env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
118 env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
120 env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
126 /* Board specific AHCI / SATA enable code */
127 int board_ahci_enable(void)
133 /* Only DB requres this configuration */
134 if (!of_machine_is_compatible("marvell,armada-3720-db"))
137 /* Configure IO exander PCA9555: 7bit address 0x22 */
138 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
140 printf("Cannot find PCA9555: %d\n", ret);
144 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
146 printf("Failed to read IO expander value via I2C\n");
151 * Enable SATA power via IO expander connected via I2C by setting
152 * the corresponding bit to output mode to enable power for SATA
154 buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
155 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
157 printf("Failed to set IO expander via I2C\n");
164 /* Board specific xHCI enable code */
165 int board_xhci_enable(fdt_addr_t base)
171 /* Only DB requres this configuration */
172 if (!of_machine_is_compatible("marvell,armada-3720-db"))
175 /* Configure IO exander PCA9555: 7bit address 0x22 */
176 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
178 printf("Cannot find PCA9555: %d\n", ret);
182 printf("Enable USB VBUS\n");
185 * Read configuration (direction) and set VBUS pin as output
186 * (reset pin = output)
188 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
190 printf("Failed to read IO expander value via I2C\n");
193 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
194 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
196 printf("Failed to set IO expander via I2C\n");
200 /* Read VBUS output value and disable it */
201 ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
203 printf("Failed to read IO expander value via I2C\n");
206 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
207 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
209 printf("Failed to set IO expander via I2C\n");
214 * Required delay for configuration to settle - must wait for
215 * power on port is disabled in case VBUS signal was high,
216 * required 3 seconds delay to let VBUS signal fully settle down
220 /* Enable VBUS power: Set output value of VBUS pin as enabled */
221 buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
222 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
224 printf("Failed to set IO expander via I2C\n");
228 mdelay(500); /* required delay to let output value settle */
233 /* Helper function for accessing switch devices in multi-chip connection mode */
234 static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
235 int smi_addr, int reg, u16 value)
239 if (bus->write(bus, dev_smi_addr, 0,
240 MVEBU_SW_SMI_DATA_REG, value) != 0) {
241 printf("Error writing to the PHY addr=%02x reg=%02x\n",
246 smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
247 (1 << SW_SMI_CMD_SMI_MODE_OFF) |
248 (1 << SW_SMI_CMD_SMI_OP_OFF) |
249 (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
250 (reg << SW_SMI_CMD_REG_ADDR_OFF);
251 if (bus->write(bus, dev_smi_addr, 0,
252 MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
253 printf("Error writing to the PHY addr=%02x reg=%02x\n",
261 /* Bring-up board-specific network stuff */
262 int board_network_enable(struct mii_dev *bus)
264 if (!of_machine_is_compatible("globalscale,espressobin"))
268 * FIXME: remove this code once Topaz driver gets available
269 * A3720 Community Board Only
270 * Configure Topaz switch (88E6341)
271 * Restrict output to ports 1,2,3 only from port 0 (CPU)
272 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
274 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
275 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
276 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
277 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
278 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
279 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
281 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
282 MVEBU_SW_PORT_CTRL_REG, 0x7f);
283 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
284 MVEBU_SW_PORT_CTRL_REG, 0x7f);
285 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
286 MVEBU_SW_PORT_CTRL_REG, 0x7f);
287 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
288 MVEBU_SW_PORT_CTRL_REG, 0x7f);
290 /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
291 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
292 MVEBU_SW_LINK_CTRL_REG, 0xe002);
294 /* Power up PHY 1, 2, 3 (through Global 2 registers) */
295 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
296 MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
297 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
298 MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
299 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
300 MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
301 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
302 MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
307 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
308 int ft_board_setup(void *blob, struct bd_info *bd)
315 /* Fill SPI MTD partitions for Linux kernel on Espressobin */
316 if (!of_machine_is_compatible("globalscale,espressobin"))
319 spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
323 /* Do not touch partitions if they are already defined */
324 if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
327 parts_off = fdt_add_subnode(blob, spi_off, "partitions");
329 printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
333 ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
335 printf("Can't set compatible property: %s\n", fdt_strerror(ret));
339 ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
341 printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
345 ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
347 printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
351 /* Add u-boot-env partition */
353 part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
355 printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
359 ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
361 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
365 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
367 printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
371 ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
373 printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
377 /* Add firmware partition */
379 part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
381 printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
385 ret = fdt_setprop_u32(blob, part_off, "reg", 0);
387 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
391 ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
393 printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
397 ret = fdt_setprop_string(blob, part_off, "label", "firmware");
399 printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));