1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Siddarth Gore <gores@marvell.com>
12 #include <asm/global_data.h>
13 #include <asm/mach-types.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/soc.h>
16 #include <asm/arch/mpp.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 int board_early_init_f(void)
24 * default gpio configuration
25 * There are maximum 64 gpios controlled through 2 sets of registers
26 * the below configuration configures mainly initial LED status
28 mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
30 GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
32 /* Multi-Purpose Pins Functionality configuration */
33 static const u32 kwmpp_config[] = {
41 MPP7_GPO, /* GPIO_RST */
80 MPP46_GPIO, /* M_RLED */
81 MPP47_GPIO, /* M_GLED */
82 MPP48_GPIO, /* B_RLED */
83 MPP49_GPIO, /* B_GLED */
86 kirkwood_mpp_conf(kwmpp_config, NULL);
93 * arch number of board
95 gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
97 /* adress of boot parameters */
98 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
103 #ifdef CONFIG_RESET_PHY_R
104 void mv_phy_88e1121_init(char *name)
109 if (miiphy_set_current_dev(name))
112 /* command to read PHY dev address */
113 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
114 printf("Err..%s could not read PHY dev address\n",
120 * Enable RGMII delay on Tx and Rx for CPU port
121 * Ref: sec 4.7.2 of chip datasheet
123 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
124 miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
125 reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
126 miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
127 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
130 miiphy_reset(name, devadr);
132 printf("88E1121 Initialized on %s\n", name);
137 /* configure and initialize both PHY's */
138 mv_phy_88e1121_init("egiga0");
139 mv_phy_88e1121_init("egiga1");
141 #endif /* CONFIG_RESET_PHY_R */