board/Marvell/dreamplug/dreamplug.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2011
   4  * Jason Cooper <u-boot@lakedaemon.net>
   5  *
   6  * Based on work by:
   7  * Marvell Semiconductor <www.marvell.com>
   8  * Written-by: Siddarth Gore <gores@marvell.com>
   9  */
  10
  11 #include <common.h>
  12 #include <init.h>
  13 #include <miiphy.h>
  14 #include <net.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/soc.h>
  17 #include <asm/arch/mpp.h>
  18 #include <asm/global_data.h>
  19 #include "dreamplug.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int board_early_init_f(void)
  24 {
  25         /*
  26          * default gpio configuration
  27          * There are maximum 64 gpios controlled through 2 sets of registers
  28          * the  below configuration configures mainly initial LED status
  29          */
  30         mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
  31                           DREAMPLUG_OE_VAL_HIGH,
  32                           DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
  33
  34         /* Multi-Purpose Pins Functionality configuration */
  35         static const u32 kwmpp_config[] = {
  36                 MPP0_SPI_SCn,           /* SPI Flash */
  37                 MPP1_SPI_MOSI,
  38                 MPP2_SPI_SCK,
  39                 MPP3_SPI_MISO,
  40                 MPP4_NF_IO6,
  41                 MPP5_NF_IO7,
  42                 MPP6_SYSRST_OUTn,
  43                 MPP7_GPO,
  44                 MPP8_TW_SDA,
  45                 MPP9_TW_SCK,
  46                 MPP10_UART0_TXD,        /* Serial */
  47                 MPP11_UART0_RXD,
  48                 MPP12_SD_CLK,           /* SDIO Slot */
  49                 MPP13_SD_CMD,
  50                 MPP14_SD_D0,
  51                 MPP15_SD_D1,
  52                 MPP16_SD_D2,
  53                 MPP17_SD_D3,
  54                 MPP18_NF_IO0,
  55                 MPP19_NF_IO1,
  56                 MPP20_GE1_0,            /* Gigabit Ethernet */
  57                 MPP21_GE1_1,
  58                 MPP22_GE1_2,
  59                 MPP23_GE1_3,
  60                 MPP24_GE1_4,
  61                 MPP25_GE1_5,
  62                 MPP26_GE1_6,
  63                 MPP27_GE1_7,
  64                 MPP28_GE1_8,
  65                 MPP29_GE1_9,
  66                 MPP30_GE1_10,
  67                 MPP31_GE1_11,
  68                 MPP32_GE1_12,
  69                 MPP33_GE1_13,
  70                 MPP34_GE1_14,
  71                 MPP35_GE1_15,
  72                 MPP36_GPIO,             /* 7 external GPIO pins (36 - 45) */
  73                 MPP37_GPIO,
  74                 MPP38_GPIO,
  75                 MPP39_GPIO,
  76                 MPP40_TDM_SPI_SCK,
  77                 MPP41_TDM_SPI_MISO,
  78                 MPP42_TDM_SPI_MOSI,
  79                 MPP43_GPIO,
  80                 MPP44_GPIO,
  81                 MPP45_GPIO,
  82                 MPP46_GPIO,
  83                 MPP47_GPIO,             /* Bluetooth LED */
  84                 MPP48_GPIO,             /* Wifi LED */
  85                 MPP49_GPIO,             /* Wifi AP LED */
  86                 0
  87         };
  88         kirkwood_mpp_conf(kwmpp_config, NULL);
  89         return 0;
  90 }
  91
  92 int board_init(void)
  93 {
  94         /* adress of boot parameters */
  95         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  96
  97         return 0;
  98 }
  99
 100 #ifdef CONFIG_RESET_PHY_R
 101 void mv_phy_88e1116_init(char *name)
 102 {
 103         u16 reg;
 104         u16 devadr;
 105
 106         if (miiphy_set_current_dev(name))
 107                 return;
 108
 109         /* command to read PHY dev address */
 110         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 111                 printf("Err..%s could not read PHY dev address\n",
 112                         __func__);
 113                 return;
 114         }
 115
 116         /*
 117          * Enable RGMII delay on Tx and Rx for CPU port
 118          * Ref: sec 4.7.2 of chip datasheet
 119          */
 120         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 121         miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
 122         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 123         miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
 124         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 125
 126         /* reset the phy */
 127         miiphy_reset(name, devadr);
 128
 129         printf("88E1116 Initialized on %s\n", name);
 130 }
 131
 132 void reset_phy(void)
 133 {
 134         /* configure and initialize both PHY's */
 135         mv_phy_88e1116_init("egiga0");
 136         mv_phy_88e1116_init("egiga1");
 137 }
 138 #endif /* CONFIG_RESET_PHY_R */