board/Marvell/db64460/sdram_init.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * adaption for the Marvell DB64460 Board
  26  * Ingo Assmus (ingo.assmus@keymile.com)
  27   ************************************************************************/
  28
  29
  30 /* sdram_init.c - automatic memory sizing */
  31
  32 #include <common.h>
  33 #include <74xx_7xx.h>
  34 #include "../include/memory.h"
  35 #include "../include/pci.h"
  36 #include "../include/mv_gen_reg.h"
  37 #include <net.h>
  38
  39 #include "eth.h"
  40 #include "mpsc.h"
  41 #include "../common/i2c.h"
  42 #include "64460.h"
  43 #include "mv_regs.h"
  44
  45 #undef  DEBUG
  46 #define MAP_PCI
  47
  48 #ifdef DEBUG
  49 #define DP(x) x
  50 #else
  51 #define DP(x)
  52 #endif
  53
  54 int set_dfcdlInit (void);       /* setup delay line of Mv64460 */
  55 int mvDmaIsChannelActive (int);
  56 int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
  57 int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
  58
  59 /* ------------------------------------------------------------------------- */
  60
  61 int
  62 memory_map_bank (unsigned int bankNo,
  63                  unsigned int bankBase, unsigned int bankLength)
  64 {
  65 #ifdef MAP_PCI
  66         PCI_HOST host;
  67 #endif
  68
  69
  70 #ifdef DEBUG
  71         if (bankLength > 0) {
  72                 printf ("mapping bank %d at %08x - %08x\n",
  73                         bankNo, bankBase, bankBase + bankLength - 1);
  74         } else {
  75                 printf ("unmapping bank %d\n", bankNo);
  76         }
  77 #endif
  78
  79         memoryMapBank (bankNo, bankBase, bankLength);
  80
  81 #ifdef MAP_PCI
  82         for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
  83                 const int features =
  84                         PREFETCH_ENABLE |
  85                         DELAYED_READ_ENABLE |
  86                         AGGRESSIVE_PREFETCH |
  87                         READ_LINE_AGGRESSIVE_PREFETCH |
  88                         READ_MULTI_AGGRESSIVE_PREFETCH |
  89                         MAX_BURST_4 | PCI_NO_SWAP;
  90
  91                 pciMapMemoryBank (host, bankNo, bankBase, bankLength);
  92
  93                 pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
  94                                        bankLength);
  95
  96                 pciSetRegionFeatures (host, bankNo, features, bankBase,
  97                                       bankLength);
  98         }
  99 #endif
 100         return 0;
 101 }
 102
 103 #define GB         (1 << 30)
 104
 105 /* much of this code is based on (or is) the code in the pip405 port */
 106 /* thanks go to the authors of said port - Josh */
 107
 108 /* structure to store the relevant information about an sdram bank */
 109 typedef struct sdram_info {
 110         uchar drb_size;
 111         uchar registered, ecc;
 112         uchar tpar;
 113         uchar tras_clocks;
 114         uchar burst_len;
 115         uchar banks, slot;
 116 } sdram_info_t;
 117
 118 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
 119
 120 typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
 121
 122 typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
 123         SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
 124 } VOLTAGE_INTERFACE;
 125
 126 typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
 127                 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
 128                 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
 129 typedef enum _max_CL_supported_SD { SD_CL_1 =
 130                 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
 131                 SD_FAULT } MAX_CL_SUPPORTED_SD;
 132
 133
 134 /* SDRAM/DDR information struct */
 135 typedef struct _gtMemoryDimmInfo {
 136         MEMORY_TYPE memoryType;
 137         unsigned int numOfRowAddresses;
 138         unsigned int numOfColAddresses;
 139         unsigned int numOfModuleBanks;
 140         unsigned int dataWidth;
 141         VOLTAGE_INTERFACE voltageInterface;
 142         unsigned int errorCheckType;    /* ECC , PARITY.. */
 143         unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
 144         unsigned int errorCheckDataWidth;       /* 0 - no, 1 - Yes */
 145         unsigned int minClkDelay;
 146         unsigned int burstLengthSupported;
 147         unsigned int numOfBanksOnEachDevice;
 148         unsigned int suportedCasLatencies;
 149         unsigned int RefreshInterval;
 150         unsigned int maxCASlatencySupported_LoP;        /* LoP left of point (measured in ns) */
 151         unsigned int maxCASlatencySupported_RoP;        /* RoP right of point (measured in ns) */
 152         MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
 153         MAX_CL_SUPPORTED_SD maxClSupported_SD;
 154         unsigned int moduleBankDensity;
 155         /* module attributes (true for yes) */
 156         bool bufferedAddrAndControlInputs;
 157         bool registeredAddrAndControlInputs;
 158         bool onCardPLL;
 159         bool bufferedDQMBinputs;
 160         bool registeredDQMBinputs;
 161         bool differentialClockInput;
 162         bool redundantRowAddressing;
 163
 164         /* module general attributes */
 165         bool suportedAutoPreCharge;
 166         bool suportedPreChargeAll;
 167         bool suportedEarlyRasPreCharge;
 168         bool suportedWrite1ReadBurst;
 169         bool suported5PercentLowVCC;
 170         bool suported5PercentUpperVCC;
 171         /* module timing parameters */
 172         unsigned int minRasToCasDelay;
 173         unsigned int minRowActiveRowActiveDelay;
 174         unsigned int minRasPulseWidth;
 175         unsigned int minRowPrechargeTime;       /* measured in ns */
 176
 177         int addrAndCommandHoldTime;     /* LoP left of point (measured in ns) */
 178         int addrAndCommandSetupTime;    /* (measured in ns/100) */
 179         int dataInputSetupTime; /* LoP left of point (measured in ns) */
 180         int dataInputHoldTime;  /* LoP left of point (measured in ns) */
 181 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
 182         unsigned int clockToDataOut_LoP;        /* LoP left of point (measured in ns) */
 183         unsigned int clockToDataOut_RoP;        /* RoP right of point (measured in ns) */
 184         unsigned int clockToDataOutMinus1_LoP;  /* LoP left of point (measured in ns) */
 185         unsigned int clockToDataOutMinus1_RoP;  /* RoP right of point (measured in ns) */
 186         unsigned int clockToDataOutMinus2_LoP;  /* LoP left of point (measured in ns) */
 187         unsigned int clockToDataOutMinus2_RoP;  /* RoP right of point (measured in ns) */
 188
 189         unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;       /* LoP left of point (measured in ns) */
 190         unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;       /* RoP right of point (measured in ns) */
 191
 192         unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
 193         unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
 194
 195         unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
 196         unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
 197
 198         /* Parameters calculated from
 199            the extracted DIMM information */
 200         unsigned int size;
 201         unsigned int deviceDensity;     /* 16,64,128,256 or 512 Mbit */
 202         unsigned int numberOfDevices;
 203         uchar drb_size;         /* DRAM size in n*64Mbit */
 204         uchar slot;             /* Slot Number this module is inserted in */
 205         uchar spd_raw_data[128];        /* Content of SPD-EEPROM copied 1:1 */
 206 #ifdef DEBUG
 207         uchar manufactura[8];   /* Content of SPD-EEPROM Byte 64-71 */
 208         uchar modul_id[18];     /* Content of SPD-EEPROM Byte 73-90 */
 209         uchar vendor_data[27];  /* Content of SPD-EEPROM Byte 99-125 */
 210         unsigned long modul_serial_no;  /* Content of SPD-EEPROM Byte 95-98 */
 211         unsigned int manufac_date;      /* Content of SPD-EEPROM Byte 93-94 */
 212         unsigned int modul_revision;    /* Content of SPD-EEPROM Byte 91-92 */
 213         uchar manufac_place;    /* Content of SPD-EEPROM Byte 72 */
 214
 215 #endif
 216 } AUX_MEM_DIMM_INFO;
 217
 218
 219 /*
 220  * translate ns.ns/10 coding of SPD timing values
 221  * into 10 ps unit values
 222  */
 223 static inline unsigned short NS10to10PS (unsigned char spd_byte)
 224 {
 225         unsigned short ns, ns10;
 226
 227         /* isolate upper nibble */
 228         ns = (spd_byte >> 4) & 0x0F;
 229         /* isolate lower nibble */
 230         ns10 = (spd_byte & 0x0F);
 231
 232         return (ns * 100 + ns10 * 10);
 233 }
 234
 235 /*
 236  * translate ns coding of SPD timing values
 237  * into 10 ps unit values
 238  */
 239 static inline unsigned short NSto10PS (unsigned char spd_byte)
 240 {
 241         return (spd_byte * 100);
 242 }
 243
 244 /* This code reads the SPD chip on the sdram and populates
 245  * the array which is passed in with the relevant information */
 246 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 247 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 248 {
 249         DECLARE_GLOBAL_DATA_PTR;
 250
 251         unsigned long spd_checksum;
 252
 253 #ifdef ZUMA_NTL
 254         /* zero all the values */
 255         memset (info, 0, sizeof (*info));
 256
 257 /*
 258         if (!slot) {
 259             info->slot = 0;
 260             info->banks = 1;
 261             info->registered = 0;
 262                     info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
 263 /*          info->tpar = 3;
 264             info->tras_clocks = 5;
 265             info->burst_len = 4;
 266 */
 267 #ifdef CONFIG_MV64460_ECC
 268         /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
 269         dimmInfo->errorCheckType = 2;
 270 /*          info->ecc = 2;*/
 271 #endif
 272 }
 273
 274 return 0;
 275
 276 #else
 277         uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
 278         int ret;
 279         unsigned int i, j, density = 1, devicesForErrCheck = 0;
 280
 281 #ifdef DEBUG
 282         unsigned int k;
 283 #endif
 284         unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
 285         int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
 286         uchar supp_cal, cal_val;
 287         ulong memclk, tmemclk;
 288         ulong tmp;
 289         uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
 290         uchar data[128];
 291
 292         memclk = gd->bus_clk;
 293         tmemclk = 1000000000 / (memclk / 100);  /* in 10 ps units */
 294
 295         DP (puts ("before i2c read\n"));
 296
 297         ret = i2c_read (addr, 0, 1, data, 128);
 298
 299         DP (puts ("after i2c read\n"));
 300
 301         /* zero all the values */
 302         memset (dimmInfo, 0, sizeof (*dimmInfo));
 303
 304         /* copy the SPD content 1:1 into the dimmInfo structure */
 305         for (i = 0; i <= 127; i++) {
 306                 dimmInfo->spd_raw_data[i] = data[i];
 307         }
 308
 309         if (ret) {
 310                 DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
 311                 return 0;
 312         } else
 313                 dimmInfo->slot = slot;  /* start to fill up dimminfo for this "slot" */
 314
 315 #ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
 316
 317         for (i = 0; i <= 127; i++) {
 318                 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
 319                         data[i]);
 320         }
 321
 322 #endif
 323 #ifdef DEBUG
 324 /* find Manufactura of Dimm Module */
 325         for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
 326                 dimmInfo->manufactura[i] = data[64 + i];
 327         }
 328         printf ("\nThis RAM-Module is produced by:              %s\n",
 329                 dimmInfo->manufactura);
 330
 331 /* find Manul-ID of Dimm Module */
 332         for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
 333                 dimmInfo->modul_id[i] = data[73 + i];
 334         }
 335         printf ("The Module-ID of this RAM-Module is:           %s\n",
 336                 dimmInfo->modul_id);
 337
 338 /* find Vendor-Data of Dimm Module */
 339         for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
 340                 dimmInfo->vendor_data[i] = data[99 + i];
 341         }
 342         printf ("Vendor Data of this RAM-Module is:             %s\n",
 343                 dimmInfo->vendor_data);
 344
 345 /* find modul_serial_no of Dimm Module */
 346         dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
 347         printf ("Serial No. of this RAM-Module is:              %ld (%lx)\n",
 348                 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
 349
 350 /* find Manufac-Data of Dimm Module */
 351         dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
 352         printf ("Manufactoring Date of this RAM-Module is:      %d.%d\n", data[93], data[94]);  /*dimmInfo->manufac_date */
 353
 354 /* find modul_revision of Dimm Module */
 355         dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
 356         printf ("Module Revision of this RAM-Module is:                 %d.%d\n", data[91], data[92]);  /* dimmInfo->modul_revision */
 357
 358 /* find manufac_place of Dimm Module */
 359         dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
 360         printf ("manufac_place of this RAM-Module is:           %d\n",
 361                 dimmInfo->manufac_place);
 362
 363 #endif
 364
 365 /*------------------------------------------------------------------------------------------------------------------------------*/
 366 /* calculate SPD checksum */
 367 /*------------------------------------------------------------------------------------------------------------------------------*/
 368         spd_checksum = 0;
 369
 370         for (i = 0; i <= 62; i++) {
 371                 spd_checksum += data[i];
 372         }
 373
 374         if ((spd_checksum & 0xff) != data[63]) {
 375                 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
 376                 hang ();
 377         }
 378
 379         else
 380                 printf ("SPD Checksum ok!\n");
 381
 382
 383 /*------------------------------------------------------------------------------------------------------------------------------*/
 384         for (i = 2; i <= 35; i++) {
 385                 switch (i) {
 386                 case 2: /* Memory type (DDR / SDRAM) */
 387                         dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
 388 #ifdef DEBUG
 389                         if (dimmInfo->memoryType == 0)
 390                                 DP (printf
 391                                     ("Dram_type in slot %d is:                  SDRAM\n",
 392                                      dimmInfo->slot));
 393                         if (dimmInfo->memoryType == 1)
 394                                 DP (printf
 395                                     ("Dram_type in slot %d is:                  DDRAM\n",
 396                                      dimmInfo->slot));
 397 #endif
 398                         break;
 399 /*------------------------------------------------------------------------------------------------------------------------------*/
 400
 401                 case 3: /* Number Of Row Addresses */
 402                         dimmInfo->numOfRowAddresses = data[i];
 403                         DP (printf
 404                             ("Module Number of row addresses:           %d\n",
 405                              dimmInfo->numOfRowAddresses));
 406                         break;
 407 /*------------------------------------------------------------------------------------------------------------------------------*/
 408
 409                 case 4: /* Number Of Column Addresses */
 410                         dimmInfo->numOfColAddresses = data[i];
 411                         DP (printf
 412                             ("Module Number of col addresses:           %d\n",
 413                              dimmInfo->numOfColAddresses));
 414                         break;
 415 /*------------------------------------------------------------------------------------------------------------------------------*/
 416
 417                 case 5: /* Number Of Module Banks */
 418                         dimmInfo->numOfModuleBanks = data[i];
 419                         DP (printf
 420                             ("Number of Banks on Mod. :                                 %d\n",
 421                              dimmInfo->numOfModuleBanks));
 422                         break;
 423 /*------------------------------------------------------------------------------------------------------------------------------*/
 424
 425                 case 6: /* Data Width */
 426                         dimmInfo->dataWidth = data[i];
 427                         DP (printf
 428                             ("Module Data Width:                                %d\n",
 429                              dimmInfo->dataWidth));
 430                         break;
 431 /*------------------------------------------------------------------------------------------------------------------------------*/
 432
 433                 case 8: /* Voltage Interface */
 434                         switch (data[i]) {
 435                         case 0x0:
 436                                 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
 437                                 DP (printf
 438                                     ("Module is                                         TTL_5V_TOLERANT\n"));
 439                                 break;
 440                         case 0x1:
 441                                 dimmInfo->voltageInterface = LVTTL;
 442                                 DP (printf
 443                                     ("Module is                                         LVTTL\n"));
 444                                 break;
 445                         case 0x2:
 446                                 dimmInfo->voltageInterface = HSTL_1_5V;
 447                                 DP (printf
 448                                     ("Module is                                         TTL_5V_TOLERANT\n"));
 449                                 break;
 450                         case 0x3:
 451                                 dimmInfo->voltageInterface = SSTL_3_3V;
 452                                 DP (printf
 453                                     ("Module is                                         HSTL_1_5V\n"));
 454                                 break;
 455                         case 0x4:
 456                                 dimmInfo->voltageInterface = SSTL_2_5V;
 457                                 DP (printf
 458                                     ("Module is                                         SSTL_2_5V\n"));
 459                                 break;
 460                         default:
 461                                 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
 462                                 DP (printf
 463                                     ("Module is                                         VOLTAGE_UNKNOWN\n"));
 464                                 break;
 465                         }
 466                         break;
 467 /*------------------------------------------------------------------------------------------------------------------------------*/
 468
 469                 case 9: /* Minimum Cycle Time At Max CasLatancy */
 470                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 471                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 472                         maskLeftOfPoint =
 473                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 474                         maskRightOfPoint =
 475                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 476                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 477                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 478                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
 479                                 leftOfPoint;
 480                         dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
 481                                 rightOfPoint;
 482                         DP (printf
 483                             ("Minimum Cycle Time At Max CasLatancy:             %d.%d [ns]\n",
 484                              leftOfPoint, rightOfPoint));
 485                         break;
 486 /*------------------------------------------------------------------------------------------------------------------------------*/
 487
 488                 case 10:        /* Clock To Data Out */
 489                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 490                         time_tmp =
 491                                 (((data[i] & 0xf0) >> 4) * 10) +
 492                                 ((data[i] & 0x0f));
 493                         leftOfPoint = time_tmp / div;
 494                         rightOfPoint = time_tmp % div;
 495                         dimmInfo->clockToDataOut_LoP = leftOfPoint;
 496                         dimmInfo->clockToDataOut_RoP = rightOfPoint;
 497                         DP (printf ("Clock To Data Out:                                 %d.%2d [ns]\n", leftOfPoint, rightOfPoint));    /*dimmInfo->clockToDataOut */
 498                         break;
 499 /*------------------------------------------------------------------------------------------------------------------------------*/
 500
 501 /*#ifdef CONFIG_ECC */
 502                 case 11:        /* Error Check Type */
 503                         dimmInfo->errorCheckType = data[i];
 504                         DP (printf
 505                             ("Error Check Type (0=NONE):                        %d\n",
 506                              dimmInfo->errorCheckType));
 507                         break;
 508 /* #endif */
 509 /*------------------------------------------------------------------------------------------------------------------------------*/
 510
 511                 case 12:        /* Refresh Interval */
 512                         dimmInfo->RefreshInterval = data[i];
 513                         DP (printf
 514                             ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
 515                              dimmInfo->RefreshInterval));
 516                         break;
 517 /*------------------------------------------------------------------------------------------------------------------------------*/
 518
 519                 case 13:        /* Sdram Width */
 520                         dimmInfo->sdramWidth = data[i];
 521                         DP (printf
 522                             ("Sdram Width:                                      %d\n",
 523                              dimmInfo->sdramWidth));
 524                         break;
 525 /*------------------------------------------------------------------------------------------------------------------------------*/
 526
 527                 case 14:        /* Error Check Data Width */
 528                         dimmInfo->errorCheckDataWidth = data[i];
 529                         DP (printf
 530                             ("Error Check Data Width:                   %d\n",
 531                              dimmInfo->errorCheckDataWidth));
 532                         break;
 533 /*------------------------------------------------------------------------------------------------------------------------------*/
 534
 535                 case 15:        /* Minimum Clock Delay */
 536                         dimmInfo->minClkDelay = data[i];
 537                         DP (printf
 538                             ("Minimum Clock Delay:                              %d\n",
 539                              dimmInfo->minClkDelay));
 540                         break;
 541 /*------------------------------------------------------------------------------------------------------------------------------*/
 542
 543                 case 16:        /* Burst Length Supported */
 544                            /******-******-******-*******
 545                            * bit3 | bit2 | bit1 | bit0 *
 546                            *******-******-******-*******
 547             burst length = *  8   |  4   |   2  |   1  *
 548                            *****************************
 549
 550             If for example bit0 and bit2 are set, the burst
 551             length supported are 1 and 4. */
 552
 553                         dimmInfo->burstLengthSupported = data[i];
 554 #ifdef DEBUG
 555                         DP (printf
 556                             ("Burst Length Supported:                   "));
 557                         if (dimmInfo->burstLengthSupported & 0x01)
 558                                 DP (printf ("1, "));
 559                         if (dimmInfo->burstLengthSupported & 0x02)
 560                                 DP (printf ("2, "));
 561                         if (dimmInfo->burstLengthSupported & 0x04)
 562                                 DP (printf ("4, "));
 563                         if (dimmInfo->burstLengthSupported & 0x08)
 564                                 DP (printf ("8, "));
 565                         DP (printf (" Bit \n"));
 566 #endif
 567                         break;
 568 /*------------------------------------------------------------------------------------------------------------------------------*/
 569
 570                 case 17:        /* Number Of Banks On Each Device */
 571                         dimmInfo->numOfBanksOnEachDevice = data[i];
 572                         DP (printf
 573                             ("Number Of Banks On Each Chip:                     %d\n",
 574                              dimmInfo->numOfBanksOnEachDevice));
 575                         break;
 576 /*------------------------------------------------------------------------------------------------------------------------------*/
 577
 578                 case 18:        /* Suported Cas Latencies */
 579
 580                         /*     DDR:
 581                          *******-******-******-******-******-******-******-*******
 582                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 583                          *******-******-******-******-******-******-******-*******
 584                          CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
 585                          *********************************************************
 586                          SDRAM:
 587                          *******-******-******-******-******-******-******-*******
 588                          * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 589                          *******-******-******-******-******-******-******-*******
 590                          CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
 591                          ********************************************************/
 592                         dimmInfo->suportedCasLatencies = data[i];
 593 #ifdef DEBUG
 594                         DP (printf
 595                             ("Suported Cas Latencies: (CL)                      "));
 596                         if (dimmInfo->memoryType == 0) {        /* SDRAM */
 597                                 for (k = 0; k <= 7; k++) {
 598                                         if (dimmInfo->
 599                                             suportedCasLatencies & (1 << k))
 600                                                 DP (printf
 601                                                     ("%d,                       ",
 602                                                      k + 1));
 603                                 }
 604
 605                         } else {        /* DDR-RAM */
 606
 607                                 if (dimmInfo->suportedCasLatencies & 1)
 608                                         DP (printf ("1, "));
 609                                 if (dimmInfo->suportedCasLatencies & 2)
 610                                         DP (printf ("1.5, "));
 611                                 if (dimmInfo->suportedCasLatencies & 4)
 612                                         DP (printf ("2, "));
 613                                 if (dimmInfo->suportedCasLatencies & 8)
 614                                         DP (printf ("2.5, "));
 615                                 if (dimmInfo->suportedCasLatencies & 16)
 616                                         DP (printf ("3, "));
 617                                 if (dimmInfo->suportedCasLatencies & 32)
 618                                         DP (printf ("3.5, "));
 619
 620                         }
 621                         DP (printf ("\n"));
 622 #endif
 623                         /* Calculating MAX CAS latency */
 624                         for (j = 7; j > 0; j--) {
 625                                 if (((dimmInfo->
 626                                       suportedCasLatencies >> j) & 0x1) ==
 627                                     1) {
 628                                         switch (dimmInfo->memoryType) {
 629                                         case DDR:
 630                                                 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
 631                                                 switch (j) {
 632                                                 case 7:
 633                                                         DP (printf
 634                                                             ("Max. Cas Latencies (DDR):                         ERROR !!!\n"));
 635                                                         dimmInfo->
 636                                                                 maxClSupported_DDR
 637                                                                 =
 638                                                                 DDR_CL_FAULT;
 639                                                         hang ();
 640                                                         break;
 641                                                 case 6:
 642                                                         DP (printf
 643                                                             ("Max. Cas Latencies (DDR):                         ERROR !!!\n"));
 644                                                         dimmInfo->
 645                                                                 maxClSupported_DDR
 646                                                                 =
 647                                                                 DDR_CL_FAULT;
 648                                                         hang ();
 649                                                         break;
 650                                                 case 5:
 651                                                         DP (printf
 652                                                             ("Max. Cas Latencies (DDR):                         3.5 clk's\n"));
 653                                                         dimmInfo->
 654                                                                 maxClSupported_DDR
 655                                                                 = DDR_CL_3_5;
 656                                                         break;
 657                                                 case 4:
 658                                                         DP (printf
 659                                                             ("Max. Cas Latencies (DDR):                         3 clk's \n"));
 660                                                         dimmInfo->
 661                                                                 maxClSupported_DDR
 662                                                                 = DDR_CL_3;
 663                                                         break;
 664                                                 case 3:
 665                                                         DP (printf
 666                                                             ("Max. Cas Latencies (DDR):                         2.5 clk's \n"));
 667                                                         dimmInfo->
 668                                                                 maxClSupported_DDR
 669                                                                 = DDR_CL_2_5;
 670                                                         break;
 671                                                 case 2:
 672                                                         DP (printf
 673                                                             ("Max. Cas Latencies (DDR):                         2 clk's \n"));
 674                                                         dimmInfo->
 675                                                                 maxClSupported_DDR
 676                                                                 = DDR_CL_2;
 677                                                         break;
 678                                                 case 1:
 679                                                         DP (printf
 680                                                             ("Max. Cas Latencies (DDR):                         1.5 clk's \n"));
 681                                                         dimmInfo->
 682                                                                 maxClSupported_DDR
 683                                                                 = DDR_CL_1_5;
 684                                                         break;
 685                                                 }
 686
 687                                                 /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
 688                                                    lower then our SDRAM cycle count, we won't be able to support this CAL
 689                                                    and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
 690                                                 if ((dimmInfo->
 691                                                      minimumCycleTimeAtMaxCasLatancy_LoP
 692                                                      <
 693                                                      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
 694                                                     ||
 695                                                     ((dimmInfo->
 696                                                       minimumCycleTimeAtMaxCasLatancy_LoP
 697                                                       ==
 698                                                       CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
 699                                                      && (dimmInfo->
 700                                                          minimumCycleTimeAtMaxCasLatancy_RoP
 701                                                          <
 702                                                          CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
 703                                                 {
 704                                                         dimmInfo->
 705                                                                 maxClSupported_DDR
 706                                                                 =
 707                                                                 dimmInfo->
 708                                                                 maxClSupported_DDR
 709                                                                 >> 1;
 710                                                         DP (printf
 711                                                             ("*** Change actual Cas Latencies cause of minimumCycleTime n"));
 712                                                 }
 713                                                 /* ronen - checkif the Dimm frequency compared to the Sysclock. */
 714                                                 if ((dimmInfo->
 715                                                      minimumCycleTimeAtMaxCasLatancy_LoP
 716                                                      >
 717                                                      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
 718                                                     ||
 719                                                     ((dimmInfo->
 720                                                       minimumCycleTimeAtMaxCasLatancy_LoP
 721                                                       ==
 722                                                       CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
 723                                                      && (dimmInfo->
 724                                                          minimumCycleTimeAtMaxCasLatancy_RoP
 725                                                          >
 726                                                          CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
 727                                                 {
 728                                                         printf ("*********************************************************\n");
 729                                                         printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
 730                                                         printf ("*********************************************************\n");
 731                                                         hang ();
 732                                                 }
 733
 734                                                 dimmInfo->
 735                                                         maxCASlatencySupported_LoP
 736                                                         =
 737                                                         1 +
 738                                                         (int) (5 * j / 10);
 739                                                 if (((5 * j) % 10) != 0)
 740                                                         dimmInfo->
 741                                                                 maxCASlatencySupported_RoP
 742                                                                 = 5;
 743                                                 else
 744                                                         dimmInfo->
 745                                                                 maxCASlatencySupported_RoP
 746                                                                 = 0;
 747                                                 DP (printf
 748                                                     ("Max. Cas Latencies (DDR LoP.RoP Notation):        %d.%d \n",
 749                                                      dimmInfo->
 750                                                      maxCASlatencySupported_LoP,
 751                                                      dimmInfo->
 752                                                      maxCASlatencySupported_RoP));
 753                                                 break;
 754                                         case SDRAM:
 755                                                 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
 756                                                 dimmInfo->maxClSupported_SD = j;        /*  Cas Latency DDR-RAM Coded                   */
 757                                                 DP (printf
 758                                                     ("Max. Cas Latencies (SD): %d\n",
 759                                                      dimmInfo->
 760                                                      maxClSupported_SD));
 761                                                 dimmInfo->
 762                                                         maxCASlatencySupported_LoP
 763                                                         = j;
 764                                                 dimmInfo->
 765                                                         maxCASlatencySupported_RoP
 766                                                         = 0;
 767                                                 DP (printf
 768                                                     ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
 769                                                      dimmInfo->
 770                                                      maxCASlatencySupported_LoP,
 771                                                      dimmInfo->
 772                                                      maxCASlatencySupported_RoP));
 773                                                 break;
 774                                         }
 775                                         break;
 776                                 }
 777                         }
 778                         break;
 779 /*------------------------------------------------------------------------------------------------------------------------------*/
 780
 781                 case 21:        /* Buffered Address And Control Inputs */
 782                         DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
 783                         dimmInfo->bufferedAddrAndControlInputs =
 784                                 data[i] & BIT0;
 785                         dimmInfo->registeredAddrAndControlInputs =
 786                                 (data[i] & BIT1) >> 1;
 787                         dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
 788                         dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
 789                         dimmInfo->registeredDQMBinputs =
 790                                 (data[i] & BIT4) >> 4;
 791                         dimmInfo->differentialClockInput =
 792                                 (data[i] & BIT5) >> 5;
 793                         dimmInfo->redundantRowAddressing =
 794                                 (data[i] & BIT6) >> 6;
 795 #ifdef DEBUG
 796                         if (dimmInfo->bufferedAddrAndControlInputs == 1)
 797                                 DP (printf
 798                                     (" - Buffered Address/Control Input:                Yes \n"));
 799                         else
 800                                 DP (printf
 801                                     (" - Buffered Address/Control Input:                No \n"));
 802
 803                         if (dimmInfo->registeredAddrAndControlInputs == 1)
 804                                 DP (printf
 805                                     (" - Registered Address/Control Input:              Yes \n"));
 806                         else
 807                                 DP (printf
 808                                     (" - Registered Address/Control Input:              No \n"));
 809
 810                         if (dimmInfo->onCardPLL == 1)
 811                                 DP (printf
 812                                     (" - On-Card PLL (clock):                           Yes \n"));
 813                         else
 814                                 DP (printf
 815                                     (" - On-Card PLL (clock):                           No \n"));
 816
 817                         if (dimmInfo->bufferedDQMBinputs == 1)
 818                                 DP (printf
 819                                     (" - Bufferd DQMB Inputs:                           Yes \n"));
 820                         else
 821                                 DP (printf
 822                                     (" - Bufferd DQMB Inputs:                           No \n"));
 823
 824                         if (dimmInfo->registeredDQMBinputs == 1)
 825                                 DP (printf
 826                                     (" - Registered DQMB Inputs:                        Yes \n"));
 827                         else
 828                                 DP (printf
 829                                     (" - Registered DQMB Inputs:                        No \n"));
 830
 831                         if (dimmInfo->differentialClockInput == 1)
 832                                 DP (printf
 833                                     (" - Differential Clock Input:                      Yes \n"));
 834                         else
 835                                 DP (printf
 836                                     (" - Differential Clock Input:                      No \n"));
 837
 838                         if (dimmInfo->redundantRowAddressing == 1)
 839                                 DP (printf
 840                                     (" - redundant Row Addressing:                      Yes \n"));
 841                         else
 842                                 DP (printf
 843                                     (" - redundant Row Addressing:                      No \n"));
 844
 845 #endif
 846                         break;
 847 /*------------------------------------------------------------------------------------------------------------------------------*/
 848
 849                 case 22:        /* Suported AutoPreCharge */
 850                         DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
 851                         dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
 852                         dimmInfo->suportedAutoPreCharge =
 853                                 (data[i] & BIT1) >> 1;
 854                         dimmInfo->suportedPreChargeAll =
 855                                 (data[i] & BIT2) >> 2;
 856                         dimmInfo->suportedWrite1ReadBurst =
 857                                 (data[i] & BIT3) >> 3;
 858                         dimmInfo->suported5PercentLowVCC =
 859                                 (data[i] & BIT4) >> 4;
 860                         dimmInfo->suported5PercentUpperVCC =
 861                                 (data[i] & BIT5) >> 5;
 862 #ifdef DEBUG
 863                         if (dimmInfo->suportedEarlyRasPreCharge == 1)
 864                                 DP (printf
 865                                     (" - Early Ras Precharge:                   Yes \n"));
 866                         else
 867                                 DP (printf
 868                                     (" -  Early Ras Precharge:                  No \n"));
 869
 870                         if (dimmInfo->suportedAutoPreCharge == 1)
 871                                 DP (printf
 872                                     (" - AutoPreCharge:                         Yes \n"));
 873                         else
 874                                 DP (printf
 875                                     (" -  AutoPreCharge:                                No \n"));
 876
 877                         if (dimmInfo->suportedPreChargeAll == 1)
 878                                 DP (printf
 879                                     (" - Precharge All:                         Yes \n"));
 880                         else
 881                                 DP (printf
 882                                     (" -  Precharge All:                                No \n"));
 883
 884                         if (dimmInfo->suportedWrite1ReadBurst == 1)
 885                                 DP (printf
 886                                     (" - Write 1/ReadBurst:                             Yes \n"));
 887                         else
 888                                 DP (printf
 889                                     (" -  Write 1/ReadBurst:                            No \n"));
 890
 891                         if (dimmInfo->suported5PercentLowVCC == 1)
 892                                 DP (printf
 893                                     (" - lower VCC tolerance:                   5 Percent \n"));
 894                         else
 895                                 DP (printf
 896                                     ("  - lower VCC tolerance:                  10 Percent \n"));
 897
 898                         if (dimmInfo->suported5PercentUpperVCC == 1)
 899                                 DP (printf
 900                                     (" - upper VCC tolerance:                   5 Percent \n"));
 901                         else
 902                                 DP (printf
 903                                     (" -  upper VCC tolerance:                  10 Percent \n"));
 904
 905 #endif
 906                         break;
 907 /*------------------------------------------------------------------------------------------------------------------------------*/
 908
 909                 case 23:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
 910                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 911                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 912                         maskLeftOfPoint =
 913                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 914                         maskRightOfPoint =
 915                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 916                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 917                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 918                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
 919                                 leftOfPoint;
 920                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
 921                                 rightOfPoint;
 922                         DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));      /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 923                         break;
 924 /*------------------------------------------------------------------------------------------------------------------------------*/
 925
 926                 case 24:        /* Clock To Data Out 2nd highest Cas Latency Value */
 927                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 928                         time_tmp =
 929                                 (((data[i] & 0xf0) >> 4) * 10) +
 930                                 ((data[i] & 0x0f));
 931                         leftOfPoint = time_tmp / div;
 932                         rightOfPoint = time_tmp % div;
 933                         dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
 934                         dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
 935                         DP (printf
 936                             ("Clock To Data Out (2nd CL value):                 %d.%2d [ns]\n",
 937                              leftOfPoint, rightOfPoint));
 938                         break;
 939 /*------------------------------------------------------------------------------------------------------------------------------*/
 940
 941                 case 25:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
 942                         shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 943                         mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 944                         maskLeftOfPoint =
 945                                 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 946                         maskRightOfPoint =
 947                                 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 948                         leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 949                         rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 950                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
 951                                 leftOfPoint;
 952                         dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
 953                                 rightOfPoint;
 954                         DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));      /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 955                         break;
 956 /*------------------------------------------------------------------------------------------------------------------------------*/
 957
 958                 case 26:        /* Clock To Data Out 3rd highest Cas Latency Value */
 959                         div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 960                         time_tmp =
 961                                 (((data[i] & 0xf0) >> 4) * 10) +
 962                                 ((data[i] & 0x0f));
 963                         leftOfPoint = time_tmp / div;
 964                         rightOfPoint = time_tmp % div;
 965                         dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
 966                         dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
 967                         DP (printf
 968                             ("Clock To Data Out (3rd CL value):                 %d.%2d [ns]\n",
 969                              leftOfPoint, rightOfPoint));
 970                         break;
 971 /*------------------------------------------------------------------------------------------------------------------------------*/
 972
 973                 case 27:        /* Minimum Row Precharge Time */
 974                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 975                         maskLeftOfPoint =
 976                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 977                         maskRightOfPoint =
 978                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 979                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 980                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 981
 982                         dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);   /* measured in n times 10ps Intervals */
 983                         trp_clocks =
 984                                 (dimmInfo->minRowPrechargeTime +
 985                                  (tmemclk - 1)) / tmemclk;
 986                         DP (printf
 987                             ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
 988                              tmemclk, tmemclk / 100, tmemclk % 100));
 989                         DP (printf
 990                             ("Minimum Row Precharge Time [ns]:          %d.%2d = in Clk cycles %d\n",
 991                              leftOfPoint, rightOfPoint, trp_clocks));
 992                         break;
 993 /*------------------------------------------------------------------------------------------------------------------------------*/
 994
 995                 case 28:        /* Minimum Row Active to Row Active Time */
 996                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 997                         maskLeftOfPoint =
 998                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 999                         maskRightOfPoint =
1000                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1001                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1002                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1003
1004                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
1005                         trrd_clocks =
1006                                 (dimmInfo->minRowActiveRowActiveDelay +
1007                                  (tmemclk - 1)) / tmemclk;
1008                         DP (printf
1009                             ("Minimum Row Active -To- Row Active Delay [ns]:    %d.%2d = in Clk cycles %d\n",
1010                              leftOfPoint, rightOfPoint, trp_clocks));
1011                         break;
1012 /*------------------------------------------------------------------------------------------------------------------------------*/
1013
1014                 case 29:        /* Minimum Ras-To-Cas Delay */
1015                         shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
1016                         maskLeftOfPoint =
1017                                 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
1018                         maskRightOfPoint =
1019                                 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
1020                         leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
1021                         rightOfPoint = (data[i] & maskRightOfPoint) * 25;
1022
1023                         dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
1024                         trcd_clocks =
1025                                 (dimmInfo->minRowActiveRowActiveDelay +
1026                                  (tmemclk - 1)) / tmemclk;
1027                         DP (printf
1028                             ("Minimum Ras-To-Cas Delay [ns]:                    %d.%2d = in Clk cycles %d\n",
1029                              leftOfPoint, rightOfPoint, trp_clocks));
1030                         break;
1031 /*------------------------------------------------------------------------------------------------------------------------------*/
1032
1033                 case 30:        /* Minimum Ras Pulse Width */
1034                         dimmInfo->minRasPulseWidth = data[i];
1035                         tras_clocks =
1036                                 (NSto10PS (data[i]) +
1037                                  (tmemclk - 1)) / tmemclk;
1038                         DP (printf
1039                             ("Minimum Ras Pulse Width [ns]:                     %d = in Clk cycles %d\n",
1040                              dimmInfo->minRasPulseWidth, tras_clocks));
1041
1042                         break;
1043 /*------------------------------------------------------------------------------------------------------------------------------*/
1044
1045                 case 31:        /* Module Bank Density */
1046                         dimmInfo->moduleBankDensity = data[i];
1047                         DP (printf
1048                             ("Module Bank Density:                              %d\n",
1049                              dimmInfo->moduleBankDensity));
1050 #ifdef DEBUG
1051                         DP (printf
1052                             ("*** Offered Densities (more than 1 = Multisize-Module): "));
1053                         {
1054                                 if (dimmInfo->moduleBankDensity & 1)
1055                                         DP (printf ("4MB, "));
1056                                 if (dimmInfo->moduleBankDensity & 2)
1057                                         DP (printf ("8MB, "));
1058                                 if (dimmInfo->moduleBankDensity & 4)
1059                                         DP (printf ("16MB, "));
1060                                 if (dimmInfo->moduleBankDensity & 8)
1061                                         DP (printf ("32MB, "));
1062                                 if (dimmInfo->moduleBankDensity & 16)
1063                                         DP (printf ("64MB, "));
1064                                 if (dimmInfo->moduleBankDensity & 32)
1065                                         DP (printf ("128MB, "));
1066                                 if ((dimmInfo->moduleBankDensity & 64)
1067                                     || (dimmInfo->moduleBankDensity & 128)) {
1068                                         DP (printf ("ERROR, "));
1069                                         hang ();
1070                                 }
1071                         }
1072                         DP (printf ("\n"));
1073 #endif
1074                         break;
1075 /*------------------------------------------------------------------------------------------------------------------------------*/
1076
1077                 case 32:        /* Address And Command Setup Time (measured in ns/1000) */
1078                         sign = 1;
1079                         switch (dimmInfo->memoryType) {
1080                         case DDR:
1081                                 time_tmp =
1082                                         (((data[i] & 0xf0) >> 4) * 10) +
1083                                         ((data[i] & 0x0f));
1084                                 leftOfPoint = time_tmp / 100;
1085                                 rightOfPoint = time_tmp % 100;
1086                                 break;
1087                         case SDRAM:
1088                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1089                                 if (leftOfPoint > 7) {
1090                                         leftOfPoint = data[i] & 0x70 >> 4;
1091                                         sign = -1;
1092                                 }
1093                                 rightOfPoint = (data[i] & 0x0f);
1094                                 break;
1095                         }
1096                         dimmInfo->addrAndCommandSetupTime =
1097                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1098                         DP (printf
1099                             ("Address And Command Setup Time [ns]:              %d.%d\n",
1100                              sign * leftOfPoint, rightOfPoint));
1101                         break;
1102 /*------------------------------------------------------------------------------------------------------------------------------*/
1103
1104                 case 33:        /* Address And Command Hold Time */
1105                         sign = 1;
1106                         switch (dimmInfo->memoryType) {
1107                         case DDR:
1108                                 time_tmp =
1109                                         (((data[i] & 0xf0) >> 4) * 10) +
1110                                         ((data[i] & 0x0f));
1111                                 leftOfPoint = time_tmp / 100;
1112                                 rightOfPoint = time_tmp % 100;
1113                                 break;
1114                         case SDRAM:
1115                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1116                                 if (leftOfPoint > 7) {
1117                                         leftOfPoint = data[i] & 0x70 >> 4;
1118                                         sign = -1;
1119                                 }
1120                                 rightOfPoint = (data[i] & 0x0f);
1121                                 break;
1122                         }
1123                         dimmInfo->addrAndCommandHoldTime =
1124                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1125                         DP (printf
1126                             ("Address And Command Hold Time [ns]:               %d.%d\n",
1127                              sign * leftOfPoint, rightOfPoint));
1128                         break;
1129 /*------------------------------------------------------------------------------------------------------------------------------*/
1130
1131                 case 34:        /* Data Input Setup Time */
1132                         sign = 1;
1133                         switch (dimmInfo->memoryType) {
1134                         case DDR:
1135                                 time_tmp =
1136                                         (((data[i] & 0xf0) >> 4) * 10) +
1137                                         ((data[i] & 0x0f));
1138                                 leftOfPoint = time_tmp / 100;
1139                                 rightOfPoint = time_tmp % 100;
1140                                 break;
1141                         case SDRAM:
1142                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1143                                 if (leftOfPoint > 7) {
1144                                         leftOfPoint = data[i] & 0x70 >> 4;
1145                                         sign = -1;
1146                                 }
1147                                 rightOfPoint = (data[i] & 0x0f);
1148                                 break;
1149                         }
1150                         dimmInfo->dataInputSetupTime =
1151                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1152                         DP (printf
1153                             ("Data Input Setup Time [ns]:                       %d.%d\n",
1154                              sign * leftOfPoint, rightOfPoint));
1155                         break;
1156 /*------------------------------------------------------------------------------------------------------------------------------*/
1157
1158                 case 35:        /* Data Input Hold Time */
1159                         sign = 1;
1160                         switch (dimmInfo->memoryType) {
1161                         case DDR:
1162                                 time_tmp =
1163                                         (((data[i] & 0xf0) >> 4) * 10) +
1164                                         ((data[i] & 0x0f));
1165                                 leftOfPoint = time_tmp / 100;
1166                                 rightOfPoint = time_tmp % 100;
1167                                 break;
1168                         case SDRAM:
1169                                 leftOfPoint = (data[i] & 0xf0) >> 4;
1170                                 if (leftOfPoint > 7) {
1171                                         leftOfPoint = data[i] & 0x70 >> 4;
1172                                         sign = -1;
1173                                 }
1174                                 rightOfPoint = (data[i] & 0x0f);
1175                                 break;
1176                         }
1177                         dimmInfo->dataInputHoldTime =
1178                                 (leftOfPoint * 100 + rightOfPoint) * sign;
1179                         DP (printf
1180                             ("Data Input Hold Time [ns]:                        %d.%d\n\n",
1181                              sign * leftOfPoint, rightOfPoint));
1182                         break;
1183 /*------------------------------------------------------------------------------------------------------------------------------*/
1184                 }
1185         }
1186         /* calculating the sdram density */
1187         for (i = 0;
1188              i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1189              i++) {
1190                 density = density * 2;
1191         }
1192         dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1193                 dimmInfo->sdramWidth;
1194         dimmInfo->numberOfDevices =
1195                 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1196                 dimmInfo->numOfModuleBanks;
1197         devicesForErrCheck =
1198                 (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1199         if ((dimmInfo->errorCheckType == 0x1)
1200             || (dimmInfo->errorCheckType == 0x2)
1201             || (dimmInfo->errorCheckType == 0x3)) {
1202                 dimmInfo->size =
1203                         (dimmInfo->deviceDensity / 8) *
1204                         (dimmInfo->numberOfDevices -
1205                          /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
1206                          dimmInfo->numberOfDevices / 8);
1207         } else {
1208                 dimmInfo->size =
1209                         (dimmInfo->deviceDensity / 8) *
1210                         dimmInfo->numberOfDevices;
1211         }
1212
1213         /* compute the module DRB size */
1214         tmp = (1 <<
1215                (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1216         tmp *= dimmInfo->numOfModuleBanks;
1217         tmp *= dimmInfo->sdramWidth;
1218         tmp = tmp >> 24;        /* div by 0x4000000 (64M)       */
1219         dimmInfo->drb_size = (uchar) tmp;
1220         DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
1221
1222         /* try a CAS latency of 3 first... */
1223
1224         /* bit 1 is CL2, bit 2 is CL3 */
1225         supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
1226
1227         cal_val = 0;
1228         if (supp_cal & 3) {
1229                 if (NS10to10PS (data[9]) <= tmemclk)
1230                         cal_val = 3;
1231         }
1232
1233         /* then 2... */
1234         if (supp_cal & 2) {
1235                 if (NS10to10PS (data[23]) <= tmemclk)
1236                         cal_val = 2;
1237         }
1238
1239         DP (printf ("cal_val = %d\n", cal_val));
1240
1241         /* bummer, did't work... */
1242         if (cal_val == 0) {
1243                 DP (printf ("Couldn't find a good CAS latency\n"));
1244                 hang ();
1245                 return 0;
1246         }
1247
1248         return true;
1249 #endif
1250 }
1251
1252 /* sets up the GT properly with information passed in */
1253 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1254 {
1255         ulong tmp, check;
1256         ulong tmp_sdram_mode = 0;       /* 0x141c */
1257         ulong tmp_dunit_control_low = 0;        /* 0x1404 */
1258         int i;
1259
1260         /* added 8/21/2003 P. Marchese */
1261         unsigned int sdram_config_reg;
1262
1263         /* added 10/10/2003 P. Marchese */
1264         ulong sdram_chip_size;
1265
1266         /* sanity checking */
1267         if (!info->numOfModuleBanks) {
1268                 printf ("setup_sdram called with 0 banks\n");
1269                 return 1;
1270         }
1271
1272         /* delay line */
1273         set_dfcdlInit ();       /* may be its not needed */
1274         DP (printf ("Delay line set done\n"));
1275
1276         /* set SDRAM mode NOP */ /* To_do check it */
1277         GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1278         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1279                 DP (printf
1280                     ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
1281         }
1282
1283         /* SDRAM configuration */
1284 /* added 8/21/2003 P. Marchese */
1285 /* code allows usage of registered DIMMS */
1286
1287         /* figure out the memory refresh internal */
1288         switch (info->RefreshInterval) {
1289         case 0x0:
1290         case 0x80:              /* refresh period is 15.625 usec */
1291                 sdram_config_reg =
1292                         (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
1293                                         / (float) 1000000.0);
1294                 break;
1295         case 0x1:
1296         case 0x81:              /* refresh period is 3.9 usec */
1297                 sdram_config_reg =
1298                         (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
1299                                         (float) 1000000.0);
1300                 break;
1301         case 0x2:
1302         case 0x82:              /* refresh period is 7.8 usec */
1303                 sdram_config_reg =
1304                         (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
1305                                         (float) 1000000.0);
1306                 break;
1307         case 0x3:
1308         case 0x83:              /* refresh period is 31.3 usec */
1309                 sdram_config_reg =
1310                         (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
1311                                         (float) 1000000.0);
1312                 break;
1313         case 0x4:
1314         case 0x84:              /* refresh period is 62.5 usec */
1315                 sdram_config_reg =
1316                         (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
1317                                         (float) 1000000.0);
1318                 break;
1319         case 0x5:
1320         case 0x85:              /* refresh period is 125 usec */
1321                 sdram_config_reg =
1322                         (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
1323                                         (float) 1000000.0);
1324                 break;
1325         default:                /* refresh period undefined */
1326                 printf ("DRAM refresh period is unknown!\n");
1327                 printf ("Aborting DRAM setup with an error\n");
1328                 hang ();
1329                 break;
1330         }
1331         DP (printf ("calculated refresh interval %0x\n", sdram_config_reg));
1332
1333         /* make sure the refresh value is only 14 bits */
1334         if (sdram_config_reg > 0x1fff)
1335                 sdram_config_reg = 0x1fff;
1336         DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg));
1337
1338         /* we want physical bank interleaving and */
1339         /* virtual bank interleaving enabled so do nothing */
1340         /* since these bits need to be zero to enable the interleaving */
1341
1342         /*  registered DRAM ? */
1343         if (info->registeredAddrAndControlInputs == 1) {
1344                 /* it's registered DRAM, so set the reg. DRAM bit */
1345                 sdram_config_reg = sdram_config_reg | BIT17;
1346                 DP (printf ("Enabling registered DRAM bit\n"));
1347         }
1348         /* turn on DRAM ECC? */
1349 #ifdef CONFIG_MV64460_ECC
1350         if (info->errorCheckType == 0x2) {
1351                 /* DRAM has ECC, so turn it on */
1352                 sdram_config_reg = sdram_config_reg | BIT18;
1353                 DP (printf ("Enabling ECC\n"));
1354         }
1355 #endif
1356         /* set the data DQS pin configuration */
1357         switch (info->sdramWidth) {
1358         case 0x4:               /* memory is x4 */
1359                 sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
1360                 DP (printf ("Data DQS pins set for 16 pins\n"));
1361                 break;
1362         case 0x8:               /* memory is x8 or x16 */
1363         case 0x10:
1364                 sdram_config_reg = sdram_config_reg | BIT21;
1365                 DP (printf ("Data DQS pins set for 8 pins\n"));
1366                 break;
1367         case 0x20:              /* memory is x32 */
1368                 /* both bits are cleared for x32 so nothing to do */
1369                 DP (printf ("Data DQS pins set for 2 pins\n"));
1370                 break;
1371         default:                /* memory width unsupported */
1372                 printf ("DRAM chip width is unknown!\n");
1373                 printf ("Aborting DRAM setup with an error\n");
1374                 hang ();
1375                 break;
1376         }
1377
1378         /*ronen db64460 */
1379         /* perform read buffer assignments */
1380         /* we are going to use the Power-up defaults */
1381         /* bit 27 = PCI bus #0 = buffer 0 */
1382         /* bit 28 = PCI bus #1 = buffer 0 */
1383         /* bit 29 = MPSC = buffer 0 */
1384         /* bit 30 = IDMA = buffer 0 */
1385         /* bit 31 = Gigabit = buffer 0 */
1386         sdram_config_reg = sdram_config_reg | 0x58000000;
1387         sdram_config_reg = sdram_config_reg & 0xffffff00;
1388         /* bit 14 FBSplit = FCRAM controller bsplit enable. */
1389         /* bit 15 vw = FCRAM Variable write length enable.   */
1390         /* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */
1391         sdram_config_reg = sdram_config_reg | BIT14 | BIT15;
1392
1393         /* write the value into the SDRAM configuration register */
1394         GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
1395         DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
1396
1397         /* SDRAM open pages control keep open as much as I can */
1398         GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1399         DP (printf
1400             ("sdram_open_pages_controll 0x1414: %08x\n",
1401              GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
1402
1403         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1404         tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1405         if (tmp == 0)
1406                 DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
1407         else
1408                 DP (printf
1409                     ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
1410
1411         /* SDRAM set CAS Latency according to SPD information */
1412         switch (info->memoryType) {
1413         case SDRAM:
1414                 printf ("### SD-RAM not supported !!!\n");
1415                 printf ("Aborting!!!\n");
1416                 hang ();
1417                 /* ToDo fill SD-RAM if needed !!!!! */
1418                 break;
1419                 /* Calculate the settings for SDRAM mode and Dunit control low registers */
1420                 /* Values set according to technical bulletin TB-92 rev. c */
1421         case DDR:
1422                 DP (printf ("### SET-CL for DDR-RAM\n"));
1423                 /* ronen db64460 - change the tmp_dunit_control_low setting!!! */
1424                 switch (info->maxClSupported_DDR) {
1425                 case DDR_CL_3:
1426                         tmp_sdram_mode = 0x32;  /* CL=3 Burstlength = 4 */
1427                         if (tmp == 1) { /* clocks sync */
1428                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1429                                         tmp_dunit_control_low = 0x05110051;
1430                                 else
1431                                         tmp_dunit_control_low = 0x24110051;
1432                                 DP (printf
1433                                     ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1434                                      tmp_sdram_mode, tmp_dunit_control_low));
1435                                 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1436                         } else {        /* clk sync. bypassed   */
1437
1438                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1439                                         tmp_dunit_control_low = 0xC5000540;
1440                                 else
1441                                         tmp_dunit_control_low = 0xC4000540;
1442                                 DP (printf
1443                                     ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1444                                      tmp_sdram_mode, tmp_dunit_control_low));
1445                         }
1446                         break;
1447                 case DDR_CL_2_5:
1448                         tmp_sdram_mode = 0x62;  /* CL=2.5 Burstlength = 4 */
1449                         if (tmp == 1) { /* clocks sync */
1450                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1451                                         tmp_dunit_control_low = 0x25110051;
1452                                 else
1453                                         tmp_dunit_control_low = 0x24110051;
1454                                 DP (printf
1455                                     ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1456                                      tmp_sdram_mode, tmp_dunit_control_low));
1457                                 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1458                         } else {        /* clk sync. bypassed   */
1459
1460                                 if (info->registeredAddrAndControlInputs == 1) {        /* registerd DDR SDRAM? */
1461                                         tmp_dunit_control_low = 0xC5000540;
1462                                         /* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1463                                         /* printf("Aborting!!!\n");1 */
1464                                         /* hang();1 */
1465                                 } else
1466                                         tmp_dunit_control_low = 0xC4000540;
1467                                 DP (printf
1468                                     ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1469                                      tmp_sdram_mode, tmp_dunit_control_low));
1470                         }
1471                         break;
1472                 case DDR_CL_2:
1473                         tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1474                         if (tmp == 1) { /* clocks sync */
1475                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1476                                         tmp_dunit_control_low = 0x04110051;
1477                                 else
1478                                         tmp_dunit_control_low = 0x03110051;
1479                                 DP (printf
1480                                     ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1481                                      tmp_sdram_mode, tmp_dunit_control_low));
1482                                 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1483                         } else {        /* clk sync. bypassed   */
1484
1485                                 if (info->registeredAddrAndControlInputs == 1) {        /* registerd DDR SDRAM? */
1486                                         /*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1487                                         /*printf("Aborting!!!\n");1 */
1488                                         /*hang();1 */
1489                                         tmp_dunit_control_low = 0xC4000540;
1490                                 } else
1491                                         tmp_dunit_control_low = 0xC3000540;;
1492                                 DP (printf
1493                                     ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1494                                      tmp_sdram_mode, tmp_dunit_control_low));
1495                         }
1496                         break;
1497                 case DDR_CL_1_5:
1498                         tmp_sdram_mode = 0x52;  /* CL=1.5 Burstlength = 4 */
1499                         if (tmp == 1) { /* clocks sync */
1500                                 if (info->registeredAddrAndControlInputs == 1)  /* registerd DDR SDRAM? */
1501                                         tmp_dunit_control_low = 0x24110051;
1502                                 else
1503                                         tmp_dunit_control_low = 0x23110051;
1504                                 DP (printf
1505                                     ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1506                                      tmp_sdram_mode, tmp_dunit_control_low));
1507                                 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1508                         } else {        /* clk sync. bypassed   */
1509
1510                                 if (info->registeredAddrAndControlInputs == 1) {        /* registerd DDR SDRAM? */
1511                                         /*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1512                                         /*printf("Aborting!!!\n");1 */
1513                                         /*hang();1 */
1514                                         tmp_dunit_control_low = 0xC4000540;
1515                                 } else
1516                                         tmp_dunit_control_low = 0xC3000540;
1517                                 DP (printf
1518                                     ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1519                                      tmp_sdram_mode, tmp_dunit_control_low));
1520                         }
1521                         break;
1522
1523                 default:
1524                         printf ("Max. CL is out of range %d\n",
1525                                 info->maxClSupported_DDR);
1526                         hang ();
1527                         break;
1528                 }               /* end DDR switch */
1529                 break;
1530         }                       /* end CL switch */
1531
1532         /* Write results of CL detection procedure */
1533         /* set SDRAM mode reg. 0x141c */
1534         GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1535
1536         /* set SDRAM mode SetCommand 0x1418 */
1537         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1538         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1539                 DP (printf
1540                     ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
1541         }
1542
1543         /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1544         GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
1545
1546         /* set SDRAM mode SetCommand 0x1418 */
1547         GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1548         while (GTREGREAD (SDRAM_OPERATION) != 0) {
1549                 DP (printf
1550                     ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
1551         }
1552
1553 /*------------------------------------------------------------------------------ */
1554
1555         /* bank parameters */
1556         /* SDRAM address decode register 0x1410 */
1557         /* program this with the default value */
1558         tmp = 0x02;             /* power-up default address select decoding value */
1559
1560         DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
1561 /* figure out the DRAM chip size */
1562         sdram_chip_size =
1563                 (1 << (info->numOfRowAddresses + info->numOfColAddresses));
1564         sdram_chip_size *= info->sdramWidth;
1565         sdram_chip_size *= 4;
1566         DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size));
1567         /* divide sdram chip size by 64 Mbits */
1568         sdram_chip_size = sdram_chip_size / 0x4000000;
1569         switch (sdram_chip_size) {
1570         case 1:         /* 64 Mbit */
1571         case 2:         /* 128 Mbit */
1572                 DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
1573                 tmp |= (0x00 << 4);
1574                 break;
1575         case 4:         /* 256 Mbit */
1576         case 8:         /* 512 Mbit */
1577                 DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
1578                 tmp |= (0x01 << 4);
1579                 break;
1580         case 16:                /* 1 Gbit */
1581         case 32:                /* 2 Gbit */
1582                 DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
1583                 tmp |= (0x02 << 4);
1584                 break;
1585         default:
1586                 printf ("Error in dram size calculation\n");
1587                 printf ("RAM-Device_size is unsupported\n");
1588                 hang ();
1589         }
1590
1591         /* SDRAM address control */
1592         GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1593         DP (printf
1594             ("setting up sdram address control (0x1410) with: %08lx \n",
1595              tmp));
1596
1597 /* ------------------------------------------------------------------------------ */
1598 /* same settings for registerd & non-registerd DDR SDRAM */
1599         DP (printf
1600             ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
1601              0x01501220));
1602         /*ronen db64460 */
1603         GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220);
1604
1605
1606 /* ------------------------------------------------------------------------------ */
1607
1608         /* SDRAM configuration */
1609         tmp = GTREGREAD (SDRAM_CONFIG);
1610
1611         if (info->registeredAddrAndControlInputs
1612             || info->registeredDQMBinputs) {
1613                 tmp |= (1 << 17);
1614                 DP (printf
1615                     ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1616                      info->registeredAddrAndControlInputs,
1617                      info->registeredDQMBinputs));
1618         }
1619
1620         /* Use buffer 1 to return read data to the CPU
1621          * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
1622
1623 indent: Standard input:1465: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
1624
1625 4460 */
1626         tmp |= (1 << 26);
1627         DP (printf
1628             ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
1629              GTREGREAD (SDRAM_CONFIG)));
1630         DP (printf
1631             ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
1632              GTREGREAD (SDRAM_CONFIG)));
1633
1634         /* SDRAM timing To_do: */
1635 /* ------------------------------------------------------------------------------ */
1636         /* ronen db64460 */
1637         DP (printf
1638             ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
1639              0xc));
1640         GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc);
1641
1642         DP (printf
1643             ("setting up sdram address pads control (0x14c0) with: %08x \n",
1644              0x7d5014a));
1645         GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
1646
1647         DP (printf
1648             ("setting up sdram data pads control (0x14c4) with: %08x \n",
1649              0x7d5014a));
1650         GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
1651
1652 /* ------------------------------------------------------------------------------ */
1653
1654         /* set the SDRAM configuration for each bank */
1655
1656 /*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1657         {
1658                 i = info->slot;
1659                 DP (printf
1660                     ("\n*** Running a MRS cycle for bank %d ***\n", i));
1661
1662                 /* map the bank */
1663                 memory_map_bank (i, 0, GB / 4);
1664
1665                 /* set SDRAM mode */ /* To_do check it */
1666                 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1667                 check = GTREGREAD (SDRAM_OPERATION);
1668                 DP (printf
1669                     ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1670                      check));
1671
1672
1673                 /* switch back to normal operation mode */
1674                 GT_REG_WRITE (SDRAM_OPERATION, 0);
1675                 check = GTREGREAD (SDRAM_OPERATION);
1676                 DP (printf
1677                     ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1678                      check));
1679
1680                 /* unmap the bank */
1681                 memory_map_bank (i, 0, 0);
1682         }
1683
1684         return 0;
1685
1686 }
1687
1688 /*
1689  * Check memory range for valid RAM. A simple memory test determines
1690  * the actually available RAM size between addresses `base' and
1691  * `base + maxsize'. Some (not all) hardware errors are detected:
1692  * - short between address lines
1693  * - short between data lines
1694  */
1695 long int dram_size (long int *base, long int maxsize)
1696 {
1697         volatile long int *addr, *b = base;
1698         long int cnt, val, save1, save2;
1699
1700 #define STARTVAL (1<<20)        /* start test at 1M */
1701         for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
1702              cnt <<= 1) {
1703                 addr = base + cnt;      /* pointer arith! */
1704
1705                 save1 = *addr;  /* save contents of addr */
1706                 save2 = *b;     /* save contents of base */
1707
1708                 *addr = cnt;    /* write cnt to addr */
1709                 *b = 0;         /* put null at base */
1710
1711                 /* check at base address */
1712                 if ((*b) != 0) {
1713                         *addr = save1;  /* restore *addr */
1714                         *b = save2;     /* restore *b */
1715                         return (0);
1716                 }
1717                 val = *addr;    /* read *addr */
1718                 val = *addr;    /* read *addr */
1719
1720                 *addr = save1;
1721                 *b = save2;
1722
1723                 if (val != cnt) {
1724                         DP (printf
1725                             ("Found %08x  at Address %08x (failure)\n",
1726                              (unsigned int) val, (unsigned int) addr));
1727                         /* fix boundary condition.. STARTVAL means zero */
1728                         if (cnt == STARTVAL / sizeof (long))
1729                                 cnt = 0;
1730                         return (cnt * sizeof (long));
1731                 }
1732         }
1733         return maxsize;
1734 }
1735
1736 /* ------------------------------------------------------------------------- */
1737
1738 /* ppcboot interface function to SDRAM init - this is where all the
1739  * controlling logic happens */
1740 long int initdram (int board_type)
1741 {
1742         int s0 = 0, s1 = 0;
1743         int checkbank[4] = {[0 ... 3] = 0 };
1744         ulong realsize, total, check;
1745         AUX_MEM_DIMM_INFO dimmInfo1;
1746         AUX_MEM_DIMM_INFO dimmInfo2;
1747         int nhr, bank_no;
1748         ulong dest, memSpaceAttr;
1749
1750         /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1751
1752         /* check the NHR bit and skip mem init if it's already done */
1753         nhr = get_hid0 () & (1 << 16);
1754
1755         if (nhr) {
1756                 printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1757         } else {
1758                 /* DIMM0 */
1759                 s0 = check_dimm (0, &dimmInfo1);
1760
1761                 /* DIMM1 */
1762                 s1 = check_dimm (1, &dimmInfo2);
1763
1764                 memory_map_bank (0, 0, 0);
1765                 memory_map_bank (1, 0, 0);
1766                 memory_map_bank (2, 0, 0);
1767                 memory_map_bank (3, 0, 0);
1768
1769                 /* ronen check correct set of DIMMS */
1770                 if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
1771                         if (dimmInfo1.errorCheckType !=
1772                             dimmInfo2.errorCheckType)
1773                                 printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
1774                         if (dimmInfo1.maxClSupported_DDR !=
1775                             dimmInfo2.maxClSupported_DDR)
1776                                 printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
1777                         if (dimmInfo1.registeredAddrAndControlInputs !=
1778                             dimmInfo2.registeredAddrAndControlInputs)
1779                                 printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
1780                 }
1781
1782                 if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
1783                         printf ("Setup for DIMM1 failed.\n");
1784                 }
1785
1786                 if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
1787                         printf ("Setup for DIMM2 failed.\n");
1788                 }
1789
1790                 /* set the NHR bit */
1791                 set_hid0 (get_hid0 () | (1 << 16));
1792         }
1793         /* next, size the SDRAM banks */
1794
1795         realsize = total = 0;
1796         check = GB / 4;
1797         if (dimmInfo1.numOfModuleBanks > 0) {
1798                 checkbank[0] = 1;
1799         }
1800         if (dimmInfo1.numOfModuleBanks > 1) {
1801                 checkbank[1] = 1;
1802         }
1803         if (dimmInfo1.numOfModuleBanks > 2)
1804                 printf ("Error, SPD claims DIMM1 has >2 banks\n");
1805
1806         printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
1807
1808         if (dimmInfo2.numOfModuleBanks > 0) {
1809                 checkbank[2] = 1;
1810         }
1811         if (dimmInfo2.numOfModuleBanks > 1) {
1812                 checkbank[3] = 1;
1813         }
1814         if (dimmInfo2.numOfModuleBanks > 2)
1815                 printf ("Error, SPD claims DIMM2 has >2 banks\n");
1816
1817         printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
1818
1819         for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
1820                 /* skip over banks that are not populated */
1821                 if (!checkbank[bank_no])
1822                         continue;
1823
1824                 /* ronen - realsize = dram_size((long int *)total, check); */
1825                 if (bank_no == 0 || bank_no == 1) {
1826                         if (checkbank[1] == 1)
1827                                 realsize = dimmInfo1.size / 2;
1828                         else
1829                                 realsize = dimmInfo1.size;
1830                 }
1831                 if (bank_no == 2 || bank_no == 3) {
1832                         if (checkbank[3] == 1)
1833                                 realsize = dimmInfo2.size / 2;
1834                         else
1835                                 realsize = dimmInfo2.size;
1836                 }
1837                 memory_map_bank (bank_no, total, realsize);
1838
1839                 /* ronen - initialize the DRAM for ECC */
1840 #ifdef CONFIG_MV64460_ECC
1841                 if ((dimmInfo1.errorCheckType != 0) &&
1842                     ((dimmInfo2.errorCheckType != 0)
1843                      || (dimmInfo2.numOfModuleBanks == 0))) {
1844                         printf ("ECC Initialization of Bank %d:", bank_no);
1845                         memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1846                         mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
1847                                              realsize);
1848                         for (dest = total; dest < total + realsize;
1849                              dest += _8M) {
1850                                 mvDmaTransfer (0, total, dest, _8M,
1851                                                BIT8 /*DMA_DTL_128BYTES */  |
1852                                                BIT3 /*DMA_HOLD_SOURCE_ADDR */
1853                                                |
1854                                                BIT11
1855                                                /*DMA_BLOCK_TRANSFER_MODE */ );
1856                                 while (mvDmaIsChannelActive (0));
1857                         }
1858                         printf (" PASS\n");
1859                 }
1860 #endif
1861
1862                 total += realsize;
1863         }
1864
1865         /* ronen */
1866         switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
1867         case 0x2:
1868                 printf ("CAS Latency = 2");
1869                 break;
1870         case 0x3:
1871                 printf ("CAS Latency = 3");
1872                 break;
1873         case 0x5:
1874                 printf ("CAS Latency = 1.5");
1875                 break;
1876         case 0x6:
1877                 printf ("CAS Latency = 2.5");
1878                 break;
1879         }
1880         printf (" tRP = %d tRAS = %d tRCD=%d\n",
1881                 ((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
1882                 ((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
1883                 ((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
1884
1885 /*      Setup Ethernet DMA Adress window to DRAM Area */
1886         if (total > _256M)
1887                 printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
1888         else
1889                 printf ("Total SDRAM memory is ");
1890         /* (cause all the 4 BATS are taken) */
1891         return (total);
1892 }
1893
1894
1895 /* ronen- add Idma functions for usage of the ecc dram init. */
1896 /*******************************************************************************
1897 * mvDmaIsChannelActive - Checks if a engine is busy.
1898 ********************************************************************************/
1899 int mvDmaIsChannelActive (int engine)
1900 {
1901         ulong data;
1902
1903         data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine);
1904         if (data & BIT14 /*activity status */ ) {
1905                 return 1;
1906         }
1907         return 0;
1908 }
1909
1910 /*******************************************************************************
1911 * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
1912 *                       map.
1913 *******************************************************************************/
1914 int mvDmaSetMemorySpace (ulong memSpace,
1915                          ulong memSpaceTarget,
1916                          ulong memSpaceAttr, ulong baseAddress, ulong size)
1917 {
1918         ulong temp;
1919
1920         /* The base address must be aligned to the size.  */
1921         if (baseAddress % size != 0) {
1922                 return 0;
1923         }
1924         if (size >= 0x10000 /*64K */ ) {
1925                 size &= 0xffff0000;
1926                 baseAddress = (baseAddress & 0xffff0000);
1927                 /* Set the new attributes */
1928                 GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
1929                               (baseAddress | memSpaceTarget | memSpaceAttr));
1930                 GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
1931                               (size - 1) & 0xffff0000);
1932                 temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
1933                 GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
1934                               (temp & ~(BIT0 << memSpace)));
1935                 return 1;
1936         }
1937         return 0;
1938 }
1939
1940
1941 /*******************************************************************************
1942 * mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
1943 *                 DMA channels.
1944 ********************************************************************************/
1945 int mvDmaTransfer (int engine, ulong sourceAddr,
1946                    ulong destAddr, ulong numOfBytes, ulong command)
1947 {
1948         ulong engOffReg = 0;    /* Engine Offset Register */
1949
1950         if (numOfBytes > 0xffff) {
1951                 command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
1952         }
1953         command = command | ((command >> 6) & 0x7);
1954         engOffReg = engine * 4;
1955         GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
1956                       numOfBytes);
1957         GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
1958                       sourceAddr);
1959         GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
1960                       destAddr);
1961         command =
1962                 command | BIT12 /*DMA_CHANNEL_ENABLE */  | BIT9
1963                 /*DMA_NON_CHAIN_MODE */ ;
1964         /* Activate DMA engine By writting to mvDmaControlRegister */
1965         GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
1966         return 1;
1967 }
1968
1969 /****************************************************************************************
1970  *                             SDRAM INIT                                               *
1971  *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb        *
1972  *               This procedure fits only the Atlantis                                  *
1973  *                                                                                      *
1974  ***************************************************************************************/
1975
1976
1977 /****************************************************************************************
1978  *                             DFCDL initialize MV643xx Design Considerations           *
1979  *                                                                                      *
1980  ***************************************************************************************/
1981 int set_dfcdlInit (void)
1982 {
1983         /*ronen the dfcdl init are done by the I2C */
1984         return (0);
1985 }