1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
10 #include <linux/mbus.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 DECLARE_GLOBAL_DATA_PTR;
18 * These values and defines are taken from the Marvell U-Boot version
19 * "u-boot-2013.01-2016_T1.0.eng_drop_v6"
21 #define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
22 | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
23 #define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
24 #define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
25 | BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))
26 #define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
27 #define DB_DX_AC3_GPP_POL_LOW 0x0
28 #define DB_DX_AC3_GPP_POL_MID 0x0
30 int board_early_init_f(void)
33 writel(0x00142222, MVEBU_MPP_BASE + 0x00);
34 writel(0x11122000, MVEBU_MPP_BASE + 0x04);
35 writel(0x44444004, MVEBU_MPP_BASE + 0x08);
36 writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
37 writel(0x00000001, MVEBU_MPP_BASE + 0x10);
39 /* Set GPP Out value */
40 writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
41 writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
43 /* Set GPP Polarity */
44 writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
45 writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
47 /* Set GPP Out Enable */
48 writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
49 writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
56 /* address of boot parameters */
57 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
62 #ifdef CONFIG_DISPLAY_BOARDINFO
65 puts("Board: " CONFIG_SYS_BOARD "\n");