1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define ETH_PHY_CTRL_REG 0
18 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
19 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
22 * Those values and defines are taken from the Marvell U-Boot version
23 * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
24 * "RD-AXP-GP rev 1.0".
28 * ----------------------------------------------
33 * 54-61 On GPP Connector ?
34 * 62 Switch Interrupt IN
35 * 63-65 Reserved from SW Board ?
36 * 66 SW_BRD connected IN
38 #define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
39 #define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
40 #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
42 #define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
43 #define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
44 #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
46 int board_early_init_f(void)
49 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
50 writel(0x00000000, MVEBU_MPP_BASE + 0x04);
51 writel(0x33000000, MVEBU_MPP_BASE + 0x08);
52 writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
53 writel(0x11111111, MVEBU_MPP_BASE + 0x10);
54 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
55 writel(0x00000003, MVEBU_MPP_BASE + 0x18);
56 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
57 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
60 writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
61 writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
62 writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
63 writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
64 writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
65 writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
72 /* adress of boot parameters */
73 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
80 puts("Board: Marvell DB-MV784MP-GP\n");
85 int board_eth_init(bd_t *bis)
87 cpu_eth_init(bis); /* Built in controller(s) come first */
88 return pci_eth_init(bis);
91 int board_phy_config(struct phy_device *phydev)
95 /* Enable QSGMII AN */
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
101 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
104 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
106 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
109 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
110 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
112 /* Power up the phy */
113 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
114 reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
115 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
117 printf("88E1545 Initialized\n");