1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
14 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
15 #include <../serdes/a38x/high_speed_env_spec.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #define ETH_PHY_CTRL_REG 0
20 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
21 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
24 * Those values and defines are taken from the Marvell U-Boot version
25 * "u-boot-2013.01-2016_T1.0.eng_drop_v10"
27 #define DB_AMC_88F68XX_GPP_OUT_ENA_LOW \
29 #define DB_AMC_88F68XX_GPP_OUT_ENA_MID \
30 (~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
31 #define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT(29))
32 #define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0
33 #define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0
34 #define DB_AMC_88F68XX_GPP_POL_LOW 0x0
35 #define DB_AMC_88F68XX_GPP_POL_MID 0x0
37 static struct serdes_map board_serdes_map[] = {
38 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
39 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
40 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
41 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
42 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
43 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
46 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
48 *serdes_map_array = board_serdes_map;
49 *count = ARRAY_SIZE(board_serdes_map);
54 * Define the DDR layout / topology here in the board file. This will
55 * be used by the DDR3 init code in the SPL U-Boot version to configure
56 * the DDR3 controller.
58 static struct mv_ddr_topology_map board_topology_map = {
60 0x1, /* active interfaces */
61 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
67 SPEED_BIN_DDR_1866L, /* speed_bin */
68 MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
69 MV_DDR_DIE_CAP_2GBIT, /* mem_size */
70 DDR_FREQ_800, /* frequency */
71 0, 0, /* cas_wl cas_l */
72 MV_DDR_TEMP_LOW} }, /* temperature */
73 BUS_MASK_32BIT, /* Busses mask */
74 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
75 { {0} }, /* raw spd data */
76 {0} /* timing parameters */
79 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
81 /* Return the board topology as defined in the board code */
82 return &board_topology_map;
85 int board_early_init_f(void)
88 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
89 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
90 writel(0x55066011, MVEBU_MPP_BASE + 0x08);
91 writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
92 writel(0x05055555, MVEBU_MPP_BASE + 0x10);
93 writel(0x01106565, MVEBU_MPP_BASE + 0x14);
94 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
95 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
97 /* Set GPP Out value */
98 writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
99 writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
101 /* Set GPP Polarity */
102 writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
103 writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
105 /* Set GPP Out Enable */
106 writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
107 writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
114 /* adress of boot parameters */
115 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
122 puts("Board: Marvell DB-88F6820-AMC\n");
127 int board_eth_init(bd_t *bis)
129 cpu_eth_init(bis); /* Built in controller(s) come first */
130 return pci_eth_init(bis);