2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/orion5x.h>
14 #include "../common/common.h"
18 DECLARE_GLOBAL_DATA_PTR;
21 * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
22 * which CFI does not properly detect, hence the LEGACY config.
24 #if defined(CONFIG_FLASH_CFI_LEGACY)
26 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
28 int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
31 if (base != CONFIG_SYS_FLASH_BASE)
35 info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
36 /* set each sector's start address and size based */
37 for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
38 info->start[sect] = base+info->size;
39 info->size += sectsz[sect];
41 /* This flash must be accessed in 8-bits mode, no buffer. */
42 info->flash_id = 0x01000000;
43 info->portwidth = FLASH_CFI_8BIT;
44 info->chipwidth = FLASH_CFI_BY8;
45 info->buffer_size = 0;
46 /* timings are derived from the Macronix datasheet. */
47 info->erase_blk_tout = 1000;
48 info->write_tout = 10;
49 info->buffer_write_tout = 300;
50 /* Commands and addresses are for AMD mode 8-bit access. */
51 info->vendor = CFI_CMDSET_AMD_LEGACY;
52 info->cmd_reset = 0xF0;
53 info->interface = FLASH_CFI_X8;
54 info->legacy_unlock = 0;
56 info->addr_unlock1 = 0x00000aaa;
57 info->addr_unlock2 = 0x00000555;
58 /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
59 info->manufacturer_id = 0x22;
60 info->device_id = 0xBA;
62 info->cfi_version = 0x3133;
63 info->cfi_offset = 0x0000;
64 info->name = "MX29LV400CB";
68 #endif /* CONFIG_SYS_FLASH_CFI */
72 /* arch number of board */
73 gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
75 /* boot parameter start at 256th byte of RAM base */
76 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
81 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
82 /* Configure and enable MV88E1116 PHY */
85 mv_phy_88e1116_init("egiga0", 8);
87 #endif /* CONFIG_RESET_PHY_R */
90 * SPL serial setup and NOR boot device selection
93 #ifdef CONFIG_SPL_BUILD
95 void spl_board_init(void)
97 preloader_console_init();
100 u32 spl_boot_device(void)
102 return BOOT_DEVICE_NOR;
105 #endif /* CONFIG_SPL_BUILD */