1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
11 #include <environment.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <dm/uclass.h>
19 #include <fdt_support.h>
22 #ifdef CONFIG_ATSHA204A
23 # include <atsha204a-i2c.h>
26 #ifdef CONFIG_WDT_ORION
30 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
31 #include <../serdes/a38x/high_speed_env_spec.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
37 #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
38 #define OMNIA_I2C_MCU_CHIP_LEN 1
40 #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
41 #define OMNIA_I2C_EEPROM_CHIP_LEN 2
42 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
45 CMD_GET_STATUS_WORD = 0x01,
47 CMD_WATCHDOG_STATE = 0x0b,
50 enum status_word_bits {
51 CARD_DET_STSBIT = 0x0010,
52 MSATA_IND_STSBIT = 0x0020,
55 #define OMNIA_ATSHA204_OTP_VERSION 0
56 #define OMNIA_ATSHA204_OTP_SERIAL 1
57 #define OMNIA_ATSHA204_OTP_MAC0 3
58 #define OMNIA_ATSHA204_OTP_MAC1 4
61 * Those values and defines are taken from the Marvell U-Boot version
62 * "u-boot-2013.01-2014_T3.0"
64 #define OMNIA_GPP_OUT_ENA_LOW \
65 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
66 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
67 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
68 #define OMNIA_GPP_OUT_ENA_MID \
69 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
70 BIT(16) | BIT(17) | BIT(18)))
72 #define OMNIA_GPP_OUT_VAL_LOW 0x0
73 #define OMNIA_GPP_OUT_VAL_MID 0x0
74 #define OMNIA_GPP_POL_LOW 0x0
75 #define OMNIA_GPP_POL_MID 0x0
77 static struct serdes_map board_serdes_map_pex[] = {
78 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
79 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
80 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
81 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
82 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
83 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
86 static struct serdes_map board_serdes_map_sata[] = {
87 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
88 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
89 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
90 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
91 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
92 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
95 static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
98 struct udevice *bus, *dev;
101 ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
103 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
104 OMNIA_I2C_BUS_NAME, ret);
108 ret = i2c_get_chip(bus, addr, offset_len, &dev);
110 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
118 static int omnia_mcu_read(u8 cmd, void *buf, int len)
120 struct udevice *chip;
122 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
123 OMNIA_I2C_MCU_CHIP_LEN);
127 return dm_i2c_read(chip, cmd, buf, len);
130 #ifndef CONFIG_SPL_BUILD
131 static int omnia_mcu_write(u8 cmd, const void *buf, int len)
133 struct udevice *chip;
135 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
136 OMNIA_I2C_MCU_CHIP_LEN);
140 return dm_i2c_write(chip, cmd, buf, len);
143 static bool disable_mcu_watchdog(void)
147 puts("Disabling MCU watchdog... ");
149 ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
151 printf("omnia_mcu_write failed: %i\n", ret);
161 static bool omnia_detect_sata(void)
166 puts("MiniPCIe/mSATA card detection... ");
168 ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
170 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
175 if (!(stsword & CARD_DET_STSBIT)) {
180 if (stsword & MSATA_IND_STSBIT)
185 return stsword & MSATA_IND_STSBIT ? true : false;
188 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
190 if (omnia_detect_sata()) {
191 *serdes_map_array = board_serdes_map_sata;
192 *count = ARRAY_SIZE(board_serdes_map_sata);
194 *serdes_map_array = board_serdes_map_pex;
195 *count = ARRAY_SIZE(board_serdes_map_pex);
201 struct omnia_eeprom {
208 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
210 struct udevice *chip;
214 chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
215 OMNIA_I2C_EEPROM_CHIP_LEN);
220 ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
222 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
226 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
227 printf("bad EEPROM magic number (%08x, should be %08x)\n",
228 oep->magic, OMNIA_I2C_EEPROM_MAGIC);
232 crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
233 if (crc != oep->crc) {
234 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
243 * Define the DDR layout / topology here in the board file. This will
244 * be used by the DDR3 init code in the SPL U-Boot version to configure
245 * the DDR3 controller.
247 static struct mv_ddr_topology_map board_topology_map_1g = {
249 0x1, /* active interfaces */
250 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
251 { { { {0x1, 0, 0, 0},
256 SPEED_BIN_DDR_1600K, /* speed_bin */
257 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
258 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
259 MV_DDR_FREQ_800, /* frequency */
260 0, 0, /* cas_wl cas_l */
261 MV_DDR_TEMP_NORMAL, /* temperature */
262 MV_DDR_TIM_2T} }, /* timing */
263 BUS_MASK_32BIT, /* Busses mask */
264 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
265 { {0} }, /* raw spd data */
266 {0} /* timing parameters */
269 static struct mv_ddr_topology_map board_topology_map_2g = {
271 0x1, /* active interfaces */
272 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
273 { { { {0x1, 0, 0, 0},
278 SPEED_BIN_DDR_1600K, /* speed_bin */
279 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
280 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
281 MV_DDR_FREQ_800, /* frequency */
282 0, 0, /* cas_wl cas_l */
283 MV_DDR_TEMP_NORMAL, /* temperature */
284 MV_DDR_TIM_2T} }, /* timing */
285 BUS_MASK_32BIT, /* Busses mask */
286 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
287 { {0} }, /* raw spd data */
288 {0} /* timing parameters */
291 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
294 struct omnia_eeprom oep;
296 /* Get the board config from EEPROM */
298 if (!omnia_read_eeprom(&oep))
301 printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
303 if (oep.ramsize == 0x2)
310 /* Hardcoded fallback */
312 puts("WARNING: Memory config from EEPROM read failed.\n");
313 puts("Falling back to default 1GiB map.\n");
317 /* Return the board topology as defined in the board code */
319 return &board_topology_map_1g;
321 return &board_topology_map_2g;
323 return &board_topology_map_1g;
326 #ifndef CONFIG_SPL_BUILD
327 static int set_regdomain(void)
329 struct omnia_eeprom oep;
330 char rd[3] = {' ', ' ', 0};
332 if (omnia_read_eeprom(&oep))
333 memcpy(rd, &oep.region, 2);
335 puts("EEPROM regdomain read failed.\n");
337 printf("Regdomain set to %s\n", rd);
338 return env_set("regdomain", rd);
342 int board_early_init_f(void)
345 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
346 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
347 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
348 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
349 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
350 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
351 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
352 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
354 /* Set GPP Out value */
355 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
356 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
358 /* Set GPP Polarity */
359 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
360 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
362 /* Set GPP Out Enable */
363 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
364 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
371 /* address of boot parameters */
372 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
374 #ifndef CONFIG_SPL_BUILD
375 disable_mcu_watchdog();
382 int board_late_init(void)
384 #ifndef CONFIG_SPL_BUILD
391 #ifdef CONFIG_ATSHA204A
392 static struct udevice *get_atsha204a_dev(void)
394 static struct udevice *dev;
399 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
400 puts("Cannot find ATSHA204A on I2C bus!\n");
410 u32 version_num, serial_num;
413 #ifdef CONFIG_ATSHA204A
414 struct udevice *dev = get_atsha204a_dev();
417 err = atsha204a_wakeup(dev);
421 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
422 OMNIA_ATSHA204_OTP_VERSION,
427 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
428 OMNIA_ATSHA204_OTP_SERIAL,
433 atsha204a_sleep(dev);
440 printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
442 printf("Board: Turris Omnia SNL %08X%08X\n",
443 be32_to_cpu(version_num), be32_to_cpu(serial_num));
448 static void increment_mac(u8 *mac)
452 for (i = 5; i >= 3; i--) {
459 int misc_init_r(void)
461 #ifdef CONFIG_ATSHA204A
463 struct udevice *dev = get_atsha204a_dev();
464 u8 mac0[4], mac1[4], mac[6];
469 err = atsha204a_wakeup(dev);
473 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
474 OMNIA_ATSHA204_OTP_MAC0, mac0);
478 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
479 OMNIA_ATSHA204_OTP_MAC1, mac1);
483 atsha204a_sleep(dev);
492 if (is_valid_ethaddr(mac))
493 eth_env_set_enetaddr("ethaddr", mac);
497 if (is_valid_ethaddr(mac))
498 eth_env_set_enetaddr("eth1addr", mac);
502 if (is_valid_ethaddr(mac))
503 eth_env_set_enetaddr("eth2addr", mac);