1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
18 #include <asm/global_data.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/soc.h>
22 #include <dm/uclass.h>
23 #include <fdt_support.h>
25 #include <linux/bitops.h>
26 #include <u-boot/crc.h>
27 # include <atsha204a-i2c.h>
29 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
30 #include <../serdes/a38x/high_speed_env_spec.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
36 #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
37 #define OMNIA_I2C_MCU_CHIP_LEN 1
39 #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
40 #define OMNIA_I2C_EEPROM_CHIP_LEN 2
41 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
44 CMD_GET_STATUS_WORD = 0x01,
46 CMD_WATCHDOG_STATE = 0x0b,
49 enum status_word_bits {
50 CARD_DET_STSBIT = 0x0010,
51 MSATA_IND_STSBIT = 0x0020,
54 #define OMNIA_ATSHA204_OTP_VERSION 0
55 #define OMNIA_ATSHA204_OTP_SERIAL 1
56 #define OMNIA_ATSHA204_OTP_MAC0 3
57 #define OMNIA_ATSHA204_OTP_MAC1 4
60 * Those values and defines are taken from the Marvell U-Boot version
61 * "u-boot-2013.01-2014_T3.0"
63 #define OMNIA_GPP_OUT_ENA_LOW \
64 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
65 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
66 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
67 #define OMNIA_GPP_OUT_ENA_MID \
68 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
69 BIT(16) | BIT(17) | BIT(18)))
71 #define OMNIA_GPP_OUT_VAL_LOW 0x0
72 #define OMNIA_GPP_OUT_VAL_MID 0x0
73 #define OMNIA_GPP_POL_LOW 0x0
74 #define OMNIA_GPP_POL_MID 0x0
76 static struct serdes_map board_serdes_map_pex[] = {
77 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
78 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
79 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
80 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
81 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
82 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
85 static struct serdes_map board_serdes_map_sata[] = {
86 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
87 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
88 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
89 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
90 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
91 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
94 static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
97 struct udevice *bus, *dev;
100 ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
102 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
103 OMNIA_I2C_BUS_NAME, ret);
107 ret = i2c_get_chip(bus, addr, offset_len, &dev);
109 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
117 static int omnia_mcu_read(u8 cmd, void *buf, int len)
119 struct udevice *chip;
121 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
122 OMNIA_I2C_MCU_CHIP_LEN);
126 return dm_i2c_read(chip, cmd, buf, len);
129 #ifndef CONFIG_SPL_BUILD
130 static int omnia_mcu_write(u8 cmd, const void *buf, int len)
132 struct udevice *chip;
134 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
135 OMNIA_I2C_MCU_CHIP_LEN);
139 return dm_i2c_write(chip, cmd, buf, len);
142 static bool disable_mcu_watchdog(void)
146 puts("Disabling MCU watchdog... ");
148 ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
150 printf("omnia_mcu_write failed: %i\n", ret);
160 static bool omnia_detect_sata(void)
165 puts("MiniPCIe/mSATA card detection... ");
167 ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
169 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
174 if (!(stsword & CARD_DET_STSBIT)) {
179 if (stsword & MSATA_IND_STSBIT)
184 return stsword & MSATA_IND_STSBIT ? true : false;
187 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
189 if (omnia_detect_sata()) {
190 *serdes_map_array = board_serdes_map_sata;
191 *count = ARRAY_SIZE(board_serdes_map_sata);
193 *serdes_map_array = board_serdes_map_pex;
194 *count = ARRAY_SIZE(board_serdes_map_pex);
200 struct omnia_eeprom {
207 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
209 struct udevice *chip;
213 chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
214 OMNIA_I2C_EEPROM_CHIP_LEN);
219 ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
221 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
225 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
226 printf("bad EEPROM magic number (%08x, should be %08x)\n",
227 oep->magic, OMNIA_I2C_EEPROM_MAGIC);
231 crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
232 if (crc != oep->crc) {
233 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
241 static int omnia_get_ram_size_gb(void)
244 struct omnia_eeprom oep;
247 /* Get the board config from EEPROM */
248 if (omnia_read_eeprom(&oep)) {
249 debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
251 if (oep.ramsize == 0x2)
256 /* Hardcoded fallback */
257 puts("Memory config from EEPROM read failed!\n");
258 puts("Falling back to default 1 GiB!\n");
267 * Define the DDR layout / topology here in the board file. This will
268 * be used by the DDR3 init code in the SPL U-Boot version to configure
269 * the DDR3 controller.
271 static struct mv_ddr_topology_map board_topology_map_1g = {
273 0x1, /* active interfaces */
274 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
275 { { { {0x1, 0, 0, 0},
280 SPEED_BIN_DDR_1600K, /* speed_bin */
281 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
282 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
283 MV_DDR_FREQ_800, /* frequency */
284 0, 0, /* cas_wl cas_l */
285 MV_DDR_TEMP_NORMAL, /* temperature */
286 MV_DDR_TIM_2T} }, /* timing */
287 BUS_MASK_32BIT, /* Busses mask */
288 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
289 NOT_COMBINED, /* ddr twin-die combined */
290 { {0} }, /* raw spd data */
291 {0} /* timing parameters */
294 static struct mv_ddr_topology_map board_topology_map_2g = {
296 0x1, /* active interfaces */
297 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
298 { { { {0x1, 0, 0, 0},
303 SPEED_BIN_DDR_1600K, /* speed_bin */
304 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
305 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
306 MV_DDR_FREQ_800, /* frequency */
307 0, 0, /* cas_wl cas_l */
308 MV_DDR_TEMP_NORMAL, /* temperature */
309 MV_DDR_TIM_2T} }, /* timing */
310 BUS_MASK_32BIT, /* Busses mask */
311 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
312 NOT_COMBINED, /* ddr twin-die combined */
313 { {0} }, /* raw spd data */
314 {0} /* timing parameters */
317 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
319 if (omnia_get_ram_size_gb() == 2)
320 return &board_topology_map_2g;
322 return &board_topology_map_1g;
325 #ifndef CONFIG_SPL_BUILD
326 static int set_regdomain(void)
328 struct omnia_eeprom oep;
329 char rd[3] = {' ', ' ', 0};
331 if (omnia_read_eeprom(&oep))
332 memcpy(rd, &oep.region, 2);
334 puts("EEPROM regdomain read failed.\n");
336 printf("Regdomain set to %s\n", rd);
337 return env_set("regdomain", rd);
340 static void handle_reset_button(void)
342 const char * const vars[1] = { "bootcmd_rescue", };
347 * Ensure that bootcmd_rescue has always stock value, so that running
349 * always works correctly.
351 env_set_default_vars(1, (char * const *)vars, 0);
353 ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
355 printf("omnia_mcu_read failed: %i, reset status unknown!\n",
360 env_set_ulong("omnia_reset", reset_status);
363 const char * const vars[2] = {
369 * Set the above envs to their default values, in case the user
370 * managed to break them.
372 env_set_default_vars(2, (char * const *)vars, 0);
374 /* Ensure bootcmd_rescue is used by distroboot */
375 env_set("boot_targets", "rescue");
377 printf("RESET button was pressed, overwriting bootcmd!\n");
380 * In case the user somehow managed to save environment with
381 * boot_targets=rescue, reset boot_targets to default value.
382 * This could happen in subsequent commands if bootcmd_rescue
385 if (!strcmp(env_get("boot_targets"), "rescue")) {
386 const char * const vars[1] = {
390 env_set_default_vars(1, (char * const *)vars, 0);
396 int board_early_init_f(void)
399 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
400 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
401 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
402 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
403 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
404 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
405 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
406 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
408 /* Set GPP Out value */
409 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
410 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
412 /* Set GPP Polarity */
413 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
414 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
416 /* Set GPP Out Enable */
417 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
418 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
425 /* address of boot parameters */
426 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
428 #ifndef CONFIG_SPL_BUILD
429 disable_mcu_watchdog();
435 int board_late_init(void)
437 #ifndef CONFIG_SPL_BUILD
439 handle_reset_button();
446 static struct udevice *get_atsha204a_dev(void)
448 static struct udevice *dev;
453 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
454 puts("Cannot find ATSHA204A on I2C bus!\n");
463 u32 version_num, serial_num;
466 struct udevice *dev = get_atsha204a_dev();
469 err = atsha204a_wakeup(dev);
473 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
474 OMNIA_ATSHA204_OTP_VERSION,
479 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
480 OMNIA_ATSHA204_OTP_SERIAL,
485 atsha204a_sleep(dev);
489 printf("Turris Omnia:\n");
490 printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
492 printf(" Serial Number: unknown\n");
494 printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
495 be32_to_cpu(serial_num));
500 static void increment_mac(u8 *mac)
504 for (i = 5; i >= 3; i--) {
511 int misc_init_r(void)
514 struct udevice *dev = get_atsha204a_dev();
515 u8 mac0[4], mac1[4], mac[6];
520 err = atsha204a_wakeup(dev);
524 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
525 OMNIA_ATSHA204_OTP_MAC0, mac0);
529 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
530 OMNIA_ATSHA204_OTP_MAC1, mac1);
534 atsha204a_sleep(dev);
543 if (is_valid_ethaddr(mac))
544 eth_env_set_enetaddr("eth1addr", mac);
548 if (is_valid_ethaddr(mac))
549 eth_env_set_enetaddr("eth2addr", mac);
553 if (is_valid_ethaddr(mac))
554 eth_env_set_enetaddr("ethaddr", mac);