1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
11 #include <environment.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <dm/uclass.h>
19 #include <fdt_support.h>
21 # include <atsha204a-i2c.h>
23 #ifdef CONFIG_WDT_ORION
27 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
28 #include <../serdes/a38x/high_speed_env_spec.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
34 #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
35 #define OMNIA_I2C_MCU_CHIP_LEN 1
37 #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
38 #define OMNIA_I2C_EEPROM_CHIP_LEN 2
39 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
42 CMD_GET_STATUS_WORD = 0x01,
44 CMD_WATCHDOG_STATE = 0x0b,
47 enum status_word_bits {
48 CARD_DET_STSBIT = 0x0010,
49 MSATA_IND_STSBIT = 0x0020,
52 #define OMNIA_ATSHA204_OTP_VERSION 0
53 #define OMNIA_ATSHA204_OTP_SERIAL 1
54 #define OMNIA_ATSHA204_OTP_MAC0 3
55 #define OMNIA_ATSHA204_OTP_MAC1 4
58 * Those values and defines are taken from the Marvell U-Boot version
59 * "u-boot-2013.01-2014_T3.0"
61 #define OMNIA_GPP_OUT_ENA_LOW \
62 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
63 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
64 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
65 #define OMNIA_GPP_OUT_ENA_MID \
66 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
67 BIT(16) | BIT(17) | BIT(18)))
69 #define OMNIA_GPP_OUT_VAL_LOW 0x0
70 #define OMNIA_GPP_OUT_VAL_MID 0x0
71 #define OMNIA_GPP_POL_LOW 0x0
72 #define OMNIA_GPP_POL_MID 0x0
74 static struct serdes_map board_serdes_map_pex[] = {
75 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
76 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
77 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
78 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
79 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
80 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
83 static struct serdes_map board_serdes_map_sata[] = {
84 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
85 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
86 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
87 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
88 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
89 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
92 static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
95 struct udevice *bus, *dev;
98 ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
100 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
101 OMNIA_I2C_BUS_NAME, ret);
105 ret = i2c_get_chip(bus, addr, offset_len, &dev);
107 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
115 static int omnia_mcu_read(u8 cmd, void *buf, int len)
117 struct udevice *chip;
119 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
120 OMNIA_I2C_MCU_CHIP_LEN);
124 return dm_i2c_read(chip, cmd, buf, len);
127 #ifndef CONFIG_SPL_BUILD
128 static int omnia_mcu_write(u8 cmd, const void *buf, int len)
130 struct udevice *chip;
132 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
133 OMNIA_I2C_MCU_CHIP_LEN);
137 return dm_i2c_write(chip, cmd, buf, len);
140 static bool disable_mcu_watchdog(void)
144 puts("Disabling MCU watchdog... ");
146 ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
148 printf("omnia_mcu_write failed: %i\n", ret);
158 static bool omnia_detect_sata(void)
163 puts("MiniPCIe/mSATA card detection... ");
165 ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
167 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
172 if (!(stsword & CARD_DET_STSBIT)) {
177 if (stsword & MSATA_IND_STSBIT)
182 return stsword & MSATA_IND_STSBIT ? true : false;
185 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
187 if (omnia_detect_sata()) {
188 *serdes_map_array = board_serdes_map_sata;
189 *count = ARRAY_SIZE(board_serdes_map_sata);
191 *serdes_map_array = board_serdes_map_pex;
192 *count = ARRAY_SIZE(board_serdes_map_pex);
198 struct omnia_eeprom {
205 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
207 struct udevice *chip;
211 chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
212 OMNIA_I2C_EEPROM_CHIP_LEN);
217 ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
219 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
223 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
224 printf("bad EEPROM magic number (%08x, should be %08x)\n",
225 oep->magic, OMNIA_I2C_EEPROM_MAGIC);
229 crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
230 if (crc != oep->crc) {
231 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
239 static int omnia_get_ram_size_gb(void)
242 struct omnia_eeprom oep;
245 /* Get the board config from EEPROM */
246 if (omnia_read_eeprom(&oep)) {
247 debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
249 if (oep.ramsize == 0x2)
254 /* Hardcoded fallback */
255 puts("Memory config from EEPROM read failed!\n");
256 puts("Falling back to default 1 GiB!\n");
265 * Define the DDR layout / topology here in the board file. This will
266 * be used by the DDR3 init code in the SPL U-Boot version to configure
267 * the DDR3 controller.
269 static struct mv_ddr_topology_map board_topology_map_1g = {
271 0x1, /* active interfaces */
272 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
273 { { { {0x1, 0, 0, 0},
278 SPEED_BIN_DDR_1600K, /* speed_bin */
279 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
280 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
281 MV_DDR_FREQ_800, /* frequency */
282 0, 0, /* cas_wl cas_l */
283 MV_DDR_TEMP_NORMAL, /* temperature */
284 MV_DDR_TIM_2T} }, /* timing */
285 BUS_MASK_32BIT, /* Busses mask */
286 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
287 { {0} }, /* raw spd data */
288 {0} /* timing parameters */
291 static struct mv_ddr_topology_map board_topology_map_2g = {
293 0x1, /* active interfaces */
294 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
295 { { { {0x1, 0, 0, 0},
300 SPEED_BIN_DDR_1600K, /* speed_bin */
301 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
302 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
303 MV_DDR_FREQ_800, /* frequency */
304 0, 0, /* cas_wl cas_l */
305 MV_DDR_TEMP_NORMAL, /* temperature */
306 MV_DDR_TIM_2T} }, /* timing */
307 BUS_MASK_32BIT, /* Busses mask */
308 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
309 { {0} }, /* raw spd data */
310 {0} /* timing parameters */
313 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
315 if (omnia_get_ram_size_gb() == 2)
316 return &board_topology_map_2g;
318 return &board_topology_map_1g;
321 #ifndef CONFIG_SPL_BUILD
322 static int set_regdomain(void)
324 struct omnia_eeprom oep;
325 char rd[3] = {' ', ' ', 0};
327 if (omnia_read_eeprom(&oep))
328 memcpy(rd, &oep.region, 2);
330 puts("EEPROM regdomain read failed.\n");
332 printf("Regdomain set to %s\n", rd);
333 return env_set("regdomain", rd);
337 int board_early_init_f(void)
340 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
341 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
342 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
343 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
344 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
345 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
346 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
347 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
349 /* Set GPP Out value */
350 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
351 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
353 /* Set GPP Polarity */
354 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
355 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
357 /* Set GPP Out Enable */
358 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
359 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
366 /* address of boot parameters */
367 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
369 #ifndef CONFIG_SPL_BUILD
370 disable_mcu_watchdog();
377 int board_late_init(void)
379 #ifndef CONFIG_SPL_BUILD
386 static struct udevice *get_atsha204a_dev(void)
388 static struct udevice *dev;
393 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
394 puts("Cannot find ATSHA204A on I2C bus!\n");
403 u32 version_num, serial_num;
406 struct udevice *dev = get_atsha204a_dev();
409 err = atsha204a_wakeup(dev);
413 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
414 OMNIA_ATSHA204_OTP_VERSION,
419 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
420 OMNIA_ATSHA204_OTP_SERIAL,
425 atsha204a_sleep(dev);
430 printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
432 printf("Board: Turris Omnia SNL %08X%08X\n",
433 be32_to_cpu(version_num), be32_to_cpu(serial_num));
438 static void increment_mac(u8 *mac)
442 for (i = 5; i >= 3; i--) {
449 int misc_init_r(void)
452 struct udevice *dev = get_atsha204a_dev();
453 u8 mac0[4], mac1[4], mac[6];
458 err = atsha204a_wakeup(dev);
462 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
463 OMNIA_ATSHA204_OTP_MAC0, mac0);
467 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
468 OMNIA_ATSHA204_OTP_MAC1, mac1);
472 atsha204a_sleep(dev);
481 if (is_valid_ethaddr(mac))
482 eth_env_set_enetaddr("ethaddr", mac);
486 if (is_valid_ethaddr(mac))
487 eth_env_set_enetaddr("eth1addr", mac);
491 if (is_valid_ethaddr(mac))
492 eth_env_set_enetaddr("eth2addr", mac);