board/BuR/tseries/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for B&R LEIT Board
   5  *
   6  * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
   7  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  *
  11  */
  12
  13 #include <common.h>
  14 #include <errno.h>
  15 #include <spl.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mem.h>
  24 #include <asm/io.h>
  25 #include <asm/emif.h>
  26 #include <asm/gpio.h>
  27 #include <i2c.h>
  28 #include <power/tps65217.h>
  29 #include "../common/bur_common.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 /* --------------------------------------------------------------------------*/
  34 /* -- defines for GPIO -- */
  35 #define ETHLED_ORANGE   (96+16) /* GPIO3_16 */
  36 #define REPSWITCH       (0+20)  /* GPIO0_20 */
  37
  38
  39 #if defined(CONFIG_SPL_BUILD)
  40 /* TODO: check ram-timing ! */
  41 static const struct ddr_data ddr3_data = {
  42         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  43         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  44         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  45         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  46 };
  47
  48 static const struct cmd_control ddr3_cmd_ctrl_data = {
  49         .cmd0csratio = MT41K256M16HA125E_RATIO,
  50         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  51
  52         .cmd1csratio = MT41K256M16HA125E_RATIO,
  53         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  54
  55         .cmd2csratio = MT41K256M16HA125E_RATIO,
  56         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  57 };
  58
  59 static struct emif_regs ddr3_emif_reg_data = {
  60         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  61         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  62         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  63         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  64         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  65         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  66         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  67 };
  68
  69 static const struct ctrl_ioregs ddr3_ioregs = {
  70         .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  71         .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  72         .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  73         .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  74         .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  75 };
  76
  77 #ifdef CONFIG_SPL_OS_BOOT
  78 /*
  79  * called from spl_nand.c
  80  * return 0 for loading linux, return 1 for loading u-boot
  81  */
  82 int spl_start_uboot(void)
  83 {
  84         if (0 == gpio_get_value(REPSWITCH)) {
  85                 blink(5, 125, ETHLED_ORANGE);
  86                 mdelay(1000);
  87                 printf("SPL: entering u-boot instead kernel image.\n");
  88                 return 1;
  89         }
  90         return 0;
  91 }
  92 #endif /* CONFIG_SPL_OS_BOOT */
  93
  94 #define OSC     (V_OSCK/1000000)
  95 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
  96
  97 void am33xx_spl_board_init(void)
  98 {
  99         pmicsetup(1000);
 100 }
 101
 102 const struct dpll_params *get_dpll_ddr_params(void)
 103 {
 104         return &dpll_ddr3;
 105 }
 106
 107 void sdram_init(void)
 108 {
 109         config_ddr(400, &ddr3_ioregs,
 110                    &ddr3_data,
 111                    &ddr3_cmd_ctrl_data,
 112                    &ddr3_emif_reg_data, 0);
 113 }
 114 #endif /* CONFIG_SPL_BUILD */
 115
 116 /* Basic board specific setup.  Pinmux has been handled already. */
 117 int board_init(void)
 118 {
 119         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 120         gpmc_init();
 121         return 0;
 122 }
 123
 124 #ifdef CONFIG_BOARD_LATE_INIT
 125 int board_late_init(void)
 126 {
 127         gpio_direction_output(ETHLED_ORANGE, 0);
 128
 129         if (0 == gpio_get_value(REPSWITCH)) {
 130                 printf("\n\n\n"
 131                 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
 132                 "!!!!!!! recovery switch activated !!!!!!!\n"
 133                 "!!!!!!!     running usbupdate     !!!!!!!\n"
 134                 "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
 135                 setenv("bootcmd", "sleep 2; run netupdate;");
 136         }
 137
 138         printf("turning on display power+backlight ... ");
 139         tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
 140                            0x09, TPS65217_MASK_ALL_BITS);       /* 200 Hz, ON */
 141         tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
 142                            0x62, TPS65217_MASK_ALL_BITS);       /* 100% */
 143         printf("ok.\n");
 144
 145         return 0;
 146 }
 147 #endif /* CONFIG_BOARD_LATE_INIT */