board/BuR/brsmarc1/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for B&R BRSMARC1 Board
   6  *
   7  * Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at>
   8  * B&R Industrial Automation GmbH - http://www.br-automation.com
   9  *
  10  */
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <init.h>
  14 #include <spl.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/omap.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/mem.h>
  22 #include <asm/io.h>
  23 #include <asm/gpio.h>
  24 #include <asm/emif.h>
  25 #include <power/tps65217.h>
  26 #include "../common/bur_common.h"
  27 #include "../common/br_resetc.h"
  28
  29 /* -------------------------------------------------------------------------*/
  30 /* -- defines for used GPIO Hardware -- */
  31 #define PER_RESET               (2 * 32 + 0)
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #if defined(CONFIG_SPL_BUILD)
  36 static const struct ddr_data ddr3_data = {
  37         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  38         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  39         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  40         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  41 };
  42
  43 static const struct cmd_control ddr3_cmd_ctrl_data = {
  44         .cmd0csratio = MT41K256M16HA125E_RATIO,
  45         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  46
  47         .cmd1csratio = MT41K256M16HA125E_RATIO,
  48         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  49
  50         .cmd2csratio = MT41K256M16HA125E_RATIO,
  51         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  52 };
  53
  54 static struct emif_regs ddr3_emif_reg_data = {
  55         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  56         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  57         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  58         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  59         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  60         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  61         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  62 };
  63
  64 static const struct ctrl_ioregs ddr3_ioregs = {
  65         .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  66         .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  67         .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  68         .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  69         .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  70 };
  71
  72 #define OSC     (V_OSCK / 1000000)
  73 const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
  74
  75 void am33xx_spl_board_init(void)
  76 {
  77         struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  78         struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  79
  80         int rc;
  81         /*
  82          * enable additional clocks of modules which are accessed later from
  83          * VxWorks OS
  84          */
  85         u32 *const clk_domains[] = { 0 };
  86         u32 *const clk_modules_specific[] = {
  87                 &cmwkup->wkup_adctscctrl,
  88                 &cmper->spi1clkctrl,
  89                 &cmper->dcan0clkctrl,
  90                 &cmper->dcan1clkctrl,
  91                 &cmper->timer4clkctrl,
  92                 &cmper->timer5clkctrl,
  93                 &cmper->lcdclkctrl,
  94                 &cmper->lcdcclkstctrl,
  95                 0
  96         };
  97         do_enable_clocks(clk_domains, clk_modules_specific, 1);
  98
  99         /* setup I2C */
 100         enable_i2c_pin_mux();
 101
 102         /* peripheral reset */
 103         rc = gpio_request(PER_RESET, "PER_RESET");
 104         if (rc != 0)
 105                 printf("cannot request PER_RESET GPIO!\n");
 106
 107         rc = gpio_direction_output(PER_RESET, 0);
 108         if (rc != 0)
 109                 printf("cannot set PER_RESET GPIO!\n");
 110
 111         /* setup pmic */
 112         pmicsetup(0, 0);
 113 }
 114
 115 const struct dpll_params *get_dpll_ddr_params(void)
 116 {
 117         return &dpll_ddr3;
 118 }
 119
 120 void sdram_init(void)
 121 {
 122         config_ddr(400, &ddr3_ioregs,
 123                    &ddr3_data,
 124                    &ddr3_cmd_ctrl_data,
 125                    &ddr3_emif_reg_data, 0);
 126 }
 127 #endif /* CONFIG_SPL_BUILD */
 128 #if !defined(CONFIG_SPL_BUILD)
 129
 130 /* decision if backlight is switched on or not on powerup */
 131 int board_backlightstate(void)
 132 {
 133         u8 bklmask, rstcause;
 134         int rc = 0;
 135
 136         rc |= br_resetc_regget(RSTCTRL_SCRATCHREG1, &bklmask);
 137         rc |= br_resetc_regget(RSTCTRL_ERSTCAUSE, &rstcause);
 138
 139         if (rc != 0) {
 140                 printf("%s: read rstctrl failed!\n", __func__);
 141                 return 1;
 142         }
 143
 144         if ((rstcause & bklmask) != 0)
 145                 return 0;
 146
 147         return 1;
 148 }
 149
 150 /* Basic board specific setup. run quite after relocation */
 151 int board_init(void)
 152 {
 153         if (power_tps65217_init(0))
 154                 printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
 155
 156         return 0;
 157 }
 158
 159 #if defined(CONFIG_BOARD_LATE_INIT)
 160
 161 int board_late_init(void)
 162 {
 163         br_resetc_bmode();
 164
 165         return 0;
 166 }
 167
 168 #endif /* CONFIG_BOARD_LATE_INIT */
 169 #endif /* !CONFIG_SPL_BUILD */