riscv: board: Add nx25-ae250 to support RISC-V
[platform/kernel/u-boot.git] / board / AndesTech / nx25-ae250 / nx25-ae250.c
1 /*
2  * Copyright (C) 2017 Andes Technology Corporation
3  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <asm/mach-types.h>
9 #include <common.h>
10 #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
11 #include <netdev.h>
12 #endif
13 #include <linux/io.h>
14 #include <faraday/ftsdc010.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 /*
19  * Miscellaneous platform dependent initializations
20  */
21
22 int board_init(void)
23 {
24         gd->bd->bi_arch_number = MACH_TYPE_AE250;
25         gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
26
27         return 0;
28 }
29
30 int dram_init(void)
31 {
32         unsigned long sdram_base = PHYS_SDRAM_0;
33         unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
34         unsigned long actual_size;
35
36         actual_size = get_ram_size((void *)sdram_base, expected_size);
37         gd->ram_size = actual_size;
38
39         if (expected_size != actual_size) {
40                 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
41                         actual_size >> 20, expected_size >> 20);
42         }
43
44         return 0;
45 }
46
47 int dram_init_banksize(void)
48 {
49         gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
50         gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
51         gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
52         gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
53
54         return 0;
55 }
56
57 #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
58 int board_eth_init(bd_t *bd)
59 {
60         return ftmac100_initialize(bd);
61 }
62 #endif
63
64 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
65 {
66         return 0;
67 }
68
69 int board_mmc_init(bd_t *bis)
70 {
71 #ifndef CONFIG_DM_MMC
72 #ifdef CONFIG_FTSDC010
73         ftsdc010_mmc_init(0);
74 #endif
75 #endif
76         return 0;
77 }