board/AndesTech/ax25-ae350/ax25-ae350.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Andes Technology Corporation
   4  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
   5  */
   6
   7 #include <common.h>
   8 #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
   9 #include <netdev.h>
  10 #endif
  11 #include <linux/io.h>
  12 #include <faraday/ftsmc020.h>
  13 #include <fdtdec.h>
  14 #include <dm.h>
  15 #include <spl.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 extern phys_addr_t prior_stage_fdt_address;
  20 /*
  21  * Miscellaneous platform dependent initializations
  22  */
  23
  24 int board_init(void)
  25 {
  26         gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
  27
  28         return 0;
  29 }
  30
  31 int dram_init(void)
  32 {
  33         unsigned long sdram_base = PHYS_SDRAM_0;
  34         unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
  35         unsigned long actual_size;
  36
  37         actual_size = get_ram_size((void *)sdram_base, expected_size);
  38         gd->ram_size = actual_size;
  39
  40         if (expected_size != actual_size) {
  41                 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
  42                         actual_size >> 20, expected_size >> 20);
  43         }
  44
  45         return 0;
  46 }
  47
  48 int dram_init_banksize(void)
  49 {
  50         gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
  51         gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
  52         gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
  53         gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
  54
  55         return 0;
  56 }
  57
  58 #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
  59 int board_eth_init(bd_t *bd)
  60 {
  61         return ftmac100_initialize(bd);
  62 }
  63 #endif
  64
  65 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  66 {
  67         return 0;
  68 }
  69
  70 void *board_fdt_blob_setup(void)
  71 {
  72         return (void *)CONFIG_SYS_FDT_BASE;
  73 }
  74
  75 int smc_init(void)
  76 {
  77         int node = -1;
  78         const char *compat = "andestech,atfsmc020";
  79         void *blob = (void *)gd->fdt_blob;
  80         fdt_addr_t addr;
  81         struct ftsmc020_bank *regs;
  82
  83         node = fdt_node_offset_by_compatible(blob, -1, compat);
  84         if (node < 0)
  85                 return -FDT_ERR_NOTFOUND;
  86
  87         addr = fdtdec_get_addr(blob, node, "reg");
  88
  89         if (addr == FDT_ADDR_T_NONE)
  90                 return -EINVAL;
  91
  92         regs = (struct ftsmc020_bank *)addr;
  93         regs->cr &= ~FTSMC020_BANK_WPROT;
  94
  95         return 0;
  96 }
  97
  98 static void v5l2_init(void)
  99 {
 100         struct udevice *dev;
 101
 102         uclass_get_device(UCLASS_CACHE, 0, &dev);
 103 }
 104
 105 #ifdef CONFIG_BOARD_EARLY_INIT_F
 106 int board_early_init_f(void)
 107 {
 108         smc_init();
 109         v5l2_init();
 110
 111         return 0;
 112 }
 113 #endif
 114
 115 #ifdef CONFIG_SPL
 116 void board_boot_order(u32 *spl_boot_list)
 117 {
 118         u8 i;
 119         u32 boot_devices[] = {
 120 #ifdef CONFIG_SPL_RAM_SUPPORT
 121                 BOOT_DEVICE_RAM,
 122 #endif
 123 #ifdef CONFIG_SPL_MMC_SUPPORT
 124                 BOOT_DEVICE_MMC1,
 125 #endif
 126         };
 127
 128         for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
 129                 spl_boot_list[i] = boot_devices[i];
 130 }
 131 #endif
 132
 133 #ifdef CONFIG_SPL_LOAD_FIT
 134 int board_fit_config_name_match(const char *name)
 135 {
 136         /* boot using first FIT config */
 137         return 0;
 138 }
 139 #endif