1 /* Xtensa configuration-specific ISA information.
2 Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
8 published by the Free Software Foundation; either version 2 of the
9 License, or (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
22 #include <xtensa-isa.h>
23 #include "xtensa-isa-internal.h"
28 static xtensa_sysreg_internal sysregs[] = {
39 { "PTEVADDR", 83, 0 },
44 { "INTERRUPT", 226, 0 },
45 { "INTCLEAR", 227, 0 },
49 { "CCOMPARE0", 240, 0 },
50 { "CCOMPARE1", 241, 0 },
51 { "CCOMPARE2", 242, 0 },
52 { "VECBASE", 231, 0 },
60 { "EXCSAVE1", 209, 0 },
61 { "EXCSAVE2", 210, 0 },
62 { "EXCSAVE3", 211, 0 },
63 { "EXCSAVE4", 212, 0 },
64 { "EXCSAVE5", 213, 0 },
65 { "EXCSAVE6", 214, 0 },
66 { "EXCSAVE7", 215, 0 },
73 { "EXCCAUSE", 232, 0 },
75 { "EXCVADDR", 238, 0 },
76 { "WINDOWBASE", 72, 0 },
77 { "WINDOWSTART", 73, 0 },
85 { "INTENABLE", 228, 0 },
86 { "DBREAKA0", 144, 0 },
87 { "DBREAKC0", 160, 0 },
88 { "DBREAKA1", 145, 0 },
89 { "DBREAKC1", 161, 0 },
90 { "IBREAKA0", 128, 0 },
91 { "IBREAKA1", 129, 0 },
92 { "IBREAKENABLE", 96, 0 },
93 { "ICOUNTLEVEL", 237, 0 },
94 { "DEBUGCAUSE", 233, 0 },
98 { "CPENABLE", 224, 0 },
99 { "SCOMPARE1", 12, 0 },
100 { "THREADPTR", 231, 1 },
105 #define NUM_SYSREGS 74
106 #define MAX_SPECIAL_REG 247
107 #define MAX_USER_REG 233
110 /* Processor states. */
112 static xtensa_state_internal states[] = {
117 { "INTERRUPT", 32, 0 },
120 { "VECBASE", 22, 0 },
128 { "EXCSAVE1", 32, 0 },
129 { "EXCSAVE2", 32, 0 },
130 { "EXCSAVE3", 32, 0 },
131 { "EXCSAVE4", 32, 0 },
132 { "EXCSAVE5", 32, 0 },
133 { "EXCSAVE6", 32, 0 },
134 { "EXCSAVE7", 32, 0 },
141 { "EXCCAUSE", 6, 0 },
142 { "PSINTLEVEL", 4, 0 },
148 { "EXCVADDR", 32, 0 },
149 { "WindowBase", 4, 0 },
150 { "WindowStart", 16, 0 },
151 { "PSCALLINC", 2, 0 },
156 { "THREADPTR", 32, 0 },
157 { "LITBADDR", 20, 0 },
164 { "InOCDMode", 1, 0 },
165 { "INTENABLE", 32, 0 },
166 { "DBREAKA0", 32, 0 },
167 { "DBREAKC0", 8, 0 },
168 { "DBREAKA1", 32, 0 },
169 { "DBREAKC1", 8, 0 },
170 { "IBREAKA0", 32, 0 },
171 { "IBREAKA1", 32, 0 },
172 { "IBREAKENABLE", 2, 0 },
173 { "ICOUNTLEVEL", 4, 0 },
174 { "DEBUGCAUSE", 6, 0 },
176 { "CCOMPARE0", 32, 0 },
177 { "CCOMPARE1", 32, 0 },
178 { "CCOMPARE2", 32, 0 },
182 { "INSTPGSZID4", 2, 0 },
183 { "DATAPGSZID4", 2, 0 },
185 { "CPENABLE", 1, 0 },
186 { "SCOMPARE1", 32, 0 },
187 { "RoundMode", 2, 0 },
188 { "InvalidEnable", 1, 0 },
189 { "DivZeroEnable", 1, 0 },
190 { "OverflowEnable", 1, 0 },
191 { "UnderflowEnable", 1, 0 },
192 { "InexactEnable", 1, 0 },
193 { "InvalidFlag", 1, 0 },
194 { "DivZeroFlag", 1, 0 },
195 { "OverflowFlag", 1, 0 },
196 { "UnderflowFlag", 1, 0 },
197 { "InexactFlag", 1, 0 },
198 { "FPreserved20", 20, 0 },
199 { "FPreserved20a", 20, 0 },
200 { "FPreserved5", 5, 0 },
201 { "FPreserved7", 7, 0 }
204 #define NUM_STATES 89
206 /* Macros for xtensa_state numbers (for use in iclasses because the
207 state numbers are not available when the iclass table is generated). */
209 #define STATE_LCOUNT 0
211 #define STATE_ICOUNT 2
213 #define STATE_INTERRUPT 4
214 #define STATE_CCOUNT 5
215 #define STATE_XTSYNC 6
216 #define STATE_VECBASE 7
219 #define STATE_EPC3 10
220 #define STATE_EPC4 11
221 #define STATE_EPC5 12
222 #define STATE_EPC6 13
223 #define STATE_EPC7 14
224 #define STATE_EXCSAVE1 15
225 #define STATE_EXCSAVE2 16
226 #define STATE_EXCSAVE3 17
227 #define STATE_EXCSAVE4 18
228 #define STATE_EXCSAVE5 19
229 #define STATE_EXCSAVE6 20
230 #define STATE_EXCSAVE7 21
231 #define STATE_EPS2 22
232 #define STATE_EPS3 23
233 #define STATE_EPS4 24
234 #define STATE_EPS5 25
235 #define STATE_EPS6 26
236 #define STATE_EPS7 27
237 #define STATE_EXCCAUSE 28
238 #define STATE_PSINTLEVEL 29
239 #define STATE_PSUM 30
240 #define STATE_PSWOE 31
241 #define STATE_PSRING 32
242 #define STATE_PSEXCM 33
243 #define STATE_DEPC 34
244 #define STATE_EXCVADDR 35
245 #define STATE_WindowBase 36
246 #define STATE_WindowStart 37
247 #define STATE_PSCALLINC 38
248 #define STATE_PSOWB 39
249 #define STATE_LBEG 40
250 #define STATE_LEND 41
252 #define STATE_THREADPTR 43
253 #define STATE_LITBADDR 44
254 #define STATE_LITBEN 45
255 #define STATE_MISC0 46
256 #define STATE_MISC1 47
257 #define STATE_MISC2 48
258 #define STATE_MISC3 49
260 #define STATE_InOCDMode 51
261 #define STATE_INTENABLE 52
262 #define STATE_DBREAKA0 53
263 #define STATE_DBREAKC0 54
264 #define STATE_DBREAKA1 55
265 #define STATE_DBREAKC1 56
266 #define STATE_IBREAKA0 57
267 #define STATE_IBREAKA1 58
268 #define STATE_IBREAKENABLE 59
269 #define STATE_ICOUNTLEVEL 60
270 #define STATE_DEBUGCAUSE 61
271 #define STATE_DBNUM 62
272 #define STATE_CCOMPARE0 63
273 #define STATE_CCOMPARE1 64
274 #define STATE_CCOMPARE2 65
275 #define STATE_ASID3 66
276 #define STATE_ASID2 67
277 #define STATE_ASID1 68
278 #define STATE_INSTPGSZID4 69
279 #define STATE_DATAPGSZID4 70
280 #define STATE_PTBASE 71
281 #define STATE_CPENABLE 72
282 #define STATE_SCOMPARE1 73
283 #define STATE_RoundMode 74
284 #define STATE_InvalidEnable 75
285 #define STATE_DivZeroEnable 76
286 #define STATE_OverflowEnable 77
287 #define STATE_UnderflowEnable 78
288 #define STATE_InexactEnable 79
289 #define STATE_InvalidFlag 80
290 #define STATE_DivZeroFlag 81
291 #define STATE_OverflowFlag 82
292 #define STATE_UnderflowFlag 83
293 #define STATE_InexactFlag 84
294 #define STATE_FPreserved20 85
295 #define STATE_FPreserved20a 86
296 #define STATE_FPreserved5 87
297 #define STATE_FPreserved7 88
300 /* Field definitions. */
303 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
306 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
311 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
314 tie_t = (val << 28) >> 28;
315 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
319 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
322 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
327 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
330 tie_t = (val << 28) >> 28;
331 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
335 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
338 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
343 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
346 tie_t = (val << 28) >> 28;
347 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
351 Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
354 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
359 Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
362 tie_t = (val << 28) >> 28;
363 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
367 Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
370 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
375 Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
378 tie_t = (val << 28) >> 28;
379 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
383 Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
386 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
391 Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
394 tie_t = (val << 28) >> 28;
395 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
399 Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
402 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
407 Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
410 tie_t = (val << 28) >> 28;
411 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
415 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
418 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
423 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
426 tie_t = (val << 31) >> 31;
427 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
431 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
434 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
435 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
440 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
443 tie_t = (val << 28) >> 28;
444 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
445 tie_t = (val << 27) >> 31;
446 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
450 Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
453 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
454 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
459 Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
462 tie_t = (val << 28) >> 28;
463 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
464 tie_t = (val << 27) >> 31;
465 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
469 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
472 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
477 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
480 tie_t = (val << 20) >> 20;
481 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
485 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
488 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
493 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
496 tie_t = (val << 24) >> 24;
497 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
501 Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
504 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
509 Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
512 tie_t = (val << 24) >> 24;
513 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
517 Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
520 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
521 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
526 Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
529 tie_t = (val << 28) >> 28;
530 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
531 tie_t = (val << 24) >> 28;
532 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
536 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
539 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
544 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
547 tie_t = (val << 28) >> 28;
548 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
552 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
555 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
560 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
563 tie_t = (val << 28) >> 28;
564 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
568 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
571 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
576 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
579 tie_t = (val << 28) >> 28;
580 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
584 Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
587 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
592 Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
595 tie_t = (val << 28) >> 28;
596 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
600 Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
603 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
608 Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
611 tie_t = (val << 28) >> 28;
612 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
616 Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
619 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
624 Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
627 tie_t = (val << 28) >> 28;
628 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
632 Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
635 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
640 Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
643 tie_t = (val << 28) >> 28;
644 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
648 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
651 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
652 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
657 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
660 tie_t = (val << 24) >> 24;
661 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
662 tie_t = (val << 20) >> 28;
663 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
667 Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
670 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
671 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
676 Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
679 tie_t = (val << 24) >> 24;
680 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
681 tie_t = (val << 20) >> 28;
682 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
686 Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
689 tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
694 Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
697 tie_t = (val << 20) >> 20;
698 insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
702 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
705 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
710 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
713 tie_t = (val << 16) >> 16;
714 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
718 Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
721 tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
726 Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
729 tie_t = (val << 16) >> 16;
730 insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
734 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
737 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
742 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
745 tie_t = (val << 30) >> 30;
746 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
750 Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
753 tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
758 Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
761 tie_t = (val << 30) >> 30;
762 insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
766 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
769 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
774 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
777 tie_t = (val << 30) >> 30;
778 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
782 Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
785 tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
790 Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
793 tie_t = (val << 30) >> 30;
794 insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
798 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
801 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
806 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
809 tie_t = (val << 14) >> 14;
810 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
814 Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
817 tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
822 Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
825 tie_t = (val << 14) >> 14;
826 insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
830 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
833 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
838 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
841 tie_t = (val << 28) >> 28;
842 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
846 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
849 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
854 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
857 tie_t = (val << 28) >> 28;
858 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
862 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
865 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
870 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
873 tie_t = (val << 28) >> 28;
874 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
878 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
881 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
886 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
889 tie_t = (val << 28) >> 28;
890 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
894 Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
897 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
902 Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
905 tie_t = (val << 28) >> 28;
906 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
910 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
913 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
918 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
921 tie_t = (val << 28) >> 28;
922 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
926 Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
929 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
934 Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
937 tie_t = (val << 28) >> 28;
938 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
942 Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
945 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
950 Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
953 tie_t = (val << 28) >> 28;
954 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
958 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
961 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
966 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
969 tie_t = (val << 28) >> 28;
970 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
974 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
977 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
982 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
985 tie_t = (val << 28) >> 28;
986 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
990 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
993 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
998 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1001 tie_t = (val << 28) >> 28;
1002 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1006 Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1009 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1014 Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1017 tie_t = (val << 28) >> 28;
1018 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1022 Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1025 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1030 Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1033 tie_t = (val << 28) >> 28;
1034 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1038 Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1041 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1046 Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1049 tie_t = (val << 28) >> 28;
1050 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1054 Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
1057 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1062 Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
1065 tie_t = (val << 28) >> 28;
1066 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1070 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
1073 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1078 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1081 tie_t = (val << 31) >> 31;
1082 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1086 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
1089 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1094 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1097 tie_t = (val << 31) >> 31;
1098 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1102 Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1105 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1110 Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1113 tie_t = (val << 31) >> 31;
1114 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1118 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
1121 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1122 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1127 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1130 tie_t = (val << 28) >> 28;
1131 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1132 tie_t = (val << 27) >> 31;
1133 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1137 Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1140 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1141 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1146 Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1149 tie_t = (val << 28) >> 28;
1150 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1151 tie_t = (val << 27) >> 31;
1152 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1156 Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1159 tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
1164 Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1167 tie_t = (val << 27) >> 27;
1168 insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
1172 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
1175 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1176 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1181 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1184 tie_t = (val << 28) >> 28;
1185 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1186 tie_t = (val << 27) >> 31;
1187 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1191 Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1194 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1195 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1200 Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1203 tie_t = (val << 28) >> 28;
1204 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1205 tie_t = (val << 27) >> 31;
1206 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1210 Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1213 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1214 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1219 Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1222 tie_t = (val << 28) >> 28;
1223 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1224 tie_t = (val << 27) >> 31;
1225 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1229 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
1232 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1233 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1238 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1241 tie_t = (val << 28) >> 28;
1242 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1243 tie_t = (val << 27) >> 31;
1244 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1248 Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1251 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1252 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1257 Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1260 tie_t = (val << 28) >> 28;
1261 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1262 tie_t = (val << 27) >> 31;
1263 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1267 Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1270 tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1275 Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1278 tie_t = (val << 27) >> 27;
1279 insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1283 Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1286 tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1291 Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1294 tie_t = (val << 27) >> 27;
1295 insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1299 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
1302 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1307 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1310 tie_t = (val << 31) >> 31;
1311 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1315 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
1318 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1319 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1324 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1327 tie_t = (val << 28) >> 28;
1328 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1329 tie_t = (val << 27) >> 31;
1330 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1334 Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1337 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
1338 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1343 Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1346 tie_t = (val << 28) >> 28;
1347 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1348 tie_t = (val << 27) >> 31;
1349 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
1353 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
1356 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1357 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1362 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1365 tie_t = (val << 28) >> 28;
1366 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1367 tie_t = (val << 24) >> 28;
1368 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1372 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
1375 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1376 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1381 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1384 tie_t = (val << 28) >> 28;
1385 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1386 tie_t = (val << 24) >> 28;
1387 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1391 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1394 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1395 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1400 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1403 tie_t = (val << 28) >> 28;
1404 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1405 tie_t = (val << 24) >> 28;
1406 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1410 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1413 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1414 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1419 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1422 tie_t = (val << 28) >> 28;
1423 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1424 tie_t = (val << 24) >> 28;
1425 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1429 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1432 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1433 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1438 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1441 tie_t = (val << 28) >> 28;
1442 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1443 tie_t = (val << 24) >> 28;
1444 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1448 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1451 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1452 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1457 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1460 tie_t = (val << 28) >> 28;
1461 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1462 tie_t = (val << 24) >> 28;
1463 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1467 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1470 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1475 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1478 tie_t = (val << 29) >> 29;
1479 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1483 Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1486 tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
1491 Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1494 tie_t = (val << 29) >> 29;
1495 insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
1499 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1502 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1507 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1510 tie_t = (val << 28) >> 28;
1511 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1515 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1518 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1523 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1526 tie_t = (val << 28) >> 28;
1527 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1531 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1534 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1539 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1542 tie_t = (val << 28) >> 28;
1543 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1547 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1550 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1551 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1556 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1559 tie_t = (val << 30) >> 30;
1560 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1561 tie_t = (val << 28) >> 30;
1562 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
1566 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1569 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1574 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1577 tie_t = (val << 31) >> 31;
1578 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1582 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
1585 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1590 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1593 tie_t = (val << 31) >> 31;
1594 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1598 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1601 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1606 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1609 tie_t = (val << 28) >> 28;
1610 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1614 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1617 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1622 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1625 tie_t = (val << 28) >> 28;
1626 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1630 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1633 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1638 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1641 tie_t = (val << 30) >> 30;
1642 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1646 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1649 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1654 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1657 tie_t = (val << 30) >> 30;
1658 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1662 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1665 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1670 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1673 tie_t = (val << 28) >> 28;
1674 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1678 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1681 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1686 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1689 tie_t = (val << 28) >> 28;
1690 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1694 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1697 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1702 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1705 tie_t = (val << 29) >> 29;
1706 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1710 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1713 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1718 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1721 tie_t = (val << 29) >> 29;
1722 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1726 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1729 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1734 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1737 tie_t = (val << 31) >> 31;
1738 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1742 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1745 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1750 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1753 tie_t = (val << 31) >> 31;
1754 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1758 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1761 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1762 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1767 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1770 tie_t = (val << 28) >> 28;
1771 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1772 tie_t = (val << 26) >> 30;
1773 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1777 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1780 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1781 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1786 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1789 tie_t = (val << 28) >> 28;
1790 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1791 tie_t = (val << 26) >> 30;
1792 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1796 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1799 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1800 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1805 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1808 tie_t = (val << 28) >> 28;
1809 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1810 tie_t = (val << 25) >> 29;
1811 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1815 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1818 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1819 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1824 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1827 tie_t = (val << 28) >> 28;
1828 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1829 tie_t = (val << 25) >> 29;
1830 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
1834 Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1837 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1842 Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1845 tie_t = (val << 25) >> 25;
1846 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
1850 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
1853 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
1858 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1861 tie_t = (val << 31) >> 31;
1862 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
1866 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
1869 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1874 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1877 tie_t = (val << 31) >> 31;
1878 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1882 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
1885 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1890 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1893 tie_t = (val << 30) >> 30;
1894 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
1898 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
1901 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1906 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1909 tie_t = (val << 31) >> 31;
1910 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
1914 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
1917 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1922 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1925 tie_t = (val << 31) >> 31;
1926 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1930 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
1933 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1938 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1941 tie_t = (val << 30) >> 30;
1942 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1946 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
1949 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
1954 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1957 tie_t = (val << 30) >> 30;
1958 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
1962 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
1965 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1970 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1973 tie_t = (val << 31) >> 31;
1974 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
1978 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
1981 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1986 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1989 tie_t = (val << 31) >> 31;
1990 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
1994 Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
1997 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2002 Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2005 tie_t = (val << 29) >> 29;
2006 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2010 Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
2013 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2018 Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2021 tie_t = (val << 29) >> 29;
2022 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2026 Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
2029 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2034 Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2037 tie_t = (val << 29) >> 29;
2038 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2042 Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
2045 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2050 Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2053 tie_t = (val << 29) >> 29;
2054 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
2058 Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
2061 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2066 Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2069 tie_t = (val << 29) >> 29;
2070 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
2074 Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
2077 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2082 Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2085 tie_t = (val << 29) >> 29;
2086 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
2090 Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
2093 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2098 Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2101 tie_t = (val << 29) >> 29;
2102 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2106 Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
2109 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2114 Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2117 tie_t = (val << 29) >> 29;
2118 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2122 Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
2125 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2130 Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2133 tie_t = (val << 29) >> 29;
2134 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2138 Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
2141 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2146 Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2149 tie_t = (val << 30) >> 30;
2150 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2154 Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
2157 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2162 Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2165 tie_t = (val << 30) >> 30;
2166 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2170 Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
2173 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2178 Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2181 tie_t = (val << 30) >> 30;
2182 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2186 Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
2189 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2194 Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2197 tie_t = (val << 30) >> 30;
2198 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2202 Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
2205 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2210 Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2213 tie_t = (val << 30) >> 30;
2214 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2218 Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
2221 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2226 Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2229 tie_t = (val << 30) >> 30;
2230 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2234 Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
2237 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2242 Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2245 tie_t = (val << 30) >> 30;
2246 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2250 Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
2253 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2258 Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2261 tie_t = (val << 30) >> 30;
2262 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2266 Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
2269 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2274 Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2277 tie_t = (val << 30) >> 30;
2278 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2282 Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
2285 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2290 Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2293 tie_t = (val << 31) >> 31;
2294 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2298 Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
2301 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2306 Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2309 tie_t = (val << 31) >> 31;
2310 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2314 Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
2317 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2322 Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2325 tie_t = (val << 31) >> 31;
2326 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2330 Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
2333 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2338 Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2341 tie_t = (val << 31) >> 31;
2342 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2346 Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
2349 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2354 Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2357 tie_t = (val << 31) >> 31;
2358 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2362 Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
2365 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2370 Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2373 tie_t = (val << 31) >> 31;
2374 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2378 Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
2381 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2386 Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2389 tie_t = (val << 31) >> 31;
2390 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2394 Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
2397 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2402 Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2405 tie_t = (val << 31) >> 31;
2406 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2410 Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
2413 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2418 Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2421 tie_t = (val << 31) >> 31;
2422 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2426 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
2429 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
2434 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2437 tie_t = (val << 17) >> 17;
2438 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
2442 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
2445 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
2450 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2453 tie_t = (val << 14) >> 14;
2454 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
2458 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2461 tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14);
2466 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2469 tie_t = (val << 14) >> 14;
2470 insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8);
2474 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2477 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
2482 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2485 tie_t = (val << 28) >> 28;
2486 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
2490 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2493 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2498 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2501 tie_t = (val << 29) >> 29;
2502 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2506 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2509 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2514 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2517 tie_t = (val << 29) >> 29;
2518 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2522 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2525 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
2530 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2533 tie_t = (val << 29) >> 29;
2534 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
2538 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2541 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
2546 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2549 tie_t = (val << 29) >> 29;
2550 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
2554 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2557 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
2558 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
2563 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2566 tie_t = (val << 28) >> 28;
2567 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
2568 tie_t = (val << 24) >> 28;
2569 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
2573 Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2576 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
2581 Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2584 tie_t = (val << 30) >> 30;
2585 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
2589 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2592 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2597 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2600 tie_t = (val << 28) >> 28;
2601 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2605 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2608 tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
2613 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2616 tie_t = (val << 31) >> 31;
2617 insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
2621 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2624 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
2629 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2632 tie_t = (val << 30) >> 30;
2633 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
2637 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2640 tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27);
2645 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2648 tie_t = (val << 27) >> 27;
2649 insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13);
2653 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2656 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2661 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2664 tie_t = (val << 26) >> 26;
2665 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2669 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2672 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2673 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2678 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2681 tie_t = (val << 29) >> 29;
2682 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2683 tie_t = (val << 23) >> 26;
2684 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2688 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2691 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2692 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2697 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2700 tie_t = (val << 29) >> 29;
2701 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2702 tie_t = (val << 23) >> 26;
2703 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2707 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2710 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2711 tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
2716 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2719 tie_t = (val << 30) >> 30;
2720 insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
2721 tie_t = (val << 24) >> 26;
2722 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2726 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2729 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2730 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2735 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2738 tie_t = (val << 31) >> 31;
2739 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2740 tie_t = (val << 25) >> 26;
2741 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2745 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2748 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2749 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
2754 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2757 tie_t = (val << 30) >> 30;
2758 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2759 tie_t = (val << 24) >> 26;
2760 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2764 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2767 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2768 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
2773 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2776 tie_t = (val << 30) >> 30;
2777 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2778 tie_t = (val << 24) >> 26;
2779 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2783 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2786 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2787 tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
2792 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2795 tie_t = (val << 31) >> 31;
2796 insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
2797 tie_t = (val << 25) >> 26;
2798 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2802 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2805 tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
2810 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2813 tie_t = (val << 29) >> 29;
2814 insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
2818 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2821 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2826 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2829 tie_t = (val << 31) >> 31;
2830 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2834 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2837 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2838 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2843 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2846 tie_t = (val << 28) >> 28;
2847 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2848 tie_t = (val << 27) >> 31;
2849 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2853 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2856 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2861 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2864 tie_t = (val << 30) >> 30;
2865 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2869 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2872 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
2873 tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
2878 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2881 tie_t = (val << 26) >> 26;
2882 insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
2883 tie_t = (val << 21) >> 27;
2884 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
2888 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2891 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2892 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2897 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2900 tie_t = (val << 28) >> 28;
2901 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2902 tie_t = (val << 27) >> 31;
2903 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2907 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2910 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2911 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
2916 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2919 tie_t = (val << 31) >> 31;
2920 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
2921 tie_t = (val << 29) >> 30;
2922 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2926 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2929 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2930 tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
2935 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2938 tie_t = (val << 27) >> 27;
2939 insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
2940 tie_t = (val << 26) >> 31;
2941 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2945 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2948 tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
2953 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2956 tie_t = (val << 29) >> 29;
2957 insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
2961 Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2964 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2969 Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2972 tie_t = (val << 29) >> 29;
2973 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2977 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2980 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2985 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2988 tie_t = (val << 31) >> 31;
2989 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2993 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2996 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2997 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3002 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3005 tie_t = (val << 31) >> 31;
3006 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3007 tie_t = (val << 30) >> 31;
3008 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3012 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3015 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3016 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3017 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
3022 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3025 tie_t = (val << 31) >> 31;
3026 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
3027 tie_t = (val << 30) >> 31;
3028 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3029 tie_t = (val << 29) >> 31;
3030 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3034 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3037 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3038 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3039 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
3044 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3047 tie_t = (val << 31) >> 31;
3048 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
3049 tie_t = (val << 30) >> 31;
3050 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3051 tie_t = (val << 29) >> 31;
3052 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3056 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3059 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3060 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
3065 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3068 tie_t = (val << 29) >> 29;
3069 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
3070 tie_t = (val << 28) >> 31;
3071 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3075 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3078 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3079 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
3084 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3087 tie_t = (val << 29) >> 29;
3088 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
3089 tie_t = (val << 28) >> 31;
3090 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3094 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3097 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3098 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
3103 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3106 tie_t = (val << 30) >> 30;
3107 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
3108 tie_t = (val << 29) >> 31;
3109 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3113 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3116 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3117 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
3122 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3125 tie_t = (val << 31) >> 31;
3126 insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
3127 tie_t = (val << 30) >> 31;
3128 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3132 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3135 tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
3140 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3143 tie_t = (val << 30) >> 30;
3144 insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
3148 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3151 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3156 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3159 tie_t = (val << 31) >> 31;
3160 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3164 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3167 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
3168 tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
3169 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3174 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3177 tie_t = (val << 28) >> 28;
3178 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3179 tie_t = (val << 26) >> 30;
3180 insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
3181 tie_t = (val << 22) >> 28;
3182 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
3186 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3189 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3190 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
3195 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3198 tie_t = (val << 31) >> 31;
3199 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
3200 tie_t = (val << 30) >> 31;
3201 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3205 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3208 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3209 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
3214 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3217 tie_t = (val << 30) >> 30;
3218 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
3219 tie_t = (val << 29) >> 31;
3220 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3224 Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3227 tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27);
3232 Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3235 tie_t = (val << 27) >> 27;
3236 insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27);
3240 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3243 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3244 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3245 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3250 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3253 tie_t = (val << 28) >> 28;
3254 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3255 tie_t = (val << 27) >> 31;
3256 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3257 tie_t = (val << 24) >> 29;
3258 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3262 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3265 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3270 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3273 tie_t = (val << 29) >> 29;
3274 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3278 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3281 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3282 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3283 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3288 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3291 tie_t = (val << 28) >> 28;
3292 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3293 tie_t = (val << 27) >> 31;
3294 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3295 tie_t = (val << 24) >> 29;
3296 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3300 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3303 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3304 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3305 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3310 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3313 tie_t = (val << 28) >> 28;
3314 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3315 tie_t = (val << 27) >> 31;
3316 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3317 tie_t = (val << 24) >> 29;
3318 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3322 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3325 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3326 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3327 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3332 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3335 tie_t = (val << 28) >> 28;
3336 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3337 tie_t = (val << 27) >> 31;
3338 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3339 tie_t = (val << 24) >> 29;
3340 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3344 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3347 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3348 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3353 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3356 tie_t = (val << 31) >> 31;
3357 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3358 tie_t = (val << 28) >> 29;
3359 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3363 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3366 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3367 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3372 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3375 tie_t = (val << 31) >> 31;
3376 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3377 tie_t = (val << 28) >> 29;
3378 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3382 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3385 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3386 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3391 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3394 tie_t = (val << 31) >> 31;
3395 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3396 tie_t = (val << 28) >> 29;
3397 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3401 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3404 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3405 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3410 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3413 tie_t = (val << 31) >> 31;
3414 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3415 tie_t = (val << 28) >> 29;
3416 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3420 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3423 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3424 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3429 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3432 tie_t = (val << 31) >> 31;
3433 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3434 tie_t = (val << 28) >> 29;
3435 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3439 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3442 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3443 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3448 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3451 tie_t = (val << 31) >> 31;
3452 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3453 tie_t = (val << 28) >> 29;
3454 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3458 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3461 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3462 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3467 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3470 tie_t = (val << 31) >> 31;
3471 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3472 tie_t = (val << 28) >> 29;
3473 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3477 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3480 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3481 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3486 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3489 tie_t = (val << 31) >> 31;
3490 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3491 tie_t = (val << 28) >> 29;
3492 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3496 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3499 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3500 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3505 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3508 tie_t = (val << 31) >> 31;
3509 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3510 tie_t = (val << 28) >> 29;
3511 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3515 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3518 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3519 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3524 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3527 tie_t = (val << 31) >> 31;
3528 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3529 tie_t = (val << 28) >> 29;
3530 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3534 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3537 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3538 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3543 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3546 tie_t = (val << 31) >> 31;
3547 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3548 tie_t = (val << 28) >> 29;
3549 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3553 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3556 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3557 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3562 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3565 tie_t = (val << 31) >> 31;
3566 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3567 tie_t = (val << 28) >> 29;
3568 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3572 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3575 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3576 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3581 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3584 tie_t = (val << 31) >> 31;
3585 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3586 tie_t = (val << 28) >> 29;
3587 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3591 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3594 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3595 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3600 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3603 tie_t = (val << 31) >> 31;
3604 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3605 tie_t = (val << 28) >> 29;
3606 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3610 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3613 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3614 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3619 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3622 tie_t = (val << 31) >> 31;
3623 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3624 tie_t = (val << 28) >> 29;
3625 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3629 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3632 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3633 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3638 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3641 tie_t = (val << 31) >> 31;
3642 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3643 tie_t = (val << 28) >> 29;
3644 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3648 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3651 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3652 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3657 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3660 tie_t = (val << 31) >> 31;
3661 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3662 tie_t = (val << 28) >> 29;
3663 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3667 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3670 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3671 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3676 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3679 tie_t = (val << 31) >> 31;
3680 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3681 tie_t = (val << 28) >> 29;
3682 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3686 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3689 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3690 tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5);
3695 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3698 tie_t = (val << 5) >> 5;
3699 insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0);
3700 tie_t = (val << 2) >> 29;
3701 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3705 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3708 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
3713 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3716 tie_t = (val << 28) >> 28;
3717 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
3721 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
3722 uint32 val ATTRIBUTE_UNUSED)
3728 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3734 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3740 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3746 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3752 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3758 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3764 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3770 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3776 Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3782 Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3788 Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3794 Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3800 /* Functional units. */
3802 static xtensa_funcUnit_internal funcUnits[] = {
3807 /* Register files. */
3809 static xtensa_regfile_internal regfiles[] = {
3810 { "AR", "a", 0, 32, 64 },
3811 { "MR", "m", 1, 32, 4 },
3812 { "BR", "b", 2, 1, 16 },
3813 { "FR", "f", 3, 32, 16 },
3814 { "BR2", "b", 2, 2, 8 },
3815 { "BR4", "b", 2, 4, 4 },
3816 { "BR8", "b", 2, 8, 2 },
3817 { "BR16", "b", 2, 16, 1 }
3823 static xtensa_interface_internal interfaces[] = {
3828 /* Constant tables. */
3830 /* constant table ai4c */
3831 static const unsigned CONST_TBL_ai4c_0[] = {
3851 /* constant table b4c */
3852 static const unsigned CONST_TBL_b4c_0[] = {
3872 /* constant table b4cu */
3873 static const unsigned CONST_TBL_b4cu_0[] = {
3894 /* Instruction operands. */
3897 Operand_soffsetx4_decode (uint32 *valp)
3899 unsigned soffsetx4_0, offset_0;
3900 offset_0 = *valp & 0x3ffff;
3901 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
3902 *valp = soffsetx4_0;
3907 Operand_soffsetx4_encode (uint32 *valp)
3909 unsigned offset_0, soffsetx4_0;
3910 soffsetx4_0 = *valp;
3911 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
3917 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
3919 *valp -= (pc & ~0x3);
3924 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
3926 *valp += (pc & ~0x3);
3931 Operand_uimm12x8_decode (uint32 *valp)
3933 unsigned uimm12x8_0, imm12_0;
3934 imm12_0 = *valp & 0xfff;
3935 uimm12x8_0 = imm12_0 << 3;
3941 Operand_uimm12x8_encode (uint32 *valp)
3943 unsigned imm12_0, uimm12x8_0;
3945 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
3951 Operand_simm4_decode (uint32 *valp)
3953 unsigned simm4_0, mn_0;
3955 simm4_0 = ((int) mn_0 << 28) >> 28;
3961 Operand_simm4_encode (uint32 *valp)
3963 unsigned mn_0, simm4_0;
3965 mn_0 = (simm4_0 & 0xf);
3971 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
3977 Operand_arr_encode (uint32 *valp)
3980 error = (*valp & ~0xf) != 0;
3985 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
3991 Operand_ars_encode (uint32 *valp)
3994 error = (*valp & ~0xf) != 0;
3999 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
4005 Operand_art_encode (uint32 *valp)
4008 error = (*valp & ~0xf) != 0;
4013 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
4019 Operand_ar0_encode (uint32 *valp)
4022 error = (*valp & ~0x3f) != 0;
4027 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
4033 Operand_ar4_encode (uint32 *valp)
4036 error = (*valp & ~0x3f) != 0;
4041 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
4047 Operand_ar8_encode (uint32 *valp)
4050 error = (*valp & ~0x3f) != 0;
4055 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
4061 Operand_ar12_encode (uint32 *valp)
4064 error = (*valp & ~0x3f) != 0;
4069 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
4075 Operand_ars_entry_encode (uint32 *valp)
4078 error = (*valp & ~0x3f) != 0;
4083 Operand_immrx4_decode (uint32 *valp)
4085 unsigned immrx4_0, r_0;
4087 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
4093 Operand_immrx4_encode (uint32 *valp)
4095 unsigned r_0, immrx4_0;
4097 r_0 = ((immrx4_0 >> 2) & 0xf);
4103 Operand_lsi4x4_decode (uint32 *valp)
4105 unsigned lsi4x4_0, r_0;
4107 lsi4x4_0 = r_0 << 2;
4113 Operand_lsi4x4_encode (uint32 *valp)
4115 unsigned r_0, lsi4x4_0;
4117 r_0 = ((lsi4x4_0 >> 2) & 0xf);
4123 Operand_simm7_decode (uint32 *valp)
4125 unsigned simm7_0, imm7_0;
4126 imm7_0 = *valp & 0x7f;
4127 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
4133 Operand_simm7_encode (uint32 *valp)
4135 unsigned imm7_0, simm7_0;
4137 imm7_0 = (simm7_0 & 0x7f);
4143 Operand_uimm6_decode (uint32 *valp)
4145 unsigned uimm6_0, imm6_0;
4146 imm6_0 = *valp & 0x3f;
4147 uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
4153 Operand_uimm6_encode (uint32 *valp)
4155 unsigned imm6_0, uimm6_0;
4157 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
4163 Operand_uimm6_ator (uint32 *valp, uint32 pc)
4170 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
4177 Operand_ai4const_decode (uint32 *valp)
4179 unsigned ai4const_0, t_0;
4181 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
4187 Operand_ai4const_encode (uint32 *valp)
4189 unsigned t_0, ai4const_0;
4193 case 0xffffffff: t_0 = 0; break;
4194 case 0x1: t_0 = 0x1; break;
4195 case 0x2: t_0 = 0x2; break;
4196 case 0x3: t_0 = 0x3; break;
4197 case 0x4: t_0 = 0x4; break;
4198 case 0x5: t_0 = 0x5; break;
4199 case 0x6: t_0 = 0x6; break;
4200 case 0x7: t_0 = 0x7; break;
4201 case 0x8: t_0 = 0x8; break;
4202 case 0x9: t_0 = 0x9; break;
4203 case 0xa: t_0 = 0xa; break;
4204 case 0xb: t_0 = 0xb; break;
4205 case 0xc: t_0 = 0xc; break;
4206 case 0xd: t_0 = 0xd; break;
4207 case 0xe: t_0 = 0xe; break;
4208 default: t_0 = 0xf; break;
4215 Operand_b4const_decode (uint32 *valp)
4217 unsigned b4const_0, r_0;
4219 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
4225 Operand_b4const_encode (uint32 *valp)
4227 unsigned r_0, b4const_0;
4231 case 0xffffffff: r_0 = 0; break;
4232 case 0x1: r_0 = 0x1; break;
4233 case 0x2: r_0 = 0x2; break;
4234 case 0x3: r_0 = 0x3; break;
4235 case 0x4: r_0 = 0x4; break;
4236 case 0x5: r_0 = 0x5; break;
4237 case 0x6: r_0 = 0x6; break;
4238 case 0x7: r_0 = 0x7; break;
4239 case 0x8: r_0 = 0x8; break;
4240 case 0xa: r_0 = 0x9; break;
4241 case 0xc: r_0 = 0xa; break;
4242 case 0x10: r_0 = 0xb; break;
4243 case 0x20: r_0 = 0xc; break;
4244 case 0x40: r_0 = 0xd; break;
4245 case 0x80: r_0 = 0xe; break;
4246 default: r_0 = 0xf; break;
4253 Operand_b4constu_decode (uint32 *valp)
4255 unsigned b4constu_0, r_0;
4257 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
4263 Operand_b4constu_encode (uint32 *valp)
4265 unsigned r_0, b4constu_0;
4269 case 0x8000: r_0 = 0; break;
4270 case 0x10000: r_0 = 0x1; break;
4271 case 0x2: r_0 = 0x2; break;
4272 case 0x3: r_0 = 0x3; break;
4273 case 0x4: r_0 = 0x4; break;
4274 case 0x5: r_0 = 0x5; break;
4275 case 0x6: r_0 = 0x6; break;
4276 case 0x7: r_0 = 0x7; break;
4277 case 0x8: r_0 = 0x8; break;
4278 case 0xa: r_0 = 0x9; break;
4279 case 0xc: r_0 = 0xa; break;
4280 case 0x10: r_0 = 0xb; break;
4281 case 0x20: r_0 = 0xc; break;
4282 case 0x40: r_0 = 0xd; break;
4283 case 0x80: r_0 = 0xe; break;
4284 default: r_0 = 0xf; break;
4291 Operand_uimm8_decode (uint32 *valp)
4293 unsigned uimm8_0, imm8_0;
4294 imm8_0 = *valp & 0xff;
4301 Operand_uimm8_encode (uint32 *valp)
4303 unsigned imm8_0, uimm8_0;
4305 imm8_0 = (uimm8_0 & 0xff);
4311 Operand_uimm8x2_decode (uint32 *valp)
4313 unsigned uimm8x2_0, imm8_0;
4314 imm8_0 = *valp & 0xff;
4315 uimm8x2_0 = imm8_0 << 1;
4321 Operand_uimm8x2_encode (uint32 *valp)
4323 unsigned imm8_0, uimm8x2_0;
4325 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
4331 Operand_uimm8x4_decode (uint32 *valp)
4333 unsigned uimm8x4_0, imm8_0;
4334 imm8_0 = *valp & 0xff;
4335 uimm8x4_0 = imm8_0 << 2;
4341 Operand_uimm8x4_encode (uint32 *valp)
4343 unsigned imm8_0, uimm8x4_0;
4345 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
4351 Operand_uimm4x16_decode (uint32 *valp)
4353 unsigned uimm4x16_0, op2_0;
4354 op2_0 = *valp & 0xf;
4355 uimm4x16_0 = op2_0 << 4;
4361 Operand_uimm4x16_encode (uint32 *valp)
4363 unsigned op2_0, uimm4x16_0;
4365 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
4371 Operand_simm8_decode (uint32 *valp)
4373 unsigned simm8_0, imm8_0;
4374 imm8_0 = *valp & 0xff;
4375 simm8_0 = ((int) imm8_0 << 24) >> 24;
4381 Operand_simm8_encode (uint32 *valp)
4383 unsigned imm8_0, simm8_0;
4385 imm8_0 = (simm8_0 & 0xff);
4391 Operand_simm8x256_decode (uint32 *valp)
4393 unsigned simm8x256_0, imm8_0;
4394 imm8_0 = *valp & 0xff;
4395 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
4396 *valp = simm8x256_0;
4401 Operand_simm8x256_encode (uint32 *valp)
4403 unsigned imm8_0, simm8x256_0;
4404 simm8x256_0 = *valp;
4405 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
4411 Operand_simm12b_decode (uint32 *valp)
4413 unsigned simm12b_0, imm12b_0;
4414 imm12b_0 = *valp & 0xfff;
4415 simm12b_0 = ((int) imm12b_0 << 20) >> 20;
4421 Operand_simm12b_encode (uint32 *valp)
4423 unsigned imm12b_0, simm12b_0;
4425 imm12b_0 = (simm12b_0 & 0xfff);
4431 Operand_msalp32_decode (uint32 *valp)
4433 unsigned msalp32_0, sal_0;
4434 sal_0 = *valp & 0x1f;
4435 msalp32_0 = 0x20 - sal_0;
4441 Operand_msalp32_encode (uint32 *valp)
4443 unsigned sal_0, msalp32_0;
4445 sal_0 = (0x20 - msalp32_0) & 0x1f;
4451 Operand_op2p1_decode (uint32 *valp)
4453 unsigned op2p1_0, op2_0;
4454 op2_0 = *valp & 0xf;
4455 op2p1_0 = op2_0 + 0x1;
4461 Operand_op2p1_encode (uint32 *valp)
4463 unsigned op2_0, op2p1_0;
4465 op2_0 = (op2p1_0 - 0x1) & 0xf;
4471 Operand_label8_decode (uint32 *valp)
4473 unsigned label8_0, imm8_0;
4474 imm8_0 = *valp & 0xff;
4475 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
4481 Operand_label8_encode (uint32 *valp)
4483 unsigned imm8_0, label8_0;
4485 imm8_0 = (label8_0 - 0x4) & 0xff;
4491 Operand_label8_ator (uint32 *valp, uint32 pc)
4498 Operand_label8_rtoa (uint32 *valp, uint32 pc)
4505 Operand_ulabel8_decode (uint32 *valp)
4507 unsigned ulabel8_0, imm8_0;
4508 imm8_0 = *valp & 0xff;
4509 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
4515 Operand_ulabel8_encode (uint32 *valp)
4517 unsigned imm8_0, ulabel8_0;
4519 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
4525 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
4532 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
4539 Operand_label12_decode (uint32 *valp)
4541 unsigned label12_0, imm12_0;
4542 imm12_0 = *valp & 0xfff;
4543 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
4549 Operand_label12_encode (uint32 *valp)
4551 unsigned imm12_0, label12_0;
4553 imm12_0 = (label12_0 - 0x4) & 0xfff;
4559 Operand_label12_ator (uint32 *valp, uint32 pc)
4566 Operand_label12_rtoa (uint32 *valp, uint32 pc)
4573 Operand_soffset_decode (uint32 *valp)
4575 unsigned soffset_0, offset_0;
4576 offset_0 = *valp & 0x3ffff;
4577 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
4583 Operand_soffset_encode (uint32 *valp)
4585 unsigned offset_0, soffset_0;
4587 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
4593 Operand_soffset_ator (uint32 *valp, uint32 pc)
4600 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
4607 Operand_uimm16x4_decode (uint32 *valp)
4609 unsigned uimm16x4_0, imm16_0;
4610 imm16_0 = *valp & 0xffff;
4611 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
4617 Operand_uimm16x4_encode (uint32 *valp)
4619 unsigned imm16_0, uimm16x4_0;
4621 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
4627 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
4629 *valp -= ((pc + 3) & ~0x3);
4634 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
4636 *valp += ((pc + 3) & ~0x3);
4641 Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
4647 Operand_mx_encode (uint32 *valp)
4650 error = (*valp & ~0x3) != 0;
4655 Operand_my_decode (uint32 *valp)
4662 Operand_my_encode (uint32 *valp)
4665 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
4671 Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
4677 Operand_mw_encode (uint32 *valp)
4680 error = (*valp & ~0x3) != 0;
4685 Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
4691 Operand_mr0_encode (uint32 *valp)
4694 error = (*valp & ~0x3) != 0;
4699 Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
4705 Operand_mr1_encode (uint32 *valp)
4708 error = (*valp & ~0x3) != 0;
4713 Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
4719 Operand_mr2_encode (uint32 *valp)
4722 error = (*valp & ~0x3) != 0;
4727 Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
4733 Operand_mr3_encode (uint32 *valp)
4736 error = (*valp & ~0x3) != 0;
4741 Operand_immt_decode (uint32 *valp)
4743 unsigned immt_0, t_0;
4751 Operand_immt_encode (uint32 *valp)
4753 unsigned t_0, immt_0;
4761 Operand_imms_decode (uint32 *valp)
4763 unsigned imms_0, s_0;
4771 Operand_imms_encode (uint32 *valp)
4773 unsigned s_0, imms_0;
4781 Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
4787 Operand_bt_encode (uint32 *valp)
4790 error = (*valp & ~0xf) != 0;
4795 Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
4801 Operand_bs_encode (uint32 *valp)
4804 error = (*valp & ~0xf) != 0;
4809 Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
4815 Operand_br_encode (uint32 *valp)
4818 error = (*valp & ~0xf) != 0;
4823 Operand_bt2_decode (uint32 *valp)
4830 Operand_bt2_encode (uint32 *valp)
4833 error = (*valp & ~(0x7 << 1)) != 0;
4839 Operand_bs2_decode (uint32 *valp)
4846 Operand_bs2_encode (uint32 *valp)
4849 error = (*valp & ~(0x7 << 1)) != 0;
4855 Operand_br2_decode (uint32 *valp)
4862 Operand_br2_encode (uint32 *valp)
4865 error = (*valp & ~(0x7 << 1)) != 0;
4871 Operand_bt4_decode (uint32 *valp)
4878 Operand_bt4_encode (uint32 *valp)
4881 error = (*valp & ~(0x3 << 2)) != 0;
4887 Operand_bs4_decode (uint32 *valp)
4894 Operand_bs4_encode (uint32 *valp)
4897 error = (*valp & ~(0x3 << 2)) != 0;
4903 Operand_br4_decode (uint32 *valp)
4910 Operand_br4_encode (uint32 *valp)
4913 error = (*valp & ~(0x3 << 2)) != 0;
4919 Operand_bt8_decode (uint32 *valp)
4926 Operand_bt8_encode (uint32 *valp)
4929 error = (*valp & ~(0x1 << 3)) != 0;
4935 Operand_bs8_decode (uint32 *valp)
4942 Operand_bs8_encode (uint32 *valp)
4945 error = (*valp & ~(0x1 << 3)) != 0;
4951 Operand_br8_decode (uint32 *valp)
4958 Operand_br8_encode (uint32 *valp)
4961 error = (*valp & ~(0x1 << 3)) != 0;
4967 Operand_bt16_decode (uint32 *valp)
4974 Operand_bt16_encode (uint32 *valp)
4977 error = (*valp & ~(0 << 4)) != 0;
4983 Operand_bs16_decode (uint32 *valp)
4990 Operand_bs16_encode (uint32 *valp)
4993 error = (*valp & ~(0 << 4)) != 0;
4999 Operand_br16_decode (uint32 *valp)
5006 Operand_br16_encode (uint32 *valp)
5009 error = (*valp & ~(0 << 4)) != 0;
5015 Operand_brall_decode (uint32 *valp)
5022 Operand_brall_encode (uint32 *valp)
5025 error = (*valp & ~(0 << 4)) != 0;
5031 Operand_tp7_decode (uint32 *valp)
5033 unsigned tp7_0, t_0;
5041 Operand_tp7_encode (uint32 *valp)
5043 unsigned t_0, tp7_0;
5045 t_0 = (tp7_0 - 0x7) & 0xf;
5051 Operand_xt_wbr15_label_decode (uint32 *valp)
5053 unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
5054 xt_wbr15_imm_0 = *valp & 0x7fff;
5055 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
5056 *valp = xt_wbr15_label_0;
5061 Operand_xt_wbr15_label_encode (uint32 *valp)
5063 unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
5064 xt_wbr15_label_0 = *valp;
5065 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
5066 *valp = xt_wbr15_imm_0;
5071 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
5078 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
5085 Operand_xt_wbr18_label_decode (uint32 *valp)
5087 unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
5088 xt_wbr18_imm_0 = *valp & 0x3ffff;
5089 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
5090 *valp = xt_wbr18_label_0;
5095 Operand_xt_wbr18_label_encode (uint32 *valp)
5097 unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
5098 xt_wbr18_label_0 = *valp;
5099 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
5100 *valp = xt_wbr18_imm_0;
5105 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
5112 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
5119 Operand_cimm8x4_decode (uint32 *valp)
5121 unsigned cimm8x4_0, imm8_0;
5122 imm8_0 = *valp & 0xff;
5123 cimm8x4_0 = (imm8_0 << 2) | 0;
5129 Operand_cimm8x4_encode (uint32 *valp)
5131 unsigned imm8_0, cimm8x4_0;
5133 imm8_0 = (cimm8x4_0 >> 2) & 0xff;
5139 Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED)
5145 Operand_frr_encode (uint32 *valp)
5148 error = (*valp & ~0xf) != 0;
5153 Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED)
5159 Operand_frs_encode (uint32 *valp)
5162 error = (*valp & ~0xf) != 0;
5167 Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED)
5173 Operand_frt_encode (uint32 *valp)
5176 error = (*valp & ~0xf) != 0;
5180 static xtensa_operand_internal operands[] = {
5181 { "soffsetx4", 10, -1, 0,
5182 XTENSA_OPERAND_IS_PCRELATIVE,
5183 Operand_soffsetx4_encode, Operand_soffsetx4_decode,
5184 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
5185 { "uimm12x8", 3, -1, 0,
5187 Operand_uimm12x8_encode, Operand_uimm12x8_decode,
5189 { "simm4", 26, -1, 0,
5191 Operand_simm4_encode, Operand_simm4_decode,
5194 XTENSA_OPERAND_IS_REGISTER,
5195 Operand_arr_encode, Operand_arr_decode,
5198 XTENSA_OPERAND_IS_REGISTER,
5199 Operand_ars_encode, Operand_ars_decode,
5201 { "*ars_invisible", 5, 0, 1,
5202 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5203 Operand_ars_encode, Operand_ars_decode,
5206 XTENSA_OPERAND_IS_REGISTER,
5207 Operand_art_encode, Operand_art_decode,
5210 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5211 Operand_ar0_encode, Operand_ar0_decode,
5214 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5215 Operand_ar4_encode, Operand_ar4_decode,
5218 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5219 Operand_ar8_encode, Operand_ar8_decode,
5221 { "ar12", 126, 0, 1,
5222 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5223 Operand_ar12_encode, Operand_ar12_decode,
5225 { "ars_entry", 5, 0, 1,
5226 XTENSA_OPERAND_IS_REGISTER,
5227 Operand_ars_entry_encode, Operand_ars_entry_decode,
5229 { "immrx4", 14, -1, 0,
5231 Operand_immrx4_encode, Operand_immrx4_decode,
5233 { "lsi4x4", 14, -1, 0,
5235 Operand_lsi4x4_encode, Operand_lsi4x4_decode,
5237 { "simm7", 34, -1, 0,
5239 Operand_simm7_encode, Operand_simm7_decode,
5241 { "uimm6", 33, -1, 0,
5242 XTENSA_OPERAND_IS_PCRELATIVE,
5243 Operand_uimm6_encode, Operand_uimm6_decode,
5244 Operand_uimm6_ator, Operand_uimm6_rtoa },
5245 { "ai4const", 0, -1, 0,
5247 Operand_ai4const_encode, Operand_ai4const_decode,
5249 { "b4const", 14, -1, 0,
5251 Operand_b4const_encode, Operand_b4const_decode,
5253 { "b4constu", 14, -1, 0,
5255 Operand_b4constu_encode, Operand_b4constu_decode,
5257 { "uimm8", 4, -1, 0,
5259 Operand_uimm8_encode, Operand_uimm8_decode,
5261 { "uimm8x2", 4, -1, 0,
5263 Operand_uimm8x2_encode, Operand_uimm8x2_decode,
5265 { "uimm8x4", 4, -1, 0,
5267 Operand_uimm8x4_encode, Operand_uimm8x4_decode,
5269 { "uimm4x16", 13, -1, 0,
5271 Operand_uimm4x16_encode, Operand_uimm4x16_decode,
5273 { "simm8", 4, -1, 0,
5275 Operand_simm8_encode, Operand_simm8_decode,
5277 { "simm8x256", 4, -1, 0,
5279 Operand_simm8x256_encode, Operand_simm8x256_decode,
5281 { "simm12b", 6, -1, 0,
5283 Operand_simm12b_encode, Operand_simm12b_decode,
5285 { "msalp32", 18, -1, 0,
5287 Operand_msalp32_encode, Operand_msalp32_decode,
5289 { "op2p1", 13, -1, 0,
5291 Operand_op2p1_encode, Operand_op2p1_decode,
5293 { "label8", 4, -1, 0,
5294 XTENSA_OPERAND_IS_PCRELATIVE,
5295 Operand_label8_encode, Operand_label8_decode,
5296 Operand_label8_ator, Operand_label8_rtoa },
5297 { "ulabel8", 4, -1, 0,
5298 XTENSA_OPERAND_IS_PCRELATIVE,
5299 Operand_ulabel8_encode, Operand_ulabel8_decode,
5300 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
5301 { "label12", 3, -1, 0,
5302 XTENSA_OPERAND_IS_PCRELATIVE,
5303 Operand_label12_encode, Operand_label12_decode,
5304 Operand_label12_ator, Operand_label12_rtoa },
5305 { "soffset", 10, -1, 0,
5306 XTENSA_OPERAND_IS_PCRELATIVE,
5307 Operand_soffset_encode, Operand_soffset_decode,
5308 Operand_soffset_ator, Operand_soffset_rtoa },
5309 { "uimm16x4", 7, -1, 0,
5310 XTENSA_OPERAND_IS_PCRELATIVE,
5311 Operand_uimm16x4_encode, Operand_uimm16x4_decode,
5312 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
5314 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
5315 Operand_mx_encode, Operand_mx_decode,
5318 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
5319 Operand_my_encode, Operand_my_decode,
5322 XTENSA_OPERAND_IS_REGISTER,
5323 Operand_mw_encode, Operand_mw_decode,
5326 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5327 Operand_mr0_encode, Operand_mr0_decode,
5330 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5331 Operand_mr1_encode, Operand_mr1_decode,
5334 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5335 Operand_mr2_encode, Operand_mr2_decode,
5338 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5339 Operand_mr3_encode, Operand_mr3_decode,
5343 Operand_immt_encode, Operand_immt_decode,
5347 Operand_imms_encode, Operand_imms_decode,
5350 XTENSA_OPERAND_IS_REGISTER,
5351 Operand_bt_encode, Operand_bt_decode,
5354 XTENSA_OPERAND_IS_REGISTER,
5355 Operand_bs_encode, Operand_bs_decode,
5358 XTENSA_OPERAND_IS_REGISTER,
5359 Operand_br_encode, Operand_br_decode,
5362 XTENSA_OPERAND_IS_REGISTER,
5363 Operand_bt2_encode, Operand_bt2_decode,
5366 XTENSA_OPERAND_IS_REGISTER,
5367 Operand_bs2_encode, Operand_bs2_decode,
5370 XTENSA_OPERAND_IS_REGISTER,
5371 Operand_br2_encode, Operand_br2_decode,
5374 XTENSA_OPERAND_IS_REGISTER,
5375 Operand_bt4_encode, Operand_bt4_decode,
5378 XTENSA_OPERAND_IS_REGISTER,
5379 Operand_bs4_encode, Operand_bs4_decode,
5382 XTENSA_OPERAND_IS_REGISTER,
5383 Operand_br4_encode, Operand_br4_decode,
5386 XTENSA_OPERAND_IS_REGISTER,
5387 Operand_bt8_encode, Operand_bt8_decode,
5390 XTENSA_OPERAND_IS_REGISTER,
5391 Operand_bs8_encode, Operand_bs8_decode,
5394 XTENSA_OPERAND_IS_REGISTER,
5395 Operand_br8_encode, Operand_br8_decode,
5397 { "bt16", 131, 2, 16,
5398 XTENSA_OPERAND_IS_REGISTER,
5399 Operand_bt16_encode, Operand_bt16_decode,
5401 { "bs16", 132, 2, 16,
5402 XTENSA_OPERAND_IS_REGISTER,
5403 Operand_bs16_encode, Operand_bs16_decode,
5405 { "br16", 133, 2, 16,
5406 XTENSA_OPERAND_IS_REGISTER,
5407 Operand_br16_encode, Operand_br16_decode,
5409 { "brall", 134, 2, 16,
5410 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5411 Operand_brall_encode, Operand_brall_decode,
5415 Operand_tp7_encode, Operand_tp7_decode,
5417 { "xt_wbr15_label", 53, -1, 0,
5418 XTENSA_OPERAND_IS_PCRELATIVE,
5419 Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
5420 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
5421 { "xt_wbr18_label", 54, -1, 0,
5422 XTENSA_OPERAND_IS_PCRELATIVE,
5423 Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
5424 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
5425 { "cimm8x4", 4, -1, 0,
5427 Operand_cimm8x4_encode, Operand_cimm8x4_decode,
5430 XTENSA_OPERAND_IS_REGISTER,
5431 Operand_frr_encode, Operand_frr_decode,
5434 XTENSA_OPERAND_IS_REGISTER,
5435 Operand_frs_encode, Operand_frs_decode,
5438 XTENSA_OPERAND_IS_REGISTER,
5439 Operand_frt_encode, Operand_frt_decode,
5441 { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
5442 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
5443 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
5444 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
5445 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
5446 { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
5447 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
5448 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
5449 { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
5450 { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
5451 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
5452 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
5453 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
5454 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
5455 { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
5456 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
5457 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
5458 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
5459 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
5460 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
5461 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
5462 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
5463 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
5464 { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
5465 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
5466 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
5467 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
5468 { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
5469 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
5470 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
5471 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
5472 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
5473 { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
5474 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
5475 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
5476 { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
5477 { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
5478 { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
5479 { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
5480 { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
5481 { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
5482 { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
5483 { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
5484 { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
5485 { "t2", 44, -1, 0, 0, 0, 0, 0, 0 },
5486 { "s2", 45, -1, 0, 0, 0, 0, 0, 0 },
5487 { "r2", 46, -1, 0, 0, 0, 0, 0, 0 },
5488 { "t4", 47, -1, 0, 0, 0, 0, 0, 0 },
5489 { "s4", 48, -1, 0, 0, 0, 0, 0, 0 },
5490 { "r4", 49, -1, 0, 0, 0, 0, 0, 0 },
5491 { "t8", 50, -1, 0, 0, 0, 0, 0, 0 },
5492 { "s8", 51, -1, 0, 0, 0, 0, 0, 0 },
5493 { "r8", 52, -1, 0, 0, 0, 0, 0, 0 },
5494 { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 },
5495 { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 },
5496 { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 },
5497 { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 },
5498 { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 },
5499 { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 },
5500 { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 },
5501 { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 },
5502 { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 },
5503 { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 },
5504 { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 },
5505 { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 },
5506 { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 },
5507 { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 },
5508 { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 },
5509 { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 },
5510 { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 },
5511 { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 },
5512 { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 },
5513 { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 },
5514 { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 },
5515 { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 },
5516 { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 },
5517 { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 },
5518 { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 },
5519 { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 },
5520 { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 },
5521 { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 },
5522 { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 },
5523 { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 },
5524 { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 },
5525 { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 },
5526 { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 },
5527 { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 },
5528 { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 },
5529 { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 },
5530 { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 },
5531 { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 },
5532 { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 },
5533 { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 },
5534 { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 },
5535 { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 },
5536 { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 },
5537 { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 },
5538 { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 },
5539 { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 },
5540 { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 },
5541 { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 },
5542 { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 },
5543 { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 },
5544 { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 },
5545 { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 },
5546 { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 },
5547 { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 },
5548 { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 },
5549 { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 },
5550 { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 },
5551 { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 },
5552 { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 },
5553 { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 },
5554 { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 },
5555 { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 },
5556 { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 },
5557 { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 },
5558 { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 },
5559 { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 },
5560 { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 },
5561 { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 },
5562 { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 },
5563 { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 }
5569 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
5570 { { STATE_PSRING }, 'i' },
5571 { { STATE_PSEXCM }, 'm' },
5572 { { STATE_EPC1 }, 'i' }
5575 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
5576 { { STATE_PSEXCM }, 'i' },
5577 { { STATE_PSRING }, 'i' },
5578 { { STATE_DEPC }, 'i' }
5581 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
5582 { { 0 /* soffsetx4 */ }, 'i' },
5583 { { 10 /* ar12 */ }, 'o' }
5586 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
5587 { { STATE_PSCALLINC }, 'o' }
5590 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
5591 { { 0 /* soffsetx4 */ }, 'i' },
5592 { { 9 /* ar8 */ }, 'o' }
5595 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
5596 { { STATE_PSCALLINC }, 'o' }
5599 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
5600 { { 0 /* soffsetx4 */ }, 'i' },
5601 { { 8 /* ar4 */ }, 'o' }
5604 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
5605 { { STATE_PSCALLINC }, 'o' }
5608 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
5609 { { 4 /* ars */ }, 'i' },
5610 { { 10 /* ar12 */ }, 'o' }
5613 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
5614 { { STATE_PSCALLINC }, 'o' }
5617 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
5618 { { 4 /* ars */ }, 'i' },
5619 { { 9 /* ar8 */ }, 'o' }
5622 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
5623 { { STATE_PSCALLINC }, 'o' }
5626 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
5627 { { 4 /* ars */ }, 'i' },
5628 { { 8 /* ar4 */ }, 'o' }
5631 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
5632 { { STATE_PSCALLINC }, 'o' }
5635 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
5636 { { 11 /* ars_entry */ }, 's' },
5637 { { 4 /* ars */ }, 'i' },
5638 { { 1 /* uimm12x8 */ }, 'i' }
5641 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
5642 { { STATE_PSCALLINC }, 'i' },
5643 { { STATE_PSEXCM }, 'i' },
5644 { { STATE_PSWOE }, 'i' },
5645 { { STATE_WindowBase }, 'm' },
5646 { { STATE_WindowStart }, 'm' }
5649 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
5650 { { 6 /* art */ }, 'o' },
5651 { { 4 /* ars */ }, 'i' }
5654 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
5655 { { STATE_WindowBase }, 'i' },
5656 { { STATE_WindowStart }, 'i' }
5659 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
5660 { { 2 /* simm4 */ }, 'i' }
5663 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
5664 { { STATE_PSEXCM }, 'i' },
5665 { { STATE_PSRING }, 'i' },
5666 { { STATE_WindowBase }, 'm' }
5669 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
5670 { { 5 /* *ars_invisible */ }, 'i' }
5673 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
5674 { { STATE_WindowBase }, 'm' },
5675 { { STATE_WindowStart }, 'm' },
5676 { { STATE_PSEXCM }, 'i' },
5677 { { STATE_PSWOE }, 'i' }
5680 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
5681 { { STATE_EPC1 }, 'i' },
5682 { { STATE_PSEXCM }, 'm' },
5683 { { STATE_PSRING }, 'i' },
5684 { { STATE_WindowBase }, 'm' },
5685 { { STATE_WindowStart }, 'm' },
5686 { { STATE_PSOWB }, 'i' }
5689 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
5690 { { 6 /* art */ }, 'o' },
5691 { { 4 /* ars */ }, 'i' },
5692 { { 12 /* immrx4 */ }, 'i' }
5695 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
5696 { { STATE_PSEXCM }, 'i' },
5697 { { STATE_PSRING }, 'i' }
5700 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
5701 { { 6 /* art */ }, 'i' },
5702 { { 4 /* ars */ }, 'i' },
5703 { { 12 /* immrx4 */ }, 'i' }
5706 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
5707 { { STATE_PSEXCM }, 'i' },
5708 { { STATE_PSRING }, 'i' }
5711 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
5712 { { 6 /* art */ }, 'o' }
5715 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
5716 { { STATE_PSEXCM }, 'i' },
5717 { { STATE_PSRING }, 'i' },
5718 { { STATE_WindowBase }, 'i' }
5721 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
5722 { { 6 /* art */ }, 'i' }
5725 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
5726 { { STATE_PSEXCM }, 'i' },
5727 { { STATE_PSRING }, 'i' },
5728 { { STATE_WindowBase }, 'o' }
5731 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
5732 { { 6 /* art */ }, 'm' }
5735 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
5736 { { STATE_PSEXCM }, 'i' },
5737 { { STATE_PSRING }, 'i' },
5738 { { STATE_WindowBase }, 'm' }
5741 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
5742 { { 6 /* art */ }, 'o' }
5745 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
5746 { { STATE_PSEXCM }, 'i' },
5747 { { STATE_PSRING }, 'i' },
5748 { { STATE_WindowStart }, 'i' }
5751 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
5752 { { 6 /* art */ }, 'i' }
5755 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
5756 { { STATE_PSEXCM }, 'i' },
5757 { { STATE_PSRING }, 'i' },
5758 { { STATE_WindowStart }, 'o' }
5761 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
5762 { { 6 /* art */ }, 'm' }
5765 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
5766 { { STATE_PSEXCM }, 'i' },
5767 { { STATE_PSRING }, 'i' },
5768 { { STATE_WindowStart }, 'm' }
5771 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
5772 { { 3 /* arr */ }, 'o' },
5773 { { 4 /* ars */ }, 'i' },
5774 { { 6 /* art */ }, 'i' }
5777 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
5778 { { 3 /* arr */ }, 'o' },
5779 { { 4 /* ars */ }, 'i' },
5780 { { 16 /* ai4const */ }, 'i' }
5783 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
5784 { { 4 /* ars */ }, 'i' },
5785 { { 15 /* uimm6 */ }, 'i' }
5788 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
5789 { { 6 /* art */ }, 'o' },
5790 { { 4 /* ars */ }, 'i' },
5791 { { 13 /* lsi4x4 */ }, 'i' }
5794 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
5795 { { 6 /* art */ }, 'o' },
5796 { { 4 /* ars */ }, 'i' }
5799 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
5800 { { 4 /* ars */ }, 'o' },
5801 { { 14 /* simm7 */ }, 'i' }
5804 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
5805 { { 5 /* *ars_invisible */ }, 'i' }
5808 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
5809 { { 6 /* art */ }, 'i' },
5810 { { 4 /* ars */ }, 'i' },
5811 { { 13 /* lsi4x4 */ }, 'i' }
5814 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
5815 { { 3 /* arr */ }, 'o' }
5818 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
5819 { { STATE_THREADPTR }, 'i' }
5822 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
5823 { { 6 /* art */ }, 'i' }
5826 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
5827 { { STATE_THREADPTR }, 'o' }
5830 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
5831 { { 6 /* art */ }, 'o' },
5832 { { 4 /* ars */ }, 'i' },
5833 { { 23 /* simm8 */ }, 'i' }
5836 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
5837 { { 6 /* art */ }, 'o' },
5838 { { 4 /* ars */ }, 'i' },
5839 { { 24 /* simm8x256 */ }, 'i' }
5842 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
5843 { { 3 /* arr */ }, 'o' },
5844 { { 4 /* ars */ }, 'i' },
5845 { { 6 /* art */ }, 'i' }
5848 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
5849 { { 3 /* arr */ }, 'o' },
5850 { { 4 /* ars */ }, 'i' },
5851 { { 6 /* art */ }, 'i' }
5854 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
5855 { { 4 /* ars */ }, 'i' },
5856 { { 17 /* b4const */ }, 'i' },
5857 { { 28 /* label8 */ }, 'i' }
5860 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
5861 { { 4 /* ars */ }, 'i' },
5862 { { 67 /* bbi */ }, 'i' },
5863 { { 28 /* label8 */ }, 'i' }
5866 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
5867 { { 4 /* ars */ }, 'i' },
5868 { { 18 /* b4constu */ }, 'i' },
5869 { { 28 /* label8 */ }, 'i' }
5872 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
5873 { { 4 /* ars */ }, 'i' },
5874 { { 6 /* art */ }, 'i' },
5875 { { 28 /* label8 */ }, 'i' }
5878 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
5879 { { 4 /* ars */ }, 'i' },
5880 { { 30 /* label12 */ }, 'i' }
5883 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
5884 { { 0 /* soffsetx4 */ }, 'i' },
5885 { { 7 /* ar0 */ }, 'o' }
5888 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
5889 { { 4 /* ars */ }, 'i' },
5890 { { 7 /* ar0 */ }, 'o' }
5893 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
5894 { { 3 /* arr */ }, 'o' },
5895 { { 6 /* art */ }, 'i' },
5896 { { 82 /* sae */ }, 'i' },
5897 { { 27 /* op2p1 */ }, 'i' }
5900 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
5901 { { 31 /* soffset */ }, 'i' }
5904 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
5905 { { 4 /* ars */ }, 'i' }
5908 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
5909 { { 6 /* art */ }, 'o' },
5910 { { 4 /* ars */ }, 'i' },
5911 { { 20 /* uimm8x2 */ }, 'i' }
5914 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
5915 { { 6 /* art */ }, 'o' },
5916 { { 4 /* ars */ }, 'i' },
5917 { { 20 /* uimm8x2 */ }, 'i' }
5920 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
5921 { { 6 /* art */ }, 'o' },
5922 { { 4 /* ars */ }, 'i' },
5923 { { 21 /* uimm8x4 */ }, 'i' }
5926 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
5927 { { 6 /* art */ }, 'o' },
5928 { { 32 /* uimm16x4 */ }, 'i' }
5931 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
5932 { { STATE_LITBADDR }, 'i' },
5933 { { STATE_LITBEN }, 'i' }
5936 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
5937 { { 6 /* art */ }, 'o' },
5938 { { 4 /* ars */ }, 'i' },
5939 { { 19 /* uimm8 */ }, 'i' }
5942 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
5943 { { 4 /* ars */ }, 'i' },
5944 { { 29 /* ulabel8 */ }, 'i' }
5947 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
5948 { { STATE_LBEG }, 'o' },
5949 { { STATE_LEND }, 'o' },
5950 { { STATE_LCOUNT }, 'o' }
5953 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
5954 { { 4 /* ars */ }, 'i' },
5955 { { 29 /* ulabel8 */ }, 'i' }
5958 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
5959 { { STATE_LBEG }, 'o' },
5960 { { STATE_LEND }, 'o' },
5961 { { STATE_LCOUNT }, 'o' }
5964 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
5965 { { 6 /* art */ }, 'o' },
5966 { { 25 /* simm12b */ }, 'i' }
5969 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
5970 { { 3 /* arr */ }, 'm' },
5971 { { 4 /* ars */ }, 'i' },
5972 { { 6 /* art */ }, 'i' }
5975 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
5976 { { 3 /* arr */ }, 'o' },
5977 { { 6 /* art */ }, 'i' }
5980 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
5981 { { 5 /* *ars_invisible */ }, 'i' }
5984 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
5985 { { 6 /* art */ }, 'i' },
5986 { { 4 /* ars */ }, 'i' },
5987 { { 20 /* uimm8x2 */ }, 'i' }
5990 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
5991 { { 6 /* art */ }, 'i' },
5992 { { 4 /* ars */ }, 'i' },
5993 { { 21 /* uimm8x4 */ }, 'i' }
5996 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
5997 { { 6 /* art */ }, 'i' },
5998 { { 4 /* ars */ }, 'i' },
5999 { { 19 /* uimm8 */ }, 'i' }
6002 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
6003 { { 4 /* ars */ }, 'i' }
6006 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
6007 { { STATE_SAR }, 'o' }
6010 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
6011 { { 86 /* sas */ }, 'i' }
6014 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
6015 { { STATE_SAR }, 'o' }
6018 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
6019 { { 3 /* arr */ }, 'o' },
6020 { { 4 /* ars */ }, 'i' }
6023 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
6024 { { STATE_SAR }, 'i' }
6027 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
6028 { { 3 /* arr */ }, 'o' },
6029 { { 4 /* ars */ }, 'i' },
6030 { { 6 /* art */ }, 'i' }
6033 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
6034 { { STATE_SAR }, 'i' }
6037 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
6038 { { 3 /* arr */ }, 'o' },
6039 { { 6 /* art */ }, 'i' }
6042 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
6043 { { STATE_SAR }, 'i' }
6046 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
6047 { { 3 /* arr */ }, 'o' },
6048 { { 4 /* ars */ }, 'i' },
6049 { { 26 /* msalp32 */ }, 'i' }
6052 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
6053 { { 3 /* arr */ }, 'o' },
6054 { { 6 /* art */ }, 'i' },
6055 { { 84 /* sargt */ }, 'i' }
6058 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
6059 { { 3 /* arr */ }, 'o' },
6060 { { 6 /* art */ }, 'i' },
6061 { { 70 /* s */ }, 'i' }
6064 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
6065 { { STATE_XTSYNC }, 'i' }
6068 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
6069 { { 6 /* art */ }, 'o' },
6070 { { 70 /* s */ }, 'i' }
6073 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
6074 { { STATE_PSWOE }, 'i' },
6075 { { STATE_PSCALLINC }, 'i' },
6076 { { STATE_PSOWB }, 'i' },
6077 { { STATE_PSRING }, 'i' },
6078 { { STATE_PSUM }, 'i' },
6079 { { STATE_PSEXCM }, 'i' },
6080 { { STATE_PSINTLEVEL }, 'm' }
6083 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
6084 { { 6 /* art */ }, 'o' }
6087 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
6088 { { STATE_LEND }, 'i' }
6091 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
6092 { { 6 /* art */ }, 'i' }
6095 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
6096 { { STATE_LEND }, 'o' }
6099 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
6100 { { 6 /* art */ }, 'm' }
6103 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
6104 { { STATE_LEND }, 'm' }
6107 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
6108 { { 6 /* art */ }, 'o' }
6111 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
6112 { { STATE_LCOUNT }, 'i' }
6115 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
6116 { { 6 /* art */ }, 'i' }
6119 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
6120 { { STATE_XTSYNC }, 'o' },
6121 { { STATE_LCOUNT }, 'o' }
6124 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
6125 { { 6 /* art */ }, 'm' }
6128 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
6129 { { STATE_XTSYNC }, 'o' },
6130 { { STATE_LCOUNT }, 'm' }
6133 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
6134 { { 6 /* art */ }, 'o' }
6137 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
6138 { { STATE_LBEG }, 'i' }
6141 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
6142 { { 6 /* art */ }, 'i' }
6145 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
6146 { { STATE_LBEG }, 'o' }
6149 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
6150 { { 6 /* art */ }, 'm' }
6153 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
6154 { { STATE_LBEG }, 'm' }
6157 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
6158 { { 6 /* art */ }, 'o' }
6161 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
6162 { { STATE_SAR }, 'i' }
6165 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
6166 { { 6 /* art */ }, 'i' }
6169 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
6170 { { STATE_SAR }, 'o' },
6171 { { STATE_XTSYNC }, 'o' }
6174 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
6175 { { 6 /* art */ }, 'm' }
6178 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
6179 { { STATE_SAR }, 'm' }
6182 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
6183 { { 6 /* art */ }, 'o' }
6186 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
6187 { { STATE_LITBADDR }, 'i' },
6188 { { STATE_LITBEN }, 'i' }
6191 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
6192 { { 6 /* art */ }, 'i' }
6195 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
6196 { { STATE_LITBADDR }, 'o' },
6197 { { STATE_LITBEN }, 'o' }
6200 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
6201 { { 6 /* art */ }, 'm' }
6204 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
6205 { { STATE_LITBADDR }, 'm' },
6206 { { STATE_LITBEN }, 'm' }
6209 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
6210 { { 6 /* art */ }, 'o' }
6213 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
6214 { { STATE_PSEXCM }, 'i' },
6215 { { STATE_PSRING }, 'i' }
6218 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
6219 { { 6 /* art */ }, 'o' }
6222 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
6223 { { STATE_PSEXCM }, 'i' },
6224 { { STATE_PSRING }, 'i' }
6227 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
6228 { { 6 /* art */ }, 'o' }
6231 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
6232 { { STATE_PSWOE }, 'i' },
6233 { { STATE_PSCALLINC }, 'i' },
6234 { { STATE_PSOWB }, 'i' },
6235 { { STATE_PSRING }, 'i' },
6236 { { STATE_PSUM }, 'i' },
6237 { { STATE_PSEXCM }, 'i' },
6238 { { STATE_PSINTLEVEL }, 'i' }
6241 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
6242 { { 6 /* art */ }, 'i' }
6245 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
6246 { { STATE_PSWOE }, 'o' },
6247 { { STATE_PSCALLINC }, 'o' },
6248 { { STATE_PSOWB }, 'o' },
6249 { { STATE_PSRING }, 'm' },
6250 { { STATE_PSUM }, 'o' },
6251 { { STATE_PSEXCM }, 'm' },
6252 { { STATE_PSINTLEVEL }, 'o' }
6255 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
6256 { { 6 /* art */ }, 'm' }
6259 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
6260 { { STATE_PSWOE }, 'm' },
6261 { { STATE_PSCALLINC }, 'm' },
6262 { { STATE_PSOWB }, 'm' },
6263 { { STATE_PSRING }, 'm' },
6264 { { STATE_PSUM }, 'm' },
6265 { { STATE_PSEXCM }, 'm' },
6266 { { STATE_PSINTLEVEL }, 'm' }
6269 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
6270 { { 6 /* art */ }, 'o' }
6273 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
6274 { { STATE_PSEXCM }, 'i' },
6275 { { STATE_PSRING }, 'i' },
6276 { { STATE_EPC1 }, 'i' }
6279 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
6280 { { 6 /* art */ }, 'i' }
6283 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
6284 { { STATE_PSEXCM }, 'i' },
6285 { { STATE_PSRING }, 'i' },
6286 { { STATE_EPC1 }, 'o' }
6289 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
6290 { { 6 /* art */ }, 'm' }
6293 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
6294 { { STATE_PSEXCM }, 'i' },
6295 { { STATE_PSRING }, 'i' },
6296 { { STATE_EPC1 }, 'm' }
6299 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
6300 { { 6 /* art */ }, 'o' }
6303 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
6304 { { STATE_PSEXCM }, 'i' },
6305 { { STATE_PSRING }, 'i' },
6306 { { STATE_EXCSAVE1 }, 'i' }
6309 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
6310 { { 6 /* art */ }, 'i' }
6313 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
6314 { { STATE_PSEXCM }, 'i' },
6315 { { STATE_PSRING }, 'i' },
6316 { { STATE_EXCSAVE1 }, 'o' }
6319 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
6320 { { 6 /* art */ }, 'm' }
6323 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
6324 { { STATE_PSEXCM }, 'i' },
6325 { { STATE_PSRING }, 'i' },
6326 { { STATE_EXCSAVE1 }, 'm' }
6329 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
6330 { { 6 /* art */ }, 'o' }
6333 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
6334 { { STATE_PSEXCM }, 'i' },
6335 { { STATE_PSRING }, 'i' },
6336 { { STATE_EPC2 }, 'i' }
6339 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
6340 { { 6 /* art */ }, 'i' }
6343 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
6344 { { STATE_PSEXCM }, 'i' },
6345 { { STATE_PSRING }, 'i' },
6346 { { STATE_EPC2 }, 'o' }
6349 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
6350 { { 6 /* art */ }, 'm' }
6353 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
6354 { { STATE_PSEXCM }, 'i' },
6355 { { STATE_PSRING }, 'i' },
6356 { { STATE_EPC2 }, 'm' }
6359 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
6360 { { 6 /* art */ }, 'o' }
6363 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
6364 { { STATE_PSEXCM }, 'i' },
6365 { { STATE_PSRING }, 'i' },
6366 { { STATE_EXCSAVE2 }, 'i' }
6369 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
6370 { { 6 /* art */ }, 'i' }
6373 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
6374 { { STATE_PSEXCM }, 'i' },
6375 { { STATE_PSRING }, 'i' },
6376 { { STATE_EXCSAVE2 }, 'o' }
6379 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
6380 { { 6 /* art */ }, 'm' }
6383 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
6384 { { STATE_PSEXCM }, 'i' },
6385 { { STATE_PSRING }, 'i' },
6386 { { STATE_EXCSAVE2 }, 'm' }
6389 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
6390 { { 6 /* art */ }, 'o' }
6393 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
6394 { { STATE_PSEXCM }, 'i' },
6395 { { STATE_PSRING }, 'i' },
6396 { { STATE_EPC3 }, 'i' }
6399 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
6400 { { 6 /* art */ }, 'i' }
6403 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
6404 { { STATE_PSEXCM }, 'i' },
6405 { { STATE_PSRING }, 'i' },
6406 { { STATE_EPC3 }, 'o' }
6409 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
6410 { { 6 /* art */ }, 'm' }
6413 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
6414 { { STATE_PSEXCM }, 'i' },
6415 { { STATE_PSRING }, 'i' },
6416 { { STATE_EPC3 }, 'm' }
6419 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
6420 { { 6 /* art */ }, 'o' }
6423 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
6424 { { STATE_PSEXCM }, 'i' },
6425 { { STATE_PSRING }, 'i' },
6426 { { STATE_EXCSAVE3 }, 'i' }
6429 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
6430 { { 6 /* art */ }, 'i' }
6433 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
6434 { { STATE_PSEXCM }, 'i' },
6435 { { STATE_PSRING }, 'i' },
6436 { { STATE_EXCSAVE3 }, 'o' }
6439 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
6440 { { 6 /* art */ }, 'm' }
6443 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
6444 { { STATE_PSEXCM }, 'i' },
6445 { { STATE_PSRING }, 'i' },
6446 { { STATE_EXCSAVE3 }, 'm' }
6449 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
6450 { { 6 /* art */ }, 'o' }
6453 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
6454 { { STATE_PSEXCM }, 'i' },
6455 { { STATE_PSRING }, 'i' },
6456 { { STATE_EPC4 }, 'i' }
6459 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
6460 { { 6 /* art */ }, 'i' }
6463 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
6464 { { STATE_PSEXCM }, 'i' },
6465 { { STATE_PSRING }, 'i' },
6466 { { STATE_EPC4 }, 'o' }
6469 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
6470 { { 6 /* art */ }, 'm' }
6473 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
6474 { { STATE_PSEXCM }, 'i' },
6475 { { STATE_PSRING }, 'i' },
6476 { { STATE_EPC4 }, 'm' }
6479 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
6480 { { 6 /* art */ }, 'o' }
6483 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
6484 { { STATE_PSEXCM }, 'i' },
6485 { { STATE_PSRING }, 'i' },
6486 { { STATE_EXCSAVE4 }, 'i' }
6489 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
6490 { { 6 /* art */ }, 'i' }
6493 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
6494 { { STATE_PSEXCM }, 'i' },
6495 { { STATE_PSRING }, 'i' },
6496 { { STATE_EXCSAVE4 }, 'o' }
6499 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
6500 { { 6 /* art */ }, 'm' }
6503 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
6504 { { STATE_PSEXCM }, 'i' },
6505 { { STATE_PSRING }, 'i' },
6506 { { STATE_EXCSAVE4 }, 'm' }
6509 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
6510 { { 6 /* art */ }, 'o' }
6513 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
6514 { { STATE_PSEXCM }, 'i' },
6515 { { STATE_PSRING }, 'i' },
6516 { { STATE_EPC5 }, 'i' }
6519 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
6520 { { 6 /* art */ }, 'i' }
6523 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
6524 { { STATE_PSEXCM }, 'i' },
6525 { { STATE_PSRING }, 'i' },
6526 { { STATE_EPC5 }, 'o' }
6529 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
6530 { { 6 /* art */ }, 'm' }
6533 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
6534 { { STATE_PSEXCM }, 'i' },
6535 { { STATE_PSRING }, 'i' },
6536 { { STATE_EPC5 }, 'm' }
6539 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
6540 { { 6 /* art */ }, 'o' }
6543 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
6544 { { STATE_PSEXCM }, 'i' },
6545 { { STATE_PSRING }, 'i' },
6546 { { STATE_EXCSAVE5 }, 'i' }
6549 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
6550 { { 6 /* art */ }, 'i' }
6553 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
6554 { { STATE_PSEXCM }, 'i' },
6555 { { STATE_PSRING }, 'i' },
6556 { { STATE_EXCSAVE5 }, 'o' }
6559 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
6560 { { 6 /* art */ }, 'm' }
6563 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
6564 { { STATE_PSEXCM }, 'i' },
6565 { { STATE_PSRING }, 'i' },
6566 { { STATE_EXCSAVE5 }, 'm' }
6569 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
6570 { { 6 /* art */ }, 'o' }
6573 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
6574 { { STATE_PSEXCM }, 'i' },
6575 { { STATE_PSRING }, 'i' },
6576 { { STATE_EPC6 }, 'i' }
6579 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
6580 { { 6 /* art */ }, 'i' }
6583 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
6584 { { STATE_PSEXCM }, 'i' },
6585 { { STATE_PSRING }, 'i' },
6586 { { STATE_EPC6 }, 'o' }
6589 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
6590 { { 6 /* art */ }, 'm' }
6593 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
6594 { { STATE_PSEXCM }, 'i' },
6595 { { STATE_PSRING }, 'i' },
6596 { { STATE_EPC6 }, 'm' }
6599 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
6600 { { 6 /* art */ }, 'o' }
6603 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
6604 { { STATE_PSEXCM }, 'i' },
6605 { { STATE_PSRING }, 'i' },
6606 { { STATE_EXCSAVE6 }, 'i' }
6609 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
6610 { { 6 /* art */ }, 'i' }
6613 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
6614 { { STATE_PSEXCM }, 'i' },
6615 { { STATE_PSRING }, 'i' },
6616 { { STATE_EXCSAVE6 }, 'o' }
6619 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
6620 { { 6 /* art */ }, 'm' }
6623 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
6624 { { STATE_PSEXCM }, 'i' },
6625 { { STATE_PSRING }, 'i' },
6626 { { STATE_EXCSAVE6 }, 'm' }
6629 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
6630 { { 6 /* art */ }, 'o' }
6633 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
6634 { { STATE_PSEXCM }, 'i' },
6635 { { STATE_PSRING }, 'i' },
6636 { { STATE_EPC7 }, 'i' }
6639 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
6640 { { 6 /* art */ }, 'i' }
6643 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
6644 { { STATE_PSEXCM }, 'i' },
6645 { { STATE_PSRING }, 'i' },
6646 { { STATE_EPC7 }, 'o' }
6649 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
6650 { { 6 /* art */ }, 'm' }
6653 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
6654 { { STATE_PSEXCM }, 'i' },
6655 { { STATE_PSRING }, 'i' },
6656 { { STATE_EPC7 }, 'm' }
6659 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
6660 { { 6 /* art */ }, 'o' }
6663 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
6664 { { STATE_PSEXCM }, 'i' },
6665 { { STATE_PSRING }, 'i' },
6666 { { STATE_EXCSAVE7 }, 'i' }
6669 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
6670 { { 6 /* art */ }, 'i' }
6673 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
6674 { { STATE_PSEXCM }, 'i' },
6675 { { STATE_PSRING }, 'i' },
6676 { { STATE_EXCSAVE7 }, 'o' }
6679 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
6680 { { 6 /* art */ }, 'm' }
6683 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
6684 { { STATE_PSEXCM }, 'i' },
6685 { { STATE_PSRING }, 'i' },
6686 { { STATE_EXCSAVE7 }, 'm' }
6689 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
6690 { { 6 /* art */ }, 'o' }
6693 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
6694 { { STATE_PSEXCM }, 'i' },
6695 { { STATE_PSRING }, 'i' },
6696 { { STATE_EPS2 }, 'i' }
6699 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
6700 { { 6 /* art */ }, 'i' }
6703 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
6704 { { STATE_PSEXCM }, 'i' },
6705 { { STATE_PSRING }, 'i' },
6706 { { STATE_EPS2 }, 'o' }
6709 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
6710 { { 6 /* art */ }, 'm' }
6713 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
6714 { { STATE_PSEXCM }, 'i' },
6715 { { STATE_PSRING }, 'i' },
6716 { { STATE_EPS2 }, 'm' }
6719 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
6720 { { 6 /* art */ }, 'o' }
6723 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
6724 { { STATE_PSEXCM }, 'i' },
6725 { { STATE_PSRING }, 'i' },
6726 { { STATE_EPS3 }, 'i' }
6729 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
6730 { { 6 /* art */ }, 'i' }
6733 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
6734 { { STATE_PSEXCM }, 'i' },
6735 { { STATE_PSRING }, 'i' },
6736 { { STATE_EPS3 }, 'o' }
6739 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
6740 { { 6 /* art */ }, 'm' }
6743 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
6744 { { STATE_PSEXCM }, 'i' },
6745 { { STATE_PSRING }, 'i' },
6746 { { STATE_EPS3 }, 'm' }
6749 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
6750 { { 6 /* art */ }, 'o' }
6753 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
6754 { { STATE_PSEXCM }, 'i' },
6755 { { STATE_PSRING }, 'i' },
6756 { { STATE_EPS4 }, 'i' }
6759 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
6760 { { 6 /* art */ }, 'i' }
6763 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
6764 { { STATE_PSEXCM }, 'i' },
6765 { { STATE_PSRING }, 'i' },
6766 { { STATE_EPS4 }, 'o' }
6769 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
6770 { { 6 /* art */ }, 'm' }
6773 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
6774 { { STATE_PSEXCM }, 'i' },
6775 { { STATE_PSRING }, 'i' },
6776 { { STATE_EPS4 }, 'm' }
6779 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
6780 { { 6 /* art */ }, 'o' }
6783 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
6784 { { STATE_PSEXCM }, 'i' },
6785 { { STATE_PSRING }, 'i' },
6786 { { STATE_EPS5 }, 'i' }
6789 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
6790 { { 6 /* art */ }, 'i' }
6793 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
6794 { { STATE_PSEXCM }, 'i' },
6795 { { STATE_PSRING }, 'i' },
6796 { { STATE_EPS5 }, 'o' }
6799 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
6800 { { 6 /* art */ }, 'm' }
6803 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
6804 { { STATE_PSEXCM }, 'i' },
6805 { { STATE_PSRING }, 'i' },
6806 { { STATE_EPS5 }, 'm' }
6809 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
6810 { { 6 /* art */ }, 'o' }
6813 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
6814 { { STATE_PSEXCM }, 'i' },
6815 { { STATE_PSRING }, 'i' },
6816 { { STATE_EPS6 }, 'i' }
6819 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
6820 { { 6 /* art */ }, 'i' }
6823 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
6824 { { STATE_PSEXCM }, 'i' },
6825 { { STATE_PSRING }, 'i' },
6826 { { STATE_EPS6 }, 'o' }
6829 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
6830 { { 6 /* art */ }, 'm' }
6833 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
6834 { { STATE_PSEXCM }, 'i' },
6835 { { STATE_PSRING }, 'i' },
6836 { { STATE_EPS6 }, 'm' }
6839 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
6840 { { 6 /* art */ }, 'o' }
6843 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
6844 { { STATE_PSEXCM }, 'i' },
6845 { { STATE_PSRING }, 'i' },
6846 { { STATE_EPS7 }, 'i' }
6849 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
6850 { { 6 /* art */ }, 'i' }
6853 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
6854 { { STATE_PSEXCM }, 'i' },
6855 { { STATE_PSRING }, 'i' },
6856 { { STATE_EPS7 }, 'o' }
6859 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
6860 { { 6 /* art */ }, 'm' }
6863 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
6864 { { STATE_PSEXCM }, 'i' },
6865 { { STATE_PSRING }, 'i' },
6866 { { STATE_EPS7 }, 'm' }
6869 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
6870 { { 6 /* art */ }, 'o' }
6873 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
6874 { { STATE_PSEXCM }, 'i' },
6875 { { STATE_PSRING }, 'i' },
6876 { { STATE_EXCVADDR }, 'i' }
6879 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
6880 { { 6 /* art */ }, 'i' }
6883 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
6884 { { STATE_PSEXCM }, 'i' },
6885 { { STATE_PSRING }, 'i' },
6886 { { STATE_EXCVADDR }, 'o' }
6889 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
6890 { { 6 /* art */ }, 'm' }
6893 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
6894 { { STATE_PSEXCM }, 'i' },
6895 { { STATE_PSRING }, 'i' },
6896 { { STATE_EXCVADDR }, 'm' }
6899 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
6900 { { 6 /* art */ }, 'o' }
6903 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
6904 { { STATE_PSEXCM }, 'i' },
6905 { { STATE_PSRING }, 'i' },
6906 { { STATE_DEPC }, 'i' }
6909 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
6910 { { 6 /* art */ }, 'i' }
6913 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
6914 { { STATE_PSEXCM }, 'i' },
6915 { { STATE_PSRING }, 'i' },
6916 { { STATE_DEPC }, 'o' }
6919 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
6920 { { 6 /* art */ }, 'm' }
6923 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
6924 { { STATE_PSEXCM }, 'i' },
6925 { { STATE_PSRING }, 'i' },
6926 { { STATE_DEPC }, 'm' }
6929 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
6930 { { 6 /* art */ }, 'o' }
6933 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
6934 { { STATE_PSEXCM }, 'i' },
6935 { { STATE_PSRING }, 'i' },
6936 { { STATE_EXCCAUSE }, 'i' },
6937 { { STATE_XTSYNC }, 'i' }
6940 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
6941 { { 6 /* art */ }, 'i' }
6944 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
6945 { { STATE_PSEXCM }, 'i' },
6946 { { STATE_PSRING }, 'i' },
6947 { { STATE_EXCCAUSE }, 'o' }
6950 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
6951 { { 6 /* art */ }, 'm' }
6954 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
6955 { { STATE_PSEXCM }, 'i' },
6956 { { STATE_PSRING }, 'i' },
6957 { { STATE_EXCCAUSE }, 'm' }
6960 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
6961 { { 6 /* art */ }, 'o' }
6964 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
6965 { { STATE_PSEXCM }, 'i' },
6966 { { STATE_PSRING }, 'i' },
6967 { { STATE_MISC0 }, 'i' }
6970 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
6971 { { 6 /* art */ }, 'i' }
6974 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
6975 { { STATE_PSEXCM }, 'i' },
6976 { { STATE_PSRING }, 'i' },
6977 { { STATE_MISC0 }, 'o' }
6980 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
6981 { { 6 /* art */ }, 'm' }
6984 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
6985 { { STATE_PSEXCM }, 'i' },
6986 { { STATE_PSRING }, 'i' },
6987 { { STATE_MISC0 }, 'm' }
6990 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
6991 { { 6 /* art */ }, 'o' }
6994 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
6995 { { STATE_PSEXCM }, 'i' },
6996 { { STATE_PSRING }, 'i' },
6997 { { STATE_MISC1 }, 'i' }
7000 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
7001 { { 6 /* art */ }, 'i' }
7004 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
7005 { { STATE_PSEXCM }, 'i' },
7006 { { STATE_PSRING }, 'i' },
7007 { { STATE_MISC1 }, 'o' }
7010 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
7011 { { 6 /* art */ }, 'm' }
7014 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
7015 { { STATE_PSEXCM }, 'i' },
7016 { { STATE_PSRING }, 'i' },
7017 { { STATE_MISC1 }, 'm' }
7020 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
7021 { { 6 /* art */ }, 'o' }
7024 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
7025 { { STATE_PSEXCM }, 'i' },
7026 { { STATE_PSRING }, 'i' },
7027 { { STATE_MISC2 }, 'i' }
7030 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
7031 { { 6 /* art */ }, 'i' }
7034 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
7035 { { STATE_PSEXCM }, 'i' },
7036 { { STATE_PSRING }, 'i' },
7037 { { STATE_MISC2 }, 'o' }
7040 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
7041 { { 6 /* art */ }, 'm' }
7044 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
7045 { { STATE_PSEXCM }, 'i' },
7046 { { STATE_PSRING }, 'i' },
7047 { { STATE_MISC2 }, 'm' }
7050 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
7051 { { 6 /* art */ }, 'o' }
7054 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
7055 { { STATE_PSEXCM }, 'i' },
7056 { { STATE_PSRING }, 'i' },
7057 { { STATE_MISC3 }, 'i' }
7060 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
7061 { { 6 /* art */ }, 'i' }
7064 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
7065 { { STATE_PSEXCM }, 'i' },
7066 { { STATE_PSRING }, 'i' },
7067 { { STATE_MISC3 }, 'o' }
7070 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
7071 { { 6 /* art */ }, 'm' }
7074 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
7075 { { STATE_PSEXCM }, 'i' },
7076 { { STATE_PSRING }, 'i' },
7077 { { STATE_MISC3 }, 'm' }
7080 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
7081 { { 6 /* art */ }, 'o' }
7084 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
7085 { { STATE_PSEXCM }, 'i' },
7086 { { STATE_PSRING }, 'i' }
7089 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
7090 { { 6 /* art */ }, 'o' }
7093 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
7094 { { STATE_PSEXCM }, 'i' },
7095 { { STATE_PSRING }, 'i' },
7096 { { STATE_VECBASE }, 'i' }
7099 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
7100 { { 6 /* art */ }, 'i' }
7103 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
7104 { { STATE_PSEXCM }, 'i' },
7105 { { STATE_PSRING }, 'i' },
7106 { { STATE_VECBASE }, 'o' }
7109 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
7110 { { 6 /* art */ }, 'm' }
7113 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
7114 { { STATE_PSEXCM }, 'i' },
7115 { { STATE_PSRING }, 'i' },
7116 { { STATE_VECBASE }, 'm' }
7119 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
7120 { { 4 /* ars */ }, 'i' },
7121 { { 6 /* art */ }, 'i' }
7124 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
7125 { { STATE_ACC }, 'o' }
7128 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
7129 { { 4 /* ars */ }, 'i' },
7130 { { 34 /* my */ }, 'i' }
7133 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
7134 { { STATE_ACC }, 'o' }
7137 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
7138 { { 33 /* mx */ }, 'i' },
7139 { { 6 /* art */ }, 'i' }
7142 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
7143 { { STATE_ACC }, 'o' }
7146 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
7147 { { 33 /* mx */ }, 'i' },
7148 { { 34 /* my */ }, 'i' }
7151 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
7152 { { STATE_ACC }, 'o' }
7155 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
7156 { { 4 /* ars */ }, 'i' },
7157 { { 6 /* art */ }, 'i' }
7160 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
7161 { { STATE_ACC }, 'm' }
7164 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
7165 { { 4 /* ars */ }, 'i' },
7166 { { 34 /* my */ }, 'i' }
7169 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
7170 { { STATE_ACC }, 'm' }
7173 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
7174 { { 33 /* mx */ }, 'i' },
7175 { { 6 /* art */ }, 'i' }
7178 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
7179 { { STATE_ACC }, 'm' }
7182 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
7183 { { 33 /* mx */ }, 'i' },
7184 { { 34 /* my */ }, 'i' }
7187 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
7188 { { STATE_ACC }, 'm' }
7191 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
7192 { { 35 /* mw */ }, 'o' },
7193 { { 4 /* ars */ }, 'm' },
7194 { { 33 /* mx */ }, 'i' },
7195 { { 6 /* art */ }, 'i' }
7198 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
7199 { { STATE_ACC }, 'm' }
7202 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
7203 { { 35 /* mw */ }, 'o' },
7204 { { 4 /* ars */ }, 'm' },
7205 { { 33 /* mx */ }, 'i' },
7206 { { 34 /* my */ }, 'i' }
7209 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
7210 { { STATE_ACC }, 'm' }
7213 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
7214 { { 35 /* mw */ }, 'o' },
7215 { { 4 /* ars */ }, 'm' }
7218 static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
7219 { { 3 /* arr */ }, 'o' },
7220 { { 4 /* ars */ }, 'i' },
7221 { { 6 /* art */ }, 'i' }
7224 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
7225 { { 6 /* art */ }, 'o' },
7226 { { 36 /* mr0 */ }, 'i' }
7229 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
7230 { { 6 /* art */ }, 'i' },
7231 { { 36 /* mr0 */ }, 'o' }
7234 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
7235 { { 6 /* art */ }, 'm' },
7236 { { 36 /* mr0 */ }, 'm' }
7239 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
7240 { { 6 /* art */ }, 'o' },
7241 { { 37 /* mr1 */ }, 'i' }
7244 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
7245 { { 6 /* art */ }, 'i' },
7246 { { 37 /* mr1 */ }, 'o' }
7249 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
7250 { { 6 /* art */ }, 'm' },
7251 { { 37 /* mr1 */ }, 'm' }
7254 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
7255 { { 6 /* art */ }, 'o' },
7256 { { 38 /* mr2 */ }, 'i' }
7259 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
7260 { { 6 /* art */ }, 'i' },
7261 { { 38 /* mr2 */ }, 'o' }
7264 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
7265 { { 6 /* art */ }, 'm' },
7266 { { 38 /* mr2 */ }, 'm' }
7269 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
7270 { { 6 /* art */ }, 'o' },
7271 { { 39 /* mr3 */ }, 'i' }
7274 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
7275 { { 6 /* art */ }, 'i' },
7276 { { 39 /* mr3 */ }, 'o' }
7279 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
7280 { { 6 /* art */ }, 'm' },
7281 { { 39 /* mr3 */ }, 'm' }
7284 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
7285 { { 6 /* art */ }, 'o' }
7288 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
7289 { { STATE_ACC }, 'i' }
7292 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
7293 { { 6 /* art */ }, 'i' }
7296 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
7297 { { STATE_ACC }, 'm' }
7300 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
7301 { { 6 /* art */ }, 'm' }
7304 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
7305 { { STATE_ACC }, 'm' }
7308 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
7309 { { 6 /* art */ }, 'o' }
7312 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
7313 { { STATE_ACC }, 'i' }
7316 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
7317 { { 6 /* art */ }, 'i' }
7320 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
7321 { { STATE_ACC }, 'm' }
7324 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
7325 { { 6 /* art */ }, 'm' }
7328 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
7329 { { STATE_ACC }, 'm' }
7332 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
7333 { { 70 /* s */ }, 'i' }
7336 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
7337 { { STATE_PSWOE }, 'o' },
7338 { { STATE_PSCALLINC }, 'o' },
7339 { { STATE_PSOWB }, 'o' },
7340 { { STATE_PSRING }, 'm' },
7341 { { STATE_PSUM }, 'o' },
7342 { { STATE_PSEXCM }, 'm' },
7343 { { STATE_PSINTLEVEL }, 'o' },
7344 { { STATE_EPC1 }, 'i' },
7345 { { STATE_EPC2 }, 'i' },
7346 { { STATE_EPC3 }, 'i' },
7347 { { STATE_EPC4 }, 'i' },
7348 { { STATE_EPC5 }, 'i' },
7349 { { STATE_EPC6 }, 'i' },
7350 { { STATE_EPC7 }, 'i' },
7351 { { STATE_EPS2 }, 'i' },
7352 { { STATE_EPS3 }, 'i' },
7353 { { STATE_EPS4 }, 'i' },
7354 { { STATE_EPS5 }, 'i' },
7355 { { STATE_EPS6 }, 'i' },
7356 { { STATE_EPS7 }, 'i' },
7357 { { STATE_InOCDMode }, 'm' }
7360 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
7361 { { 70 /* s */ }, 'i' }
7364 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
7365 { { STATE_PSEXCM }, 'i' },
7366 { { STATE_PSRING }, 'i' },
7367 { { STATE_PSINTLEVEL }, 'o' }
7370 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
7371 { { 6 /* art */ }, 'o' }
7374 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
7375 { { STATE_PSEXCM }, 'i' },
7376 { { STATE_PSRING }, 'i' },
7377 { { STATE_INTERRUPT }, 'i' }
7380 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
7381 { { 6 /* art */ }, 'i' }
7384 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
7385 { { STATE_PSEXCM }, 'i' },
7386 { { STATE_PSRING }, 'i' },
7387 { { STATE_XTSYNC }, 'o' },
7388 { { STATE_INTERRUPT }, 'm' }
7391 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
7392 { { 6 /* art */ }, 'i' }
7395 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
7396 { { STATE_PSEXCM }, 'i' },
7397 { { STATE_PSRING }, 'i' },
7398 { { STATE_XTSYNC }, 'o' },
7399 { { STATE_INTERRUPT }, 'm' }
7402 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
7403 { { 6 /* art */ }, 'o' }
7406 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
7407 { { STATE_PSEXCM }, 'i' },
7408 { { STATE_PSRING }, 'i' },
7409 { { STATE_INTENABLE }, 'i' }
7412 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
7413 { { 6 /* art */ }, 'i' }
7416 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
7417 { { STATE_PSEXCM }, 'i' },
7418 { { STATE_PSRING }, 'i' },
7419 { { STATE_INTENABLE }, 'o' }
7422 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
7423 { { 6 /* art */ }, 'm' }
7426 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
7427 { { STATE_PSEXCM }, 'i' },
7428 { { STATE_PSRING }, 'i' },
7429 { { STATE_INTENABLE }, 'm' }
7432 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
7433 { { 41 /* imms */ }, 'i' },
7434 { { 40 /* immt */ }, 'i' }
7437 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
7438 { { STATE_PSEXCM }, 'i' },
7439 { { STATE_PSINTLEVEL }, 'i' }
7442 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
7443 { { 41 /* imms */ }, 'i' }
7446 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
7447 { { STATE_PSEXCM }, 'i' },
7448 { { STATE_PSINTLEVEL }, 'i' }
7451 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
7452 { { 6 /* art */ }, 'o' }
7455 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
7456 { { STATE_PSEXCM }, 'i' },
7457 { { STATE_PSRING }, 'i' },
7458 { { STATE_DBREAKA0 }, 'i' }
7461 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
7462 { { 6 /* art */ }, 'i' }
7465 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
7466 { { STATE_PSEXCM }, 'i' },
7467 { { STATE_PSRING }, 'i' },
7468 { { STATE_DBREAKA0 }, 'o' },
7469 { { STATE_XTSYNC }, 'o' }
7472 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
7473 { { 6 /* art */ }, 'm' }
7476 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
7477 { { STATE_PSEXCM }, 'i' },
7478 { { STATE_PSRING }, 'i' },
7479 { { STATE_DBREAKA0 }, 'm' },
7480 { { STATE_XTSYNC }, 'o' }
7483 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
7484 { { 6 /* art */ }, 'o' }
7487 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
7488 { { STATE_PSEXCM }, 'i' },
7489 { { STATE_PSRING }, 'i' },
7490 { { STATE_DBREAKC0 }, 'i' }
7493 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
7494 { { 6 /* art */ }, 'i' }
7497 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
7498 { { STATE_PSEXCM }, 'i' },
7499 { { STATE_PSRING }, 'i' },
7500 { { STATE_DBREAKC0 }, 'o' },
7501 { { STATE_XTSYNC }, 'o' }
7504 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
7505 { { 6 /* art */ }, 'm' }
7508 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
7509 { { STATE_PSEXCM }, 'i' },
7510 { { STATE_PSRING }, 'i' },
7511 { { STATE_DBREAKC0 }, 'm' },
7512 { { STATE_XTSYNC }, 'o' }
7515 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
7516 { { 6 /* art */ }, 'o' }
7519 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
7520 { { STATE_PSEXCM }, 'i' },
7521 { { STATE_PSRING }, 'i' },
7522 { { STATE_DBREAKA1 }, 'i' }
7525 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
7526 { { 6 /* art */ }, 'i' }
7529 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
7530 { { STATE_PSEXCM }, 'i' },
7531 { { STATE_PSRING }, 'i' },
7532 { { STATE_DBREAKA1 }, 'o' },
7533 { { STATE_XTSYNC }, 'o' }
7536 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
7537 { { 6 /* art */ }, 'm' }
7540 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
7541 { { STATE_PSEXCM }, 'i' },
7542 { { STATE_PSRING }, 'i' },
7543 { { STATE_DBREAKA1 }, 'm' },
7544 { { STATE_XTSYNC }, 'o' }
7547 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
7548 { { 6 /* art */ }, 'o' }
7551 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
7552 { { STATE_PSEXCM }, 'i' },
7553 { { STATE_PSRING }, 'i' },
7554 { { STATE_DBREAKC1 }, 'i' }
7557 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
7558 { { 6 /* art */ }, 'i' }
7561 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
7562 { { STATE_PSEXCM }, 'i' },
7563 { { STATE_PSRING }, 'i' },
7564 { { STATE_DBREAKC1 }, 'o' },
7565 { { STATE_XTSYNC }, 'o' }
7568 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
7569 { { 6 /* art */ }, 'm' }
7572 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
7573 { { STATE_PSEXCM }, 'i' },
7574 { { STATE_PSRING }, 'i' },
7575 { { STATE_DBREAKC1 }, 'm' },
7576 { { STATE_XTSYNC }, 'o' }
7579 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
7580 { { 6 /* art */ }, 'o' }
7583 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
7584 { { STATE_PSEXCM }, 'i' },
7585 { { STATE_PSRING }, 'i' },
7586 { { STATE_IBREAKA0 }, 'i' }
7589 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
7590 { { 6 /* art */ }, 'i' }
7593 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
7594 { { STATE_PSEXCM }, 'i' },
7595 { { STATE_PSRING }, 'i' },
7596 { { STATE_IBREAKA0 }, 'o' }
7599 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
7600 { { 6 /* art */ }, 'm' }
7603 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
7604 { { STATE_PSEXCM }, 'i' },
7605 { { STATE_PSRING }, 'i' },
7606 { { STATE_IBREAKA0 }, 'm' }
7609 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
7610 { { 6 /* art */ }, 'o' }
7613 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
7614 { { STATE_PSEXCM }, 'i' },
7615 { { STATE_PSRING }, 'i' },
7616 { { STATE_IBREAKA1 }, 'i' }
7619 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
7620 { { 6 /* art */ }, 'i' }
7623 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
7624 { { STATE_PSEXCM }, 'i' },
7625 { { STATE_PSRING }, 'i' },
7626 { { STATE_IBREAKA1 }, 'o' }
7629 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
7630 { { 6 /* art */ }, 'm' }
7633 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
7634 { { STATE_PSEXCM }, 'i' },
7635 { { STATE_PSRING }, 'i' },
7636 { { STATE_IBREAKA1 }, 'm' }
7639 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
7640 { { 6 /* art */ }, 'o' }
7643 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
7644 { { STATE_PSEXCM }, 'i' },
7645 { { STATE_PSRING }, 'i' },
7646 { { STATE_IBREAKENABLE }, 'i' }
7649 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
7650 { { 6 /* art */ }, 'i' }
7653 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
7654 { { STATE_PSEXCM }, 'i' },
7655 { { STATE_PSRING }, 'i' },
7656 { { STATE_IBREAKENABLE }, 'o' }
7659 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
7660 { { 6 /* art */ }, 'm' }
7663 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
7664 { { STATE_PSEXCM }, 'i' },
7665 { { STATE_PSRING }, 'i' },
7666 { { STATE_IBREAKENABLE }, 'm' }
7669 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
7670 { { 6 /* art */ }, 'o' }
7673 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
7674 { { STATE_PSEXCM }, 'i' },
7675 { { STATE_PSRING }, 'i' },
7676 { { STATE_DEBUGCAUSE }, 'i' },
7677 { { STATE_DBNUM }, 'i' }
7680 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
7681 { { 6 /* art */ }, 'i' }
7684 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
7685 { { STATE_PSEXCM }, 'i' },
7686 { { STATE_PSRING }, 'i' },
7687 { { STATE_DEBUGCAUSE }, 'o' },
7688 { { STATE_DBNUM }, 'o' }
7691 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
7692 { { 6 /* art */ }, 'm' }
7695 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
7696 { { STATE_PSEXCM }, 'i' },
7697 { { STATE_PSRING }, 'i' },
7698 { { STATE_DEBUGCAUSE }, 'm' },
7699 { { STATE_DBNUM }, 'm' }
7702 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
7703 { { 6 /* art */ }, 'o' }
7706 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
7707 { { STATE_PSEXCM }, 'i' },
7708 { { STATE_PSRING }, 'i' },
7709 { { STATE_ICOUNT }, 'i' }
7712 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
7713 { { 6 /* art */ }, 'i' }
7716 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
7717 { { STATE_PSEXCM }, 'i' },
7718 { { STATE_PSRING }, 'i' },
7719 { { STATE_XTSYNC }, 'o' },
7720 { { STATE_ICOUNT }, 'o' }
7723 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
7724 { { 6 /* art */ }, 'm' }
7727 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
7728 { { STATE_PSEXCM }, 'i' },
7729 { { STATE_PSRING }, 'i' },
7730 { { STATE_XTSYNC }, 'o' },
7731 { { STATE_ICOUNT }, 'm' }
7734 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
7735 { { 6 /* art */ }, 'o' }
7738 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
7739 { { STATE_PSEXCM }, 'i' },
7740 { { STATE_PSRING }, 'i' },
7741 { { STATE_ICOUNTLEVEL }, 'i' }
7744 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
7745 { { 6 /* art */ }, 'i' }
7748 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
7749 { { STATE_PSEXCM }, 'i' },
7750 { { STATE_PSRING }, 'i' },
7751 { { STATE_ICOUNTLEVEL }, 'o' }
7754 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
7755 { { 6 /* art */ }, 'm' }
7758 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
7759 { { STATE_PSEXCM }, 'i' },
7760 { { STATE_PSRING }, 'i' },
7761 { { STATE_ICOUNTLEVEL }, 'm' }
7764 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
7765 { { 6 /* art */ }, 'o' }
7768 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
7769 { { STATE_PSEXCM }, 'i' },
7770 { { STATE_PSRING }, 'i' },
7771 { { STATE_DDR }, 'i' }
7774 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
7775 { { 6 /* art */ }, 'i' }
7778 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
7779 { { STATE_PSEXCM }, 'i' },
7780 { { STATE_PSRING }, 'i' },
7781 { { STATE_XTSYNC }, 'o' },
7782 { { STATE_DDR }, 'o' }
7785 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
7786 { { 6 /* art */ }, 'm' }
7789 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
7790 { { STATE_PSEXCM }, 'i' },
7791 { { STATE_PSRING }, 'i' },
7792 { { STATE_XTSYNC }, 'o' },
7793 { { STATE_DDR }, 'm' }
7796 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
7797 { { 41 /* imms */ }, 'i' }
7800 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
7801 { { STATE_InOCDMode }, 'm' },
7802 { { STATE_EPC6 }, 'i' },
7803 { { STATE_PSWOE }, 'o' },
7804 { { STATE_PSCALLINC }, 'o' },
7805 { { STATE_PSOWB }, 'o' },
7806 { { STATE_PSRING }, 'o' },
7807 { { STATE_PSUM }, 'o' },
7808 { { STATE_PSEXCM }, 'o' },
7809 { { STATE_PSINTLEVEL }, 'o' },
7810 { { STATE_EPS6 }, 'i' }
7813 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
7814 { { STATE_InOCDMode }, 'm' }
7817 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
7818 { { 6 /* art */ }, 'i' }
7821 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
7822 { { STATE_PSEXCM }, 'i' },
7823 { { STATE_PSRING }, 'i' },
7824 { { STATE_XTSYNC }, 'o' }
7827 static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
7828 { { 44 /* br */ }, 'o' },
7829 { { 43 /* bs */ }, 'i' },
7830 { { 42 /* bt */ }, 'i' }
7833 static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
7834 { { 42 /* bt */ }, 'o' },
7835 { { 49 /* bs4 */ }, 'i' }
7838 static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
7839 { { 42 /* bt */ }, 'o' },
7840 { { 52 /* bs8 */ }, 'i' }
7843 static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
7844 { { 43 /* bs */ }, 'i' },
7845 { { 28 /* label8 */ }, 'i' }
7848 static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
7849 { { 3 /* arr */ }, 'm' },
7850 { { 4 /* ars */ }, 'i' },
7851 { { 42 /* bt */ }, 'i' }
7854 static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
7855 { { 6 /* art */ }, 'o' },
7856 { { 57 /* brall */ }, 'i' }
7859 static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
7860 { { 6 /* art */ }, 'i' },
7861 { { 57 /* brall */ }, 'o' }
7864 static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
7865 { { 6 /* art */ }, 'm' },
7866 { { 57 /* brall */ }, 'm' }
7869 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
7870 { { 6 /* art */ }, 'o' }
7873 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
7874 { { STATE_PSEXCM }, 'i' },
7875 { { STATE_PSRING }, 'i' },
7876 { { STATE_CCOUNT }, 'i' }
7879 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
7880 { { 6 /* art */ }, 'i' }
7883 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
7884 { { STATE_PSEXCM }, 'i' },
7885 { { STATE_PSRING }, 'i' },
7886 { { STATE_XTSYNC }, 'o' },
7887 { { STATE_CCOUNT }, 'o' }
7890 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
7891 { { 6 /* art */ }, 'm' }
7894 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
7895 { { STATE_PSEXCM }, 'i' },
7896 { { STATE_PSRING }, 'i' },
7897 { { STATE_XTSYNC }, 'o' },
7898 { { STATE_CCOUNT }, 'm' }
7901 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
7902 { { 6 /* art */ }, 'o' }
7905 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
7906 { { STATE_PSEXCM }, 'i' },
7907 { { STATE_PSRING }, 'i' },
7908 { { STATE_CCOMPARE0 }, 'i' }
7911 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
7912 { { 6 /* art */ }, 'i' }
7915 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
7916 { { STATE_PSEXCM }, 'i' },
7917 { { STATE_PSRING }, 'i' },
7918 { { STATE_CCOMPARE0 }, 'o' },
7919 { { STATE_INTERRUPT }, 'm' }
7922 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
7923 { { 6 /* art */ }, 'm' }
7926 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
7927 { { STATE_PSEXCM }, 'i' },
7928 { { STATE_PSRING }, 'i' },
7929 { { STATE_CCOMPARE0 }, 'm' },
7930 { { STATE_INTERRUPT }, 'm' }
7933 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
7934 { { 6 /* art */ }, 'o' }
7937 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
7938 { { STATE_PSEXCM }, 'i' },
7939 { { STATE_PSRING }, 'i' },
7940 { { STATE_CCOMPARE1 }, 'i' }
7943 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
7944 { { 6 /* art */ }, 'i' }
7947 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
7948 { { STATE_PSEXCM }, 'i' },
7949 { { STATE_PSRING }, 'i' },
7950 { { STATE_CCOMPARE1 }, 'o' },
7951 { { STATE_INTERRUPT }, 'm' }
7954 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
7955 { { 6 /* art */ }, 'm' }
7958 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
7959 { { STATE_PSEXCM }, 'i' },
7960 { { STATE_PSRING }, 'i' },
7961 { { STATE_CCOMPARE1 }, 'm' },
7962 { { STATE_INTERRUPT }, 'm' }
7965 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
7966 { { 6 /* art */ }, 'o' }
7969 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
7970 { { STATE_PSEXCM }, 'i' },
7971 { { STATE_PSRING }, 'i' },
7972 { { STATE_CCOMPARE2 }, 'i' }
7975 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
7976 { { 6 /* art */ }, 'i' }
7979 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
7980 { { STATE_PSEXCM }, 'i' },
7981 { { STATE_PSRING }, 'i' },
7982 { { STATE_CCOMPARE2 }, 'o' },
7983 { { STATE_INTERRUPT }, 'm' }
7986 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
7987 { { 6 /* art */ }, 'm' }
7990 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
7991 { { STATE_PSEXCM }, 'i' },
7992 { { STATE_PSRING }, 'i' },
7993 { { STATE_CCOMPARE2 }, 'm' },
7994 { { STATE_INTERRUPT }, 'm' }
7997 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
7998 { { 4 /* ars */ }, 'i' },
7999 { { 21 /* uimm8x4 */ }, 'i' }
8002 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
8003 { { 4 /* ars */ }, 'i' },
8004 { { 22 /* uimm4x16 */ }, 'i' }
8007 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
8008 { { STATE_PSEXCM }, 'i' },
8009 { { STATE_PSRING }, 'i' }
8012 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
8013 { { 4 /* ars */ }, 'i' },
8014 { { 21 /* uimm8x4 */ }, 'i' }
8017 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
8018 { { STATE_PSEXCM }, 'i' },
8019 { { STATE_PSRING }, 'i' }
8022 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
8023 { { 6 /* art */ }, 'o' },
8024 { { 4 /* ars */ }, 'i' }
8027 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
8028 { { STATE_PSEXCM }, 'i' },
8029 { { STATE_PSRING }, 'i' }
8032 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
8033 { { 6 /* art */ }, 'i' },
8034 { { 4 /* ars */ }, 'i' }
8037 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
8038 { { STATE_PSEXCM }, 'i' },
8039 { { STATE_PSRING }, 'i' }
8042 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
8043 { { 4 /* ars */ }, 'i' },
8044 { { 21 /* uimm8x4 */ }, 'i' }
8047 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
8048 { { 4 /* ars */ }, 'i' },
8049 { { 22 /* uimm4x16 */ }, 'i' }
8052 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
8053 { { STATE_PSEXCM }, 'i' },
8054 { { STATE_PSRING }, 'i' }
8057 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
8058 { { 4 /* ars */ }, 'i' },
8059 { { 21 /* uimm8x4 */ }, 'i' }
8062 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
8063 { { STATE_PSEXCM }, 'i' },
8064 { { STATE_PSRING }, 'i' }
8067 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
8068 { { 4 /* ars */ }, 'i' },
8069 { { 21 /* uimm8x4 */ }, 'i' }
8072 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
8073 { { 4 /* ars */ }, 'i' },
8074 { { 22 /* uimm4x16 */ }, 'i' }
8077 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
8078 { { STATE_PSEXCM }, 'i' },
8079 { { STATE_PSRING }, 'i' }
8082 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
8083 { { 6 /* art */ }, 'i' },
8084 { { 4 /* ars */ }, 'i' }
8087 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
8088 { { STATE_PSEXCM }, 'i' },
8089 { { STATE_PSRING }, 'i' }
8092 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
8093 { { 6 /* art */ }, 'o' },
8094 { { 4 /* ars */ }, 'i' }
8097 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
8098 { { STATE_PSEXCM }, 'i' },
8099 { { STATE_PSRING }, 'i' }
8102 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
8103 { { 6 /* art */ }, 'i' }
8106 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
8107 { { STATE_PSEXCM }, 'i' },
8108 { { STATE_PSRING }, 'i' },
8109 { { STATE_PTBASE }, 'o' },
8110 { { STATE_XTSYNC }, 'o' }
8113 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
8114 { { 6 /* art */ }, 'o' }
8117 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
8118 { { STATE_PSEXCM }, 'i' },
8119 { { STATE_PSRING }, 'i' },
8120 { { STATE_PTBASE }, 'i' },
8121 { { STATE_EXCVADDR }, 'i' }
8124 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
8125 { { 6 /* art */ }, 'm' }
8128 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
8129 { { STATE_PSEXCM }, 'i' },
8130 { { STATE_PSRING }, 'i' },
8131 { { STATE_PTBASE }, 'm' },
8132 { { STATE_EXCVADDR }, 'i' },
8133 { { STATE_XTSYNC }, 'o' }
8136 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
8137 { { 6 /* art */ }, 'o' }
8140 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
8141 { { STATE_PSEXCM }, 'i' },
8142 { { STATE_PSRING }, 'i' },
8143 { { STATE_ASID3 }, 'i' },
8144 { { STATE_ASID2 }, 'i' },
8145 { { STATE_ASID1 }, 'i' }
8148 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
8149 { { 6 /* art */ }, 'i' }
8152 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
8153 { { STATE_XTSYNC }, 'o' },
8154 { { STATE_PSEXCM }, 'i' },
8155 { { STATE_PSRING }, 'i' },
8156 { { STATE_ASID3 }, 'o' },
8157 { { STATE_ASID2 }, 'o' },
8158 { { STATE_ASID1 }, 'o' }
8161 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
8162 { { 6 /* art */ }, 'm' }
8165 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
8166 { { STATE_XTSYNC }, 'o' },
8167 { { STATE_PSEXCM }, 'i' },
8168 { { STATE_PSRING }, 'i' },
8169 { { STATE_ASID3 }, 'm' },
8170 { { STATE_ASID2 }, 'm' },
8171 { { STATE_ASID1 }, 'm' }
8174 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
8175 { { 6 /* art */ }, 'o' }
8178 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
8179 { { STATE_PSEXCM }, 'i' },
8180 { { STATE_PSRING }, 'i' },
8181 { { STATE_INSTPGSZID4 }, 'i' }
8184 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
8185 { { 6 /* art */ }, 'i' }
8188 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
8189 { { STATE_XTSYNC }, 'o' },
8190 { { STATE_PSEXCM }, 'i' },
8191 { { STATE_PSRING }, 'i' },
8192 { { STATE_INSTPGSZID4 }, 'o' }
8195 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
8196 { { 6 /* art */ }, 'm' }
8199 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
8200 { { STATE_XTSYNC }, 'o' },
8201 { { STATE_PSEXCM }, 'i' },
8202 { { STATE_PSRING }, 'i' },
8203 { { STATE_INSTPGSZID4 }, 'm' }
8206 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
8207 { { 6 /* art */ }, 'o' }
8210 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
8211 { { STATE_PSEXCM }, 'i' },
8212 { { STATE_PSRING }, 'i' },
8213 { { STATE_DATAPGSZID4 }, 'i' }
8216 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
8217 { { 6 /* art */ }, 'i' }
8220 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
8221 { { STATE_XTSYNC }, 'o' },
8222 { { STATE_PSEXCM }, 'i' },
8223 { { STATE_PSRING }, 'i' },
8224 { { STATE_DATAPGSZID4 }, 'o' }
8227 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
8228 { { 6 /* art */ }, 'm' }
8231 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
8232 { { STATE_XTSYNC }, 'o' },
8233 { { STATE_PSEXCM }, 'i' },
8234 { { STATE_PSRING }, 'i' },
8235 { { STATE_DATAPGSZID4 }, 'm' }
8238 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
8239 { { 4 /* ars */ }, 'i' }
8242 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
8243 { { STATE_PSEXCM }, 'i' },
8244 { { STATE_PSRING }, 'i' },
8245 { { STATE_XTSYNC }, 'o' }
8248 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
8249 { { 6 /* art */ }, 'o' },
8250 { { 4 /* ars */ }, 'i' }
8253 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
8254 { { STATE_PSEXCM }, 'i' },
8255 { { STATE_PSRING }, 'i' }
8258 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
8259 { { 6 /* art */ }, 'i' },
8260 { { 4 /* ars */ }, 'i' }
8263 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
8264 { { STATE_PSEXCM }, 'i' },
8265 { { STATE_PSRING }, 'i' },
8266 { { STATE_XTSYNC }, 'o' }
8269 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
8270 { { 4 /* ars */ }, 'i' }
8273 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
8274 { { STATE_PSEXCM }, 'i' },
8275 { { STATE_PSRING }, 'i' }
8278 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
8279 { { 6 /* art */ }, 'o' },
8280 { { 4 /* ars */ }, 'i' }
8283 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
8284 { { STATE_PSEXCM }, 'i' },
8285 { { STATE_PSRING }, 'i' }
8288 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
8289 { { 6 /* art */ }, 'i' },
8290 { { 4 /* ars */ }, 'i' }
8293 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
8294 { { STATE_PSEXCM }, 'i' },
8295 { { STATE_PSRING }, 'i' }
8298 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
8299 { { STATE_PTBASE }, 'i' },
8300 { { STATE_EXCVADDR }, 'i' }
8303 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
8304 { { STATE_EXCVADDR }, 'i' }
8307 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
8308 { { STATE_EXCVADDR }, 'i' }
8311 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
8312 { { 6 /* art */ }, 'o' }
8315 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
8316 { { STATE_PSEXCM }, 'i' },
8317 { { STATE_PSRING }, 'i' },
8318 { { STATE_CPENABLE }, 'i' }
8321 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
8322 { { 6 /* art */ }, 'i' }
8325 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
8326 { { STATE_PSEXCM }, 'i' },
8327 { { STATE_PSRING }, 'i' },
8328 { { STATE_CPENABLE }, 'o' }
8331 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
8332 { { 6 /* art */ }, 'm' }
8335 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
8336 { { STATE_PSEXCM }, 'i' },
8337 { { STATE_PSRING }, 'i' },
8338 { { STATE_CPENABLE }, 'm' }
8341 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
8342 { { 3 /* arr */ }, 'o' },
8343 { { 4 /* ars */ }, 'i' },
8344 { { 58 /* tp7 */ }, 'i' }
8347 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
8348 { { 3 /* arr */ }, 'o' },
8349 { { 4 /* ars */ }, 'i' },
8350 { { 6 /* art */ }, 'i' }
8353 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
8354 { { 6 /* art */ }, 'o' },
8355 { { 4 /* ars */ }, 'i' }
8358 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
8359 { { 3 /* arr */ }, 'o' },
8360 { { 4 /* ars */ }, 'i' },
8361 { { 58 /* tp7 */ }, 'i' }
8364 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
8365 { { 6 /* art */ }, 'o' },
8366 { { 4 /* ars */ }, 'i' },
8367 { { 21 /* uimm8x4 */ }, 'i' }
8370 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
8371 { { 6 /* art */ }, 'i' },
8372 { { 4 /* ars */ }, 'i' },
8373 { { 21 /* uimm8x4 */ }, 'i' }
8376 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
8377 { { 6 /* art */ }, 'm' },
8378 { { 4 /* ars */ }, 'i' },
8379 { { 21 /* uimm8x4 */ }, 'i' }
8382 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
8383 { { STATE_SCOMPARE1 }, 'i' },
8384 { { STATE_SCOMPARE1 }, 'i' }
8387 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
8388 { { 6 /* art */ }, 'o' }
8391 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
8392 { { STATE_SCOMPARE1 }, 'i' }
8395 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
8396 { { 6 /* art */ }, 'i' }
8399 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
8400 { { STATE_SCOMPARE1 }, 'o' }
8403 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
8404 { { 6 /* art */ }, 'm' }
8407 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
8408 { { STATE_SCOMPARE1 }, 'm' }
8411 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
8412 { { 3 /* arr */ }, 'o' },
8413 { { 4 /* ars */ }, 'i' },
8414 { { 6 /* art */ }, 'i' }
8417 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
8418 { { 3 /* arr */ }, 'o' },
8419 { { 4 /* ars */ }, 'i' },
8420 { { 6 /* art */ }, 'i' }
8423 static xtensa_arg_internal Iclass_rur_fcr_args[] = {
8424 { { 3 /* arr */ }, 'o' }
8427 static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
8428 { { STATE_RoundMode }, 'i' },
8429 { { STATE_InvalidEnable }, 'i' },
8430 { { STATE_DivZeroEnable }, 'i' },
8431 { { STATE_OverflowEnable }, 'i' },
8432 { { STATE_UnderflowEnable }, 'i' },
8433 { { STATE_InexactEnable }, 'i' },
8434 { { STATE_FPreserved20 }, 'i' },
8435 { { STATE_FPreserved5 }, 'i' },
8436 { { STATE_CPENABLE }, 'i' }
8439 static xtensa_arg_internal Iclass_wur_fcr_args[] = {
8440 { { 6 /* art */ }, 'i' }
8443 static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
8444 { { STATE_RoundMode }, 'o' },
8445 { { STATE_InvalidEnable }, 'o' },
8446 { { STATE_DivZeroEnable }, 'o' },
8447 { { STATE_OverflowEnable }, 'o' },
8448 { { STATE_UnderflowEnable }, 'o' },
8449 { { STATE_InexactEnable }, 'o' },
8450 { { STATE_FPreserved20 }, 'o' },
8451 { { STATE_FPreserved5 }, 'o' },
8452 { { STATE_CPENABLE }, 'i' }
8455 static xtensa_arg_internal Iclass_rur_fsr_args[] = {
8456 { { 3 /* arr */ }, 'o' }
8459 static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
8460 { { STATE_InvalidFlag }, 'i' },
8461 { { STATE_DivZeroFlag }, 'i' },
8462 { { STATE_OverflowFlag }, 'i' },
8463 { { STATE_UnderflowFlag }, 'i' },
8464 { { STATE_InexactFlag }, 'i' },
8465 { { STATE_FPreserved20a }, 'i' },
8466 { { STATE_FPreserved7 }, 'i' },
8467 { { STATE_CPENABLE }, 'i' }
8470 static xtensa_arg_internal Iclass_wur_fsr_args[] = {
8471 { { 6 /* art */ }, 'i' }
8474 static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
8475 { { STATE_InvalidFlag }, 'o' },
8476 { { STATE_DivZeroFlag }, 'o' },
8477 { { STATE_OverflowFlag }, 'o' },
8478 { { STATE_UnderflowFlag }, 'o' },
8479 { { STATE_InexactFlag }, 'o' },
8480 { { STATE_FPreserved20a }, 'o' },
8481 { { STATE_FPreserved7 }, 'o' },
8482 { { STATE_CPENABLE }, 'i' }
8485 static xtensa_arg_internal Iclass_fp_args[] = {
8486 { { 62 /* frr */ }, 'o' },
8487 { { 63 /* frs */ }, 'i' },
8488 { { 64 /* frt */ }, 'i' }
8491 static xtensa_arg_internal Iclass_fp_stateArgs[] = {
8492 { { STATE_RoundMode }, 'i' },
8493 { { STATE_CPENABLE }, 'i' }
8496 static xtensa_arg_internal Iclass_fp_mac_args[] = {
8497 { { 62 /* frr */ }, 'm' },
8498 { { 63 /* frs */ }, 'i' },
8499 { { 64 /* frt */ }, 'i' }
8502 static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
8503 { { STATE_RoundMode }, 'i' },
8504 { { STATE_CPENABLE }, 'i' }
8507 static xtensa_arg_internal Iclass_fp_cmov_args[] = {
8508 { { 62 /* frr */ }, 'm' },
8509 { { 63 /* frs */ }, 'i' },
8510 { { 42 /* bt */ }, 'i' }
8513 static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
8514 { { STATE_CPENABLE }, 'i' }
8517 static xtensa_arg_internal Iclass_fp_mov_args[] = {
8518 { { 62 /* frr */ }, 'm' },
8519 { { 63 /* frs */ }, 'i' },
8520 { { 6 /* art */ }, 'i' }
8523 static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
8524 { { STATE_CPENABLE }, 'i' }
8527 static xtensa_arg_internal Iclass_fp_mov2_args[] = {
8528 { { 62 /* frr */ }, 'o' },
8529 { { 63 /* frs */ }, 'i' }
8532 static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
8533 { { STATE_CPENABLE }, 'i' }
8536 static xtensa_arg_internal Iclass_fp_cmp_args[] = {
8537 { { 44 /* br */ }, 'o' },
8538 { { 63 /* frs */ }, 'i' },
8539 { { 64 /* frt */ }, 'i' }
8542 static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
8543 { { STATE_CPENABLE }, 'i' }
8546 static xtensa_arg_internal Iclass_fp_float_args[] = {
8547 { { 62 /* frr */ }, 'o' },
8548 { { 4 /* ars */ }, 'i' },
8549 { { 65 /* t */ }, 'i' }
8552 static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
8553 { { STATE_RoundMode }, 'i' },
8554 { { STATE_CPENABLE }, 'i' }
8557 static xtensa_arg_internal Iclass_fp_int_args[] = {
8558 { { 3 /* arr */ }, 'o' },
8559 { { 63 /* frs */ }, 'i' },
8560 { { 65 /* t */ }, 'i' }
8563 static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
8564 { { STATE_CPENABLE }, 'i' }
8567 static xtensa_arg_internal Iclass_fp_rfr_args[] = {
8568 { { 3 /* arr */ }, 'o' },
8569 { { 63 /* frs */ }, 'i' }
8572 static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
8573 { { STATE_CPENABLE }, 'i' }
8576 static xtensa_arg_internal Iclass_fp_wfr_args[] = {
8577 { { 62 /* frr */ }, 'o' },
8578 { { 4 /* ars */ }, 'i' }
8581 static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
8582 { { STATE_CPENABLE }, 'i' }
8585 static xtensa_arg_internal Iclass_fp_lsi_args[] = {
8586 { { 64 /* frt */ }, 'o' },
8587 { { 4 /* ars */ }, 'i' },
8588 { { 61 /* cimm8x4 */ }, 'i' }
8591 static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
8592 { { STATE_CPENABLE }, 'i' }
8595 static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
8596 { { 64 /* frt */ }, 'o' },
8597 { { 4 /* ars */ }, 'm' },
8598 { { 61 /* cimm8x4 */ }, 'i' }
8601 static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
8602 { { STATE_CPENABLE }, 'i' }
8605 static xtensa_arg_internal Iclass_fp_lsx_args[] = {
8606 { { 62 /* frr */ }, 'o' },
8607 { { 4 /* ars */ }, 'i' },
8608 { { 6 /* art */ }, 'i' }
8611 static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
8612 { { STATE_CPENABLE }, 'i' }
8615 static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
8616 { { 62 /* frr */ }, 'o' },
8617 { { 4 /* ars */ }, 'm' },
8618 { { 6 /* art */ }, 'i' }
8621 static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
8622 { { STATE_CPENABLE }, 'i' }
8625 static xtensa_arg_internal Iclass_fp_ssi_args[] = {
8626 { { 64 /* frt */ }, 'i' },
8627 { { 4 /* ars */ }, 'i' },
8628 { { 61 /* cimm8x4 */ }, 'i' }
8631 static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
8632 { { STATE_CPENABLE }, 'i' }
8635 static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
8636 { { 64 /* frt */ }, 'i' },
8637 { { 4 /* ars */ }, 'm' },
8638 { { 61 /* cimm8x4 */ }, 'i' }
8641 static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
8642 { { STATE_CPENABLE }, 'i' }
8645 static xtensa_arg_internal Iclass_fp_ssx_args[] = {
8646 { { 62 /* frr */ }, 'i' },
8647 { { 4 /* ars */ }, 'i' },
8648 { { 6 /* art */ }, 'i' }
8651 static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
8652 { { STATE_CPENABLE }, 'i' }
8655 static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
8656 { { 62 /* frr */ }, 'i' },
8657 { { 4 /* ars */ }, 'm' },
8658 { { 6 /* art */ }, 'i' }
8661 static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
8662 { { STATE_CPENABLE }, 'i' }
8665 static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
8666 { { 4 /* ars */ }, 'i' },
8667 { { 60 /* xt_wbr18_label */ }, 'i' }
8670 static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
8671 { { 4 /* ars */ }, 'i' },
8672 { { 17 /* b4const */ }, 'i' },
8673 { { 60 /* xt_wbr18_label */ }, 'i' }
8676 static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
8677 { { 4 /* ars */ }, 'i' },
8678 { { 18 /* b4constu */ }, 'i' },
8679 { { 60 /* xt_wbr18_label */ }, 'i' }
8682 static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
8683 { { 4 /* ars */ }, 'i' },
8684 { { 67 /* bbi */ }, 'i' },
8685 { { 60 /* xt_wbr18_label */ }, 'i' }
8688 static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
8689 { { 4 /* ars */ }, 'i' },
8690 { { 6 /* art */ }, 'i' },
8691 { { 60 /* xt_wbr18_label */ }, 'i' }
8694 static xtensa_iclass_internal iclasses[] = {
8695 { 0, 0 /* xt_iclass_excw */,
8697 { 0, 0 /* xt_iclass_rfe */,
8698 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
8699 { 0, 0 /* xt_iclass_rfde */,
8700 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
8701 { 0, 0 /* xt_iclass_syscall */,
8703 { 0, 0 /* xt_iclass_simcall */,
8705 { 2, Iclass_xt_iclass_call12_args,
8706 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
8707 { 2, Iclass_xt_iclass_call8_args,
8708 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
8709 { 2, Iclass_xt_iclass_call4_args,
8710 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
8711 { 2, Iclass_xt_iclass_callx12_args,
8712 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
8713 { 2, Iclass_xt_iclass_callx8_args,
8714 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
8715 { 2, Iclass_xt_iclass_callx4_args,
8716 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
8717 { 3, Iclass_xt_iclass_entry_args,
8718 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
8719 { 2, Iclass_xt_iclass_movsp_args,
8720 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
8721 { 1, Iclass_xt_iclass_rotw_args,
8722 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
8723 { 1, Iclass_xt_iclass_retw_args,
8724 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
8725 { 0, 0 /* xt_iclass_rfwou */,
8726 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
8727 { 3, Iclass_xt_iclass_l32e_args,
8728 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
8729 { 3, Iclass_xt_iclass_s32e_args,
8730 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
8731 { 1, Iclass_xt_iclass_rsr_windowbase_args,
8732 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
8733 { 1, Iclass_xt_iclass_wsr_windowbase_args,
8734 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
8735 { 1, Iclass_xt_iclass_xsr_windowbase_args,
8736 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
8737 { 1, Iclass_xt_iclass_rsr_windowstart_args,
8738 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
8739 { 1, Iclass_xt_iclass_wsr_windowstart_args,
8740 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
8741 { 1, Iclass_xt_iclass_xsr_windowstart_args,
8742 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
8743 { 3, Iclass_xt_iclass_add_n_args,
8745 { 3, Iclass_xt_iclass_addi_n_args,
8747 { 2, Iclass_xt_iclass_bz6_args,
8749 { 0, 0 /* xt_iclass_ill_n */,
8751 { 3, Iclass_xt_iclass_loadi4_args,
8753 { 2, Iclass_xt_iclass_mov_n_args,
8755 { 2, Iclass_xt_iclass_movi_n_args,
8757 { 0, 0 /* xt_iclass_nopn */,
8759 { 1, Iclass_xt_iclass_retn_args,
8761 { 3, Iclass_xt_iclass_storei4_args,
8763 { 1, Iclass_rur_threadptr_args,
8764 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
8765 { 1, Iclass_wur_threadptr_args,
8766 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
8767 { 3, Iclass_xt_iclass_addi_args,
8769 { 3, Iclass_xt_iclass_addmi_args,
8771 { 3, Iclass_xt_iclass_addsub_args,
8773 { 3, Iclass_xt_iclass_bit_args,
8775 { 3, Iclass_xt_iclass_bsi8_args,
8777 { 3, Iclass_xt_iclass_bsi8b_args,
8779 { 3, Iclass_xt_iclass_bsi8u_args,
8781 { 3, Iclass_xt_iclass_bst8_args,
8783 { 2, Iclass_xt_iclass_bsz12_args,
8785 { 2, Iclass_xt_iclass_call0_args,
8787 { 2, Iclass_xt_iclass_callx0_args,
8789 { 4, Iclass_xt_iclass_exti_args,
8791 { 0, 0 /* xt_iclass_ill */,
8793 { 1, Iclass_xt_iclass_jump_args,
8795 { 1, Iclass_xt_iclass_jumpx_args,
8797 { 3, Iclass_xt_iclass_l16ui_args,
8799 { 3, Iclass_xt_iclass_l16si_args,
8801 { 3, Iclass_xt_iclass_l32i_args,
8803 { 2, Iclass_xt_iclass_l32r_args,
8804 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
8805 { 3, Iclass_xt_iclass_l8i_args,
8807 { 2, Iclass_xt_iclass_loop_args,
8808 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
8809 { 2, Iclass_xt_iclass_loopz_args,
8810 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
8811 { 2, Iclass_xt_iclass_movi_args,
8813 { 3, Iclass_xt_iclass_movz_args,
8815 { 2, Iclass_xt_iclass_neg_args,
8817 { 0, 0 /* xt_iclass_nop */,
8819 { 1, Iclass_xt_iclass_return_args,
8821 { 3, Iclass_xt_iclass_s16i_args,
8823 { 3, Iclass_xt_iclass_s32i_args,
8825 { 3, Iclass_xt_iclass_s8i_args,
8827 { 1, Iclass_xt_iclass_sar_args,
8828 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
8829 { 1, Iclass_xt_iclass_sari_args,
8830 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
8831 { 2, Iclass_xt_iclass_shifts_args,
8832 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
8833 { 3, Iclass_xt_iclass_shiftst_args,
8834 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
8835 { 2, Iclass_xt_iclass_shiftt_args,
8836 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
8837 { 3, Iclass_xt_iclass_slli_args,
8839 { 3, Iclass_xt_iclass_srai_args,
8841 { 3, Iclass_xt_iclass_srli_args,
8843 { 0, 0 /* xt_iclass_memw */,
8845 { 0, 0 /* xt_iclass_extw */,
8847 { 0, 0 /* xt_iclass_isync */,
8849 { 0, 0 /* xt_iclass_sync */,
8850 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
8851 { 2, Iclass_xt_iclass_rsil_args,
8852 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
8853 { 1, Iclass_xt_iclass_rsr_lend_args,
8854 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
8855 { 1, Iclass_xt_iclass_wsr_lend_args,
8856 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
8857 { 1, Iclass_xt_iclass_xsr_lend_args,
8858 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
8859 { 1, Iclass_xt_iclass_rsr_lcount_args,
8860 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
8861 { 1, Iclass_xt_iclass_wsr_lcount_args,
8862 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
8863 { 1, Iclass_xt_iclass_xsr_lcount_args,
8864 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
8865 { 1, Iclass_xt_iclass_rsr_lbeg_args,
8866 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
8867 { 1, Iclass_xt_iclass_wsr_lbeg_args,
8868 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
8869 { 1, Iclass_xt_iclass_xsr_lbeg_args,
8870 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
8871 { 1, Iclass_xt_iclass_rsr_sar_args,
8872 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
8873 { 1, Iclass_xt_iclass_wsr_sar_args,
8874 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
8875 { 1, Iclass_xt_iclass_xsr_sar_args,
8876 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
8877 { 1, Iclass_xt_iclass_rsr_litbase_args,
8878 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
8879 { 1, Iclass_xt_iclass_wsr_litbase_args,
8880 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
8881 { 1, Iclass_xt_iclass_xsr_litbase_args,
8882 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
8883 { 1, Iclass_xt_iclass_rsr_176_args,
8884 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
8885 { 1, Iclass_xt_iclass_rsr_208_args,
8886 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
8887 { 1, Iclass_xt_iclass_rsr_ps_args,
8888 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
8889 { 1, Iclass_xt_iclass_wsr_ps_args,
8890 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
8891 { 1, Iclass_xt_iclass_xsr_ps_args,
8892 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
8893 { 1, Iclass_xt_iclass_rsr_epc1_args,
8894 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
8895 { 1, Iclass_xt_iclass_wsr_epc1_args,
8896 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
8897 { 1, Iclass_xt_iclass_xsr_epc1_args,
8898 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
8899 { 1, Iclass_xt_iclass_rsr_excsave1_args,
8900 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
8901 { 1, Iclass_xt_iclass_wsr_excsave1_args,
8902 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
8903 { 1, Iclass_xt_iclass_xsr_excsave1_args,
8904 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
8905 { 1, Iclass_xt_iclass_rsr_epc2_args,
8906 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
8907 { 1, Iclass_xt_iclass_wsr_epc2_args,
8908 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
8909 { 1, Iclass_xt_iclass_xsr_epc2_args,
8910 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
8911 { 1, Iclass_xt_iclass_rsr_excsave2_args,
8912 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
8913 { 1, Iclass_xt_iclass_wsr_excsave2_args,
8914 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
8915 { 1, Iclass_xt_iclass_xsr_excsave2_args,
8916 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
8917 { 1, Iclass_xt_iclass_rsr_epc3_args,
8918 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
8919 { 1, Iclass_xt_iclass_wsr_epc3_args,
8920 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
8921 { 1, Iclass_xt_iclass_xsr_epc3_args,
8922 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
8923 { 1, Iclass_xt_iclass_rsr_excsave3_args,
8924 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
8925 { 1, Iclass_xt_iclass_wsr_excsave3_args,
8926 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
8927 { 1, Iclass_xt_iclass_xsr_excsave3_args,
8928 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
8929 { 1, Iclass_xt_iclass_rsr_epc4_args,
8930 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
8931 { 1, Iclass_xt_iclass_wsr_epc4_args,
8932 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
8933 { 1, Iclass_xt_iclass_xsr_epc4_args,
8934 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
8935 { 1, Iclass_xt_iclass_rsr_excsave4_args,
8936 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
8937 { 1, Iclass_xt_iclass_wsr_excsave4_args,
8938 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
8939 { 1, Iclass_xt_iclass_xsr_excsave4_args,
8940 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
8941 { 1, Iclass_xt_iclass_rsr_epc5_args,
8942 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
8943 { 1, Iclass_xt_iclass_wsr_epc5_args,
8944 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
8945 { 1, Iclass_xt_iclass_xsr_epc5_args,
8946 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
8947 { 1, Iclass_xt_iclass_rsr_excsave5_args,
8948 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
8949 { 1, Iclass_xt_iclass_wsr_excsave5_args,
8950 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
8951 { 1, Iclass_xt_iclass_xsr_excsave5_args,
8952 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
8953 { 1, Iclass_xt_iclass_rsr_epc6_args,
8954 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
8955 { 1, Iclass_xt_iclass_wsr_epc6_args,
8956 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
8957 { 1, Iclass_xt_iclass_xsr_epc6_args,
8958 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
8959 { 1, Iclass_xt_iclass_rsr_excsave6_args,
8960 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
8961 { 1, Iclass_xt_iclass_wsr_excsave6_args,
8962 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
8963 { 1, Iclass_xt_iclass_xsr_excsave6_args,
8964 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
8965 { 1, Iclass_xt_iclass_rsr_epc7_args,
8966 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
8967 { 1, Iclass_xt_iclass_wsr_epc7_args,
8968 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
8969 { 1, Iclass_xt_iclass_xsr_epc7_args,
8970 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
8971 { 1, Iclass_xt_iclass_rsr_excsave7_args,
8972 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
8973 { 1, Iclass_xt_iclass_wsr_excsave7_args,
8974 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
8975 { 1, Iclass_xt_iclass_xsr_excsave7_args,
8976 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
8977 { 1, Iclass_xt_iclass_rsr_eps2_args,
8978 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
8979 { 1, Iclass_xt_iclass_wsr_eps2_args,
8980 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
8981 { 1, Iclass_xt_iclass_xsr_eps2_args,
8982 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
8983 { 1, Iclass_xt_iclass_rsr_eps3_args,
8984 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
8985 { 1, Iclass_xt_iclass_wsr_eps3_args,
8986 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
8987 { 1, Iclass_xt_iclass_xsr_eps3_args,
8988 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
8989 { 1, Iclass_xt_iclass_rsr_eps4_args,
8990 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
8991 { 1, Iclass_xt_iclass_wsr_eps4_args,
8992 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
8993 { 1, Iclass_xt_iclass_xsr_eps4_args,
8994 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
8995 { 1, Iclass_xt_iclass_rsr_eps5_args,
8996 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
8997 { 1, Iclass_xt_iclass_wsr_eps5_args,
8998 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
8999 { 1, Iclass_xt_iclass_xsr_eps5_args,
9000 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
9001 { 1, Iclass_xt_iclass_rsr_eps6_args,
9002 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
9003 { 1, Iclass_xt_iclass_wsr_eps6_args,
9004 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
9005 { 1, Iclass_xt_iclass_xsr_eps6_args,
9006 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
9007 { 1, Iclass_xt_iclass_rsr_eps7_args,
9008 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
9009 { 1, Iclass_xt_iclass_wsr_eps7_args,
9010 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
9011 { 1, Iclass_xt_iclass_xsr_eps7_args,
9012 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
9013 { 1, Iclass_xt_iclass_rsr_excvaddr_args,
9014 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
9015 { 1, Iclass_xt_iclass_wsr_excvaddr_args,
9016 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
9017 { 1, Iclass_xt_iclass_xsr_excvaddr_args,
9018 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
9019 { 1, Iclass_xt_iclass_rsr_depc_args,
9020 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
9021 { 1, Iclass_xt_iclass_wsr_depc_args,
9022 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
9023 { 1, Iclass_xt_iclass_xsr_depc_args,
9024 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
9025 { 1, Iclass_xt_iclass_rsr_exccause_args,
9026 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
9027 { 1, Iclass_xt_iclass_wsr_exccause_args,
9028 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
9029 { 1, Iclass_xt_iclass_xsr_exccause_args,
9030 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
9031 { 1, Iclass_xt_iclass_rsr_misc0_args,
9032 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
9033 { 1, Iclass_xt_iclass_wsr_misc0_args,
9034 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
9035 { 1, Iclass_xt_iclass_xsr_misc0_args,
9036 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
9037 { 1, Iclass_xt_iclass_rsr_misc1_args,
9038 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
9039 { 1, Iclass_xt_iclass_wsr_misc1_args,
9040 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
9041 { 1, Iclass_xt_iclass_xsr_misc1_args,
9042 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
9043 { 1, Iclass_xt_iclass_rsr_misc2_args,
9044 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
9045 { 1, Iclass_xt_iclass_wsr_misc2_args,
9046 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
9047 { 1, Iclass_xt_iclass_xsr_misc2_args,
9048 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
9049 { 1, Iclass_xt_iclass_rsr_misc3_args,
9050 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
9051 { 1, Iclass_xt_iclass_wsr_misc3_args,
9052 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
9053 { 1, Iclass_xt_iclass_xsr_misc3_args,
9054 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
9055 { 1, Iclass_xt_iclass_rsr_prid_args,
9056 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
9057 { 1, Iclass_xt_iclass_rsr_vecbase_args,
9058 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
9059 { 1, Iclass_xt_iclass_wsr_vecbase_args,
9060 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
9061 { 1, Iclass_xt_iclass_xsr_vecbase_args,
9062 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
9063 { 2, Iclass_xt_iclass_mac16_aa_args,
9064 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
9065 { 2, Iclass_xt_iclass_mac16_ad_args,
9066 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
9067 { 2, Iclass_xt_iclass_mac16_da_args,
9068 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
9069 { 2, Iclass_xt_iclass_mac16_dd_args,
9070 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
9071 { 2, Iclass_xt_iclass_mac16a_aa_args,
9072 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
9073 { 2, Iclass_xt_iclass_mac16a_ad_args,
9074 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
9075 { 2, Iclass_xt_iclass_mac16a_da_args,
9076 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
9077 { 2, Iclass_xt_iclass_mac16a_dd_args,
9078 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
9079 { 4, Iclass_xt_iclass_mac16al_da_args,
9080 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
9081 { 4, Iclass_xt_iclass_mac16al_dd_args,
9082 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
9083 { 2, Iclass_xt_iclass_mac16_l_args,
9085 { 3, Iclass_xt_iclass_mul16_args,
9087 { 2, Iclass_xt_iclass_rsr_m0_args,
9089 { 2, Iclass_xt_iclass_wsr_m0_args,
9091 { 2, Iclass_xt_iclass_xsr_m0_args,
9093 { 2, Iclass_xt_iclass_rsr_m1_args,
9095 { 2, Iclass_xt_iclass_wsr_m1_args,
9097 { 2, Iclass_xt_iclass_xsr_m1_args,
9099 { 2, Iclass_xt_iclass_rsr_m2_args,
9101 { 2, Iclass_xt_iclass_wsr_m2_args,
9103 { 2, Iclass_xt_iclass_xsr_m2_args,
9105 { 2, Iclass_xt_iclass_rsr_m3_args,
9107 { 2, Iclass_xt_iclass_wsr_m3_args,
9109 { 2, Iclass_xt_iclass_xsr_m3_args,
9111 { 1, Iclass_xt_iclass_rsr_acclo_args,
9112 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
9113 { 1, Iclass_xt_iclass_wsr_acclo_args,
9114 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
9115 { 1, Iclass_xt_iclass_xsr_acclo_args,
9116 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
9117 { 1, Iclass_xt_iclass_rsr_acchi_args,
9118 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
9119 { 1, Iclass_xt_iclass_wsr_acchi_args,
9120 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
9121 { 1, Iclass_xt_iclass_xsr_acchi_args,
9122 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
9123 { 1, Iclass_xt_iclass_rfi_args,
9124 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
9125 { 1, Iclass_xt_iclass_wait_args,
9126 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
9127 { 1, Iclass_xt_iclass_rsr_interrupt_args,
9128 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
9129 { 1, Iclass_xt_iclass_wsr_intset_args,
9130 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
9131 { 1, Iclass_xt_iclass_wsr_intclear_args,
9132 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
9133 { 1, Iclass_xt_iclass_rsr_intenable_args,
9134 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
9135 { 1, Iclass_xt_iclass_wsr_intenable_args,
9136 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
9137 { 1, Iclass_xt_iclass_xsr_intenable_args,
9138 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
9139 { 2, Iclass_xt_iclass_break_args,
9140 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
9141 { 1, Iclass_xt_iclass_break_n_args,
9142 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
9143 { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
9144 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
9145 { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
9146 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
9147 { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
9148 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
9149 { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
9150 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
9151 { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
9152 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
9153 { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
9154 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
9155 { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
9156 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
9157 { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
9158 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
9159 { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
9160 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
9161 { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
9162 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
9163 { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
9164 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
9165 { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
9166 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
9167 { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
9168 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
9169 { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
9170 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
9171 { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
9172 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
9173 { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
9174 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
9175 { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
9176 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
9177 { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
9178 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
9179 { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
9180 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
9181 { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
9182 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
9183 { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
9184 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
9185 { 1, Iclass_xt_iclass_rsr_debugcause_args,
9186 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
9187 { 1, Iclass_xt_iclass_wsr_debugcause_args,
9188 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
9189 { 1, Iclass_xt_iclass_xsr_debugcause_args,
9190 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
9191 { 1, Iclass_xt_iclass_rsr_icount_args,
9192 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
9193 { 1, Iclass_xt_iclass_wsr_icount_args,
9194 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
9195 { 1, Iclass_xt_iclass_xsr_icount_args,
9196 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
9197 { 1, Iclass_xt_iclass_rsr_icountlevel_args,
9198 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
9199 { 1, Iclass_xt_iclass_wsr_icountlevel_args,
9200 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
9201 { 1, Iclass_xt_iclass_xsr_icountlevel_args,
9202 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
9203 { 1, Iclass_xt_iclass_rsr_ddr_args,
9204 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
9205 { 1, Iclass_xt_iclass_wsr_ddr_args,
9206 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
9207 { 1, Iclass_xt_iclass_xsr_ddr_args,
9208 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
9209 { 1, Iclass_xt_iclass_rfdo_args,
9210 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
9211 { 0, 0 /* xt_iclass_rfdd */,
9212 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
9213 { 1, Iclass_xt_iclass_wsr_mmid_args,
9214 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
9215 { 3, Iclass_xt_iclass_bbool1_args,
9217 { 2, Iclass_xt_iclass_bbool4_args,
9219 { 2, Iclass_xt_iclass_bbool8_args,
9221 { 2, Iclass_xt_iclass_bbranch_args,
9223 { 3, Iclass_xt_iclass_bmove_args,
9225 { 2, Iclass_xt_iclass_RSR_BR_args,
9227 { 2, Iclass_xt_iclass_WSR_BR_args,
9229 { 2, Iclass_xt_iclass_XSR_BR_args,
9231 { 1, Iclass_xt_iclass_rsr_ccount_args,
9232 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
9233 { 1, Iclass_xt_iclass_wsr_ccount_args,
9234 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
9235 { 1, Iclass_xt_iclass_xsr_ccount_args,
9236 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
9237 { 1, Iclass_xt_iclass_rsr_ccompare0_args,
9238 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
9239 { 1, Iclass_xt_iclass_wsr_ccompare0_args,
9240 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
9241 { 1, Iclass_xt_iclass_xsr_ccompare0_args,
9242 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
9243 { 1, Iclass_xt_iclass_rsr_ccompare1_args,
9244 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
9245 { 1, Iclass_xt_iclass_wsr_ccompare1_args,
9246 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
9247 { 1, Iclass_xt_iclass_xsr_ccompare1_args,
9248 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
9249 { 1, Iclass_xt_iclass_rsr_ccompare2_args,
9250 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
9251 { 1, Iclass_xt_iclass_wsr_ccompare2_args,
9252 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
9253 { 1, Iclass_xt_iclass_xsr_ccompare2_args,
9254 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
9255 { 2, Iclass_xt_iclass_icache_args,
9257 { 2, Iclass_xt_iclass_icache_lock_args,
9258 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
9259 { 2, Iclass_xt_iclass_icache_inv_args,
9260 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
9261 { 2, Iclass_xt_iclass_licx_args,
9262 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
9263 { 2, Iclass_xt_iclass_sicx_args,
9264 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
9265 { 2, Iclass_xt_iclass_dcache_args,
9267 { 2, Iclass_xt_iclass_dcache_ind_args,
9268 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
9269 { 2, Iclass_xt_iclass_dcache_inv_args,
9270 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
9271 { 2, Iclass_xt_iclass_dpf_args,
9273 { 2, Iclass_xt_iclass_dcache_lock_args,
9274 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
9275 { 2, Iclass_xt_iclass_sdct_args,
9276 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
9277 { 2, Iclass_xt_iclass_ldct_args,
9278 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
9279 { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
9280 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
9281 { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
9282 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
9283 { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
9284 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
9285 { 1, Iclass_xt_iclass_rsr_rasid_args,
9286 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
9287 { 1, Iclass_xt_iclass_wsr_rasid_args,
9288 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
9289 { 1, Iclass_xt_iclass_xsr_rasid_args,
9290 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
9291 { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
9292 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
9293 { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
9294 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
9295 { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
9296 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
9297 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
9298 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
9299 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
9300 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
9301 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
9302 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
9303 { 1, Iclass_xt_iclass_idtlb_args,
9304 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
9305 { 2, Iclass_xt_iclass_rdtlb_args,
9306 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
9307 { 2, Iclass_xt_iclass_wdtlb_args,
9308 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
9309 { 1, Iclass_xt_iclass_iitlb_args,
9310 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
9311 { 2, Iclass_xt_iclass_ritlb_args,
9312 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
9313 { 2, Iclass_xt_iclass_witlb_args,
9314 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
9315 { 0, 0 /* xt_iclass_ldpte */,
9316 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
9317 { 0, 0 /* xt_iclass_hwwitlba */,
9318 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
9319 { 0, 0 /* xt_iclass_hwwdtlba */,
9320 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
9321 { 1, Iclass_xt_iclass_rsr_cpenable_args,
9322 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
9323 { 1, Iclass_xt_iclass_wsr_cpenable_args,
9324 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
9325 { 1, Iclass_xt_iclass_xsr_cpenable_args,
9326 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
9327 { 3, Iclass_xt_iclass_clamp_args,
9329 { 3, Iclass_xt_iclass_minmax_args,
9331 { 2, Iclass_xt_iclass_nsa_args,
9333 { 3, Iclass_xt_iclass_sx_args,
9335 { 3, Iclass_xt_iclass_l32ai_args,
9337 { 3, Iclass_xt_iclass_s32ri_args,
9339 { 3, Iclass_xt_iclass_s32c1i_args,
9340 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
9341 { 1, Iclass_xt_iclass_rsr_scompare1_args,
9342 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
9343 { 1, Iclass_xt_iclass_wsr_scompare1_args,
9344 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
9345 { 1, Iclass_xt_iclass_xsr_scompare1_args,
9346 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
9347 { 3, Iclass_xt_iclass_div_args,
9349 { 3, Iclass_xt_mul32_args,
9351 { 1, Iclass_rur_fcr_args,
9352 9, Iclass_rur_fcr_stateArgs, 0, 0 },
9353 { 1, Iclass_wur_fcr_args,
9354 9, Iclass_wur_fcr_stateArgs, 0, 0 },
9355 { 1, Iclass_rur_fsr_args,
9356 8, Iclass_rur_fsr_stateArgs, 0, 0 },
9357 { 1, Iclass_wur_fsr_args,
9358 8, Iclass_wur_fsr_stateArgs, 0, 0 },
9359 { 3, Iclass_fp_args,
9360 2, Iclass_fp_stateArgs, 0, 0 },
9361 { 3, Iclass_fp_mac_args,
9362 2, Iclass_fp_mac_stateArgs, 0, 0 },
9363 { 3, Iclass_fp_cmov_args,
9364 1, Iclass_fp_cmov_stateArgs, 0, 0 },
9365 { 3, Iclass_fp_mov_args,
9366 1, Iclass_fp_mov_stateArgs, 0, 0 },
9367 { 2, Iclass_fp_mov2_args,
9368 1, Iclass_fp_mov2_stateArgs, 0, 0 },
9369 { 3, Iclass_fp_cmp_args,
9370 1, Iclass_fp_cmp_stateArgs, 0, 0 },
9371 { 3, Iclass_fp_float_args,
9372 2, Iclass_fp_float_stateArgs, 0, 0 },
9373 { 3, Iclass_fp_int_args,
9374 1, Iclass_fp_int_stateArgs, 0, 0 },
9375 { 2, Iclass_fp_rfr_args,
9376 1, Iclass_fp_rfr_stateArgs, 0, 0 },
9377 { 2, Iclass_fp_wfr_args,
9378 1, Iclass_fp_wfr_stateArgs, 0, 0 },
9379 { 3, Iclass_fp_lsi_args,
9380 1, Iclass_fp_lsi_stateArgs, 0, 0 },
9381 { 3, Iclass_fp_lsiu_args,
9382 1, Iclass_fp_lsiu_stateArgs, 0, 0 },
9383 { 3, Iclass_fp_lsx_args,
9384 1, Iclass_fp_lsx_stateArgs, 0, 0 },
9385 { 3, Iclass_fp_lsxu_args,
9386 1, Iclass_fp_lsxu_stateArgs, 0, 0 },
9387 { 3, Iclass_fp_ssi_args,
9388 1, Iclass_fp_ssi_stateArgs, 0, 0 },
9389 { 3, Iclass_fp_ssiu_args,
9390 1, Iclass_fp_ssiu_stateArgs, 0, 0 },
9391 { 3, Iclass_fp_ssx_args,
9392 1, Iclass_fp_ssx_stateArgs, 0, 0 },
9393 { 3, Iclass_fp_ssxu_args,
9394 1, Iclass_fp_ssxu_stateArgs, 0, 0 },
9395 { 2, Iclass_xt_iclass_wb18_0_args,
9397 { 3, Iclass_xt_iclass_wb18_1_args,
9399 { 3, Iclass_xt_iclass_wb18_2_args,
9401 { 3, Iclass_xt_iclass_wb18_3_args,
9403 { 3, Iclass_xt_iclass_wb18_4_args,
9408 /* Opcode encodings. */
9411 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9413 slotbuf[0] = 0x2080;
9417 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
9419 slotbuf[0] = 0x3000;
9423 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
9425 slotbuf[0] = 0x3200;
9429 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9431 slotbuf[0] = 0x5000;
9435 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9437 slotbuf[0] = 0x5100;
9441 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
9447 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9453 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9459 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
9465 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9471 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9477 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
9483 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
9485 slotbuf[0] = 0x1000;
9489 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9491 slotbuf[0] = 0x408000;
9495 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9501 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9503 slotbuf[0] = 0xf01d;
9507 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
9509 slotbuf[0] = 0x3400;
9513 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
9515 slotbuf[0] = 0x3500;
9519 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
9521 slotbuf[0] = 0x90000;
9525 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
9527 slotbuf[0] = 0x490000;
9531 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9533 slotbuf[0] = 0x34800;
9537 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9539 slotbuf[0] = 0x134800;
9543 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9545 slotbuf[0] = 0x614800;
9549 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9551 slotbuf[0] = 0x34900;
9555 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9557 slotbuf[0] = 0x134900;
9561 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9563 slotbuf[0] = 0x614900;
9567 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9573 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9579 Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9581 slotbuf[0] = 0x3000;
9585 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9591 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9597 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9599 slotbuf[0] = 0xf06d;
9603 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9609 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9615 Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9617 slotbuf[0] = 0x6000;
9621 Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9623 slotbuf[0] = 0xa3000;
9627 Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9629 slotbuf[0] = 0xc080;
9633 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9639 Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9641 slotbuf[0] = 0xc000;
9645 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9647 slotbuf[0] = 0xf03d;
9651 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9653 slotbuf[0] = 0xf00d;
9657 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9663 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
9665 slotbuf[0] = 0xe30e70;
9669 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
9671 slotbuf[0] = 0xf3e700;
9675 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9677 slotbuf[0] = 0xc002;
9681 Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9683 slotbuf[0] = 0x60000;
9687 Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9689 slotbuf[0] = 0x200c00;
9693 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9695 slotbuf[0] = 0xd002;
9699 Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9701 slotbuf[0] = 0x70000;
9705 Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9707 slotbuf[0] = 0x200d00;
9711 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
9713 slotbuf[0] = 0x800000;
9717 Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9719 slotbuf[0] = 0x92000;
9723 Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9725 slotbuf[0] = 0x2000;
9729 Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9731 slotbuf[0] = 0x80000;
9735 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
9737 slotbuf[0] = 0xc00000;
9741 Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9743 slotbuf[0] = 0xa8000;
9747 Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9749 slotbuf[0] = 0xa000;
9753 Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9755 slotbuf[0] = 0xc0000;
9759 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
9761 slotbuf[0] = 0x900000;
9765 Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9767 slotbuf[0] = 0x94000;
9771 Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9773 slotbuf[0] = 0x4000;
9777 Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9779 slotbuf[0] = 0x90000;
9783 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9785 slotbuf[0] = 0xa00000;
9789 Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9791 slotbuf[0] = 0x98000;
9795 Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9797 slotbuf[0] = 0x5000;
9801 Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9803 slotbuf[0] = 0xa0000;
9807 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9809 slotbuf[0] = 0xb00000;
9813 Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9815 slotbuf[0] = 0x93000;
9819 Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9821 slotbuf[0] = 0xb0000;
9825 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
9827 slotbuf[0] = 0xd00000;
9831 Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9833 slotbuf[0] = 0xd0000;
9837 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9839 slotbuf[0] = 0xe00000;
9843 Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9845 slotbuf[0] = 0xe0000;
9849 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9851 slotbuf[0] = 0xf00000;
9855 Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9857 slotbuf[0] = 0xf0000;
9861 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
9863 slotbuf[0] = 0x100000;
9867 Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9869 slotbuf[0] = 0x95000;
9873 Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9875 slotbuf[0] = 0x6000;
9879 Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9881 slotbuf[0] = 0x10000;
9885 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
9887 slotbuf[0] = 0x200000;
9891 Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9893 slotbuf[0] = 0x9e000;
9897 Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9899 slotbuf[0] = 0x7000;
9903 Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9905 slotbuf[0] = 0x20000;
9909 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
9911 slotbuf[0] = 0x300000;
9915 Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9917 slotbuf[0] = 0xb0000;
9921 Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9923 slotbuf[0] = 0xb000;
9927 Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9929 slotbuf[0] = 0x30000;
9933 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9939 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
9945 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
9951 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
9957 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
9959 slotbuf[0] = 0x6007;
9963 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9965 slotbuf[0] = 0xe007;
9969 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9975 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9981 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
9983 slotbuf[0] = 0x1007;
9987 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
9989 slotbuf[0] = 0x9007;
9993 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
9995 slotbuf[0] = 0xa007;
9999 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
10001 slotbuf[0] = 0x2007;
10005 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
10007 slotbuf[0] = 0xb007;
10011 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
10013 slotbuf[0] = 0x3007;
10017 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
10019 slotbuf[0] = 0x8007;
10023 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
10029 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
10031 slotbuf[0] = 0x4007;
10035 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
10037 slotbuf[0] = 0xc007;
10041 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
10043 slotbuf[0] = 0x5007;
10047 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
10049 slotbuf[0] = 0xd007;
10053 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10059 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10065 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10071 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10077 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10083 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10089 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10091 slotbuf[0] = 0x40000;
10095 Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10097 slotbuf[0] = 0x40000;
10101 Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10103 slotbuf[0] = 0x4000;
10107 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
10113 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
10119 Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10121 slotbuf[0] = 0xc0000;
10125 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
10131 Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10133 slotbuf[0] = 0xa3010;
10137 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10139 slotbuf[0] = 0x1002;
10143 Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10145 slotbuf[0] = 0x200100;
10149 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
10151 slotbuf[0] = 0x9002;
10155 Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10157 slotbuf[0] = 0x200900;
10161 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10163 slotbuf[0] = 0x2002;
10167 Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10169 slotbuf[0] = 0x200200;
10173 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
10179 Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10181 slotbuf[0] = 0x100000;
10185 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10191 Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10193 slotbuf[0] = 0x200000;
10197 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
10199 slotbuf[0] = 0x8076;
10203 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10205 slotbuf[0] = 0x9076;
10209 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10211 slotbuf[0] = 0xa076;
10215 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
10217 slotbuf[0] = 0xa002;
10221 Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10223 slotbuf[0] = 0x80000;
10227 Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10229 slotbuf[0] = 0x200a00;
10233 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10235 slotbuf[0] = 0x830000;
10239 Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10241 slotbuf[0] = 0x96000;
10245 Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10247 slotbuf[0] = 0x83000;
10251 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10253 slotbuf[0] = 0x930000;
10257 Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10259 slotbuf[0] = 0x9a000;
10263 Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10265 slotbuf[0] = 0x93000;
10269 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10271 slotbuf[0] = 0xa30000;
10275 Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10277 slotbuf[0] = 0x99000;
10281 Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10283 slotbuf[0] = 0xa3000;
10287 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10289 slotbuf[0] = 0xb30000;
10293 Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10295 slotbuf[0] = 0x97000;
10299 Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10301 slotbuf[0] = 0xb3000;
10305 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10307 slotbuf[0] = 0x600000;
10311 Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10313 slotbuf[0] = 0xa5000;
10317 Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10319 slotbuf[0] = 0xd100;
10323 Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10325 slotbuf[0] = 0x60000;
10329 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
10331 slotbuf[0] = 0x600100;
10335 Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10337 slotbuf[0] = 0xd000;
10341 Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10343 slotbuf[0] = 0x60010;
10347 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
10349 slotbuf[0] = 0x20f0;
10353 Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10355 slotbuf[0] = 0xa3040;
10359 Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10361 slotbuf[0] = 0xc090;
10365 Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
10367 slotbuf[0] = 0xc8000000;
10372 Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10374 slotbuf[0] = 0x20f;
10378 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
10384 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10386 slotbuf[0] = 0x5002;
10390 Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10392 slotbuf[0] = 0x200500;
10396 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10398 slotbuf[0] = 0x6002;
10402 Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10404 slotbuf[0] = 0x200600;
10408 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10410 slotbuf[0] = 0x4002;
10414 Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10416 slotbuf[0] = 0x200400;
10420 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
10422 slotbuf[0] = 0x400000;
10426 Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10428 slotbuf[0] = 0x40000;
10432 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10434 slotbuf[0] = 0x401000;
10438 Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10440 slotbuf[0] = 0xa3020;
10444 Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10446 slotbuf[0] = 0x40100;
10450 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
10452 slotbuf[0] = 0x402000;
10456 Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10458 slotbuf[0] = 0x40200;
10462 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
10464 slotbuf[0] = 0x403000;
10468 Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10470 slotbuf[0] = 0x40300;
10474 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
10476 slotbuf[0] = 0x404000;
10480 Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10482 slotbuf[0] = 0x40400;
10486 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
10488 slotbuf[0] = 0xa10000;
10492 Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10494 slotbuf[0] = 0xa6000;
10498 Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10500 slotbuf[0] = 0xa1000;
10504 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
10506 slotbuf[0] = 0x810000;
10510 Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10512 slotbuf[0] = 0xa2000;
10516 Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10518 slotbuf[0] = 0x81000;
10522 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10524 slotbuf[0] = 0x910000;
10528 Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10530 slotbuf[0] = 0xa5200;
10534 Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10536 slotbuf[0] = 0xd400;
10540 Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10542 slotbuf[0] = 0x91000;
10546 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
10548 slotbuf[0] = 0xb10000;
10552 Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10554 slotbuf[0] = 0xa5100;
10558 Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10560 slotbuf[0] = 0xd200;
10564 Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10566 slotbuf[0] = 0xb1000;
10570 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
10572 slotbuf[0] = 0x10000;
10576 Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10578 slotbuf[0] = 0x90000;
10582 Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10584 slotbuf[0] = 0x1000;
10588 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
10590 slotbuf[0] = 0x210000;
10594 Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10596 slotbuf[0] = 0xa0000;
10600 Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10602 slotbuf[0] = 0xe000;
10606 Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10608 slotbuf[0] = 0x21000;
10612 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
10614 slotbuf[0] = 0x410000;
10618 Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10620 slotbuf[0] = 0xa4000;
10624 Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10626 slotbuf[0] = 0x9000;
10630 Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10632 slotbuf[0] = 0x41000;
10636 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
10638 slotbuf[0] = 0x20c0;
10642 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
10644 slotbuf[0] = 0x20d0;
10648 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10650 slotbuf[0] = 0x2000;
10654 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10656 slotbuf[0] = 0x2010;
10660 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10662 slotbuf[0] = 0x2020;
10666 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10668 slotbuf[0] = 0x2030;
10672 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
10674 slotbuf[0] = 0x6000;
10678 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10680 slotbuf[0] = 0x30100;
10684 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10686 slotbuf[0] = 0x130100;
10690 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10692 slotbuf[0] = 0x610100;
10696 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10698 slotbuf[0] = 0x30200;
10702 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10704 slotbuf[0] = 0x130200;
10708 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10710 slotbuf[0] = 0x610200;
10714 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10716 slotbuf[0] = 0x30000;
10720 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10722 slotbuf[0] = 0x130000;
10726 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10728 slotbuf[0] = 0x610000;
10732 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10734 slotbuf[0] = 0x30300;
10738 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10740 slotbuf[0] = 0x130300;
10744 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10746 slotbuf[0] = 0x610300;
10750 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10752 slotbuf[0] = 0x30500;
10756 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10758 slotbuf[0] = 0x130500;
10762 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10764 slotbuf[0] = 0x610500;
10768 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
10770 slotbuf[0] = 0x3b000;
10774 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
10776 slotbuf[0] = 0x3d000;
10780 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10782 slotbuf[0] = 0x3e600;
10786 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10788 slotbuf[0] = 0x13e600;
10792 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10794 slotbuf[0] = 0x61e600;
10798 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10800 slotbuf[0] = 0x3b100;
10804 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10806 slotbuf[0] = 0x13b100;
10810 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10812 slotbuf[0] = 0x61b100;
10816 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10818 slotbuf[0] = 0x3d100;
10822 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10824 slotbuf[0] = 0x13d100;
10828 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10830 slotbuf[0] = 0x61d100;
10834 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10836 slotbuf[0] = 0x3b200;
10840 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10842 slotbuf[0] = 0x13b200;
10846 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10848 slotbuf[0] = 0x61b200;
10852 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10854 slotbuf[0] = 0x3d200;
10858 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10860 slotbuf[0] = 0x13d200;
10864 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10866 slotbuf[0] = 0x61d200;
10870 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10872 slotbuf[0] = 0x3b300;
10876 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10878 slotbuf[0] = 0x13b300;
10882 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10884 slotbuf[0] = 0x61b300;
10888 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10890 slotbuf[0] = 0x3d300;
10894 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10896 slotbuf[0] = 0x13d300;
10900 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10902 slotbuf[0] = 0x61d300;
10906 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10908 slotbuf[0] = 0x3b400;
10912 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10914 slotbuf[0] = 0x13b400;
10918 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10920 slotbuf[0] = 0x61b400;
10924 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10926 slotbuf[0] = 0x3d400;
10930 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10932 slotbuf[0] = 0x13d400;
10936 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10938 slotbuf[0] = 0x61d400;
10942 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10944 slotbuf[0] = 0x3b500;
10948 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10950 slotbuf[0] = 0x13b500;
10954 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10956 slotbuf[0] = 0x61b500;
10960 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10962 slotbuf[0] = 0x3d500;
10966 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10968 slotbuf[0] = 0x13d500;
10972 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10974 slotbuf[0] = 0x61d500;
10978 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10980 slotbuf[0] = 0x3b600;
10984 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10986 slotbuf[0] = 0x13b600;
10990 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10992 slotbuf[0] = 0x61b600;
10996 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10998 slotbuf[0] = 0x3d600;
11002 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11004 slotbuf[0] = 0x13d600;
11008 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11010 slotbuf[0] = 0x61d600;
11014 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11016 slotbuf[0] = 0x3b700;
11020 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11022 slotbuf[0] = 0x13b700;
11026 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11028 slotbuf[0] = 0x61b700;
11032 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11034 slotbuf[0] = 0x3d700;
11038 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11040 slotbuf[0] = 0x13d700;
11044 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11046 slotbuf[0] = 0x61d700;
11050 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11052 slotbuf[0] = 0x3c200;
11056 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11058 slotbuf[0] = 0x13c200;
11062 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11064 slotbuf[0] = 0x61c200;
11068 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11070 slotbuf[0] = 0x3c300;
11074 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11076 slotbuf[0] = 0x13c300;
11080 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11082 slotbuf[0] = 0x61c300;
11086 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11088 slotbuf[0] = 0x3c400;
11092 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11094 slotbuf[0] = 0x13c400;
11098 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11100 slotbuf[0] = 0x61c400;
11104 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11106 slotbuf[0] = 0x3c500;
11110 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11112 slotbuf[0] = 0x13c500;
11116 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11118 slotbuf[0] = 0x61c500;
11122 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11124 slotbuf[0] = 0x3c600;
11128 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11130 slotbuf[0] = 0x13c600;
11134 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11136 slotbuf[0] = 0x61c600;
11140 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11142 slotbuf[0] = 0x3c700;
11146 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11148 slotbuf[0] = 0x13c700;
11152 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11154 slotbuf[0] = 0x61c700;
11158 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11160 slotbuf[0] = 0x3ee00;
11164 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11166 slotbuf[0] = 0x13ee00;
11170 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11172 slotbuf[0] = 0x61ee00;
11176 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11178 slotbuf[0] = 0x3c000;
11182 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11184 slotbuf[0] = 0x13c000;
11188 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11190 slotbuf[0] = 0x61c000;
11194 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11196 slotbuf[0] = 0x3e800;
11200 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11202 slotbuf[0] = 0x13e800;
11206 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11208 slotbuf[0] = 0x61e800;
11212 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11214 slotbuf[0] = 0x3f400;
11218 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11220 slotbuf[0] = 0x13f400;
11224 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11226 slotbuf[0] = 0x61f400;
11230 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11232 slotbuf[0] = 0x3f500;
11236 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11238 slotbuf[0] = 0x13f500;
11242 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11244 slotbuf[0] = 0x61f500;
11248 Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11250 slotbuf[0] = 0x3f600;
11254 Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11256 slotbuf[0] = 0x13f600;
11260 Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11262 slotbuf[0] = 0x61f600;
11266 Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11268 slotbuf[0] = 0x3f700;
11272 Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11274 slotbuf[0] = 0x13f700;
11278 Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11280 slotbuf[0] = 0x61f700;
11284 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
11286 slotbuf[0] = 0x3eb00;
11290 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11292 slotbuf[0] = 0x3e700;
11296 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11298 slotbuf[0] = 0x13e700;
11302 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11304 slotbuf[0] = 0x61e700;
11308 Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11310 slotbuf[0] = 0x740004;
11314 Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11316 slotbuf[0] = 0x750004;
11320 Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11322 slotbuf[0] = 0x760004;
11326 Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11328 slotbuf[0] = 0x770004;
11332 Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11334 slotbuf[0] = 0x700004;
11338 Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11340 slotbuf[0] = 0x710004;
11344 Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11346 slotbuf[0] = 0x720004;
11350 Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11352 slotbuf[0] = 0x730004;
11356 Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11358 slotbuf[0] = 0x340004;
11362 Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11364 slotbuf[0] = 0x350004;
11368 Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11370 slotbuf[0] = 0x360004;
11374 Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11376 slotbuf[0] = 0x370004;
11380 Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11382 slotbuf[0] = 0x640004;
11386 Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11388 slotbuf[0] = 0x650004;
11392 Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11394 slotbuf[0] = 0x660004;
11398 Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11400 slotbuf[0] = 0x670004;
11404 Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11406 slotbuf[0] = 0x240004;
11410 Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11412 slotbuf[0] = 0x250004;
11416 Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11418 slotbuf[0] = 0x260004;
11422 Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11424 slotbuf[0] = 0x270004;
11428 Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11430 slotbuf[0] = 0x780004;
11434 Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11436 slotbuf[0] = 0x790004;
11440 Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11442 slotbuf[0] = 0x7a0004;
11446 Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11448 slotbuf[0] = 0x7b0004;
11452 Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11454 slotbuf[0] = 0x7c0004;
11458 Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11460 slotbuf[0] = 0x7d0004;
11464 Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11466 slotbuf[0] = 0x7e0004;
11470 Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11472 slotbuf[0] = 0x7f0004;
11476 Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11478 slotbuf[0] = 0x380004;
11482 Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11484 slotbuf[0] = 0x390004;
11488 Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11490 slotbuf[0] = 0x3a0004;
11494 Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11496 slotbuf[0] = 0x3b0004;
11500 Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11502 slotbuf[0] = 0x3c0004;
11506 Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11508 slotbuf[0] = 0x3d0004;
11512 Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11514 slotbuf[0] = 0x3e0004;
11518 Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11520 slotbuf[0] = 0x3f0004;
11524 Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11526 slotbuf[0] = 0x680004;
11530 Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11532 slotbuf[0] = 0x690004;
11536 Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11538 slotbuf[0] = 0x6a0004;
11542 Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11544 slotbuf[0] = 0x6b0004;
11548 Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11550 slotbuf[0] = 0x6c0004;
11554 Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11556 slotbuf[0] = 0x6d0004;
11560 Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11562 slotbuf[0] = 0x6e0004;
11566 Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11568 slotbuf[0] = 0x6f0004;
11572 Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11574 slotbuf[0] = 0x280004;
11578 Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11580 slotbuf[0] = 0x290004;
11584 Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11586 slotbuf[0] = 0x2a0004;
11590 Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11592 slotbuf[0] = 0x2b0004;
11596 Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11598 slotbuf[0] = 0x2c0004;
11602 Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11604 slotbuf[0] = 0x2d0004;
11608 Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11610 slotbuf[0] = 0x2e0004;
11614 Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11616 slotbuf[0] = 0x2f0004;
11620 Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11622 slotbuf[0] = 0x580004;
11626 Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11628 slotbuf[0] = 0x480004;
11632 Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11634 slotbuf[0] = 0x590004;
11638 Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11640 slotbuf[0] = 0x490004;
11644 Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11646 slotbuf[0] = 0x5a0004;
11650 Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11652 slotbuf[0] = 0x4a0004;
11656 Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11658 slotbuf[0] = 0x5b0004;
11662 Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11664 slotbuf[0] = 0x4b0004;
11668 Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11670 slotbuf[0] = 0x180004;
11674 Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11676 slotbuf[0] = 0x80004;
11680 Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11682 slotbuf[0] = 0x190004;
11686 Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11688 slotbuf[0] = 0x90004;
11692 Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11694 slotbuf[0] = 0x1a0004;
11698 Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11700 slotbuf[0] = 0xa0004;
11704 Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11706 slotbuf[0] = 0x1b0004;
11710 Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11712 slotbuf[0] = 0xb0004;
11716 Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
11718 slotbuf[0] = 0x900004;
11722 Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11724 slotbuf[0] = 0x800004;
11728 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
11730 slotbuf[0] = 0xc10000;
11734 Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
11736 slotbuf[0] = 0x9b000;
11740 Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
11742 slotbuf[0] = 0xc1000;
11746 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
11748 slotbuf[0] = 0xd10000;
11752 Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
11754 slotbuf[0] = 0x9c000;
11758 Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
11760 slotbuf[0] = 0xd1000;
11764 Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11766 slotbuf[0] = 0x32000;
11770 Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11772 slotbuf[0] = 0x132000;
11776 Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11778 slotbuf[0] = 0x612000;
11782 Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11784 slotbuf[0] = 0x32100;
11788 Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11790 slotbuf[0] = 0x132100;
11794 Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11796 slotbuf[0] = 0x612100;
11800 Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11802 slotbuf[0] = 0x32200;
11806 Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11808 slotbuf[0] = 0x132200;
11812 Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11814 slotbuf[0] = 0x612200;
11818 Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11820 slotbuf[0] = 0x32300;
11824 Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11826 slotbuf[0] = 0x132300;
11830 Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11832 slotbuf[0] = 0x612300;
11836 Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11838 slotbuf[0] = 0x31000;
11842 Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11844 slotbuf[0] = 0x131000;
11848 Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
11850 slotbuf[0] = 0x611000;
11854 Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11856 slotbuf[0] = 0x31100;
11860 Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11862 slotbuf[0] = 0x131100;
11866 Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11868 slotbuf[0] = 0x611100;
11872 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
11874 slotbuf[0] = 0x3010;
11878 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
11880 slotbuf[0] = 0x7000;
11884 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
11886 slotbuf[0] = 0x3e200;
11890 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
11892 slotbuf[0] = 0x13e200;
11896 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
11898 slotbuf[0] = 0x13e300;
11902 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11904 slotbuf[0] = 0x3e400;
11908 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11910 slotbuf[0] = 0x13e400;
11914 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
11916 slotbuf[0] = 0x61e400;
11920 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
11922 slotbuf[0] = 0x4000;
11926 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
11928 slotbuf[0] = 0xf02d;
11932 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11934 slotbuf[0] = 0x39000;
11938 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11940 slotbuf[0] = 0x139000;
11944 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11946 slotbuf[0] = 0x619000;
11950 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11952 slotbuf[0] = 0x3a000;
11956 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11958 slotbuf[0] = 0x13a000;
11962 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11964 slotbuf[0] = 0x61a000;
11968 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11970 slotbuf[0] = 0x39100;
11974 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11976 slotbuf[0] = 0x139100;
11980 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11982 slotbuf[0] = 0x619100;
11986 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11988 slotbuf[0] = 0x3a100;
11992 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11994 slotbuf[0] = 0x13a100;
11998 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12000 slotbuf[0] = 0x61a100;
12004 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12006 slotbuf[0] = 0x38000;
12010 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12012 slotbuf[0] = 0x138000;
12016 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12018 slotbuf[0] = 0x618000;
12022 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12024 slotbuf[0] = 0x38100;
12028 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12030 slotbuf[0] = 0x138100;
12034 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12036 slotbuf[0] = 0x618100;
12040 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12042 slotbuf[0] = 0x36000;
12046 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12048 slotbuf[0] = 0x136000;
12052 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12054 slotbuf[0] = 0x616000;
12058 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
12060 slotbuf[0] = 0x3e900;
12064 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
12066 slotbuf[0] = 0x13e900;
12070 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
12072 slotbuf[0] = 0x61e900;
12076 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12078 slotbuf[0] = 0x3ec00;
12082 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12084 slotbuf[0] = 0x13ec00;
12088 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12090 slotbuf[0] = 0x61ec00;
12094 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12096 slotbuf[0] = 0x3ed00;
12100 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12102 slotbuf[0] = 0x13ed00;
12106 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12108 slotbuf[0] = 0x61ed00;
12112 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12114 slotbuf[0] = 0x36800;
12118 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12120 slotbuf[0] = 0x136800;
12124 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12126 slotbuf[0] = 0x616800;
12130 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12132 slotbuf[0] = 0xf1e000;
12136 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
12138 slotbuf[0] = 0xf1e010;
12142 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12144 slotbuf[0] = 0x135900;
12148 Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12150 slotbuf[0] = 0x20000;
12154 Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
12156 slotbuf[0] = 0x120000;
12160 Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12162 slotbuf[0] = 0x220000;
12166 Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
12168 slotbuf[0] = 0x320000;
12172 Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12174 slotbuf[0] = 0x420000;
12178 Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12180 slotbuf[0] = 0x8000;
12184 Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12186 slotbuf[0] = 0x9000;
12190 Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12192 slotbuf[0] = 0xa000;
12196 Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12198 slotbuf[0] = 0xb000;
12202 Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
12208 Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
12210 slotbuf[0] = 0x1076;
12214 Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
12216 slotbuf[0] = 0xc30000;
12220 Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
12222 slotbuf[0] = 0xd30000;
12226 Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
12228 slotbuf[0] = 0x30400;
12232 Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
12234 slotbuf[0] = 0x130400;
12238 Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
12240 slotbuf[0] = 0x610400;
12244 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12246 slotbuf[0] = 0x3ea00;
12250 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12252 slotbuf[0] = 0x13ea00;
12256 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12258 slotbuf[0] = 0x61ea00;
12262 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12264 slotbuf[0] = 0x3f000;
12268 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12270 slotbuf[0] = 0x13f000;
12274 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12276 slotbuf[0] = 0x61f000;
12280 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12282 slotbuf[0] = 0x3f100;
12286 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12288 slotbuf[0] = 0x13f100;
12292 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12294 slotbuf[0] = 0x61f100;
12298 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12300 slotbuf[0] = 0x3f200;
12304 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12306 slotbuf[0] = 0x13f200;
12310 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12312 slotbuf[0] = 0x61f200;
12316 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
12318 slotbuf[0] = 0x70c2;
12322 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12324 slotbuf[0] = 0x70e2;
12328 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
12330 slotbuf[0] = 0x70d2;
12334 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12336 slotbuf[0] = 0x270d2;
12340 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12342 slotbuf[0] = 0x370d2;
12346 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
12348 slotbuf[0] = 0x70f2;
12352 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
12354 slotbuf[0] = 0xf10000;
12358 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
12360 slotbuf[0] = 0xf12000;
12364 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
12366 slotbuf[0] = 0xf11000;
12370 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
12372 slotbuf[0] = 0xf13000;
12376 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12378 slotbuf[0] = 0x7042;
12382 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12384 slotbuf[0] = 0x7052;
12388 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12390 slotbuf[0] = 0x47082;
12394 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12396 slotbuf[0] = 0x57082;
12400 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12402 slotbuf[0] = 0x7062;
12406 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
12408 slotbuf[0] = 0x7072;
12412 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12414 slotbuf[0] = 0x7002;
12418 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
12420 slotbuf[0] = 0x7012;
12424 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
12426 slotbuf[0] = 0x7022;
12430 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12432 slotbuf[0] = 0x7032;
12436 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
12438 slotbuf[0] = 0x7082;
12442 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12444 slotbuf[0] = 0x27082;
12448 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12450 slotbuf[0] = 0x37082;
12454 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
12456 slotbuf[0] = 0xf19000;
12460 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
12462 slotbuf[0] = 0xf18000;
12466 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12468 slotbuf[0] = 0x135300;
12472 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12474 slotbuf[0] = 0x35300;
12478 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12480 slotbuf[0] = 0x615300;
12484 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12486 slotbuf[0] = 0x35a00;
12490 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12492 slotbuf[0] = 0x135a00;
12496 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12498 slotbuf[0] = 0x615a00;
12502 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12504 slotbuf[0] = 0x35b00;
12508 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12510 slotbuf[0] = 0x135b00;
12514 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12516 slotbuf[0] = 0x615b00;
12520 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12522 slotbuf[0] = 0x35c00;
12526 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12528 slotbuf[0] = 0x135c00;
12532 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12534 slotbuf[0] = 0x615c00;
12538 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12540 slotbuf[0] = 0x50c000;
12544 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12546 slotbuf[0] = 0x50d000;
12550 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12552 slotbuf[0] = 0x50b000;
12556 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12558 slotbuf[0] = 0x50f000;
12562 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12564 slotbuf[0] = 0x50e000;
12568 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12570 slotbuf[0] = 0x504000;
12574 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12576 slotbuf[0] = 0x505000;
12580 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12582 slotbuf[0] = 0x503000;
12586 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12588 slotbuf[0] = 0x507000;
12592 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12594 slotbuf[0] = 0x506000;
12598 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
12600 slotbuf[0] = 0xf1f000;
12604 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
12606 slotbuf[0] = 0x501000;
12610 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
12612 slotbuf[0] = 0x509000;
12616 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12618 slotbuf[0] = 0x3e000;
12622 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12624 slotbuf[0] = 0x13e000;
12628 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
12630 slotbuf[0] = 0x61e000;
12634 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
12636 slotbuf[0] = 0x330000;
12640 Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12642 slotbuf[0] = 0x33000;
12646 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
12648 slotbuf[0] = 0x430000;
12652 Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12654 slotbuf[0] = 0x43000;
12658 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
12660 slotbuf[0] = 0x530000;
12664 Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12666 slotbuf[0] = 0x53000;
12670 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12672 slotbuf[0] = 0x630000;
12676 Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12678 slotbuf[0] = 0x63000;
12682 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12684 slotbuf[0] = 0x730000;
12688 Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12690 slotbuf[0] = 0x73000;
12694 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
12696 slotbuf[0] = 0x40e000;
12700 Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12702 slotbuf[0] = 0x40e00;
12706 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
12708 slotbuf[0] = 0x40f000;
12712 Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12714 slotbuf[0] = 0x40f00;
12718 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
12720 slotbuf[0] = 0x230000;
12724 Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12726 slotbuf[0] = 0x9f000;
12730 Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12732 slotbuf[0] = 0x8000;
12736 Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12738 slotbuf[0] = 0x23000;
12742 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
12744 slotbuf[0] = 0xb002;
12748 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
12750 slotbuf[0] = 0xf002;
12754 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12756 slotbuf[0] = 0xe002;
12760 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12762 slotbuf[0] = 0x30c00;
12766 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12768 slotbuf[0] = 0x130c00;
12772 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
12774 slotbuf[0] = 0x610c00;
12778 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
12780 slotbuf[0] = 0xc20000;
12784 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
12786 slotbuf[0] = 0xd20000;
12790 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12792 slotbuf[0] = 0xe20000;
12796 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
12798 slotbuf[0] = 0xf20000;
12802 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
12804 slotbuf[0] = 0x820000;
12808 Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12810 slotbuf[0] = 0x9d000;
12814 Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12816 slotbuf[0] = 0x82000;
12820 Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
12822 slotbuf[0] = 0xa20000;
12826 Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
12828 slotbuf[0] = 0xb20000;
12832 Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12834 slotbuf[0] = 0xe30e80;
12838 Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12840 slotbuf[0] = 0xf3e800;
12844 Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12846 slotbuf[0] = 0xe30e90;
12850 Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12852 slotbuf[0] = 0xf3e900;
12856 Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12858 slotbuf[0] = 0xa0000;
12862 Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12864 slotbuf[0] = 0x1a0000;
12868 Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12870 slotbuf[0] = 0x2a0000;
12874 Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12876 slotbuf[0] = 0x4a0000;
12880 Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12882 slotbuf[0] = 0x5a0000;
12886 Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12888 slotbuf[0] = 0xcb0000;
12892 Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12894 slotbuf[0] = 0xdb0000;
12898 Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12900 slotbuf[0] = 0x8b0000;
12904 Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12906 slotbuf[0] = 0x9b0000;
12910 Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12912 slotbuf[0] = 0xab0000;
12916 Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12918 slotbuf[0] = 0xbb0000;
12922 Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12924 slotbuf[0] = 0xfa0010;
12928 Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12930 slotbuf[0] = 0xfa0000;
12934 Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12936 slotbuf[0] = 0xfa0060;
12940 Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12942 slotbuf[0] = 0x1b0000;
12946 Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12948 slotbuf[0] = 0x2b0000;
12952 Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12954 slotbuf[0] = 0x3b0000;
12958 Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12960 slotbuf[0] = 0x4b0000;
12964 Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12966 slotbuf[0] = 0x5b0000;
12970 Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12972 slotbuf[0] = 0x6b0000;
12976 Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12978 slotbuf[0] = 0x7b0000;
12982 Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12984 slotbuf[0] = 0xca0000;
12988 Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12990 slotbuf[0] = 0xda0000;
12994 Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
12996 slotbuf[0] = 0x8a0000;
13000 Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
13002 slotbuf[0] = 0xba0000;
13006 Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
13008 slotbuf[0] = 0xaa0000;
13012 Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
13014 slotbuf[0] = 0x9a0000;
13018 Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
13020 slotbuf[0] = 0xea0000;
13024 Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13026 slotbuf[0] = 0xfa0040;
13030 Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13032 slotbuf[0] = 0xfa0050;
13036 Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
13042 Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
13044 slotbuf[0] = 0x8003;
13048 Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
13050 slotbuf[0] = 0x80000;
13054 Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
13056 slotbuf[0] = 0x180000;
13060 Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
13062 slotbuf[0] = 0x4003;
13066 Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
13068 slotbuf[0] = 0xc003;
13072 Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
13074 slotbuf[0] = 0x480000;
13078 Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
13080 slotbuf[0] = 0x580000;
13084 Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13086 slotbuf[0] = 0xa8000000;
13091 Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13093 slotbuf[0] = 0xc0000000;
13098 Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13100 slotbuf[0] = 0xb0000000;
13105 Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13107 slotbuf[0] = 0xb8000000;
13112 Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13114 slotbuf[0] = 0x40000000;
13119 Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13121 slotbuf[0] = 0x98000000;
13126 Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13128 slotbuf[0] = 0x50000000;
13133 Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13135 slotbuf[0] = 0x70000000;
13140 Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13142 slotbuf[0] = 0x60000000;
13147 Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13149 slotbuf[0] = 0x80000000;
13154 Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13156 slotbuf[0] = 0x8000000;
13161 Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13163 slotbuf[0] = 0x10000000;
13168 Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13170 slotbuf[0] = 0x38000000;
13175 Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13177 slotbuf[0] = 0x90000000;
13182 Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13184 slotbuf[0] = 0x48000000;
13189 Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13191 slotbuf[0] = 0x68000000;
13196 Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13198 slotbuf[0] = 0x58000000;
13203 Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13205 slotbuf[0] = 0x78000000;
13210 Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13212 slotbuf[0] = 0x20000000;
13217 Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13219 slotbuf[0] = 0xa0000000;
13224 Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13226 slotbuf[0] = 0x18000000;
13231 Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13233 slotbuf[0] = 0x88000000;
13238 Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13240 slotbuf[0] = 0x28000000;
13245 Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
13247 slotbuf[0] = 0x30000000;
13251 xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
13252 Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13255 xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
13256 Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13259 xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
13260 Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13263 xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
13264 Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13267 xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
13268 Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13271 xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
13272 Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13275 xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
13276 Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13279 xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
13280 Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13283 xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
13284 Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13287 xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
13288 Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13291 xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
13292 Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13295 xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
13296 Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13299 xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
13300 Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13303 xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
13304 Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13307 xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
13308 Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13311 xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
13312 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13315 xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
13316 Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13319 xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
13320 Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13323 xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
13324 Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13327 xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
13328 Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13331 xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
13332 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13335 xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
13336 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13339 xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
13340 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13343 xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
13344 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13347 xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
13348 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13351 xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
13352 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13355 xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
13356 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13359 xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
13360 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
13363 xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
13364 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13367 xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
13368 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13371 xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
13372 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13375 xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
13376 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13379 xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
13380 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
13383 xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
13384 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
13387 xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
13388 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13391 xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
13392 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13395 xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
13396 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13399 xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
13400 Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13403 xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
13404 Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13407 xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
13408 Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
13411 xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
13412 Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
13415 xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
13416 Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
13419 xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
13420 Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
13423 xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
13424 Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
13427 xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
13428 Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
13431 xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
13432 Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
13435 xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
13436 Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
13439 xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
13440 Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
13443 xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
13444 Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
13447 xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
13448 Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
13451 xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
13452 Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
13455 xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
13456 Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
13459 xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
13460 Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13463 xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
13464 Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13467 xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
13468 Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13471 xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
13472 Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13475 xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
13476 Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13479 xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
13480 Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13483 xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
13484 Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13487 xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
13488 Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13491 xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
13492 Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13495 xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
13496 Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13499 xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
13500 Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13503 xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
13504 Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13507 xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
13508 Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13511 xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
13512 Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13515 xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
13516 Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13519 xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
13520 Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13523 xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
13524 Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13527 xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
13528 Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13531 xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
13532 Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13535 xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
13536 Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13539 xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
13540 Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13543 xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
13544 Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13547 xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
13548 Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13551 xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
13552 Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13555 xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
13556 Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13559 xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
13560 Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13563 xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
13564 Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
13567 xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
13568 Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13571 xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
13572 Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
13575 xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
13576 Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
13579 xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
13580 Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
13583 xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
13584 Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
13587 xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
13588 Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13591 xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
13592 Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
13595 xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
13596 Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
13599 xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
13600 Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13603 xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
13604 Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13607 xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
13608 Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13611 xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
13612 Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
13615 xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
13616 Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
13619 xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
13620 Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
13623 xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
13624 Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
13627 xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
13628 Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
13631 xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
13632 Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
13635 xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
13636 Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
13639 xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
13640 Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
13643 xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
13644 Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13647 xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
13648 Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13651 xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
13652 Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13655 xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
13656 Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13659 xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
13660 Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
13663 xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
13664 Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
13667 xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
13668 Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
13671 xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
13672 Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
13675 xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
13676 Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
13679 xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
13680 Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
13683 xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
13684 Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
13687 xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
13688 Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
13691 xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
13692 Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
13695 xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
13696 Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
13699 xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
13700 Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
13703 xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
13704 Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
13707 xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
13708 Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13711 xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
13712 Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13715 xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
13716 Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13719 xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
13720 Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13723 xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
13724 Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13727 xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
13728 Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13731 xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
13732 Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13735 xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
13736 Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13739 xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
13740 Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13743 xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
13744 Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13747 xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
13748 Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13751 xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
13752 Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13755 xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
13756 Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13759 xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
13760 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13763 xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
13764 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13767 xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
13768 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13771 xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
13772 Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13775 xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
13776 Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13779 xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
13780 Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13783 xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
13784 Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13787 xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
13788 Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13791 xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
13792 Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13795 xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
13796 Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13799 xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
13800 Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13803 xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
13804 Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13807 xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
13808 Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13811 xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
13812 Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13815 xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
13816 Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13819 xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
13820 Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13823 xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
13824 Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13827 xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
13828 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13831 xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
13832 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13835 xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
13836 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13839 xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
13840 Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13843 xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
13844 Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13847 xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
13848 Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13851 xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
13852 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13855 xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
13856 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13859 xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
13860 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13863 xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
13864 Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13867 xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
13868 Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13871 xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
13872 Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13875 xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
13876 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13879 xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
13880 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13883 xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
13884 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13887 xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
13888 Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13891 xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
13892 Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13895 xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
13896 Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13899 xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
13900 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13903 xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
13904 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13907 xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
13908 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13911 xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
13912 Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13915 xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
13916 Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13919 xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
13920 Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13923 xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
13924 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13927 xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
13928 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13931 xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
13932 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13935 xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
13936 Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13939 xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
13940 Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13943 xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
13944 Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13947 xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
13948 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13951 xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
13952 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13955 xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
13956 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13959 xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
13960 Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13963 xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
13964 Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13967 xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
13968 Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13971 xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
13972 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13975 xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
13976 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13979 xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
13980 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13983 xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
13984 Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13987 xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
13988 Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13991 xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
13992 Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13995 xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
13996 Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13999 xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
14000 Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14003 xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
14004 Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14007 xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
14008 Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14011 xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
14012 Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14015 xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
14016 Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14019 xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
14020 Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14023 xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
14024 Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14027 xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
14028 Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14031 xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
14032 Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14035 xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
14036 Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14039 xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
14040 Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14043 xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
14044 Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14047 xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
14048 Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14051 xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
14052 Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14055 xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
14056 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14059 xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
14060 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14063 xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
14064 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14067 xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
14068 Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14071 xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
14072 Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14075 xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
14076 Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14079 xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
14080 Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14083 xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
14084 Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14087 xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
14088 Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14091 xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
14092 Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14095 xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
14096 Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14099 xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
14100 Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14103 xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
14104 Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14107 xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
14108 Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14111 xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
14112 Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14115 xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
14116 Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14119 xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
14120 Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14123 xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
14124 Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14127 xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
14128 Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14131 xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
14132 Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14135 xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
14136 Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14139 xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
14140 Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14143 xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
14144 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14147 xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
14148 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14151 xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
14152 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14155 xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
14156 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14159 xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
14160 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14163 xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
14164 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14167 xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
14168 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14171 xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
14172 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14175 xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
14176 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14179 xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
14180 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14183 xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
14184 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14187 xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
14188 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14191 xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
14192 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14195 xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
14196 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14199 xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
14200 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14203 xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
14204 Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14207 xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
14208 Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14211 xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
14212 Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14215 xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
14216 Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14219 xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
14220 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14223 xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
14224 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14227 xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
14228 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14231 xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
14232 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14235 xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
14236 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14239 xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
14240 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14243 xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
14244 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14247 xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
14248 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14251 xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
14252 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14255 xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
14256 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14259 xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
14260 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14263 xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
14264 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14267 xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
14268 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14271 xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
14272 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14275 xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
14276 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14279 xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
14280 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14283 xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
14284 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14287 xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
14288 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14291 xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
14292 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14295 xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
14296 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14299 xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
14300 Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14303 xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
14304 Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14307 xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
14308 Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14311 xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
14312 Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14315 xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
14316 Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14319 xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
14320 Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14323 xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
14324 Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14327 xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
14328 Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14331 xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
14332 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14335 xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
14336 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14339 xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
14340 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14343 xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
14344 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14347 xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
14348 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14351 xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
14352 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14355 xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
14356 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14359 xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
14360 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14363 xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
14364 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14367 xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
14368 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14371 xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
14372 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14375 xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
14376 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14379 xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
14380 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14383 xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
14384 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14387 xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
14388 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14391 xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
14392 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14395 xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
14396 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14399 xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
14400 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14403 xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
14404 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14407 xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
14408 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14411 xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
14412 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14415 xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
14416 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14419 xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
14420 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14423 xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
14424 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14427 xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
14428 Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14431 xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
14432 Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14435 xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
14436 Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
14439 xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
14440 Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
14443 xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
14444 Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14447 xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
14448 Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14451 xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
14452 Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14455 xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
14456 Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14459 xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
14460 Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14463 xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
14464 Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14467 xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
14468 Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14471 xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
14472 Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14475 xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
14476 Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14479 xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
14480 Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14483 xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
14484 Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14487 xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
14488 Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14491 xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
14492 Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14495 xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
14496 Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14499 xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
14500 Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14503 xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
14504 Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14507 xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
14508 Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14511 xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
14512 Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14515 xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
14516 Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14519 xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
14520 Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14523 xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
14524 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14527 xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
14528 Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14531 xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
14532 Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14535 xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
14536 Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14539 xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
14540 Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14543 xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
14544 Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14547 xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
14548 Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14551 xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
14552 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
14555 xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
14556 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14559 xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
14560 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14563 xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
14564 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14567 xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
14568 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14571 xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
14572 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14575 xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
14576 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14579 xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
14580 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14583 xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
14584 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14587 xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
14588 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14591 xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
14592 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14595 xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
14596 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14599 xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
14600 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14603 xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
14604 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14607 xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
14608 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14611 xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
14612 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14615 xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
14616 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14619 xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
14620 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14623 xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
14624 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14627 xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
14628 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14631 xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
14632 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14635 xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
14636 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14639 xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
14640 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14643 xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
14644 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14647 xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
14648 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14651 xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
14652 Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14655 xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
14656 Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14659 xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
14660 Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14663 xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
14664 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14667 xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
14668 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14671 xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
14672 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14675 xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
14676 Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14679 xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
14680 Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14683 xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
14684 Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14687 xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
14688 Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14691 xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
14692 Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14695 xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
14696 Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14699 xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
14700 Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14703 xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
14704 Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14707 xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
14708 Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14711 xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
14712 Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14715 xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
14716 Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14719 xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
14720 Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14723 xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
14724 Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14727 xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
14728 Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14731 xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
14732 Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14735 xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
14736 Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14739 xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
14740 Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14743 xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
14744 Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14747 xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
14748 Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14751 xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
14752 Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14755 xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
14756 Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14759 xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
14760 Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14763 xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
14764 Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14767 xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
14768 Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14771 xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
14772 Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14775 xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
14776 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14779 xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
14780 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14783 xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
14784 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14787 xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
14788 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14791 xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
14792 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14795 xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
14796 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14799 xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
14800 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14803 xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
14804 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14807 xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
14808 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14811 xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
14812 Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14815 xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
14816 Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14819 xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
14820 Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14823 xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
14824 Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14827 xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
14828 Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14831 xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
14832 Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14835 xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
14836 Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14839 xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
14840 Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14843 xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
14844 Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14847 xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
14848 Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14851 xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
14852 Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14855 xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
14856 Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14859 xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
14860 Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14863 xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
14864 Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14867 xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
14868 Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14871 xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
14872 Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14875 xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
14876 Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14879 xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
14880 Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14883 xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
14884 Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14887 xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
14888 Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14891 xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
14892 Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14895 xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
14896 Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14899 xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
14900 Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14903 xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
14904 Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14907 xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
14908 Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14911 xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
14912 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14915 xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
14916 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14919 xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
14920 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14923 xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
14924 Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14927 xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
14928 Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14931 xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
14932 Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14935 xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
14936 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14939 xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
14940 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14943 xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
14944 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14947 xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
14948 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14951 xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
14952 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14955 xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
14956 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14959 xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
14960 Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14963 xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
14964 Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14967 xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
14968 Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14971 xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
14972 Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14975 xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
14976 Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14979 xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
14980 Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14983 xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
14984 Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14987 xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
14988 Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14991 xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
14992 Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14995 xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
14996 Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
14999 xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
15000 Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15003 xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
15004 Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15007 xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
15008 Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15011 xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
15012 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15015 xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
15016 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15019 xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
15020 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15023 xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
15024 Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
15027 xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
15028 Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
15031 xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
15032 Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
15035 xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
15036 Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
15039 xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
15040 Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
15043 xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
15044 Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
15047 xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
15048 Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
15051 xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
15052 Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
15055 xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
15056 Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15059 xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
15060 Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15063 xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
15064 Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15067 xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
15068 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15071 xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
15072 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15075 xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
15076 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15079 xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
15080 Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15083 xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
15084 Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15087 xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
15088 Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15091 xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
15092 Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15095 xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
15096 Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
15099 xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
15100 Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15103 xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
15104 Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15107 xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
15108 Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15111 xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
15112 Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15115 xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
15116 Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15119 xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
15120 Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15123 xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
15124 Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15127 xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
15128 Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15131 xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
15132 Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15135 xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
15136 Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15139 xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
15140 Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15143 xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
15144 Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15147 xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
15148 Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15151 xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
15152 Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15155 xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
15156 Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15159 xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
15160 Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15163 xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
15164 Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15167 xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
15168 Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15171 xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
15172 Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15175 xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
15176 Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15179 xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
15180 Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15183 xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
15184 Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15187 xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
15188 Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15191 xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
15192 Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15195 xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
15196 Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15199 xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
15200 Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15203 xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
15204 Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15207 xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
15208 Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15211 xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
15212 Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15215 xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
15216 Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15219 xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
15220 Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15223 xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
15224 Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15227 xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
15228 Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15231 xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
15232 Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15235 xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
15236 Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15239 xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
15240 Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15243 xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
15244 Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15247 xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
15248 Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15251 xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
15252 Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15255 xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
15256 Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15259 xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
15260 Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15263 xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
15264 Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15267 xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
15268 Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15271 xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
15272 Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15275 xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
15276 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
15279 xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
15280 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
15283 xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
15284 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
15287 xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
15288 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
15291 xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
15292 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
15295 xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
15296 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
15299 xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
15300 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
15303 xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
15304 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
15307 xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
15308 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
15311 xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
15312 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
15315 xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
15316 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
15319 xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
15320 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
15323 xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
15324 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
15327 xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
15328 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
15331 xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
15332 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
15335 xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
15336 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
15339 xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
15340 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
15343 xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
15344 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
15347 xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
15348 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
15351 xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
15352 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
15355 xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
15356 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
15359 xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
15360 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
15363 xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
15364 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
15367 xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
15368 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
15372 /* Opcode table. */
15374 static xtensa_opcode_internal opcodes[] = {
15375 { "excw", 0 /* xt_iclass_excw */,
15377 Opcode_excw_encode_fns, 0, 0 },
15378 { "rfe", 1 /* xt_iclass_rfe */,
15379 XTENSA_OPCODE_IS_JUMP,
15380 Opcode_rfe_encode_fns, 0, 0 },
15381 { "rfde", 2 /* xt_iclass_rfde */,
15382 XTENSA_OPCODE_IS_JUMP,
15383 Opcode_rfde_encode_fns, 0, 0 },
15384 { "syscall", 3 /* xt_iclass_syscall */,
15386 Opcode_syscall_encode_fns, 0, 0 },
15387 { "simcall", 4 /* xt_iclass_simcall */,
15389 Opcode_simcall_encode_fns, 0, 0 },
15390 { "call12", 5 /* xt_iclass_call12 */,
15391 XTENSA_OPCODE_IS_CALL,
15392 Opcode_call12_encode_fns, 0, 0 },
15393 { "call8", 6 /* xt_iclass_call8 */,
15394 XTENSA_OPCODE_IS_CALL,
15395 Opcode_call8_encode_fns, 0, 0 },
15396 { "call4", 7 /* xt_iclass_call4 */,
15397 XTENSA_OPCODE_IS_CALL,
15398 Opcode_call4_encode_fns, 0, 0 },
15399 { "callx12", 8 /* xt_iclass_callx12 */,
15400 XTENSA_OPCODE_IS_CALL,
15401 Opcode_callx12_encode_fns, 0, 0 },
15402 { "callx8", 9 /* xt_iclass_callx8 */,
15403 XTENSA_OPCODE_IS_CALL,
15404 Opcode_callx8_encode_fns, 0, 0 },
15405 { "callx4", 10 /* xt_iclass_callx4 */,
15406 XTENSA_OPCODE_IS_CALL,
15407 Opcode_callx4_encode_fns, 0, 0 },
15408 { "entry", 11 /* xt_iclass_entry */,
15410 Opcode_entry_encode_fns, 0, 0 },
15411 { "movsp", 12 /* xt_iclass_movsp */,
15413 Opcode_movsp_encode_fns, 0, 0 },
15414 { "rotw", 13 /* xt_iclass_rotw */,
15416 Opcode_rotw_encode_fns, 0, 0 },
15417 { "retw", 14 /* xt_iclass_retw */,
15418 XTENSA_OPCODE_IS_JUMP,
15419 Opcode_retw_encode_fns, 0, 0 },
15420 { "retw.n", 14 /* xt_iclass_retw */,
15421 XTENSA_OPCODE_IS_JUMP,
15422 Opcode_retw_n_encode_fns, 0, 0 },
15423 { "rfwo", 15 /* xt_iclass_rfwou */,
15424 XTENSA_OPCODE_IS_JUMP,
15425 Opcode_rfwo_encode_fns, 0, 0 },
15426 { "rfwu", 15 /* xt_iclass_rfwou */,
15427 XTENSA_OPCODE_IS_JUMP,
15428 Opcode_rfwu_encode_fns, 0, 0 },
15429 { "l32e", 16 /* xt_iclass_l32e */,
15431 Opcode_l32e_encode_fns, 0, 0 },
15432 { "s32e", 17 /* xt_iclass_s32e */,
15434 Opcode_s32e_encode_fns, 0, 0 },
15435 { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
15437 Opcode_rsr_windowbase_encode_fns, 0, 0 },
15438 { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
15440 Opcode_wsr_windowbase_encode_fns, 0, 0 },
15441 { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
15443 Opcode_xsr_windowbase_encode_fns, 0, 0 },
15444 { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
15446 Opcode_rsr_windowstart_encode_fns, 0, 0 },
15447 { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
15449 Opcode_wsr_windowstart_encode_fns, 0, 0 },
15450 { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
15452 Opcode_xsr_windowstart_encode_fns, 0, 0 },
15453 { "add.n", 24 /* xt_iclass_add.n */,
15455 Opcode_add_n_encode_fns, 0, 0 },
15456 { "addi.n", 25 /* xt_iclass_addi.n */,
15458 Opcode_addi_n_encode_fns, 0, 0 },
15459 { "beqz.n", 26 /* xt_iclass_bz6 */,
15460 XTENSA_OPCODE_IS_BRANCH,
15461 Opcode_beqz_n_encode_fns, 0, 0 },
15462 { "bnez.n", 26 /* xt_iclass_bz6 */,
15463 XTENSA_OPCODE_IS_BRANCH,
15464 Opcode_bnez_n_encode_fns, 0, 0 },
15465 { "ill.n", 27 /* xt_iclass_ill.n */,
15467 Opcode_ill_n_encode_fns, 0, 0 },
15468 { "l32i.n", 28 /* xt_iclass_loadi4 */,
15470 Opcode_l32i_n_encode_fns, 0, 0 },
15471 { "mov.n", 29 /* xt_iclass_mov.n */,
15473 Opcode_mov_n_encode_fns, 0, 0 },
15474 { "movi.n", 30 /* xt_iclass_movi.n */,
15476 Opcode_movi_n_encode_fns, 0, 0 },
15477 { "nop.n", 31 /* xt_iclass_nopn */,
15479 Opcode_nop_n_encode_fns, 0, 0 },
15480 { "ret.n", 32 /* xt_iclass_retn */,
15481 XTENSA_OPCODE_IS_JUMP,
15482 Opcode_ret_n_encode_fns, 0, 0 },
15483 { "s32i.n", 33 /* xt_iclass_storei4 */,
15485 Opcode_s32i_n_encode_fns, 0, 0 },
15486 { "rur.threadptr", 34 /* rur_threadptr */,
15488 Opcode_rur_threadptr_encode_fns, 0, 0 },
15489 { "wur.threadptr", 35 /* wur_threadptr */,
15491 Opcode_wur_threadptr_encode_fns, 0, 0 },
15492 { "addi", 36 /* xt_iclass_addi */,
15494 Opcode_addi_encode_fns, 0, 0 },
15495 { "addmi", 37 /* xt_iclass_addmi */,
15497 Opcode_addmi_encode_fns, 0, 0 },
15498 { "add", 38 /* xt_iclass_addsub */,
15500 Opcode_add_encode_fns, 0, 0 },
15501 { "sub", 38 /* xt_iclass_addsub */,
15503 Opcode_sub_encode_fns, 0, 0 },
15504 { "addx2", 38 /* xt_iclass_addsub */,
15506 Opcode_addx2_encode_fns, 0, 0 },
15507 { "addx4", 38 /* xt_iclass_addsub */,
15509 Opcode_addx4_encode_fns, 0, 0 },
15510 { "addx8", 38 /* xt_iclass_addsub */,
15512 Opcode_addx8_encode_fns, 0, 0 },
15513 { "subx2", 38 /* xt_iclass_addsub */,
15515 Opcode_subx2_encode_fns, 0, 0 },
15516 { "subx4", 38 /* xt_iclass_addsub */,
15518 Opcode_subx4_encode_fns, 0, 0 },
15519 { "subx8", 38 /* xt_iclass_addsub */,
15521 Opcode_subx8_encode_fns, 0, 0 },
15522 { "and", 39 /* xt_iclass_bit */,
15524 Opcode_and_encode_fns, 0, 0 },
15525 { "or", 39 /* xt_iclass_bit */,
15527 Opcode_or_encode_fns, 0, 0 },
15528 { "xor", 39 /* xt_iclass_bit */,
15530 Opcode_xor_encode_fns, 0, 0 },
15531 { "beqi", 40 /* xt_iclass_bsi8 */,
15532 XTENSA_OPCODE_IS_BRANCH,
15533 Opcode_beqi_encode_fns, 0, 0 },
15534 { "bnei", 40 /* xt_iclass_bsi8 */,
15535 XTENSA_OPCODE_IS_BRANCH,
15536 Opcode_bnei_encode_fns, 0, 0 },
15537 { "bgei", 40 /* xt_iclass_bsi8 */,
15538 XTENSA_OPCODE_IS_BRANCH,
15539 Opcode_bgei_encode_fns, 0, 0 },
15540 { "blti", 40 /* xt_iclass_bsi8 */,
15541 XTENSA_OPCODE_IS_BRANCH,
15542 Opcode_blti_encode_fns, 0, 0 },
15543 { "bbci", 41 /* xt_iclass_bsi8b */,
15544 XTENSA_OPCODE_IS_BRANCH,
15545 Opcode_bbci_encode_fns, 0, 0 },
15546 { "bbsi", 41 /* xt_iclass_bsi8b */,
15547 XTENSA_OPCODE_IS_BRANCH,
15548 Opcode_bbsi_encode_fns, 0, 0 },
15549 { "bgeui", 42 /* xt_iclass_bsi8u */,
15550 XTENSA_OPCODE_IS_BRANCH,
15551 Opcode_bgeui_encode_fns, 0, 0 },
15552 { "bltui", 42 /* xt_iclass_bsi8u */,
15553 XTENSA_OPCODE_IS_BRANCH,
15554 Opcode_bltui_encode_fns, 0, 0 },
15555 { "beq", 43 /* xt_iclass_bst8 */,
15556 XTENSA_OPCODE_IS_BRANCH,
15557 Opcode_beq_encode_fns, 0, 0 },
15558 { "bne", 43 /* xt_iclass_bst8 */,
15559 XTENSA_OPCODE_IS_BRANCH,
15560 Opcode_bne_encode_fns, 0, 0 },
15561 { "bge", 43 /* xt_iclass_bst8 */,
15562 XTENSA_OPCODE_IS_BRANCH,
15563 Opcode_bge_encode_fns, 0, 0 },
15564 { "blt", 43 /* xt_iclass_bst8 */,
15565 XTENSA_OPCODE_IS_BRANCH,
15566 Opcode_blt_encode_fns, 0, 0 },
15567 { "bgeu", 43 /* xt_iclass_bst8 */,
15568 XTENSA_OPCODE_IS_BRANCH,
15569 Opcode_bgeu_encode_fns, 0, 0 },
15570 { "bltu", 43 /* xt_iclass_bst8 */,
15571 XTENSA_OPCODE_IS_BRANCH,
15572 Opcode_bltu_encode_fns, 0, 0 },
15573 { "bany", 43 /* xt_iclass_bst8 */,
15574 XTENSA_OPCODE_IS_BRANCH,
15575 Opcode_bany_encode_fns, 0, 0 },
15576 { "bnone", 43 /* xt_iclass_bst8 */,
15577 XTENSA_OPCODE_IS_BRANCH,
15578 Opcode_bnone_encode_fns, 0, 0 },
15579 { "ball", 43 /* xt_iclass_bst8 */,
15580 XTENSA_OPCODE_IS_BRANCH,
15581 Opcode_ball_encode_fns, 0, 0 },
15582 { "bnall", 43 /* xt_iclass_bst8 */,
15583 XTENSA_OPCODE_IS_BRANCH,
15584 Opcode_bnall_encode_fns, 0, 0 },
15585 { "bbc", 43 /* xt_iclass_bst8 */,
15586 XTENSA_OPCODE_IS_BRANCH,
15587 Opcode_bbc_encode_fns, 0, 0 },
15588 { "bbs", 43 /* xt_iclass_bst8 */,
15589 XTENSA_OPCODE_IS_BRANCH,
15590 Opcode_bbs_encode_fns, 0, 0 },
15591 { "beqz", 44 /* xt_iclass_bsz12 */,
15592 XTENSA_OPCODE_IS_BRANCH,
15593 Opcode_beqz_encode_fns, 0, 0 },
15594 { "bnez", 44 /* xt_iclass_bsz12 */,
15595 XTENSA_OPCODE_IS_BRANCH,
15596 Opcode_bnez_encode_fns, 0, 0 },
15597 { "bgez", 44 /* xt_iclass_bsz12 */,
15598 XTENSA_OPCODE_IS_BRANCH,
15599 Opcode_bgez_encode_fns, 0, 0 },
15600 { "bltz", 44 /* xt_iclass_bsz12 */,
15601 XTENSA_OPCODE_IS_BRANCH,
15602 Opcode_bltz_encode_fns, 0, 0 },
15603 { "call0", 45 /* xt_iclass_call0 */,
15604 XTENSA_OPCODE_IS_CALL,
15605 Opcode_call0_encode_fns, 0, 0 },
15606 { "callx0", 46 /* xt_iclass_callx0 */,
15607 XTENSA_OPCODE_IS_CALL,
15608 Opcode_callx0_encode_fns, 0, 0 },
15609 { "extui", 47 /* xt_iclass_exti */,
15611 Opcode_extui_encode_fns, 0, 0 },
15612 { "ill", 48 /* xt_iclass_ill */,
15614 Opcode_ill_encode_fns, 0, 0 },
15615 { "j", 49 /* xt_iclass_jump */,
15616 XTENSA_OPCODE_IS_JUMP,
15617 Opcode_j_encode_fns, 0, 0 },
15618 { "jx", 50 /* xt_iclass_jumpx */,
15619 XTENSA_OPCODE_IS_JUMP,
15620 Opcode_jx_encode_fns, 0, 0 },
15621 { "l16ui", 51 /* xt_iclass_l16ui */,
15623 Opcode_l16ui_encode_fns, 0, 0 },
15624 { "l16si", 52 /* xt_iclass_l16si */,
15626 Opcode_l16si_encode_fns, 0, 0 },
15627 { "l32i", 53 /* xt_iclass_l32i */,
15629 Opcode_l32i_encode_fns, 0, 0 },
15630 { "l32r", 54 /* xt_iclass_l32r */,
15632 Opcode_l32r_encode_fns, 0, 0 },
15633 { "l8ui", 55 /* xt_iclass_l8i */,
15635 Opcode_l8ui_encode_fns, 0, 0 },
15636 { "loop", 56 /* xt_iclass_loop */,
15637 XTENSA_OPCODE_IS_LOOP,
15638 Opcode_loop_encode_fns, 0, 0 },
15639 { "loopnez", 57 /* xt_iclass_loopz */,
15640 XTENSA_OPCODE_IS_LOOP,
15641 Opcode_loopnez_encode_fns, 0, 0 },
15642 { "loopgtz", 57 /* xt_iclass_loopz */,
15643 XTENSA_OPCODE_IS_LOOP,
15644 Opcode_loopgtz_encode_fns, 0, 0 },
15645 { "movi", 58 /* xt_iclass_movi */,
15647 Opcode_movi_encode_fns, 0, 0 },
15648 { "moveqz", 59 /* xt_iclass_movz */,
15650 Opcode_moveqz_encode_fns, 0, 0 },
15651 { "movnez", 59 /* xt_iclass_movz */,
15653 Opcode_movnez_encode_fns, 0, 0 },
15654 { "movltz", 59 /* xt_iclass_movz */,
15656 Opcode_movltz_encode_fns, 0, 0 },
15657 { "movgez", 59 /* xt_iclass_movz */,
15659 Opcode_movgez_encode_fns, 0, 0 },
15660 { "neg", 60 /* xt_iclass_neg */,
15662 Opcode_neg_encode_fns, 0, 0 },
15663 { "abs", 60 /* xt_iclass_neg */,
15665 Opcode_abs_encode_fns, 0, 0 },
15666 { "nop", 61 /* xt_iclass_nop */,
15668 Opcode_nop_encode_fns, 0, 0 },
15669 { "ret", 62 /* xt_iclass_return */,
15670 XTENSA_OPCODE_IS_JUMP,
15671 Opcode_ret_encode_fns, 0, 0 },
15672 { "s16i", 63 /* xt_iclass_s16i */,
15674 Opcode_s16i_encode_fns, 0, 0 },
15675 { "s32i", 64 /* xt_iclass_s32i */,
15677 Opcode_s32i_encode_fns, 0, 0 },
15678 { "s8i", 65 /* xt_iclass_s8i */,
15680 Opcode_s8i_encode_fns, 0, 0 },
15681 { "ssr", 66 /* xt_iclass_sar */,
15683 Opcode_ssr_encode_fns, 0, 0 },
15684 { "ssl", 66 /* xt_iclass_sar */,
15686 Opcode_ssl_encode_fns, 0, 0 },
15687 { "ssa8l", 66 /* xt_iclass_sar */,
15689 Opcode_ssa8l_encode_fns, 0, 0 },
15690 { "ssa8b", 66 /* xt_iclass_sar */,
15692 Opcode_ssa8b_encode_fns, 0, 0 },
15693 { "ssai", 67 /* xt_iclass_sari */,
15695 Opcode_ssai_encode_fns, 0, 0 },
15696 { "sll", 68 /* xt_iclass_shifts */,
15698 Opcode_sll_encode_fns, 0, 0 },
15699 { "src", 69 /* xt_iclass_shiftst */,
15701 Opcode_src_encode_fns, 0, 0 },
15702 { "srl", 70 /* xt_iclass_shiftt */,
15704 Opcode_srl_encode_fns, 0, 0 },
15705 { "sra", 70 /* xt_iclass_shiftt */,
15707 Opcode_sra_encode_fns, 0, 0 },
15708 { "slli", 71 /* xt_iclass_slli */,
15710 Opcode_slli_encode_fns, 0, 0 },
15711 { "srai", 72 /* xt_iclass_srai */,
15713 Opcode_srai_encode_fns, 0, 0 },
15714 { "srli", 73 /* xt_iclass_srli */,
15716 Opcode_srli_encode_fns, 0, 0 },
15717 { "memw", 74 /* xt_iclass_memw */,
15719 Opcode_memw_encode_fns, 0, 0 },
15720 { "extw", 75 /* xt_iclass_extw */,
15722 Opcode_extw_encode_fns, 0, 0 },
15723 { "isync", 76 /* xt_iclass_isync */,
15725 Opcode_isync_encode_fns, 0, 0 },
15726 { "rsync", 77 /* xt_iclass_sync */,
15728 Opcode_rsync_encode_fns, 0, 0 },
15729 { "esync", 77 /* xt_iclass_sync */,
15731 Opcode_esync_encode_fns, 0, 0 },
15732 { "dsync", 77 /* xt_iclass_sync */,
15734 Opcode_dsync_encode_fns, 0, 0 },
15735 { "rsil", 78 /* xt_iclass_rsil */,
15737 Opcode_rsil_encode_fns, 0, 0 },
15738 { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
15740 Opcode_rsr_lend_encode_fns, 0, 0 },
15741 { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
15743 Opcode_wsr_lend_encode_fns, 0, 0 },
15744 { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
15746 Opcode_xsr_lend_encode_fns, 0, 0 },
15747 { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
15749 Opcode_rsr_lcount_encode_fns, 0, 0 },
15750 { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
15752 Opcode_wsr_lcount_encode_fns, 0, 0 },
15753 { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
15755 Opcode_xsr_lcount_encode_fns, 0, 0 },
15756 { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
15758 Opcode_rsr_lbeg_encode_fns, 0, 0 },
15759 { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
15761 Opcode_wsr_lbeg_encode_fns, 0, 0 },
15762 { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
15764 Opcode_xsr_lbeg_encode_fns, 0, 0 },
15765 { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
15767 Opcode_rsr_sar_encode_fns, 0, 0 },
15768 { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
15770 Opcode_wsr_sar_encode_fns, 0, 0 },
15771 { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
15773 Opcode_xsr_sar_encode_fns, 0, 0 },
15774 { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
15776 Opcode_rsr_litbase_encode_fns, 0, 0 },
15777 { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
15779 Opcode_wsr_litbase_encode_fns, 0, 0 },
15780 { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
15782 Opcode_xsr_litbase_encode_fns, 0, 0 },
15783 { "rsr.176", 94 /* xt_iclass_rsr.176 */,
15785 Opcode_rsr_176_encode_fns, 0, 0 },
15786 { "rsr.208", 95 /* xt_iclass_rsr.208 */,
15788 Opcode_rsr_208_encode_fns, 0, 0 },
15789 { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
15791 Opcode_rsr_ps_encode_fns, 0, 0 },
15792 { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
15794 Opcode_wsr_ps_encode_fns, 0, 0 },
15795 { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
15797 Opcode_xsr_ps_encode_fns, 0, 0 },
15798 { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
15800 Opcode_rsr_epc1_encode_fns, 0, 0 },
15801 { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
15803 Opcode_wsr_epc1_encode_fns, 0, 0 },
15804 { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
15806 Opcode_xsr_epc1_encode_fns, 0, 0 },
15807 { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
15809 Opcode_rsr_excsave1_encode_fns, 0, 0 },
15810 { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
15812 Opcode_wsr_excsave1_encode_fns, 0, 0 },
15813 { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
15815 Opcode_xsr_excsave1_encode_fns, 0, 0 },
15816 { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
15818 Opcode_rsr_epc2_encode_fns, 0, 0 },
15819 { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
15821 Opcode_wsr_epc2_encode_fns, 0, 0 },
15822 { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
15824 Opcode_xsr_epc2_encode_fns, 0, 0 },
15825 { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
15827 Opcode_rsr_excsave2_encode_fns, 0, 0 },
15828 { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
15830 Opcode_wsr_excsave2_encode_fns, 0, 0 },
15831 { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
15833 Opcode_xsr_excsave2_encode_fns, 0, 0 },
15834 { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
15836 Opcode_rsr_epc3_encode_fns, 0, 0 },
15837 { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
15839 Opcode_wsr_epc3_encode_fns, 0, 0 },
15840 { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
15842 Opcode_xsr_epc3_encode_fns, 0, 0 },
15843 { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
15845 Opcode_rsr_excsave3_encode_fns, 0, 0 },
15846 { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
15848 Opcode_wsr_excsave3_encode_fns, 0, 0 },
15849 { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
15851 Opcode_xsr_excsave3_encode_fns, 0, 0 },
15852 { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
15854 Opcode_rsr_epc4_encode_fns, 0, 0 },
15855 { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
15857 Opcode_wsr_epc4_encode_fns, 0, 0 },
15858 { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
15860 Opcode_xsr_epc4_encode_fns, 0, 0 },
15861 { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
15863 Opcode_rsr_excsave4_encode_fns, 0, 0 },
15864 { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
15866 Opcode_wsr_excsave4_encode_fns, 0, 0 },
15867 { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
15869 Opcode_xsr_excsave4_encode_fns, 0, 0 },
15870 { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
15872 Opcode_rsr_epc5_encode_fns, 0, 0 },
15873 { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
15875 Opcode_wsr_epc5_encode_fns, 0, 0 },
15876 { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
15878 Opcode_xsr_epc5_encode_fns, 0, 0 },
15879 { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
15881 Opcode_rsr_excsave5_encode_fns, 0, 0 },
15882 { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
15884 Opcode_wsr_excsave5_encode_fns, 0, 0 },
15885 { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
15887 Opcode_xsr_excsave5_encode_fns, 0, 0 },
15888 { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
15890 Opcode_rsr_epc6_encode_fns, 0, 0 },
15891 { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
15893 Opcode_wsr_epc6_encode_fns, 0, 0 },
15894 { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
15896 Opcode_xsr_epc6_encode_fns, 0, 0 },
15897 { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
15899 Opcode_rsr_excsave6_encode_fns, 0, 0 },
15900 { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
15902 Opcode_wsr_excsave6_encode_fns, 0, 0 },
15903 { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
15905 Opcode_xsr_excsave6_encode_fns, 0, 0 },
15906 { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
15908 Opcode_rsr_epc7_encode_fns, 0, 0 },
15909 { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
15911 Opcode_wsr_epc7_encode_fns, 0, 0 },
15912 { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
15914 Opcode_xsr_epc7_encode_fns, 0, 0 },
15915 { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
15917 Opcode_rsr_excsave7_encode_fns, 0, 0 },
15918 { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
15920 Opcode_wsr_excsave7_encode_fns, 0, 0 },
15921 { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
15923 Opcode_xsr_excsave7_encode_fns, 0, 0 },
15924 { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
15926 Opcode_rsr_eps2_encode_fns, 0, 0 },
15927 { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
15929 Opcode_wsr_eps2_encode_fns, 0, 0 },
15930 { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
15932 Opcode_xsr_eps2_encode_fns, 0, 0 },
15933 { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
15935 Opcode_rsr_eps3_encode_fns, 0, 0 },
15936 { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
15938 Opcode_wsr_eps3_encode_fns, 0, 0 },
15939 { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
15941 Opcode_xsr_eps3_encode_fns, 0, 0 },
15942 { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
15944 Opcode_rsr_eps4_encode_fns, 0, 0 },
15945 { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
15947 Opcode_wsr_eps4_encode_fns, 0, 0 },
15948 { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
15950 Opcode_xsr_eps4_encode_fns, 0, 0 },
15951 { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
15953 Opcode_rsr_eps5_encode_fns, 0, 0 },
15954 { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
15956 Opcode_wsr_eps5_encode_fns, 0, 0 },
15957 { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
15959 Opcode_xsr_eps5_encode_fns, 0, 0 },
15960 { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
15962 Opcode_rsr_eps6_encode_fns, 0, 0 },
15963 { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
15965 Opcode_wsr_eps6_encode_fns, 0, 0 },
15966 { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
15968 Opcode_xsr_eps6_encode_fns, 0, 0 },
15969 { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
15971 Opcode_rsr_eps7_encode_fns, 0, 0 },
15972 { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
15974 Opcode_wsr_eps7_encode_fns, 0, 0 },
15975 { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
15977 Opcode_xsr_eps7_encode_fns, 0, 0 },
15978 { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
15980 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
15981 { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
15983 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
15984 { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
15986 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
15987 { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
15989 Opcode_rsr_depc_encode_fns, 0, 0 },
15990 { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
15992 Opcode_wsr_depc_encode_fns, 0, 0 },
15993 { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
15995 Opcode_xsr_depc_encode_fns, 0, 0 },
15996 { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
15998 Opcode_rsr_exccause_encode_fns, 0, 0 },
15999 { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
16001 Opcode_wsr_exccause_encode_fns, 0, 0 },
16002 { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
16004 Opcode_xsr_exccause_encode_fns, 0, 0 },
16005 { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
16007 Opcode_rsr_misc0_encode_fns, 0, 0 },
16008 { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
16010 Opcode_wsr_misc0_encode_fns, 0, 0 },
16011 { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
16013 Opcode_xsr_misc0_encode_fns, 0, 0 },
16014 { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
16016 Opcode_rsr_misc1_encode_fns, 0, 0 },
16017 { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
16019 Opcode_wsr_misc1_encode_fns, 0, 0 },
16020 { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
16022 Opcode_xsr_misc1_encode_fns, 0, 0 },
16023 { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */,
16025 Opcode_rsr_misc2_encode_fns, 0, 0 },
16026 { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */,
16028 Opcode_wsr_misc2_encode_fns, 0, 0 },
16029 { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */,
16031 Opcode_xsr_misc2_encode_fns, 0, 0 },
16032 { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */,
16034 Opcode_rsr_misc3_encode_fns, 0, 0 },
16035 { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */,
16037 Opcode_wsr_misc3_encode_fns, 0, 0 },
16038 { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */,
16040 Opcode_xsr_misc3_encode_fns, 0, 0 },
16041 { "rsr.prid", 180 /* xt_iclass_rsr.prid */,
16043 Opcode_rsr_prid_encode_fns, 0, 0 },
16044 { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */,
16046 Opcode_rsr_vecbase_encode_fns, 0, 0 },
16047 { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */,
16049 Opcode_wsr_vecbase_encode_fns, 0, 0 },
16050 { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */,
16052 Opcode_xsr_vecbase_encode_fns, 0, 0 },
16053 { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */,
16055 Opcode_mul_aa_ll_encode_fns, 0, 0 },
16056 { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */,
16058 Opcode_mul_aa_hl_encode_fns, 0, 0 },
16059 { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */,
16061 Opcode_mul_aa_lh_encode_fns, 0, 0 },
16062 { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */,
16064 Opcode_mul_aa_hh_encode_fns, 0, 0 },
16065 { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */,
16067 Opcode_umul_aa_ll_encode_fns, 0, 0 },
16068 { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */,
16070 Opcode_umul_aa_hl_encode_fns, 0, 0 },
16071 { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */,
16073 Opcode_umul_aa_lh_encode_fns, 0, 0 },
16074 { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */,
16076 Opcode_umul_aa_hh_encode_fns, 0, 0 },
16077 { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */,
16079 Opcode_mul_ad_ll_encode_fns, 0, 0 },
16080 { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */,
16082 Opcode_mul_ad_hl_encode_fns, 0, 0 },
16083 { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */,
16085 Opcode_mul_ad_lh_encode_fns, 0, 0 },
16086 { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */,
16088 Opcode_mul_ad_hh_encode_fns, 0, 0 },
16089 { "mul.da.ll", 186 /* xt_iclass_mac16_da */,
16091 Opcode_mul_da_ll_encode_fns, 0, 0 },
16092 { "mul.da.hl", 186 /* xt_iclass_mac16_da */,
16094 Opcode_mul_da_hl_encode_fns, 0, 0 },
16095 { "mul.da.lh", 186 /* xt_iclass_mac16_da */,
16097 Opcode_mul_da_lh_encode_fns, 0, 0 },
16098 { "mul.da.hh", 186 /* xt_iclass_mac16_da */,
16100 Opcode_mul_da_hh_encode_fns, 0, 0 },
16101 { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */,
16103 Opcode_mul_dd_ll_encode_fns, 0, 0 },
16104 { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */,
16106 Opcode_mul_dd_hl_encode_fns, 0, 0 },
16107 { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */,
16109 Opcode_mul_dd_lh_encode_fns, 0, 0 },
16110 { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */,
16112 Opcode_mul_dd_hh_encode_fns, 0, 0 },
16113 { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */,
16115 Opcode_mula_aa_ll_encode_fns, 0, 0 },
16116 { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */,
16118 Opcode_mula_aa_hl_encode_fns, 0, 0 },
16119 { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */,
16121 Opcode_mula_aa_lh_encode_fns, 0, 0 },
16122 { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */,
16124 Opcode_mula_aa_hh_encode_fns, 0, 0 },
16125 { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */,
16127 Opcode_muls_aa_ll_encode_fns, 0, 0 },
16128 { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */,
16130 Opcode_muls_aa_hl_encode_fns, 0, 0 },
16131 { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */,
16133 Opcode_muls_aa_lh_encode_fns, 0, 0 },
16134 { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */,
16136 Opcode_muls_aa_hh_encode_fns, 0, 0 },
16137 { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */,
16139 Opcode_mula_ad_ll_encode_fns, 0, 0 },
16140 { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */,
16142 Opcode_mula_ad_hl_encode_fns, 0, 0 },
16143 { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */,
16145 Opcode_mula_ad_lh_encode_fns, 0, 0 },
16146 { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */,
16148 Opcode_mula_ad_hh_encode_fns, 0, 0 },
16149 { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */,
16151 Opcode_muls_ad_ll_encode_fns, 0, 0 },
16152 { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */,
16154 Opcode_muls_ad_hl_encode_fns, 0, 0 },
16155 { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */,
16157 Opcode_muls_ad_lh_encode_fns, 0, 0 },
16158 { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */,
16160 Opcode_muls_ad_hh_encode_fns, 0, 0 },
16161 { "mula.da.ll", 190 /* xt_iclass_mac16a_da */,
16163 Opcode_mula_da_ll_encode_fns, 0, 0 },
16164 { "mula.da.hl", 190 /* xt_iclass_mac16a_da */,
16166 Opcode_mula_da_hl_encode_fns, 0, 0 },
16167 { "mula.da.lh", 190 /* xt_iclass_mac16a_da */,
16169 Opcode_mula_da_lh_encode_fns, 0, 0 },
16170 { "mula.da.hh", 190 /* xt_iclass_mac16a_da */,
16172 Opcode_mula_da_hh_encode_fns, 0, 0 },
16173 { "muls.da.ll", 190 /* xt_iclass_mac16a_da */,
16175 Opcode_muls_da_ll_encode_fns, 0, 0 },
16176 { "muls.da.hl", 190 /* xt_iclass_mac16a_da */,
16178 Opcode_muls_da_hl_encode_fns, 0, 0 },
16179 { "muls.da.lh", 190 /* xt_iclass_mac16a_da */,
16181 Opcode_muls_da_lh_encode_fns, 0, 0 },
16182 { "muls.da.hh", 190 /* xt_iclass_mac16a_da */,
16184 Opcode_muls_da_hh_encode_fns, 0, 0 },
16185 { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */,
16187 Opcode_mula_dd_ll_encode_fns, 0, 0 },
16188 { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */,
16190 Opcode_mula_dd_hl_encode_fns, 0, 0 },
16191 { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */,
16193 Opcode_mula_dd_lh_encode_fns, 0, 0 },
16194 { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */,
16196 Opcode_mula_dd_hh_encode_fns, 0, 0 },
16197 { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */,
16199 Opcode_muls_dd_ll_encode_fns, 0, 0 },
16200 { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */,
16202 Opcode_muls_dd_hl_encode_fns, 0, 0 },
16203 { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */,
16205 Opcode_muls_dd_lh_encode_fns, 0, 0 },
16206 { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */,
16208 Opcode_muls_dd_hh_encode_fns, 0, 0 },
16209 { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */,
16211 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
16212 { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */,
16214 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
16215 { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */,
16217 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
16218 { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */,
16220 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
16221 { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */,
16223 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
16224 { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */,
16226 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
16227 { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */,
16229 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
16230 { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */,
16232 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
16233 { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */,
16235 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
16236 { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */,
16238 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
16239 { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */,
16241 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
16242 { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */,
16244 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
16245 { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */,
16247 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
16248 { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */,
16250 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
16251 { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */,
16253 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
16254 { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */,
16256 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
16257 { "lddec", 194 /* xt_iclass_mac16_l */,
16259 Opcode_lddec_encode_fns, 0, 0 },
16260 { "ldinc", 194 /* xt_iclass_mac16_l */,
16262 Opcode_ldinc_encode_fns, 0, 0 },
16263 { "mul16u", 195 /* xt_iclass_mul16 */,
16265 Opcode_mul16u_encode_fns, 0, 0 },
16266 { "mul16s", 195 /* xt_iclass_mul16 */,
16268 Opcode_mul16s_encode_fns, 0, 0 },
16269 { "rsr.m0", 196 /* xt_iclass_rsr.m0 */,
16271 Opcode_rsr_m0_encode_fns, 0, 0 },
16272 { "wsr.m0", 197 /* xt_iclass_wsr.m0 */,
16274 Opcode_wsr_m0_encode_fns, 0, 0 },
16275 { "xsr.m0", 198 /* xt_iclass_xsr.m0 */,
16277 Opcode_xsr_m0_encode_fns, 0, 0 },
16278 { "rsr.m1", 199 /* xt_iclass_rsr.m1 */,
16280 Opcode_rsr_m1_encode_fns, 0, 0 },
16281 { "wsr.m1", 200 /* xt_iclass_wsr.m1 */,
16283 Opcode_wsr_m1_encode_fns, 0, 0 },
16284 { "xsr.m1", 201 /* xt_iclass_xsr.m1 */,
16286 Opcode_xsr_m1_encode_fns, 0, 0 },
16287 { "rsr.m2", 202 /* xt_iclass_rsr.m2 */,
16289 Opcode_rsr_m2_encode_fns, 0, 0 },
16290 { "wsr.m2", 203 /* xt_iclass_wsr.m2 */,
16292 Opcode_wsr_m2_encode_fns, 0, 0 },
16293 { "xsr.m2", 204 /* xt_iclass_xsr.m2 */,
16295 Opcode_xsr_m2_encode_fns, 0, 0 },
16296 { "rsr.m3", 205 /* xt_iclass_rsr.m3 */,
16298 Opcode_rsr_m3_encode_fns, 0, 0 },
16299 { "wsr.m3", 206 /* xt_iclass_wsr.m3 */,
16301 Opcode_wsr_m3_encode_fns, 0, 0 },
16302 { "xsr.m3", 207 /* xt_iclass_xsr.m3 */,
16304 Opcode_xsr_m3_encode_fns, 0, 0 },
16305 { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */,
16307 Opcode_rsr_acclo_encode_fns, 0, 0 },
16308 { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */,
16310 Opcode_wsr_acclo_encode_fns, 0, 0 },
16311 { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */,
16313 Opcode_xsr_acclo_encode_fns, 0, 0 },
16314 { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */,
16316 Opcode_rsr_acchi_encode_fns, 0, 0 },
16317 { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */,
16319 Opcode_wsr_acchi_encode_fns, 0, 0 },
16320 { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */,
16322 Opcode_xsr_acchi_encode_fns, 0, 0 },
16323 { "rfi", 214 /* xt_iclass_rfi */,
16324 XTENSA_OPCODE_IS_JUMP,
16325 Opcode_rfi_encode_fns, 0, 0 },
16326 { "waiti", 215 /* xt_iclass_wait */,
16328 Opcode_waiti_encode_fns, 0, 0 },
16329 { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */,
16331 Opcode_rsr_interrupt_encode_fns, 0, 0 },
16332 { "wsr.intset", 217 /* xt_iclass_wsr.intset */,
16334 Opcode_wsr_intset_encode_fns, 0, 0 },
16335 { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */,
16337 Opcode_wsr_intclear_encode_fns, 0, 0 },
16338 { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */,
16340 Opcode_rsr_intenable_encode_fns, 0, 0 },
16341 { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */,
16343 Opcode_wsr_intenable_encode_fns, 0, 0 },
16344 { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */,
16346 Opcode_xsr_intenable_encode_fns, 0, 0 },
16347 { "break", 222 /* xt_iclass_break */,
16349 Opcode_break_encode_fns, 0, 0 },
16350 { "break.n", 223 /* xt_iclass_break.n */,
16352 Opcode_break_n_encode_fns, 0, 0 },
16353 { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */,
16355 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
16356 { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */,
16358 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
16359 { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */,
16361 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
16362 { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */,
16364 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
16365 { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */,
16367 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
16368 { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */,
16370 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
16371 { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */,
16373 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
16374 { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */,
16376 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
16377 { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */,
16379 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
16380 { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */,
16382 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
16383 { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */,
16385 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
16386 { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */,
16388 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
16389 { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */,
16391 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
16392 { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */,
16394 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
16395 { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */,
16397 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
16398 { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */,
16400 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
16401 { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */,
16403 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
16404 { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */,
16406 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
16407 { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */,
16409 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
16410 { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */,
16412 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
16413 { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */,
16415 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
16416 { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */,
16418 Opcode_rsr_debugcause_encode_fns, 0, 0 },
16419 { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */,
16421 Opcode_wsr_debugcause_encode_fns, 0, 0 },
16422 { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */,
16424 Opcode_xsr_debugcause_encode_fns, 0, 0 },
16425 { "rsr.icount", 248 /* xt_iclass_rsr.icount */,
16427 Opcode_rsr_icount_encode_fns, 0, 0 },
16428 { "wsr.icount", 249 /* xt_iclass_wsr.icount */,
16430 Opcode_wsr_icount_encode_fns, 0, 0 },
16431 { "xsr.icount", 250 /* xt_iclass_xsr.icount */,
16433 Opcode_xsr_icount_encode_fns, 0, 0 },
16434 { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */,
16436 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
16437 { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */,
16439 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
16440 { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */,
16442 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
16443 { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */,
16445 Opcode_rsr_ddr_encode_fns, 0, 0 },
16446 { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */,
16448 Opcode_wsr_ddr_encode_fns, 0, 0 },
16449 { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */,
16451 Opcode_xsr_ddr_encode_fns, 0, 0 },
16452 { "rfdo", 257 /* xt_iclass_rfdo */,
16453 XTENSA_OPCODE_IS_JUMP,
16454 Opcode_rfdo_encode_fns, 0, 0 },
16455 { "rfdd", 258 /* xt_iclass_rfdd */,
16456 XTENSA_OPCODE_IS_JUMP,
16457 Opcode_rfdd_encode_fns, 0, 0 },
16458 { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */,
16460 Opcode_wsr_mmid_encode_fns, 0, 0 },
16461 { "andb", 260 /* xt_iclass_bbool1 */,
16463 Opcode_andb_encode_fns, 0, 0 },
16464 { "andbc", 260 /* xt_iclass_bbool1 */,
16466 Opcode_andbc_encode_fns, 0, 0 },
16467 { "orb", 260 /* xt_iclass_bbool1 */,
16469 Opcode_orb_encode_fns, 0, 0 },
16470 { "orbc", 260 /* xt_iclass_bbool1 */,
16472 Opcode_orbc_encode_fns, 0, 0 },
16473 { "xorb", 260 /* xt_iclass_bbool1 */,
16475 Opcode_xorb_encode_fns, 0, 0 },
16476 { "any4", 261 /* xt_iclass_bbool4 */,
16478 Opcode_any4_encode_fns, 0, 0 },
16479 { "all4", 261 /* xt_iclass_bbool4 */,
16481 Opcode_all4_encode_fns, 0, 0 },
16482 { "any8", 262 /* xt_iclass_bbool8 */,
16484 Opcode_any8_encode_fns, 0, 0 },
16485 { "all8", 262 /* xt_iclass_bbool8 */,
16487 Opcode_all8_encode_fns, 0, 0 },
16488 { "bf", 263 /* xt_iclass_bbranch */,
16489 XTENSA_OPCODE_IS_BRANCH,
16490 Opcode_bf_encode_fns, 0, 0 },
16491 { "bt", 263 /* xt_iclass_bbranch */,
16492 XTENSA_OPCODE_IS_BRANCH,
16493 Opcode_bt_encode_fns, 0, 0 },
16494 { "movf", 264 /* xt_iclass_bmove */,
16496 Opcode_movf_encode_fns, 0, 0 },
16497 { "movt", 264 /* xt_iclass_bmove */,
16499 Opcode_movt_encode_fns, 0, 0 },
16500 { "rsr.br", 265 /* xt_iclass_RSR.BR */,
16502 Opcode_rsr_br_encode_fns, 0, 0 },
16503 { "wsr.br", 266 /* xt_iclass_WSR.BR */,
16505 Opcode_wsr_br_encode_fns, 0, 0 },
16506 { "xsr.br", 267 /* xt_iclass_XSR.BR */,
16508 Opcode_xsr_br_encode_fns, 0, 0 },
16509 { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */,
16511 Opcode_rsr_ccount_encode_fns, 0, 0 },
16512 { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */,
16514 Opcode_wsr_ccount_encode_fns, 0, 0 },
16515 { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */,
16517 Opcode_xsr_ccount_encode_fns, 0, 0 },
16518 { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */,
16520 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
16521 { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */,
16523 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
16524 { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */,
16526 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
16527 { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */,
16529 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
16530 { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */,
16532 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
16533 { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */,
16535 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
16536 { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */,
16538 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
16539 { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */,
16541 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
16542 { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */,
16544 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
16545 { "ipf", 280 /* xt_iclass_icache */,
16547 Opcode_ipf_encode_fns, 0, 0 },
16548 { "ihi", 280 /* xt_iclass_icache */,
16550 Opcode_ihi_encode_fns, 0, 0 },
16551 { "ipfl", 281 /* xt_iclass_icache_lock */,
16553 Opcode_ipfl_encode_fns, 0, 0 },
16554 { "ihu", 281 /* xt_iclass_icache_lock */,
16556 Opcode_ihu_encode_fns, 0, 0 },
16557 { "iiu", 281 /* xt_iclass_icache_lock */,
16559 Opcode_iiu_encode_fns, 0, 0 },
16560 { "iii", 282 /* xt_iclass_icache_inv */,
16562 Opcode_iii_encode_fns, 0, 0 },
16563 { "lict", 283 /* xt_iclass_licx */,
16565 Opcode_lict_encode_fns, 0, 0 },
16566 { "licw", 283 /* xt_iclass_licx */,
16568 Opcode_licw_encode_fns, 0, 0 },
16569 { "sict", 284 /* xt_iclass_sicx */,
16571 Opcode_sict_encode_fns, 0, 0 },
16572 { "sicw", 284 /* xt_iclass_sicx */,
16574 Opcode_sicw_encode_fns, 0, 0 },
16575 { "dhwb", 285 /* xt_iclass_dcache */,
16577 Opcode_dhwb_encode_fns, 0, 0 },
16578 { "dhwbi", 285 /* xt_iclass_dcache */,
16580 Opcode_dhwbi_encode_fns, 0, 0 },
16581 { "diwb", 286 /* xt_iclass_dcache_ind */,
16583 Opcode_diwb_encode_fns, 0, 0 },
16584 { "diwbi", 286 /* xt_iclass_dcache_ind */,
16586 Opcode_diwbi_encode_fns, 0, 0 },
16587 { "dhi", 287 /* xt_iclass_dcache_inv */,
16589 Opcode_dhi_encode_fns, 0, 0 },
16590 { "dii", 287 /* xt_iclass_dcache_inv */,
16592 Opcode_dii_encode_fns, 0, 0 },
16593 { "dpfr", 288 /* xt_iclass_dpf */,
16595 Opcode_dpfr_encode_fns, 0, 0 },
16596 { "dpfw", 288 /* xt_iclass_dpf */,
16598 Opcode_dpfw_encode_fns, 0, 0 },
16599 { "dpfro", 288 /* xt_iclass_dpf */,
16601 Opcode_dpfro_encode_fns, 0, 0 },
16602 { "dpfwo", 288 /* xt_iclass_dpf */,
16604 Opcode_dpfwo_encode_fns, 0, 0 },
16605 { "dpfl", 289 /* xt_iclass_dcache_lock */,
16607 Opcode_dpfl_encode_fns, 0, 0 },
16608 { "dhu", 289 /* xt_iclass_dcache_lock */,
16610 Opcode_dhu_encode_fns, 0, 0 },
16611 { "diu", 289 /* xt_iclass_dcache_lock */,
16613 Opcode_diu_encode_fns, 0, 0 },
16614 { "sdct", 290 /* xt_iclass_sdct */,
16616 Opcode_sdct_encode_fns, 0, 0 },
16617 { "ldct", 291 /* xt_iclass_ldct */,
16619 Opcode_ldct_encode_fns, 0, 0 },
16620 { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */,
16622 Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
16623 { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */,
16625 Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
16626 { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */,
16628 Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
16629 { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */,
16631 Opcode_rsr_rasid_encode_fns, 0, 0 },
16632 { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */,
16634 Opcode_wsr_rasid_encode_fns, 0, 0 },
16635 { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */,
16637 Opcode_xsr_rasid_encode_fns, 0, 0 },
16638 { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */,
16640 Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
16641 { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */,
16643 Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
16644 { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */,
16646 Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
16647 { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */,
16649 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
16650 { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */,
16652 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
16653 { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */,
16655 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
16656 { "idtlb", 304 /* xt_iclass_idtlb */,
16658 Opcode_idtlb_encode_fns, 0, 0 },
16659 { "pdtlb", 305 /* xt_iclass_rdtlb */,
16661 Opcode_pdtlb_encode_fns, 0, 0 },
16662 { "rdtlb0", 305 /* xt_iclass_rdtlb */,
16664 Opcode_rdtlb0_encode_fns, 0, 0 },
16665 { "rdtlb1", 305 /* xt_iclass_rdtlb */,
16667 Opcode_rdtlb1_encode_fns, 0, 0 },
16668 { "wdtlb", 306 /* xt_iclass_wdtlb */,
16670 Opcode_wdtlb_encode_fns, 0, 0 },
16671 { "iitlb", 307 /* xt_iclass_iitlb */,
16673 Opcode_iitlb_encode_fns, 0, 0 },
16674 { "pitlb", 308 /* xt_iclass_ritlb */,
16676 Opcode_pitlb_encode_fns, 0, 0 },
16677 { "ritlb0", 308 /* xt_iclass_ritlb */,
16679 Opcode_ritlb0_encode_fns, 0, 0 },
16680 { "ritlb1", 308 /* xt_iclass_ritlb */,
16682 Opcode_ritlb1_encode_fns, 0, 0 },
16683 { "witlb", 309 /* xt_iclass_witlb */,
16685 Opcode_witlb_encode_fns, 0, 0 },
16686 { "ldpte", 310 /* xt_iclass_ldpte */,
16688 Opcode_ldpte_encode_fns, 0, 0 },
16689 { "hwwitlba", 311 /* xt_iclass_hwwitlba */,
16690 XTENSA_OPCODE_IS_BRANCH,
16691 Opcode_hwwitlba_encode_fns, 0, 0 },
16692 { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */,
16694 Opcode_hwwdtlba_encode_fns, 0, 0 },
16695 { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */,
16697 Opcode_rsr_cpenable_encode_fns, 0, 0 },
16698 { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */,
16700 Opcode_wsr_cpenable_encode_fns, 0, 0 },
16701 { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */,
16703 Opcode_xsr_cpenable_encode_fns, 0, 0 },
16704 { "clamps", 316 /* xt_iclass_clamp */,
16706 Opcode_clamps_encode_fns, 0, 0 },
16707 { "min", 317 /* xt_iclass_minmax */,
16709 Opcode_min_encode_fns, 0, 0 },
16710 { "max", 317 /* xt_iclass_minmax */,
16712 Opcode_max_encode_fns, 0, 0 },
16713 { "minu", 317 /* xt_iclass_minmax */,
16715 Opcode_minu_encode_fns, 0, 0 },
16716 { "maxu", 317 /* xt_iclass_minmax */,
16718 Opcode_maxu_encode_fns, 0, 0 },
16719 { "nsa", 318 /* xt_iclass_nsa */,
16721 Opcode_nsa_encode_fns, 0, 0 },
16722 { "nsau", 318 /* xt_iclass_nsa */,
16724 Opcode_nsau_encode_fns, 0, 0 },
16725 { "sext", 319 /* xt_iclass_sx */,
16727 Opcode_sext_encode_fns, 0, 0 },
16728 { "l32ai", 320 /* xt_iclass_l32ai */,
16730 Opcode_l32ai_encode_fns, 0, 0 },
16731 { "s32ri", 321 /* xt_iclass_s32ri */,
16733 Opcode_s32ri_encode_fns, 0, 0 },
16734 { "s32c1i", 322 /* xt_iclass_s32c1i */,
16736 Opcode_s32c1i_encode_fns, 0, 0 },
16737 { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */,
16739 Opcode_rsr_scompare1_encode_fns, 0, 0 },
16740 { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */,
16742 Opcode_wsr_scompare1_encode_fns, 0, 0 },
16743 { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */,
16745 Opcode_xsr_scompare1_encode_fns, 0, 0 },
16746 { "quou", 326 /* xt_iclass_div */,
16748 Opcode_quou_encode_fns, 0, 0 },
16749 { "quos", 326 /* xt_iclass_div */,
16751 Opcode_quos_encode_fns, 0, 0 },
16752 { "remu", 326 /* xt_iclass_div */,
16754 Opcode_remu_encode_fns, 0, 0 },
16755 { "rems", 326 /* xt_iclass_div */,
16757 Opcode_rems_encode_fns, 0, 0 },
16758 { "mull", 327 /* xt_mul32 */,
16760 Opcode_mull_encode_fns, 0, 0 },
16761 { "muluh", 327 /* xt_mul32 */,
16763 Opcode_muluh_encode_fns, 0, 0 },
16764 { "mulsh", 327 /* xt_mul32 */,
16766 Opcode_mulsh_encode_fns, 0, 0 },
16767 { "rur.fcr", 328 /* rur_fcr */,
16769 Opcode_rur_fcr_encode_fns, 0, 0 },
16770 { "wur.fcr", 329 /* wur_fcr */,
16772 Opcode_wur_fcr_encode_fns, 0, 0 },
16773 { "rur.fsr", 330 /* rur_fsr */,
16775 Opcode_rur_fsr_encode_fns, 0, 0 },
16776 { "wur.fsr", 331 /* wur_fsr */,
16778 Opcode_wur_fsr_encode_fns, 0, 0 },
16779 { "add.s", 332 /* fp */,
16781 Opcode_add_s_encode_fns, 0, 0 },
16782 { "sub.s", 332 /* fp */,
16784 Opcode_sub_s_encode_fns, 0, 0 },
16785 { "mul.s", 332 /* fp */,
16787 Opcode_mul_s_encode_fns, 0, 0 },
16788 { "madd.s", 333 /* fp_mac */,
16790 Opcode_madd_s_encode_fns, 0, 0 },
16791 { "msub.s", 333 /* fp_mac */,
16793 Opcode_msub_s_encode_fns, 0, 0 },
16794 { "movf.s", 334 /* fp_cmov */,
16796 Opcode_movf_s_encode_fns, 0, 0 },
16797 { "movt.s", 334 /* fp_cmov */,
16799 Opcode_movt_s_encode_fns, 0, 0 },
16800 { "moveqz.s", 335 /* fp_mov */,
16802 Opcode_moveqz_s_encode_fns, 0, 0 },
16803 { "movnez.s", 335 /* fp_mov */,
16805 Opcode_movnez_s_encode_fns, 0, 0 },
16806 { "movltz.s", 335 /* fp_mov */,
16808 Opcode_movltz_s_encode_fns, 0, 0 },
16809 { "movgez.s", 335 /* fp_mov */,
16811 Opcode_movgez_s_encode_fns, 0, 0 },
16812 { "abs.s", 336 /* fp_mov2 */,
16814 Opcode_abs_s_encode_fns, 0, 0 },
16815 { "mov.s", 336 /* fp_mov2 */,
16817 Opcode_mov_s_encode_fns, 0, 0 },
16818 { "neg.s", 336 /* fp_mov2 */,
16820 Opcode_neg_s_encode_fns, 0, 0 },
16821 { "un.s", 337 /* fp_cmp */,
16823 Opcode_un_s_encode_fns, 0, 0 },
16824 { "oeq.s", 337 /* fp_cmp */,
16826 Opcode_oeq_s_encode_fns, 0, 0 },
16827 { "ueq.s", 337 /* fp_cmp */,
16829 Opcode_ueq_s_encode_fns, 0, 0 },
16830 { "olt.s", 337 /* fp_cmp */,
16832 Opcode_olt_s_encode_fns, 0, 0 },
16833 { "ult.s", 337 /* fp_cmp */,
16835 Opcode_ult_s_encode_fns, 0, 0 },
16836 { "ole.s", 337 /* fp_cmp */,
16838 Opcode_ole_s_encode_fns, 0, 0 },
16839 { "ule.s", 337 /* fp_cmp */,
16841 Opcode_ule_s_encode_fns, 0, 0 },
16842 { "float.s", 338 /* fp_float */,
16844 Opcode_float_s_encode_fns, 0, 0 },
16845 { "ufloat.s", 338 /* fp_float */,
16847 Opcode_ufloat_s_encode_fns, 0, 0 },
16848 { "round.s", 339 /* fp_int */,
16850 Opcode_round_s_encode_fns, 0, 0 },
16851 { "ceil.s", 339 /* fp_int */,
16853 Opcode_ceil_s_encode_fns, 0, 0 },
16854 { "floor.s", 339 /* fp_int */,
16856 Opcode_floor_s_encode_fns, 0, 0 },
16857 { "trunc.s", 339 /* fp_int */,
16859 Opcode_trunc_s_encode_fns, 0, 0 },
16860 { "utrunc.s", 339 /* fp_int */,
16862 Opcode_utrunc_s_encode_fns, 0, 0 },
16863 { "rfr", 340 /* fp_rfr */,
16865 Opcode_rfr_encode_fns, 0, 0 },
16866 { "wfr", 341 /* fp_wfr */,
16868 Opcode_wfr_encode_fns, 0, 0 },
16869 { "lsi", 342 /* fp_lsi */,
16871 Opcode_lsi_encode_fns, 0, 0 },
16872 { "lsiu", 343 /* fp_lsiu */,
16874 Opcode_lsiu_encode_fns, 0, 0 },
16875 { "lsx", 344 /* fp_lsx */,
16877 Opcode_lsx_encode_fns, 0, 0 },
16878 { "lsxu", 345 /* fp_lsxu */,
16880 Opcode_lsxu_encode_fns, 0, 0 },
16881 { "ssi", 346 /* fp_ssi */,
16883 Opcode_ssi_encode_fns, 0, 0 },
16884 { "ssiu", 347 /* fp_ssiu */,
16886 Opcode_ssiu_encode_fns, 0, 0 },
16887 { "ssx", 348 /* fp_ssx */,
16889 Opcode_ssx_encode_fns, 0, 0 },
16890 { "ssxu", 349 /* fp_ssxu */,
16892 Opcode_ssxu_encode_fns, 0, 0 },
16893 { "beqz.w18", 350 /* xt_iclass_wb18_0 */,
16894 XTENSA_OPCODE_IS_BRANCH,
16895 Opcode_beqz_w18_encode_fns, 0, 0 },
16896 { "bnez.w18", 350 /* xt_iclass_wb18_0 */,
16897 XTENSA_OPCODE_IS_BRANCH,
16898 Opcode_bnez_w18_encode_fns, 0, 0 },
16899 { "bgez.w18", 350 /* xt_iclass_wb18_0 */,
16900 XTENSA_OPCODE_IS_BRANCH,
16901 Opcode_bgez_w18_encode_fns, 0, 0 },
16902 { "bltz.w18", 350 /* xt_iclass_wb18_0 */,
16903 XTENSA_OPCODE_IS_BRANCH,
16904 Opcode_bltz_w18_encode_fns, 0, 0 },
16905 { "beqi.w18", 351 /* xt_iclass_wb18_1 */,
16906 XTENSA_OPCODE_IS_BRANCH,
16907 Opcode_beqi_w18_encode_fns, 0, 0 },
16908 { "bnei.w18", 351 /* xt_iclass_wb18_1 */,
16909 XTENSA_OPCODE_IS_BRANCH,
16910 Opcode_bnei_w18_encode_fns, 0, 0 },
16911 { "bgei.w18", 351 /* xt_iclass_wb18_1 */,
16912 XTENSA_OPCODE_IS_BRANCH,
16913 Opcode_bgei_w18_encode_fns, 0, 0 },
16914 { "blti.w18", 351 /* xt_iclass_wb18_1 */,
16915 XTENSA_OPCODE_IS_BRANCH,
16916 Opcode_blti_w18_encode_fns, 0, 0 },
16917 { "bgeui.w18", 352 /* xt_iclass_wb18_2 */,
16918 XTENSA_OPCODE_IS_BRANCH,
16919 Opcode_bgeui_w18_encode_fns, 0, 0 },
16920 { "bltui.w18", 352 /* xt_iclass_wb18_2 */,
16921 XTENSA_OPCODE_IS_BRANCH,
16922 Opcode_bltui_w18_encode_fns, 0, 0 },
16923 { "bbci.w18", 353 /* xt_iclass_wb18_3 */,
16924 XTENSA_OPCODE_IS_BRANCH,
16925 Opcode_bbci_w18_encode_fns, 0, 0 },
16926 { "bbsi.w18", 353 /* xt_iclass_wb18_3 */,
16927 XTENSA_OPCODE_IS_BRANCH,
16928 Opcode_bbsi_w18_encode_fns, 0, 0 },
16929 { "beq.w18", 354 /* xt_iclass_wb18_4 */,
16930 XTENSA_OPCODE_IS_BRANCH,
16931 Opcode_beq_w18_encode_fns, 0, 0 },
16932 { "bne.w18", 354 /* xt_iclass_wb18_4 */,
16933 XTENSA_OPCODE_IS_BRANCH,
16934 Opcode_bne_w18_encode_fns, 0, 0 },
16935 { "bge.w18", 354 /* xt_iclass_wb18_4 */,
16936 XTENSA_OPCODE_IS_BRANCH,
16937 Opcode_bge_w18_encode_fns, 0, 0 },
16938 { "blt.w18", 354 /* xt_iclass_wb18_4 */,
16939 XTENSA_OPCODE_IS_BRANCH,
16940 Opcode_blt_w18_encode_fns, 0, 0 },
16941 { "bgeu.w18", 354 /* xt_iclass_wb18_4 */,
16942 XTENSA_OPCODE_IS_BRANCH,
16943 Opcode_bgeu_w18_encode_fns, 0, 0 },
16944 { "bltu.w18", 354 /* xt_iclass_wb18_4 */,
16945 XTENSA_OPCODE_IS_BRANCH,
16946 Opcode_bltu_w18_encode_fns, 0, 0 },
16947 { "bany.w18", 354 /* xt_iclass_wb18_4 */,
16948 XTENSA_OPCODE_IS_BRANCH,
16949 Opcode_bany_w18_encode_fns, 0, 0 },
16950 { "bnone.w18", 354 /* xt_iclass_wb18_4 */,
16951 XTENSA_OPCODE_IS_BRANCH,
16952 Opcode_bnone_w18_encode_fns, 0, 0 },
16953 { "ball.w18", 354 /* xt_iclass_wb18_4 */,
16954 XTENSA_OPCODE_IS_BRANCH,
16955 Opcode_ball_w18_encode_fns, 0, 0 },
16956 { "bnall.w18", 354 /* xt_iclass_wb18_4 */,
16957 XTENSA_OPCODE_IS_BRANCH,
16958 Opcode_bnall_w18_encode_fns, 0, 0 },
16959 { "bbc.w18", 354 /* xt_iclass_wb18_4 */,
16960 XTENSA_OPCODE_IS_BRANCH,
16961 Opcode_bbc_w18_encode_fns, 0, 0 },
16962 { "bbs.w18", 354 /* xt_iclass_wb18_4 */,
16963 XTENSA_OPCODE_IS_BRANCH,
16964 Opcode_bbs_w18_encode_fns, 0, 0 }
16968 /* Slot-specific opcode decode functions. */
16971 Slot_inst_decode (const xtensa_insnbuf insn)
16973 switch (Field_op0_Slot_inst_get (insn))
16976 switch (Field_op1_Slot_inst_get (insn))
16979 switch (Field_op2_Slot_inst_get (insn))
16982 switch (Field_r_Slot_inst_get (insn))
16985 switch (Field_m_Slot_inst_get (insn))
16988 if (Field_s_Slot_inst_get (insn) == 0 &&
16989 Field_n_Slot_inst_get (insn) == 0)
16990 return 79; /* ill */
16993 switch (Field_n_Slot_inst_get (insn))
16996 return 98; /* ret */
16998 return 14; /* retw */
17000 return 81; /* jx */
17004 switch (Field_n_Slot_inst_get (insn))
17007 return 77; /* callx0 */
17009 return 10; /* callx4 */
17011 return 9; /* callx8 */
17013 return 8; /* callx12 */
17019 return 12; /* movsp */
17021 if (Field_s_Slot_inst_get (insn) == 0)
17023 switch (Field_t_Slot_inst_get (insn))
17026 return 116; /* isync */
17028 return 117; /* rsync */
17030 return 118; /* esync */
17032 return 119; /* dsync */
17034 return 0; /* excw */
17036 return 114; /* memw */
17038 return 115; /* extw */
17040 return 97; /* nop */
17045 switch (Field_t_Slot_inst_get (insn))
17048 switch (Field_s_Slot_inst_get (insn))
17051 return 1; /* rfe */
17053 return 2; /* rfde */
17055 return 16; /* rfwo */
17057 return 17; /* rfwu */
17061 return 316; /* rfi */
17065 return 324; /* break */
17067 switch (Field_s_Slot_inst_get (insn))
17070 if (Field_t_Slot_inst_get (insn) == 0)
17071 return 3; /* syscall */
17074 if (Field_t_Slot_inst_get (insn) == 0)
17075 return 4; /* simcall */
17080 return 120; /* rsil */
17082 if (Field_t_Slot_inst_get (insn) == 0)
17083 return 317; /* waiti */
17086 return 367; /* any4 */
17088 return 368; /* all4 */
17090 return 369; /* any8 */
17092 return 370; /* all8 */
17096 return 49; /* and */
17098 return 50; /* or */
17100 return 51; /* xor */
17102 switch (Field_r_Slot_inst_get (insn))
17105 if (Field_t_Slot_inst_get (insn) == 0)
17106 return 102; /* ssr */
17109 if (Field_t_Slot_inst_get (insn) == 0)
17110 return 103; /* ssl */
17113 if (Field_t_Slot_inst_get (insn) == 0)
17114 return 104; /* ssa8l */
17117 if (Field_t_Slot_inst_get (insn) == 0)
17118 return 105; /* ssa8b */
17121 if (Field_thi3_Slot_inst_get (insn) == 0)
17122 return 106; /* ssai */
17125 if (Field_s_Slot_inst_get (insn) == 0)
17126 return 13; /* rotw */
17129 return 448; /* nsa */
17131 return 449; /* nsau */
17135 switch (Field_r_Slot_inst_get (insn))
17138 return 438; /* hwwitlba */
17140 return 434; /* ritlb0 */
17142 if (Field_t_Slot_inst_get (insn) == 0)
17143 return 432; /* iitlb */
17146 return 433; /* pitlb */
17148 return 436; /* witlb */
17150 return 435; /* ritlb1 */
17152 return 439; /* hwwdtlba */
17154 return 429; /* rdtlb0 */
17156 if (Field_t_Slot_inst_get (insn) == 0)
17157 return 427; /* idtlb */
17160 return 428; /* pdtlb */
17162 return 431; /* wdtlb */
17164 return 430; /* rdtlb1 */
17168 switch (Field_s_Slot_inst_get (insn))
17171 return 95; /* neg */
17173 return 96; /* abs */
17177 return 41; /* add */
17179 return 43; /* addx2 */
17181 return 44; /* addx4 */
17183 return 45; /* addx8 */
17185 return 42; /* sub */
17187 return 46; /* subx2 */
17189 return 47; /* subx4 */
17191 return 48; /* subx8 */
17195 switch (Field_op2_Slot_inst_get (insn))
17199 return 111; /* slli */
17202 return 112; /* srai */
17204 return 113; /* srli */
17206 switch (Field_sr_Slot_inst_get (insn))
17209 return 129; /* xsr.lbeg */
17211 return 123; /* xsr.lend */
17213 return 126; /* xsr.lcount */
17215 return 132; /* xsr.sar */
17217 return 377; /* xsr.br */
17219 return 135; /* xsr.litbase */
17221 return 456; /* xsr.scompare1 */
17223 return 312; /* xsr.acclo */
17225 return 315; /* xsr.acchi */
17227 return 300; /* xsr.m0 */
17229 return 303; /* xsr.m1 */
17231 return 306; /* xsr.m2 */
17233 return 309; /* xsr.m3 */
17235 return 22; /* xsr.windowbase */
17237 return 25; /* xsr.windowstart */
17239 return 417; /* xsr.ptevaddr */
17241 return 420; /* xsr.rasid */
17243 return 423; /* xsr.itlbcfg */
17245 return 426; /* xsr.dtlbcfg */
17247 return 346; /* xsr.ibreakenable */
17249 return 358; /* xsr.ddr */
17251 return 340; /* xsr.ibreaka0 */
17253 return 343; /* xsr.ibreaka1 */
17255 return 328; /* xsr.dbreaka0 */
17257 return 334; /* xsr.dbreaka1 */
17259 return 331; /* xsr.dbreakc0 */
17261 return 337; /* xsr.dbreakc1 */
17263 return 143; /* xsr.epc1 */
17265 return 149; /* xsr.epc2 */
17267 return 155; /* xsr.epc3 */
17269 return 161; /* xsr.epc4 */
17271 return 167; /* xsr.epc5 */
17273 return 173; /* xsr.epc6 */
17275 return 179; /* xsr.epc7 */
17277 return 206; /* xsr.depc */
17279 return 185; /* xsr.eps2 */
17281 return 188; /* xsr.eps3 */
17283 return 191; /* xsr.eps4 */
17285 return 194; /* xsr.eps5 */
17287 return 197; /* xsr.eps6 */
17289 return 200; /* xsr.eps7 */
17291 return 146; /* xsr.excsave1 */
17293 return 152; /* xsr.excsave2 */
17295 return 158; /* xsr.excsave3 */
17297 return 164; /* xsr.excsave4 */
17299 return 170; /* xsr.excsave5 */
17301 return 176; /* xsr.excsave6 */
17303 return 182; /* xsr.excsave7 */
17305 return 442; /* xsr.cpenable */
17307 return 323; /* xsr.intenable */
17309 return 140; /* xsr.ps */
17311 return 225; /* xsr.vecbase */
17313 return 209; /* xsr.exccause */
17315 return 349; /* xsr.debugcause */
17317 return 380; /* xsr.ccount */
17319 return 352; /* xsr.icount */
17321 return 355; /* xsr.icountlevel */
17323 return 203; /* xsr.excvaddr */
17325 return 383; /* xsr.ccompare0 */
17327 return 386; /* xsr.ccompare1 */
17329 return 389; /* xsr.ccompare2 */
17331 return 212; /* xsr.misc0 */
17333 return 215; /* xsr.misc1 */
17335 return 218; /* xsr.misc2 */
17337 return 221; /* xsr.misc3 */
17341 return 108; /* src */
17343 if (Field_s_Slot_inst_get (insn) == 0)
17344 return 109; /* srl */
17347 if (Field_t_Slot_inst_get (insn) == 0)
17348 return 107; /* sll */
17351 if (Field_s_Slot_inst_get (insn) == 0)
17352 return 110; /* sra */
17355 return 296; /* mul16u */
17357 return 297; /* mul16s */
17359 switch (Field_r_Slot_inst_get (insn))
17362 return 396; /* lict */
17364 return 398; /* sict */
17366 return 397; /* licw */
17368 return 399; /* sicw */
17370 return 414; /* ldct */
17372 return 413; /* sdct */
17374 if (Field_t_Slot_inst_get (insn) == 0)
17375 return 359; /* rfdo */
17376 if (Field_t_Slot_inst_get (insn) == 1)
17377 return 360; /* rfdd */
17380 return 437; /* ldpte */
17386 switch (Field_op2_Slot_inst_get (insn))
17389 return 362; /* andb */
17391 return 363; /* andbc */
17393 return 364; /* orb */
17395 return 365; /* orbc */
17397 return 366; /* xorb */
17399 return 461; /* mull */
17401 return 462; /* muluh */
17403 return 463; /* mulsh */
17405 return 457; /* quou */
17407 return 458; /* quos */
17409 return 459; /* remu */
17411 return 460; /* rems */
17415 switch (Field_op2_Slot_inst_get (insn))
17418 switch (Field_sr_Slot_inst_get (insn))
17421 return 127; /* rsr.lbeg */
17423 return 121; /* rsr.lend */
17425 return 124; /* rsr.lcount */
17427 return 130; /* rsr.sar */
17429 return 375; /* rsr.br */
17431 return 133; /* rsr.litbase */
17433 return 454; /* rsr.scompare1 */
17435 return 310; /* rsr.acclo */
17437 return 313; /* rsr.acchi */
17439 return 298; /* rsr.m0 */
17441 return 301; /* rsr.m1 */
17443 return 304; /* rsr.m2 */
17445 return 307; /* rsr.m3 */
17447 return 20; /* rsr.windowbase */
17449 return 23; /* rsr.windowstart */
17451 return 416; /* rsr.ptevaddr */
17453 return 418; /* rsr.rasid */
17455 return 421; /* rsr.itlbcfg */
17457 return 424; /* rsr.dtlbcfg */
17459 return 344; /* rsr.ibreakenable */
17461 return 356; /* rsr.ddr */
17463 return 338; /* rsr.ibreaka0 */
17465 return 341; /* rsr.ibreaka1 */
17467 return 326; /* rsr.dbreaka0 */
17469 return 332; /* rsr.dbreaka1 */
17471 return 329; /* rsr.dbreakc0 */
17473 return 335; /* rsr.dbreakc1 */
17475 return 136; /* rsr.176 */
17477 return 141; /* rsr.epc1 */
17479 return 147; /* rsr.epc2 */
17481 return 153; /* rsr.epc3 */
17483 return 159; /* rsr.epc4 */
17485 return 165; /* rsr.epc5 */
17487 return 171; /* rsr.epc6 */
17489 return 177; /* rsr.epc7 */
17491 return 204; /* rsr.depc */
17493 return 183; /* rsr.eps2 */
17495 return 186; /* rsr.eps3 */
17497 return 189; /* rsr.eps4 */
17499 return 192; /* rsr.eps5 */
17501 return 195; /* rsr.eps6 */
17503 return 198; /* rsr.eps7 */
17505 return 137; /* rsr.208 */
17507 return 144; /* rsr.excsave1 */
17509 return 150; /* rsr.excsave2 */
17511 return 156; /* rsr.excsave3 */
17513 return 162; /* rsr.excsave4 */
17515 return 168; /* rsr.excsave5 */
17517 return 174; /* rsr.excsave6 */
17519 return 180; /* rsr.excsave7 */
17521 return 440; /* rsr.cpenable */
17523 return 318; /* rsr.interrupt */
17525 return 321; /* rsr.intenable */
17527 return 138; /* rsr.ps */
17529 return 223; /* rsr.vecbase */
17531 return 207; /* rsr.exccause */
17533 return 347; /* rsr.debugcause */
17535 return 378; /* rsr.ccount */
17537 return 222; /* rsr.prid */
17539 return 350; /* rsr.icount */
17541 return 353; /* rsr.icountlevel */
17543 return 201; /* rsr.excvaddr */
17545 return 381; /* rsr.ccompare0 */
17547 return 384; /* rsr.ccompare1 */
17549 return 387; /* rsr.ccompare2 */
17551 return 210; /* rsr.misc0 */
17553 return 213; /* rsr.misc1 */
17555 return 216; /* rsr.misc2 */
17557 return 219; /* rsr.misc3 */
17561 switch (Field_sr_Slot_inst_get (insn))
17564 return 128; /* wsr.lbeg */
17566 return 122; /* wsr.lend */
17568 return 125; /* wsr.lcount */
17570 return 131; /* wsr.sar */
17572 return 376; /* wsr.br */
17574 return 134; /* wsr.litbase */
17576 return 455; /* wsr.scompare1 */
17578 return 311; /* wsr.acclo */
17580 return 314; /* wsr.acchi */
17582 return 299; /* wsr.m0 */
17584 return 302; /* wsr.m1 */
17586 return 305; /* wsr.m2 */
17588 return 308; /* wsr.m3 */
17590 return 21; /* wsr.windowbase */
17592 return 24; /* wsr.windowstart */
17594 return 415; /* wsr.ptevaddr */
17596 return 361; /* wsr.mmid */
17598 return 419; /* wsr.rasid */
17600 return 422; /* wsr.itlbcfg */
17602 return 425; /* wsr.dtlbcfg */
17604 return 345; /* wsr.ibreakenable */
17606 return 357; /* wsr.ddr */
17608 return 339; /* wsr.ibreaka0 */
17610 return 342; /* wsr.ibreaka1 */
17612 return 327; /* wsr.dbreaka0 */
17614 return 333; /* wsr.dbreaka1 */
17616 return 330; /* wsr.dbreakc0 */
17618 return 336; /* wsr.dbreakc1 */
17620 return 142; /* wsr.epc1 */
17622 return 148; /* wsr.epc2 */
17624 return 154; /* wsr.epc3 */
17626 return 160; /* wsr.epc4 */
17628 return 166; /* wsr.epc5 */
17630 return 172; /* wsr.epc6 */
17632 return 178; /* wsr.epc7 */
17634 return 205; /* wsr.depc */
17636 return 184; /* wsr.eps2 */
17638 return 187; /* wsr.eps3 */
17640 return 190; /* wsr.eps4 */
17642 return 193; /* wsr.eps5 */
17644 return 196; /* wsr.eps6 */
17646 return 199; /* wsr.eps7 */
17648 return 145; /* wsr.excsave1 */
17650 return 151; /* wsr.excsave2 */
17652 return 157; /* wsr.excsave3 */
17654 return 163; /* wsr.excsave4 */
17656 return 169; /* wsr.excsave5 */
17658 return 175; /* wsr.excsave6 */
17660 return 181; /* wsr.excsave7 */
17662 return 441; /* wsr.cpenable */
17664 return 319; /* wsr.intset */
17666 return 320; /* wsr.intclear */
17668 return 322; /* wsr.intenable */
17670 return 139; /* wsr.ps */
17672 return 224; /* wsr.vecbase */
17674 return 208; /* wsr.exccause */
17676 return 348; /* wsr.debugcause */
17678 return 379; /* wsr.ccount */
17680 return 351; /* wsr.icount */
17682 return 354; /* wsr.icountlevel */
17684 return 202; /* wsr.excvaddr */
17686 return 382; /* wsr.ccompare0 */
17688 return 385; /* wsr.ccompare1 */
17690 return 388; /* wsr.ccompare2 */
17692 return 211; /* wsr.misc0 */
17694 return 214; /* wsr.misc1 */
17696 return 217; /* wsr.misc2 */
17698 return 220; /* wsr.misc3 */
17702 return 450; /* sext */
17704 return 443; /* clamps */
17706 return 444; /* min */
17708 return 445; /* max */
17710 return 446; /* minu */
17712 return 447; /* maxu */
17714 return 91; /* moveqz */
17716 return 92; /* movnez */
17718 return 93; /* movltz */
17720 return 94; /* movgez */
17722 return 373; /* movf */
17724 return 374; /* movt */
17726 switch (Field_st_Slot_inst_get (insn))
17729 return 37; /* rur.threadptr */
17731 return 464; /* rur.fcr */
17733 return 466; /* rur.fsr */
17737 switch (Field_sr_Slot_inst_get (insn))
17740 return 38; /* wur.threadptr */
17742 return 465; /* wur.fcr */
17744 return 467; /* wur.fsr */
17751 return 78; /* extui */
17753 switch (Field_op2_Slot_inst_get (insn))
17756 return 500; /* lsx */
17758 return 501; /* lsxu */
17760 return 504; /* ssx */
17762 return 505; /* ssxu */
17766 switch (Field_op2_Slot_inst_get (insn))
17769 return 18; /* l32e */
17771 return 19; /* s32e */
17775 switch (Field_op2_Slot_inst_get (insn))
17778 return 468; /* add.s */
17780 return 469; /* sub.s */
17782 return 470; /* mul.s */
17784 return 471; /* madd.s */
17786 return 472; /* msub.s */
17788 return 491; /* round.s */
17790 return 494; /* trunc.s */
17792 return 493; /* floor.s */
17794 return 492; /* ceil.s */
17796 return 489; /* float.s */
17798 return 490; /* ufloat.s */
17800 return 495; /* utrunc.s */
17802 switch (Field_t_Slot_inst_get (insn))
17805 return 480; /* mov.s */
17807 return 479; /* abs.s */
17809 return 496; /* rfr */
17811 return 497; /* wfr */
17813 return 481; /* neg.s */
17819 switch (Field_op2_Slot_inst_get (insn))
17822 return 482; /* un.s */
17824 return 483; /* oeq.s */
17826 return 484; /* ueq.s */
17828 return 485; /* olt.s */
17830 return 486; /* ult.s */
17832 return 487; /* ole.s */
17834 return 488; /* ule.s */
17836 return 475; /* moveqz.s */
17838 return 476; /* movnez.s */
17840 return 477; /* movltz.s */
17842 return 478; /* movgez.s */
17844 return 473; /* movf.s */
17846 return 474; /* movt.s */
17852 return 85; /* l32r */
17854 switch (Field_r_Slot_inst_get (insn))
17857 return 86; /* l8ui */
17859 return 82; /* l16ui */
17861 return 84; /* l32i */
17863 return 101; /* s8i */
17865 return 99; /* s16i */
17867 return 100; /* s32i */
17869 switch (Field_t_Slot_inst_get (insn))
17872 return 406; /* dpfr */
17874 return 407; /* dpfw */
17876 return 408; /* dpfro */
17878 return 409; /* dpfwo */
17880 return 400; /* dhwb */
17882 return 401; /* dhwbi */
17884 return 404; /* dhi */
17886 return 405; /* dii */
17888 switch (Field_op1_Slot_inst_get (insn))
17891 return 410; /* dpfl */
17893 return 411; /* dhu */
17895 return 412; /* diu */
17897 return 402; /* diwb */
17899 return 403; /* diwbi */
17903 return 390; /* ipf */
17905 switch (Field_op1_Slot_inst_get (insn))
17908 return 392; /* ipfl */
17910 return 393; /* ihu */
17912 return 394; /* iiu */
17916 return 391; /* ihi */
17918 return 395; /* iii */
17922 return 83; /* l16si */
17924 return 90; /* movi */
17926 return 451; /* l32ai */
17928 return 39; /* addi */
17930 return 40; /* addmi */
17932 return 453; /* s32c1i */
17934 return 452; /* s32ri */
17938 switch (Field_r_Slot_inst_get (insn))
17941 return 498; /* lsi */
17943 return 502; /* ssi */
17945 return 499; /* lsiu */
17947 return 503; /* ssiu */
17951 switch (Field_op2_Slot_inst_get (insn))
17954 switch (Field_op1_Slot_inst_get (insn))
17957 if (Field_t3_Slot_inst_get (insn) == 0 &&
17958 Field_tlo_Slot_inst_get (insn) == 0 &&
17959 Field_r3_Slot_inst_get (insn) == 0)
17960 return 287; /* mula.dd.ll.ldinc */
17963 if (Field_t3_Slot_inst_get (insn) == 0 &&
17964 Field_tlo_Slot_inst_get (insn) == 0 &&
17965 Field_r3_Slot_inst_get (insn) == 0)
17966 return 289; /* mula.dd.hl.ldinc */
17969 if (Field_t3_Slot_inst_get (insn) == 0 &&
17970 Field_tlo_Slot_inst_get (insn) == 0 &&
17971 Field_r3_Slot_inst_get (insn) == 0)
17972 return 291; /* mula.dd.lh.ldinc */
17975 if (Field_t3_Slot_inst_get (insn) == 0 &&
17976 Field_tlo_Slot_inst_get (insn) == 0 &&
17977 Field_r3_Slot_inst_get (insn) == 0)
17978 return 293; /* mula.dd.hh.ldinc */
17983 switch (Field_op1_Slot_inst_get (insn))
17986 if (Field_t3_Slot_inst_get (insn) == 0 &&
17987 Field_tlo_Slot_inst_get (insn) == 0 &&
17988 Field_r3_Slot_inst_get (insn) == 0)
17989 return 286; /* mula.dd.ll.lddec */
17992 if (Field_t3_Slot_inst_get (insn) == 0 &&
17993 Field_tlo_Slot_inst_get (insn) == 0 &&
17994 Field_r3_Slot_inst_get (insn) == 0)
17995 return 288; /* mula.dd.hl.lddec */
17998 if (Field_t3_Slot_inst_get (insn) == 0 &&
17999 Field_tlo_Slot_inst_get (insn) == 0 &&
18000 Field_r3_Slot_inst_get (insn) == 0)
18001 return 290; /* mula.dd.lh.lddec */
18004 if (Field_t3_Slot_inst_get (insn) == 0 &&
18005 Field_tlo_Slot_inst_get (insn) == 0 &&
18006 Field_r3_Slot_inst_get (insn) == 0)
18007 return 292; /* mula.dd.hh.lddec */
18012 switch (Field_op1_Slot_inst_get (insn))
18015 if (Field_s_Slot_inst_get (insn) == 0 &&
18016 Field_w_Slot_inst_get (insn) == 0 &&
18017 Field_r3_Slot_inst_get (insn) == 0 &&
18018 Field_t3_Slot_inst_get (insn) == 0 &&
18019 Field_tlo_Slot_inst_get (insn) == 0)
18020 return 242; /* mul.dd.ll */
18023 if (Field_s_Slot_inst_get (insn) == 0 &&
18024 Field_w_Slot_inst_get (insn) == 0 &&
18025 Field_r3_Slot_inst_get (insn) == 0 &&
18026 Field_t3_Slot_inst_get (insn) == 0 &&
18027 Field_tlo_Slot_inst_get (insn) == 0)
18028 return 243; /* mul.dd.hl */
18031 if (Field_s_Slot_inst_get (insn) == 0 &&
18032 Field_w_Slot_inst_get (insn) == 0 &&
18033 Field_r3_Slot_inst_get (insn) == 0 &&
18034 Field_t3_Slot_inst_get (insn) == 0 &&
18035 Field_tlo_Slot_inst_get (insn) == 0)
18036 return 244; /* mul.dd.lh */
18039 if (Field_s_Slot_inst_get (insn) == 0 &&
18040 Field_w_Slot_inst_get (insn) == 0 &&
18041 Field_r3_Slot_inst_get (insn) == 0 &&
18042 Field_t3_Slot_inst_get (insn) == 0 &&
18043 Field_tlo_Slot_inst_get (insn) == 0)
18044 return 245; /* mul.dd.hh */
18047 if (Field_s_Slot_inst_get (insn) == 0 &&
18048 Field_w_Slot_inst_get (insn) == 0 &&
18049 Field_r3_Slot_inst_get (insn) == 0 &&
18050 Field_t3_Slot_inst_get (insn) == 0 &&
18051 Field_tlo_Slot_inst_get (insn) == 0)
18052 return 270; /* mula.dd.ll */
18055 if (Field_s_Slot_inst_get (insn) == 0 &&
18056 Field_w_Slot_inst_get (insn) == 0 &&
18057 Field_r3_Slot_inst_get (insn) == 0 &&
18058 Field_t3_Slot_inst_get (insn) == 0 &&
18059 Field_tlo_Slot_inst_get (insn) == 0)
18060 return 271; /* mula.dd.hl */
18063 if (Field_s_Slot_inst_get (insn) == 0 &&
18064 Field_w_Slot_inst_get (insn) == 0 &&
18065 Field_r3_Slot_inst_get (insn) == 0 &&
18066 Field_t3_Slot_inst_get (insn) == 0 &&
18067 Field_tlo_Slot_inst_get (insn) == 0)
18068 return 272; /* mula.dd.lh */
18071 if (Field_s_Slot_inst_get (insn) == 0 &&
18072 Field_w_Slot_inst_get (insn) == 0 &&
18073 Field_r3_Slot_inst_get (insn) == 0 &&
18074 Field_t3_Slot_inst_get (insn) == 0 &&
18075 Field_tlo_Slot_inst_get (insn) == 0)
18076 return 273; /* mula.dd.hh */
18079 if (Field_s_Slot_inst_get (insn) == 0 &&
18080 Field_w_Slot_inst_get (insn) == 0 &&
18081 Field_r3_Slot_inst_get (insn) == 0 &&
18082 Field_t3_Slot_inst_get (insn) == 0 &&
18083 Field_tlo_Slot_inst_get (insn) == 0)
18084 return 274; /* muls.dd.ll */
18087 if (Field_s_Slot_inst_get (insn) == 0 &&
18088 Field_w_Slot_inst_get (insn) == 0 &&
18089 Field_r3_Slot_inst_get (insn) == 0 &&
18090 Field_t3_Slot_inst_get (insn) == 0 &&
18091 Field_tlo_Slot_inst_get (insn) == 0)
18092 return 275; /* muls.dd.hl */
18095 if (Field_s_Slot_inst_get (insn) == 0 &&
18096 Field_w_Slot_inst_get (insn) == 0 &&
18097 Field_r3_Slot_inst_get (insn) == 0 &&
18098 Field_t3_Slot_inst_get (insn) == 0 &&
18099 Field_tlo_Slot_inst_get (insn) == 0)
18100 return 276; /* muls.dd.lh */
18103 if (Field_s_Slot_inst_get (insn) == 0 &&
18104 Field_w_Slot_inst_get (insn) == 0 &&
18105 Field_r3_Slot_inst_get (insn) == 0 &&
18106 Field_t3_Slot_inst_get (insn) == 0 &&
18107 Field_tlo_Slot_inst_get (insn) == 0)
18108 return 277; /* muls.dd.hh */
18113 switch (Field_op1_Slot_inst_get (insn))
18116 if (Field_r_Slot_inst_get (insn) == 0 &&
18117 Field_t3_Slot_inst_get (insn) == 0 &&
18118 Field_tlo_Slot_inst_get (insn) == 0)
18119 return 234; /* mul.ad.ll */
18122 if (Field_r_Slot_inst_get (insn) == 0 &&
18123 Field_t3_Slot_inst_get (insn) == 0 &&
18124 Field_tlo_Slot_inst_get (insn) == 0)
18125 return 235; /* mul.ad.hl */
18128 if (Field_r_Slot_inst_get (insn) == 0 &&
18129 Field_t3_Slot_inst_get (insn) == 0 &&
18130 Field_tlo_Slot_inst_get (insn) == 0)
18131 return 236; /* mul.ad.lh */
18134 if (Field_r_Slot_inst_get (insn) == 0 &&
18135 Field_t3_Slot_inst_get (insn) == 0 &&
18136 Field_tlo_Slot_inst_get (insn) == 0)
18137 return 237; /* mul.ad.hh */
18140 if (Field_r_Slot_inst_get (insn) == 0 &&
18141 Field_t3_Slot_inst_get (insn) == 0 &&
18142 Field_tlo_Slot_inst_get (insn) == 0)
18143 return 254; /* mula.ad.ll */
18146 if (Field_r_Slot_inst_get (insn) == 0 &&
18147 Field_t3_Slot_inst_get (insn) == 0 &&
18148 Field_tlo_Slot_inst_get (insn) == 0)
18149 return 255; /* mula.ad.hl */
18152 if (Field_r_Slot_inst_get (insn) == 0 &&
18153 Field_t3_Slot_inst_get (insn) == 0 &&
18154 Field_tlo_Slot_inst_get (insn) == 0)
18155 return 256; /* mula.ad.lh */
18158 if (Field_r_Slot_inst_get (insn) == 0 &&
18159 Field_t3_Slot_inst_get (insn) == 0 &&
18160 Field_tlo_Slot_inst_get (insn) == 0)
18161 return 257; /* mula.ad.hh */
18164 if (Field_r_Slot_inst_get (insn) == 0 &&
18165 Field_t3_Slot_inst_get (insn) == 0 &&
18166 Field_tlo_Slot_inst_get (insn) == 0)
18167 return 258; /* muls.ad.ll */
18170 if (Field_r_Slot_inst_get (insn) == 0 &&
18171 Field_t3_Slot_inst_get (insn) == 0 &&
18172 Field_tlo_Slot_inst_get (insn) == 0)
18173 return 259; /* muls.ad.hl */
18176 if (Field_r_Slot_inst_get (insn) == 0 &&
18177 Field_t3_Slot_inst_get (insn) == 0 &&
18178 Field_tlo_Slot_inst_get (insn) == 0)
18179 return 260; /* muls.ad.lh */
18182 if (Field_r_Slot_inst_get (insn) == 0 &&
18183 Field_t3_Slot_inst_get (insn) == 0 &&
18184 Field_tlo_Slot_inst_get (insn) == 0)
18185 return 261; /* muls.ad.hh */
18190 switch (Field_op1_Slot_inst_get (insn))
18193 if (Field_r3_Slot_inst_get (insn) == 0)
18194 return 279; /* mula.da.ll.ldinc */
18197 if (Field_r3_Slot_inst_get (insn) == 0)
18198 return 281; /* mula.da.hl.ldinc */
18201 if (Field_r3_Slot_inst_get (insn) == 0)
18202 return 283; /* mula.da.lh.ldinc */
18205 if (Field_r3_Slot_inst_get (insn) == 0)
18206 return 285; /* mula.da.hh.ldinc */
18211 switch (Field_op1_Slot_inst_get (insn))
18214 if (Field_r3_Slot_inst_get (insn) == 0)
18215 return 278; /* mula.da.ll.lddec */
18218 if (Field_r3_Slot_inst_get (insn) == 0)
18219 return 280; /* mula.da.hl.lddec */
18222 if (Field_r3_Slot_inst_get (insn) == 0)
18223 return 282; /* mula.da.lh.lddec */
18226 if (Field_r3_Slot_inst_get (insn) == 0)
18227 return 284; /* mula.da.hh.lddec */
18232 switch (Field_op1_Slot_inst_get (insn))
18235 if (Field_s_Slot_inst_get (insn) == 0 &&
18236 Field_w_Slot_inst_get (insn) == 0 &&
18237 Field_r3_Slot_inst_get (insn) == 0)
18238 return 238; /* mul.da.ll */
18241 if (Field_s_Slot_inst_get (insn) == 0 &&
18242 Field_w_Slot_inst_get (insn) == 0 &&
18243 Field_r3_Slot_inst_get (insn) == 0)
18244 return 239; /* mul.da.hl */
18247 if (Field_s_Slot_inst_get (insn) == 0 &&
18248 Field_w_Slot_inst_get (insn) == 0 &&
18249 Field_r3_Slot_inst_get (insn) == 0)
18250 return 240; /* mul.da.lh */
18253 if (Field_s_Slot_inst_get (insn) == 0 &&
18254 Field_w_Slot_inst_get (insn) == 0 &&
18255 Field_r3_Slot_inst_get (insn) == 0)
18256 return 241; /* mul.da.hh */
18259 if (Field_s_Slot_inst_get (insn) == 0 &&
18260 Field_w_Slot_inst_get (insn) == 0 &&
18261 Field_r3_Slot_inst_get (insn) == 0)
18262 return 262; /* mula.da.ll */
18265 if (Field_s_Slot_inst_get (insn) == 0 &&
18266 Field_w_Slot_inst_get (insn) == 0 &&
18267 Field_r3_Slot_inst_get (insn) == 0)
18268 return 263; /* mula.da.hl */
18271 if (Field_s_Slot_inst_get (insn) == 0 &&
18272 Field_w_Slot_inst_get (insn) == 0 &&
18273 Field_r3_Slot_inst_get (insn) == 0)
18274 return 264; /* mula.da.lh */
18277 if (Field_s_Slot_inst_get (insn) == 0 &&
18278 Field_w_Slot_inst_get (insn) == 0 &&
18279 Field_r3_Slot_inst_get (insn) == 0)
18280 return 265; /* mula.da.hh */
18283 if (Field_s_Slot_inst_get (insn) == 0 &&
18284 Field_w_Slot_inst_get (insn) == 0 &&
18285 Field_r3_Slot_inst_get (insn) == 0)
18286 return 266; /* muls.da.ll */
18289 if (Field_s_Slot_inst_get (insn) == 0 &&
18290 Field_w_Slot_inst_get (insn) == 0 &&
18291 Field_r3_Slot_inst_get (insn) == 0)
18292 return 267; /* muls.da.hl */
18295 if (Field_s_Slot_inst_get (insn) == 0 &&
18296 Field_w_Slot_inst_get (insn) == 0 &&
18297 Field_r3_Slot_inst_get (insn) == 0)
18298 return 268; /* muls.da.lh */
18301 if (Field_s_Slot_inst_get (insn) == 0 &&
18302 Field_w_Slot_inst_get (insn) == 0 &&
18303 Field_r3_Slot_inst_get (insn) == 0)
18304 return 269; /* muls.da.hh */
18309 switch (Field_op1_Slot_inst_get (insn))
18312 if (Field_r_Slot_inst_get (insn) == 0)
18313 return 230; /* umul.aa.ll */
18316 if (Field_r_Slot_inst_get (insn) == 0)
18317 return 231; /* umul.aa.hl */
18320 if (Field_r_Slot_inst_get (insn) == 0)
18321 return 232; /* umul.aa.lh */
18324 if (Field_r_Slot_inst_get (insn) == 0)
18325 return 233; /* umul.aa.hh */
18328 if (Field_r_Slot_inst_get (insn) == 0)
18329 return 226; /* mul.aa.ll */
18332 if (Field_r_Slot_inst_get (insn) == 0)
18333 return 227; /* mul.aa.hl */
18336 if (Field_r_Slot_inst_get (insn) == 0)
18337 return 228; /* mul.aa.lh */
18340 if (Field_r_Slot_inst_get (insn) == 0)
18341 return 229; /* mul.aa.hh */
18344 if (Field_r_Slot_inst_get (insn) == 0)
18345 return 246; /* mula.aa.ll */
18348 if (Field_r_Slot_inst_get (insn) == 0)
18349 return 247; /* mula.aa.hl */
18352 if (Field_r_Slot_inst_get (insn) == 0)
18353 return 248; /* mula.aa.lh */
18356 if (Field_r_Slot_inst_get (insn) == 0)
18357 return 249; /* mula.aa.hh */
18360 if (Field_r_Slot_inst_get (insn) == 0)
18361 return 250; /* muls.aa.ll */
18364 if (Field_r_Slot_inst_get (insn) == 0)
18365 return 251; /* muls.aa.hl */
18368 if (Field_r_Slot_inst_get (insn) == 0)
18369 return 252; /* muls.aa.lh */
18372 if (Field_r_Slot_inst_get (insn) == 0)
18373 return 253; /* muls.aa.hh */
18378 if (Field_op1_Slot_inst_get (insn) == 0 &&
18379 Field_t_Slot_inst_get (insn) == 0 &&
18380 Field_rhi_Slot_inst_get (insn) == 0)
18381 return 295; /* ldinc */
18384 if (Field_op1_Slot_inst_get (insn) == 0 &&
18385 Field_t_Slot_inst_get (insn) == 0 &&
18386 Field_rhi_Slot_inst_get (insn) == 0)
18387 return 294; /* lddec */
18392 switch (Field_n_Slot_inst_get (insn))
18395 return 76; /* call0 */
18397 return 7; /* call4 */
18399 return 6; /* call8 */
18401 return 5; /* call12 */
18405 switch (Field_n_Slot_inst_get (insn))
18410 switch (Field_m_Slot_inst_get (insn))
18413 return 72; /* beqz */
18415 return 73; /* bnez */
18417 return 75; /* bltz */
18419 return 74; /* bgez */
18423 switch (Field_m_Slot_inst_get (insn))
18426 return 52; /* beqi */
18428 return 53; /* bnei */
18430 return 55; /* blti */
18432 return 54; /* bgei */
18436 switch (Field_m_Slot_inst_get (insn))
18439 return 11; /* entry */
18441 switch (Field_r_Slot_inst_get (insn))
18444 return 371; /* bf */
18446 return 372; /* bt */
18448 return 87; /* loop */
18450 return 88; /* loopnez */
18452 return 89; /* loopgtz */
18456 return 59; /* bltui */
18458 return 58; /* bgeui */
18464 switch (Field_r_Slot_inst_get (insn))
18467 return 67; /* bnone */
18469 return 60; /* beq */
18471 return 63; /* blt */
18473 return 65; /* bltu */
18475 return 68; /* ball */
18477 return 70; /* bbc */
18480 return 56; /* bbci */
18482 return 66; /* bany */
18484 return 61; /* bne */
18486 return 62; /* bge */
18488 return 64; /* bgeu */
18490 return 69; /* bnall */
18492 return 71; /* bbs */
18495 return 57; /* bbsi */
18503 Slot_inst16b_decode (const xtensa_insnbuf insn)
18505 switch (Field_op0_Slot_inst16b_get (insn))
18508 switch (Field_i_Slot_inst16b_get (insn))
18511 return 33; /* movi.n */
18513 switch (Field_z_Slot_inst16b_get (insn))
18516 return 28; /* beqz.n */
18518 return 29; /* bnez.n */
18524 switch (Field_r_Slot_inst16b_get (insn))
18527 return 32; /* mov.n */
18529 switch (Field_t_Slot_inst16b_get (insn))
18532 return 35; /* ret.n */
18534 return 15; /* retw.n */
18536 return 325; /* break.n */
18538 if (Field_s_Slot_inst16b_get (insn) == 0)
18539 return 34; /* nop.n */
18542 if (Field_s_Slot_inst16b_get (insn) == 0)
18543 return 30; /* ill.n */
18554 Slot_inst16a_decode (const xtensa_insnbuf insn)
18556 switch (Field_op0_Slot_inst16a_get (insn))
18559 return 31; /* l32i.n */
18561 return 36; /* s32i.n */
18563 return 26; /* add.n */
18565 return 27; /* addi.n */
18571 Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn)
18573 switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn))
18576 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
18577 return 41; /* add */
18578 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
18579 return 42; /* sub */
18580 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
18581 return 43; /* addx2 */
18582 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
18583 return 49; /* and */
18584 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
18585 return 450; /* sext */
18588 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
18589 return 27; /* addi.n */
18590 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
18591 return 44; /* addx4 */
18592 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
18593 return 50; /* or */
18594 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
18595 return 51; /* xor */
18596 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
18597 return 113; /* srli */
18600 if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 &&
18601 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6)
18602 return 33; /* movi.n */
18603 if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 &&
18604 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18605 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18606 return 32; /* mov.n */
18607 if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
18608 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18609 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18610 return 97; /* nop */
18611 if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 &&
18612 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18613 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18614 return 96; /* abs */
18615 if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 &&
18616 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18617 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18618 return 95; /* neg */
18619 if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 &&
18620 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18621 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18622 return 110; /* sra */
18623 if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
18624 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18625 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18626 return 109; /* srl */
18627 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7)
18628 return 112; /* srai */
18633 Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn)
18635 switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn))
18638 if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2)
18639 return 78; /* extui */
18640 switch (Field_op1_Slot_xt_flix64_slot0_get (insn))
18643 switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18646 if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2)
18648 if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18650 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15)
18651 return 97; /* nop */
18656 return 49; /* and */
18658 return 50; /* or */
18660 return 51; /* xor */
18662 switch (Field_r_Slot_xt_flix64_slot0_get (insn))
18665 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18666 return 102; /* ssr */
18669 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18670 return 103; /* ssl */
18673 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18674 return 104; /* ssa8l */
18677 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18678 return 105; /* ssa8b */
18681 if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0)
18682 return 106; /* ssai */
18685 return 448; /* nsa */
18687 return 449; /* nsau */
18691 switch (Field_s_Slot_xt_flix64_slot0_get (insn))
18694 return 95; /* neg */
18696 return 96; /* abs */
18700 return 41; /* add */
18702 return 43; /* addx2 */
18704 return 44; /* addx4 */
18706 return 45; /* addx8 */
18708 return 42; /* sub */
18710 return 46; /* subx2 */
18712 return 47; /* subx4 */
18714 return 48; /* subx8 */
18718 if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1)
18719 return 112; /* srai */
18720 if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0)
18721 return 111; /* slli */
18722 switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18725 return 113; /* srli */
18727 return 108; /* src */
18729 if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18730 return 109; /* srl */
18733 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18734 return 107; /* sll */
18737 if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18738 return 110; /* sra */
18741 return 296; /* mul16u */
18743 return 297; /* mul16s */
18747 if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8)
18748 return 461; /* mull */
18751 switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18754 return 450; /* sext */
18756 return 443; /* clamps */
18758 return 444; /* min */
18760 return 445; /* max */
18762 return 446; /* minu */
18764 return 447; /* maxu */
18766 return 91; /* moveqz */
18768 return 92; /* movnez */
18770 return 93; /* movltz */
18772 return 94; /* movgez */
18778 switch (Field_r_Slot_xt_flix64_slot0_get (insn))
18781 return 86; /* l8ui */
18783 return 82; /* l16ui */
18785 return 84; /* l32i */
18787 return 101; /* s8i */
18789 return 99; /* s16i */
18791 return 100; /* s32i */
18793 return 83; /* l16si */
18795 return 90; /* movi */
18797 return 39; /* addi */
18799 return 40; /* addmi */
18803 if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1)
18804 return 85; /* l32r */
18805 if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 &&
18806 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 &&
18807 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 &&
18808 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0)
18809 return 32; /* mov.n */
18814 Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn)
18816 if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 &&
18817 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18818 return 78; /* extui */
18819 switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18822 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18823 return 90; /* movi */
18826 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18827 return 39; /* addi */
18830 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18831 return 40; /* addmi */
18832 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18833 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0)
18834 return 51; /* xor */
18837 switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18840 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18841 return 111; /* slli */
18844 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18845 return 112; /* srai */
18848 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18849 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18850 return 107; /* sll */
18853 switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18856 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18857 return 41; /* add */
18860 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18861 return 45; /* addx8 */
18864 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18865 return 43; /* addx2 */
18868 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18869 return 49; /* and */
18872 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18873 return 91; /* moveqz */
18876 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18877 return 94; /* movgez */
18880 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18881 return 44; /* addx4 */
18884 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18885 return 93; /* movltz */
18888 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18889 return 92; /* movnez */
18892 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18893 return 296; /* mul16u */
18896 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18897 return 297; /* mul16s */
18900 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18901 return 461; /* mull */
18904 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18905 return 50; /* or */
18908 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18909 return 450; /* sext */
18912 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18913 return 108; /* src */
18916 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18917 return 113; /* srli */
18920 if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 &&
18921 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18922 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18923 return 32; /* mov.n */
18924 if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 &&
18925 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18926 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18927 return 81; /* jx */
18928 if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 &&
18929 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18930 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18931 return 103; /* ssl */
18932 if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 &&
18933 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18934 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18935 return 97; /* nop */
18936 if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 &&
18937 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18938 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18939 return 95; /* neg */
18940 if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 &&
18941 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18942 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18943 return 110; /* sra */
18944 if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 &&
18945 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18946 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18947 return 109; /* srl */
18948 if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 &&
18949 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18950 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18951 return 42; /* sub */
18952 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3)
18958 Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn)
18960 switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn))
18963 if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
18964 return 516; /* bbci.w18 */
18967 if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
18968 return 517; /* bbsi.w18 */
18971 if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18972 return 526; /* ball.w18 */
18975 if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18976 return 524; /* bany.w18 */
18979 if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18980 return 528; /* bbc.w18 */
18983 if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18984 return 529; /* bbs.w18 */
18987 if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18988 return 518; /* beq.w18 */
18991 if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18992 return 510; /* beqi.w18 */
18995 if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18996 return 520; /* bge.w18 */
18999 if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19000 return 512; /* bgei.w18 */
19003 if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19004 return 522; /* bgeu.w18 */
19007 if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19008 return 514; /* bgeui.w18 */
19011 if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19012 return 521; /* blt.w18 */
19015 if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19016 return 513; /* blti.w18 */
19019 if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19020 return 523; /* bltu.w18 */
19023 if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19024 return 515; /* bltui.w18 */
19027 if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19028 return 527; /* bnall.w18 */
19031 if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19032 return 519; /* bne.w18 */
19035 if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19036 return 511; /* bnei.w18 */
19039 if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19040 return 525; /* bnone.w18 */
19043 if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19044 return 506; /* beqz.w18 */
19047 if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19048 return 508; /* bgez.w18 */
19051 if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19052 return 509; /* bltz.w18 */
19055 if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19056 return 507; /* bnez.w18 */
19059 if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19060 return 97; /* nop */
19067 /* Instruction slots. */
19070 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
19071 xtensa_insnbuf slotbuf)
19074 slotbuf[0] = (insn[0] & 0xffffff);
19078 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
19079 const xtensa_insnbuf slotbuf)
19081 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
19085 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
19086 xtensa_insnbuf slotbuf)
19089 slotbuf[0] = (insn[0] & 0xffff);
19093 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
19094 const xtensa_insnbuf slotbuf)
19096 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
19100 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
19101 xtensa_insnbuf slotbuf)
19104 slotbuf[0] = (insn[0] & 0xffff);
19108 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
19109 const xtensa_insnbuf slotbuf)
19111 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
19115 Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
19116 xtensa_insnbuf slotbuf)
19119 slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
19123 Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
19124 const xtensa_insnbuf slotbuf)
19126 insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
19130 Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
19131 xtensa_insnbuf slotbuf)
19134 slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
19138 Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
19139 const xtensa_insnbuf slotbuf)
19141 insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
19145 Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn,
19146 xtensa_insnbuf slotbuf)
19149 slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
19150 slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4);
19154 Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn,
19155 const xtensa_insnbuf slotbuf)
19157 insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
19158 insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4);
19162 Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn,
19163 xtensa_insnbuf slotbuf)
19166 slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
19170 Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn,
19171 const xtensa_insnbuf slotbuf)
19173 insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
19177 Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn,
19178 xtensa_insnbuf slotbuf)
19180 slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
19181 slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4);
19182 slotbuf[1] = ((insn[1] & 0x70000000) >> 28);
19186 Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn,
19187 const xtensa_insnbuf slotbuf)
19189 insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
19190 insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4);
19191 insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28);
19194 static xtensa_get_field_fn
19195 Slot_inst_get_field_fns[] = {
19196 Field_t_Slot_inst_get,
19197 Field_bbi4_Slot_inst_get,
19198 Field_bbi_Slot_inst_get,
19199 Field_imm12_Slot_inst_get,
19200 Field_imm8_Slot_inst_get,
19201 Field_s_Slot_inst_get,
19202 Field_imm12b_Slot_inst_get,
19203 Field_imm16_Slot_inst_get,
19204 Field_m_Slot_inst_get,
19205 Field_n_Slot_inst_get,
19206 Field_offset_Slot_inst_get,
19207 Field_op0_Slot_inst_get,
19208 Field_op1_Slot_inst_get,
19209 Field_op2_Slot_inst_get,
19210 Field_r_Slot_inst_get,
19211 Field_sa4_Slot_inst_get,
19212 Field_sae4_Slot_inst_get,
19213 Field_sae_Slot_inst_get,
19214 Field_sal_Slot_inst_get,
19215 Field_sargt_Slot_inst_get,
19216 Field_sas4_Slot_inst_get,
19217 Field_sas_Slot_inst_get,
19218 Field_sr_Slot_inst_get,
19219 Field_st_Slot_inst_get,
19220 Field_thi3_Slot_inst_get,
19221 Field_imm4_Slot_inst_get,
19222 Field_mn_Slot_inst_get,
19231 Field_r3_Slot_inst_get,
19232 Field_rbit2_Slot_inst_get,
19233 Field_rhi_Slot_inst_get,
19234 Field_t3_Slot_inst_get,
19235 Field_tbit2_Slot_inst_get,
19236 Field_tlo_Slot_inst_get,
19237 Field_w_Slot_inst_get,
19238 Field_y_Slot_inst_get,
19239 Field_x_Slot_inst_get,
19240 Field_t2_Slot_inst_get,
19241 Field_s2_Slot_inst_get,
19242 Field_r2_Slot_inst_get,
19243 Field_t4_Slot_inst_get,
19244 Field_s4_Slot_inst_get,
19245 Field_r4_Slot_inst_get,
19246 Field_t8_Slot_inst_get,
19247 Field_s8_Slot_inst_get,
19248 Field_r8_Slot_inst_get,
19249 Field_xt_wbr15_imm_Slot_inst_get,
19250 Field_xt_wbr18_imm_Slot_inst_get,
19319 Implicit_Field_ar0_get,
19320 Implicit_Field_ar4_get,
19321 Implicit_Field_ar8_get,
19322 Implicit_Field_ar12_get,
19323 Implicit_Field_mr0_get,
19324 Implicit_Field_mr1_get,
19325 Implicit_Field_mr2_get,
19326 Implicit_Field_mr3_get,
19327 Implicit_Field_bt16_get,
19328 Implicit_Field_bs16_get,
19329 Implicit_Field_br16_get,
19330 Implicit_Field_brall_get
19333 static xtensa_set_field_fn
19334 Slot_inst_set_field_fns[] = {
19335 Field_t_Slot_inst_set,
19336 Field_bbi4_Slot_inst_set,
19337 Field_bbi_Slot_inst_set,
19338 Field_imm12_Slot_inst_set,
19339 Field_imm8_Slot_inst_set,
19340 Field_s_Slot_inst_set,
19341 Field_imm12b_Slot_inst_set,
19342 Field_imm16_Slot_inst_set,
19343 Field_m_Slot_inst_set,
19344 Field_n_Slot_inst_set,
19345 Field_offset_Slot_inst_set,
19346 Field_op0_Slot_inst_set,
19347 Field_op1_Slot_inst_set,
19348 Field_op2_Slot_inst_set,
19349 Field_r_Slot_inst_set,
19350 Field_sa4_Slot_inst_set,
19351 Field_sae4_Slot_inst_set,
19352 Field_sae_Slot_inst_set,
19353 Field_sal_Slot_inst_set,
19354 Field_sargt_Slot_inst_set,
19355 Field_sas4_Slot_inst_set,
19356 Field_sas_Slot_inst_set,
19357 Field_sr_Slot_inst_set,
19358 Field_st_Slot_inst_set,
19359 Field_thi3_Slot_inst_set,
19360 Field_imm4_Slot_inst_set,
19361 Field_mn_Slot_inst_set,
19370 Field_r3_Slot_inst_set,
19371 Field_rbit2_Slot_inst_set,
19372 Field_rhi_Slot_inst_set,
19373 Field_t3_Slot_inst_set,
19374 Field_tbit2_Slot_inst_set,
19375 Field_tlo_Slot_inst_set,
19376 Field_w_Slot_inst_set,
19377 Field_y_Slot_inst_set,
19378 Field_x_Slot_inst_set,
19379 Field_t2_Slot_inst_set,
19380 Field_s2_Slot_inst_set,
19381 Field_r2_Slot_inst_set,
19382 Field_t4_Slot_inst_set,
19383 Field_s4_Slot_inst_set,
19384 Field_r4_Slot_inst_set,
19385 Field_t8_Slot_inst_set,
19386 Field_s8_Slot_inst_set,
19387 Field_r8_Slot_inst_set,
19388 Field_xt_wbr15_imm_Slot_inst_set,
19389 Field_xt_wbr18_imm_Slot_inst_set,
19458 Implicit_Field_set,
19459 Implicit_Field_set,
19460 Implicit_Field_set,
19461 Implicit_Field_set,
19462 Implicit_Field_set,
19463 Implicit_Field_set,
19464 Implicit_Field_set,
19465 Implicit_Field_set,
19466 Implicit_Field_set,
19467 Implicit_Field_set,
19468 Implicit_Field_set,
19472 static xtensa_get_field_fn
19473 Slot_inst16a_get_field_fns[] = {
19474 Field_t_Slot_inst16a_get,
19479 Field_s_Slot_inst16a_get,
19485 Field_op0_Slot_inst16a_get,
19488 Field_r_Slot_inst16a_get,
19496 Field_sr_Slot_inst16a_get,
19497 Field_st_Slot_inst16a_get,
19499 Field_imm4_Slot_inst16a_get,
19501 Field_i_Slot_inst16a_get,
19502 Field_imm6lo_Slot_inst16a_get,
19503 Field_imm6hi_Slot_inst16a_get,
19504 Field_imm7lo_Slot_inst16a_get,
19505 Field_imm7hi_Slot_inst16a_get,
19506 Field_z_Slot_inst16a_get,
19507 Field_imm6_Slot_inst16a_get,
19508 Field_imm7_Slot_inst16a_get,
19518 Field_t2_Slot_inst16a_get,
19519 Field_s2_Slot_inst16a_get,
19520 Field_r2_Slot_inst16a_get,
19521 Field_t4_Slot_inst16a_get,
19522 Field_s4_Slot_inst16a_get,
19523 Field_r4_Slot_inst16a_get,
19524 Field_t8_Slot_inst16a_get,
19525 Field_s8_Slot_inst16a_get,
19526 Field_r8_Slot_inst16a_get,
19597 Implicit_Field_ar0_get,
19598 Implicit_Field_ar4_get,
19599 Implicit_Field_ar8_get,
19600 Implicit_Field_ar12_get,
19601 Implicit_Field_mr0_get,
19602 Implicit_Field_mr1_get,
19603 Implicit_Field_mr2_get,
19604 Implicit_Field_mr3_get,
19605 Implicit_Field_bt16_get,
19606 Implicit_Field_bs16_get,
19607 Implicit_Field_br16_get,
19608 Implicit_Field_brall_get
19611 static xtensa_set_field_fn
19612 Slot_inst16a_set_field_fns[] = {
19613 Field_t_Slot_inst16a_set,
19618 Field_s_Slot_inst16a_set,
19624 Field_op0_Slot_inst16a_set,
19627 Field_r_Slot_inst16a_set,
19635 Field_sr_Slot_inst16a_set,
19636 Field_st_Slot_inst16a_set,
19638 Field_imm4_Slot_inst16a_set,
19640 Field_i_Slot_inst16a_set,
19641 Field_imm6lo_Slot_inst16a_set,
19642 Field_imm6hi_Slot_inst16a_set,
19643 Field_imm7lo_Slot_inst16a_set,
19644 Field_imm7hi_Slot_inst16a_set,
19645 Field_z_Slot_inst16a_set,
19646 Field_imm6_Slot_inst16a_set,
19647 Field_imm7_Slot_inst16a_set,
19657 Field_t2_Slot_inst16a_set,
19658 Field_s2_Slot_inst16a_set,
19659 Field_r2_Slot_inst16a_set,
19660 Field_t4_Slot_inst16a_set,
19661 Field_s4_Slot_inst16a_set,
19662 Field_r4_Slot_inst16a_set,
19663 Field_t8_Slot_inst16a_set,
19664 Field_s8_Slot_inst16a_set,
19665 Field_r8_Slot_inst16a_set,
19736 Implicit_Field_set,
19737 Implicit_Field_set,
19738 Implicit_Field_set,
19739 Implicit_Field_set,
19740 Implicit_Field_set,
19741 Implicit_Field_set,
19742 Implicit_Field_set,
19743 Implicit_Field_set,
19744 Implicit_Field_set,
19745 Implicit_Field_set,
19746 Implicit_Field_set,
19750 static xtensa_get_field_fn
19751 Slot_inst16b_get_field_fns[] = {
19752 Field_t_Slot_inst16b_get,
19757 Field_s_Slot_inst16b_get,
19763 Field_op0_Slot_inst16b_get,
19766 Field_r_Slot_inst16b_get,
19774 Field_sr_Slot_inst16b_get,
19775 Field_st_Slot_inst16b_get,
19777 Field_imm4_Slot_inst16b_get,
19779 Field_i_Slot_inst16b_get,
19780 Field_imm6lo_Slot_inst16b_get,
19781 Field_imm6hi_Slot_inst16b_get,
19782 Field_imm7lo_Slot_inst16b_get,
19783 Field_imm7hi_Slot_inst16b_get,
19784 Field_z_Slot_inst16b_get,
19785 Field_imm6_Slot_inst16b_get,
19786 Field_imm7_Slot_inst16b_get,
19796 Field_t2_Slot_inst16b_get,
19797 Field_s2_Slot_inst16b_get,
19798 Field_r2_Slot_inst16b_get,
19799 Field_t4_Slot_inst16b_get,
19800 Field_s4_Slot_inst16b_get,
19801 Field_r4_Slot_inst16b_get,
19802 Field_t8_Slot_inst16b_get,
19803 Field_s8_Slot_inst16b_get,
19804 Field_r8_Slot_inst16b_get,
19875 Implicit_Field_ar0_get,
19876 Implicit_Field_ar4_get,
19877 Implicit_Field_ar8_get,
19878 Implicit_Field_ar12_get,
19879 Implicit_Field_mr0_get,
19880 Implicit_Field_mr1_get,
19881 Implicit_Field_mr2_get,
19882 Implicit_Field_mr3_get,
19883 Implicit_Field_bt16_get,
19884 Implicit_Field_bs16_get,
19885 Implicit_Field_br16_get,
19886 Implicit_Field_brall_get
19889 static xtensa_set_field_fn
19890 Slot_inst16b_set_field_fns[] = {
19891 Field_t_Slot_inst16b_set,
19896 Field_s_Slot_inst16b_set,
19902 Field_op0_Slot_inst16b_set,
19905 Field_r_Slot_inst16b_set,
19913 Field_sr_Slot_inst16b_set,
19914 Field_st_Slot_inst16b_set,
19916 Field_imm4_Slot_inst16b_set,
19918 Field_i_Slot_inst16b_set,
19919 Field_imm6lo_Slot_inst16b_set,
19920 Field_imm6hi_Slot_inst16b_set,
19921 Field_imm7lo_Slot_inst16b_set,
19922 Field_imm7hi_Slot_inst16b_set,
19923 Field_z_Slot_inst16b_set,
19924 Field_imm6_Slot_inst16b_set,
19925 Field_imm7_Slot_inst16b_set,
19935 Field_t2_Slot_inst16b_set,
19936 Field_s2_Slot_inst16b_set,
19937 Field_r2_Slot_inst16b_set,
19938 Field_t4_Slot_inst16b_set,
19939 Field_s4_Slot_inst16b_set,
19940 Field_r4_Slot_inst16b_set,
19941 Field_t8_Slot_inst16b_set,
19942 Field_s8_Slot_inst16b_set,
19943 Field_r8_Slot_inst16b_set,
20014 Implicit_Field_set,
20015 Implicit_Field_set,
20016 Implicit_Field_set,
20017 Implicit_Field_set,
20018 Implicit_Field_set,
20019 Implicit_Field_set,
20020 Implicit_Field_set,
20021 Implicit_Field_set,
20022 Implicit_Field_set,
20023 Implicit_Field_set,
20024 Implicit_Field_set,
20028 static xtensa_get_field_fn
20029 Slot_xt_flix64_slot0_get_field_fns[] = {
20030 Field_t_Slot_xt_flix64_slot0_get,
20034 Field_imm8_Slot_xt_flix64_slot0_get,
20035 Field_s_Slot_xt_flix64_slot0_get,
20036 Field_imm12b_Slot_xt_flix64_slot0_get,
20037 Field_imm16_Slot_xt_flix64_slot0_get,
20038 Field_m_Slot_xt_flix64_slot0_get,
20039 Field_n_Slot_xt_flix64_slot0_get,
20042 Field_op1_Slot_xt_flix64_slot0_get,
20043 Field_op2_Slot_xt_flix64_slot0_get,
20044 Field_r_Slot_xt_flix64_slot0_get,
20046 Field_sae4_Slot_xt_flix64_slot0_get,
20047 Field_sae_Slot_xt_flix64_slot0_get,
20048 Field_sal_Slot_xt_flix64_slot0_get,
20049 Field_sargt_Slot_xt_flix64_slot0_get,
20051 Field_sas_Slot_xt_flix64_slot0_get,
20054 Field_thi3_Slot_xt_flix64_slot0_get,
20085 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get,
20086 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get,
20087 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get,
20088 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get,
20089 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get,
20090 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get,
20152 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get,
20153 Implicit_Field_ar0_get,
20154 Implicit_Field_ar4_get,
20155 Implicit_Field_ar8_get,
20156 Implicit_Field_ar12_get,
20157 Implicit_Field_mr0_get,
20158 Implicit_Field_mr1_get,
20159 Implicit_Field_mr2_get,
20160 Implicit_Field_mr3_get,
20161 Implicit_Field_bt16_get,
20162 Implicit_Field_bs16_get,
20163 Implicit_Field_br16_get,
20164 Implicit_Field_brall_get
20167 static xtensa_set_field_fn
20168 Slot_xt_flix64_slot0_set_field_fns[] = {
20169 Field_t_Slot_xt_flix64_slot0_set,
20173 Field_imm8_Slot_xt_flix64_slot0_set,
20174 Field_s_Slot_xt_flix64_slot0_set,
20175 Field_imm12b_Slot_xt_flix64_slot0_set,
20176 Field_imm16_Slot_xt_flix64_slot0_set,
20177 Field_m_Slot_xt_flix64_slot0_set,
20178 Field_n_Slot_xt_flix64_slot0_set,
20181 Field_op1_Slot_xt_flix64_slot0_set,
20182 Field_op2_Slot_xt_flix64_slot0_set,
20183 Field_r_Slot_xt_flix64_slot0_set,
20185 Field_sae4_Slot_xt_flix64_slot0_set,
20186 Field_sae_Slot_xt_flix64_slot0_set,
20187 Field_sal_Slot_xt_flix64_slot0_set,
20188 Field_sargt_Slot_xt_flix64_slot0_set,
20190 Field_sas_Slot_xt_flix64_slot0_set,
20193 Field_thi3_Slot_xt_flix64_slot0_set,
20224 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set,
20225 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set,
20226 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set,
20227 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set,
20228 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set,
20229 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set,
20291 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set,
20292 Implicit_Field_set,
20293 Implicit_Field_set,
20294 Implicit_Field_set,
20295 Implicit_Field_set,
20296 Implicit_Field_set,
20297 Implicit_Field_set,
20298 Implicit_Field_set,
20299 Implicit_Field_set,
20300 Implicit_Field_set,
20301 Implicit_Field_set,
20302 Implicit_Field_set,
20306 static xtensa_get_field_fn
20307 Slot_xt_flix64_slot1_get_field_fns[] = {
20308 Field_t_Slot_xt_flix64_slot1_get,
20312 Field_imm8_Slot_xt_flix64_slot1_get,
20313 Field_s_Slot_xt_flix64_slot1_get,
20314 Field_imm12b_Slot_xt_flix64_slot1_get,
20318 Field_offset_Slot_xt_flix64_slot1_get,
20321 Field_op2_Slot_xt_flix64_slot1_get,
20322 Field_r_Slot_xt_flix64_slot1_get,
20325 Field_sae_Slot_xt_flix64_slot1_get,
20326 Field_sal_Slot_xt_flix64_slot1_get,
20327 Field_sargt_Slot_xt_flix64_slot1_get,
20369 Field_op0_s4_Slot_xt_flix64_slot1_get,
20370 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get,
20371 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20372 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20373 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20374 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20375 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20376 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20377 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20378 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20379 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20380 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20381 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20382 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20383 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20384 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20385 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20386 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20387 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20388 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20389 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20390 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20431 Implicit_Field_ar0_get,
20432 Implicit_Field_ar4_get,
20433 Implicit_Field_ar8_get,
20434 Implicit_Field_ar12_get,
20435 Implicit_Field_mr0_get,
20436 Implicit_Field_mr1_get,
20437 Implicit_Field_mr2_get,
20438 Implicit_Field_mr3_get,
20439 Implicit_Field_bt16_get,
20440 Implicit_Field_bs16_get,
20441 Implicit_Field_br16_get,
20442 Implicit_Field_brall_get
20445 static xtensa_set_field_fn
20446 Slot_xt_flix64_slot1_set_field_fns[] = {
20447 Field_t_Slot_xt_flix64_slot1_set,
20451 Field_imm8_Slot_xt_flix64_slot1_set,
20452 Field_s_Slot_xt_flix64_slot1_set,
20453 Field_imm12b_Slot_xt_flix64_slot1_set,
20457 Field_offset_Slot_xt_flix64_slot1_set,
20460 Field_op2_Slot_xt_flix64_slot1_set,
20461 Field_r_Slot_xt_flix64_slot1_set,
20464 Field_sae_Slot_xt_flix64_slot1_set,
20465 Field_sal_Slot_xt_flix64_slot1_set,
20466 Field_sargt_Slot_xt_flix64_slot1_set,
20508 Field_op0_s4_Slot_xt_flix64_slot1_set,
20509 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set,
20510 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20511 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20512 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20513 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20514 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20515 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20516 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20517 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20518 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20519 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20520 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20521 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20522 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20523 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20524 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20525 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20526 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20527 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20528 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20529 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20570 Implicit_Field_set,
20571 Implicit_Field_set,
20572 Implicit_Field_set,
20573 Implicit_Field_set,
20574 Implicit_Field_set,
20575 Implicit_Field_set,
20576 Implicit_Field_set,
20577 Implicit_Field_set,
20578 Implicit_Field_set,
20579 Implicit_Field_set,
20580 Implicit_Field_set,
20584 static xtensa_get_field_fn
20585 Slot_xt_flix64_slot2_get_field_fns[] = {
20586 Field_t_Slot_xt_flix64_slot2_get,
20591 Field_s_Slot_xt_flix64_slot2_get,
20600 Field_r_Slot_xt_flix64_slot2_get,
20605 Field_sargt_Slot_xt_flix64_slot2_get,
20620 Field_imm7_Slot_xt_flix64_slot2_get,
20669 Field_op0_s5_Slot_xt_flix64_slot2_get,
20670 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20671 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20672 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20673 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20674 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20675 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20676 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20677 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20678 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20679 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20680 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20681 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20682 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20709 Implicit_Field_ar0_get,
20710 Implicit_Field_ar4_get,
20711 Implicit_Field_ar8_get,
20712 Implicit_Field_ar12_get,
20713 Implicit_Field_mr0_get,
20714 Implicit_Field_mr1_get,
20715 Implicit_Field_mr2_get,
20716 Implicit_Field_mr3_get,
20717 Implicit_Field_bt16_get,
20718 Implicit_Field_bs16_get,
20719 Implicit_Field_br16_get,
20720 Implicit_Field_brall_get
20723 static xtensa_set_field_fn
20724 Slot_xt_flix64_slot2_set_field_fns[] = {
20725 Field_t_Slot_xt_flix64_slot2_set,
20730 Field_s_Slot_xt_flix64_slot2_set,
20739 Field_r_Slot_xt_flix64_slot2_set,
20744 Field_sargt_Slot_xt_flix64_slot2_set,
20759 Field_imm7_Slot_xt_flix64_slot2_set,
20808 Field_op0_s5_Slot_xt_flix64_slot2_set,
20809 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20810 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20811 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20812 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20813 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20814 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20815 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20816 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20817 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20818 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20819 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20820 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20821 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20848 Implicit_Field_set,
20849 Implicit_Field_set,
20850 Implicit_Field_set,
20851 Implicit_Field_set,
20852 Implicit_Field_set,
20853 Implicit_Field_set,
20854 Implicit_Field_set,
20855 Implicit_Field_set,
20856 Implicit_Field_set,
20857 Implicit_Field_set,
20858 Implicit_Field_set,
20862 static xtensa_get_field_fn
20863 Slot_xt_flix64_slot3_get_field_fns[] = {
20864 Field_t_Slot_xt_flix64_slot3_get,
20866 Field_bbi_Slot_xt_flix64_slot3_get,
20869 Field_s_Slot_xt_flix64_slot3_get,
20878 Field_r_Slot_xt_flix64_slot3_get,
20918 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get,
20961 Field_op0_s6_Slot_xt_flix64_slot3_get,
20962 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20963 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get,
20964 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20965 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20966 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20967 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20968 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20969 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20970 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20971 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20972 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20973 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20974 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20975 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20976 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20977 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20978 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20979 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20980 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20981 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20982 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20983 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20984 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20985 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20987 Implicit_Field_ar0_get,
20988 Implicit_Field_ar4_get,
20989 Implicit_Field_ar8_get,
20990 Implicit_Field_ar12_get,
20991 Implicit_Field_mr0_get,
20992 Implicit_Field_mr1_get,
20993 Implicit_Field_mr2_get,
20994 Implicit_Field_mr3_get,
20995 Implicit_Field_bt16_get,
20996 Implicit_Field_bs16_get,
20997 Implicit_Field_br16_get,
20998 Implicit_Field_brall_get
21001 static xtensa_set_field_fn
21002 Slot_xt_flix64_slot3_set_field_fns[] = {
21003 Field_t_Slot_xt_flix64_slot3_set,
21005 Field_bbi_Slot_xt_flix64_slot3_set,
21008 Field_s_Slot_xt_flix64_slot3_set,
21017 Field_r_Slot_xt_flix64_slot3_set,
21057 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set,
21100 Field_op0_s6_Slot_xt_flix64_slot3_set,
21101 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21102 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set,
21103 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21104 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21105 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21106 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21107 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21108 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21109 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21110 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21111 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21112 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21113 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21114 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21115 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21116 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21117 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21118 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21119 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21120 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21121 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21122 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21123 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21124 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21126 Implicit_Field_set,
21127 Implicit_Field_set,
21128 Implicit_Field_set,
21129 Implicit_Field_set,
21130 Implicit_Field_set,
21131 Implicit_Field_set,
21132 Implicit_Field_set,
21133 Implicit_Field_set,
21134 Implicit_Field_set,
21135 Implicit_Field_set,
21136 Implicit_Field_set,
21140 static xtensa_slot_internal slots[] = {
21141 { "Inst", "x24", 0,
21142 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
21143 Slot_inst_get_field_fns, Slot_inst_set_field_fns,
21144 Slot_inst_decode, "nop" },
21145 { "Inst16a", "x16a", 0,
21146 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
21147 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
21148 Slot_inst16a_decode, "" },
21149 { "Inst16b", "x16b", 0,
21150 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
21151 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
21152 Slot_inst16b_decode, "nop.n" },
21153 { "xt_flix64_slot0", "xt_format1", 0,
21154 Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set,
21155 Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
21156 Slot_xt_flix64_slot0_decode, "nop" },
21157 { "xt_flix64_slot0", "xt_format2", 0,
21158 Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set,
21159 Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
21160 Slot_xt_flix64_slot0_decode, "nop" },
21161 { "xt_flix64_slot1", "xt_format1", 1,
21162 Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set,
21163 Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns,
21164 Slot_xt_flix64_slot1_decode, "nop" },
21165 { "xt_flix64_slot2", "xt_format1", 2,
21166 Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set,
21167 Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns,
21168 Slot_xt_flix64_slot2_decode, "nop" },
21169 { "xt_flix64_slot3", "xt_format2", 1,
21170 Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set,
21171 Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns,
21172 Slot_xt_flix64_slot3_decode, "nop" }
21176 /* Instruction formats. */
21179 Format_x24_encode (xtensa_insnbuf insn)
21186 Format_x16a_encode (xtensa_insnbuf insn)
21193 Format_x16b_encode (xtensa_insnbuf insn)
21200 Format_xt_format1_encode (xtensa_insnbuf insn)
21207 Format_xt_format2_encode (xtensa_insnbuf insn)
21213 static int Format_x24_slots[] = { 0 };
21215 static int Format_x16a_slots[] = { 1 };
21217 static int Format_x16b_slots[] = { 2 };
21219 static int Format_xt_format1_slots[] = { 3, 5, 6 };
21221 static int Format_xt_format2_slots[] = { 4, 7 };
21223 static xtensa_format_internal formats[] = {
21224 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
21225 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
21226 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
21227 { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots },
21228 { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots }
21233 format_decoder (const xtensa_insnbuf insn)
21235 if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
21236 return 0; /* x24 */
21237 if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
21238 return 1; /* x16a */
21239 if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
21240 return 2; /* x16b */
21241 if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0)
21242 return 3; /* xt_format1 */
21243 if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0)
21244 return 4; /* xt_format2 */
21248 static int length_table[16] = {
21268 length_decoder (const unsigned char *insn)
21270 int op0 = insn[0] & 0xf;
21271 return length_table[op0];
21275 /* Top-level ISA structure. */
21277 xtensa_isa_internal xtensa_modules = {
21278 0 /* little-endian */,
21279 8 /* insn_size */, 0,
21280 5, formats, format_decoder, length_decoder,
21282 135 /* num_fields */,
21287 NUM_STATES, states, 0,
21288 NUM_SYSREGS, sysregs, 0,
21289 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },