1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2018 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok - presently
91 . generated only when linking i960 coff files with i960 b.out
92 . symbols. If this type is returned, the error_message argument
93 . to bfd_perform_relocation will be set. *}
96 . bfd_reloc_status_type;
99 .typedef struct reloc_cache_entry
101 . {* A pointer into the canonical table of pointers. *}
102 . struct bfd_symbol **sym_ptr_ptr;
104 . {* offset in section. *}
105 . bfd_size_type address;
107 . {* addend for relocation value. *}
110 . {* Pointer to how to perform the required relocation. *}
111 . reloc_howto_type *howto;
121 Here is a description of each of the fields within an <<arelent>>:
125 The symbol table pointer points to a pointer to the symbol
126 associated with the relocation request. It is the pointer
127 into the table returned by the back end's
128 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
129 referenced through a pointer to a pointer so that tools like
130 the linker can fix up all the symbols of the same name by
131 modifying only one pointer. The relocation routine looks in
132 the symbol and uses the base of the section the symbol is
133 attached to and the value of the symbol as the initial
134 relocation offset. If the symbol pointer is zero, then the
135 section provided is looked up.
139 The <<address>> field gives the offset in bytes from the base of
140 the section data which owns the relocation record to the first
141 byte of relocatable information. The actual data relocated
142 will be relative to this point; for example, a relocation
143 type which modifies the bottom two bytes of a four byte word
144 would not touch the first byte pointed to in a big endian
149 The <<addend>> is a value provided by the back end to be added (!)
150 to the relocation offset. Its interpretation is dependent upon
151 the howto. For example, on the 68k the code:
156 | return foo[0x12345678];
159 Could be compiled into:
162 | moveb @@#12345678,d0
167 This could create a reloc pointing to <<foo>>, but leave the
168 offset in the data, something like:
170 |RELOCATION RECORDS FOR [.text]:
174 |00000000 4e56 fffc ; linkw fp,#-4
175 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
176 |0000000a 49c0 ; extbl d0
177 |0000000c 4e5e ; unlk fp
180 Using coff and an 88k, some instructions don't have enough
181 space in them to represent the full address range, and
182 pointers have to be loaded in two parts. So you'd get something like:
184 | or.u r13,r0,hi16(_foo+0x12345678)
185 | ld.b r2,r13,lo16(_foo+0x12345678)
188 This should create two relocs, both pointing to <<_foo>>, and with
189 0x12340000 in their addend field. The data would consist of:
191 |RELOCATION RECORDS FOR [.text]:
193 |00000002 HVRT16 _foo+0x12340000
194 |00000006 LVRT16 _foo+0x12340000
196 |00000000 5da05678 ; or.u r13,r0,0x5678
197 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
198 |00000008 f400c001 ; jmp r1
200 The relocation routine digs out the value from the data, adds
201 it to the addend to get the original offset, and then adds the
202 value of <<_foo>>. Note that all 32 bits have to be kept around
203 somewhere, to cope with carry from bit 15 to bit 16.
205 One further example is the sparc and the a.out format. The
206 sparc has a similar problem to the 88k, in that some
207 instructions don't have room for an entire offset, but on the
208 sparc the parts are created in odd sized lumps. The designers of
209 the a.out format chose to not use the data within the section
210 for storing part of the offset; all the offset is kept within
211 the reloc. Anything in the data should be ignored.
214 | sethi %hi(_foo+0x12345678),%g2
215 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
219 Both relocs contain a pointer to <<foo>>, and the offsets
222 |RELOCATION RECORDS FOR [.text]:
224 |00000004 HI22 _foo+0x12345678
225 |00000008 LO10 _foo+0x12345678
227 |00000000 9de3bf90 ; save %sp,-112,%sp
228 |00000004 05000000 ; sethi %hi(_foo+0),%g2
229 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
230 |0000000c 81c7e008 ; ret
231 |00000010 81e80000 ; restore
235 The <<howto>> field can be imagined as a
236 relocation instruction. It is a pointer to a structure which
237 contains information on what to do with all of the other
238 information in the reloc record and data section. A back end
239 would normally have a relocation instruction set and turn
240 relocations into pointers to the correct structure on input -
241 but it would be possible to create each howto field on demand.
247 <<enum complain_overflow>>
249 Indicates what sort of overflow checking should be done when
250 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct bfd_symbol; {* Forward declaration. *}
285 .struct reloc_howto_struct
287 . {* The type field has mainly a documentary use - the back end can
288 . do what it wants with it, though normally the back end's
289 . external idea of what a reloc number is stored
290 . in this field. For example, a PC relative word relocation
291 . in a coff environment has the type 023 - because that's
292 . what the outside world calls a R_PCRWORD reloc. *}
295 . {* The value the final relocation is shifted right by. This drops
296 . unwanted data from the relocation. *}
297 . unsigned int rightshift;
299 . {* The size of the item to be relocated. This is *not* a
300 . power-of-two measure. To get the number of bytes operated
301 . on by a type of relocation, use bfd_get_reloc_size. *}
304 . {* The number of bits in the item to be relocated. This is used
305 . when doing overflow checking. *}
306 . unsigned int bitsize;
308 . {* The relocation is relative to the field being relocated. *}
309 . bfd_boolean pc_relative;
311 . {* The bit position of the reloc value in the destination.
312 . The relocated value is left shifted by this amount. *}
313 . unsigned int bitpos;
315 . {* What type of overflow error should be checked for when
317 . enum complain_overflow complain_on_overflow;
319 . {* If this field is non null, then the supplied function is
320 . called rather than the normal function. This allows really
321 . strange relocation methods to be accommodated (e.g., i960 callj
323 . bfd_reloc_status_type (*special_function)
324 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
327 . {* The textual name of the relocation type. *}
330 . {* Some formats record a relocation addend in the section contents
331 . rather than with the relocation. For ELF formats this is the
332 . distinction between USE_REL and USE_RELA (though the code checks
333 . for USE_REL == 1/0). The value of this field is TRUE if the
334 . addend is recorded with the section contents; when performing a
335 . partial link (ld -r) the section contents (the data) will be
336 . modified. The value of this field is FALSE if addends are
337 . recorded with the relocation (in arelent.addend); when performing
338 . a partial link the relocation will be modified.
339 . All relocations for all ELF USE_RELA targets should set this field
340 . to FALSE (values of TRUE should be looked on with suspicion).
341 . However, the converse is not true: not all relocations of all ELF
342 . USE_REL targets set this field to TRUE. Why this is so is peculiar
343 . to each particular target. For relocs that aren't used in partial
344 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
345 . bfd_boolean partial_inplace;
347 . {* src_mask selects the part of the instruction (or data) to be used
348 . in the relocation sum. If the target relocations don't have an
349 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
350 . dst_mask to extract the addend from the section contents. If
351 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
352 . field should be zero. Non-zero values for ELF USE_RELA targets are
353 . bogus as in those cases the value in the dst_mask part of the
354 . section contents should be treated as garbage. *}
357 . {* dst_mask selects which parts of the instruction (or data) are
358 . replaced with a relocated value. *}
361 . {* When some formats create PC relative instructions, they leave
362 . the value of the pc of the place being relocated in the offset
363 . slot of the instruction, so that a PC relative relocation can
364 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
365 . Some formats leave the displacement part of an instruction
366 . empty (e.g., m88k bcs); this flag signals the fact. *}
367 . bfd_boolean pcrel_offset;
377 The HOWTO define is horrible and will go away.
379 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
380 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
383 And will be replaced with the totally magic way. But for the
384 moment, we are compatible, so do it this way.
386 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
387 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
388 . NAME, FALSE, 0, 0, IN)
392 This is used to fill in an empty howto entry in an array.
394 .#define EMPTY_HOWTO(C) \
395 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
396 . NULL, FALSE, 0, 0, FALSE)
400 Helper routine to turn a symbol into a relocation value.
402 .#define HOWTO_PREPARE(relocation, symbol) \
404 . if (symbol != NULL) \
406 . if (bfd_is_com_section (symbol->section)) \
412 . relocation = symbol->value; \
424 unsigned int bfd_get_reloc_size (reloc_howto_type *);
427 For a reloc_howto_type that operates on a fixed number of bytes,
428 this returns the number of bytes operated on.
432 bfd_get_reloc_size (reloc_howto_type *howto)
454 How relocs are tied together in an <<asection>>:
456 .typedef struct relent_chain
459 . struct relent_chain *next;
465 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
466 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
473 bfd_reloc_status_type bfd_check_overflow
474 (enum complain_overflow how,
475 unsigned int bitsize,
476 unsigned int rightshift,
477 unsigned int addrsize,
481 Perform overflow checking on @var{relocation} which has
482 @var{bitsize} significant bits and will be shifted right by
483 @var{rightshift} bits, on a machine with addresses containing
484 @var{addrsize} significant bits. The result is either of
485 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
489 bfd_reloc_status_type
490 bfd_check_overflow (enum complain_overflow how,
491 unsigned int bitsize,
492 unsigned int rightshift,
493 unsigned int addrsize,
496 bfd_vma fieldmask, addrmask, signmask, ss, a;
497 bfd_reloc_status_type flag = bfd_reloc_ok;
499 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
500 we'll be permissive: extra bits in the field mask will
501 automatically extend the address mask for purposes of the
503 fieldmask = N_ONES (bitsize);
504 signmask = ~fieldmask;
505 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
506 a = (relocation & addrmask) >> rightshift;
510 case complain_overflow_dont:
513 case complain_overflow_signed:
514 /* If any sign bits are set, all sign bits must be set. That
515 is, A must be a valid negative address after shifting. */
516 signmask = ~ (fieldmask >> 1);
519 case complain_overflow_bitfield:
520 /* Bitfields are sometimes signed, sometimes unsigned. We
521 explicitly allow an address wrap too, which means a bitfield
522 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
523 if the value has some, but not all, bits set outside the
526 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
527 flag = bfd_reloc_overflow;
530 case complain_overflow_unsigned:
531 /* We have an overflow if the address does not fit in the field. */
532 if ((a & signmask) != 0)
533 flag = bfd_reloc_overflow;
545 bfd_reloc_offset_in_range
548 bfd_boolean bfd_reloc_offset_in_range
549 (reloc_howto_type *howto,
552 bfd_size_type offset);
555 Returns TRUE if the reloc described by @var{HOWTO} can be
556 applied at @var{OFFSET} octets in @var{SECTION}.
560 /* HOWTO describes a relocation, at offset OCTET. Return whether the
561 relocation field is within SECTION of ABFD. */
564 bfd_reloc_offset_in_range (reloc_howto_type *howto,
569 bfd_size_type octet_end = bfd_get_section_limit_octets (abfd, section);
570 bfd_size_type reloc_size = bfd_get_reloc_size (howto);
572 /* The reloc field must be contained entirely within the section.
573 Allow zero length fields (marker relocs or NONE relocs where no
574 relocation will be performed) at the end of the section. */
575 return octet <= octet_end && octet + reloc_size <= octet_end;
580 bfd_perform_relocation
583 bfd_reloc_status_type bfd_perform_relocation
585 arelent *reloc_entry,
587 asection *input_section,
589 char **error_message);
592 If @var{output_bfd} is supplied to this function, the
593 generated image will be relocatable; the relocations are
594 copied to the output file after they have been changed to
595 reflect the new state of the world. There are two ways of
596 reflecting the results of partial linkage in an output file:
597 by modifying the output data in place, and by modifying the
598 relocation record. Some native formats (e.g., basic a.out and
599 basic coff) have no way of specifying an addend in the
600 relocation type, so the addend has to go in the output data.
601 This is no big deal since in these formats the output data
602 slot will always be big enough for the addend. Complex reloc
603 types with addends were invented to solve just this problem.
604 The @var{error_message} argument is set to an error message if
605 this return @code{bfd_reloc_dangerous}.
609 bfd_reloc_status_type
610 bfd_perform_relocation (bfd *abfd,
611 arelent *reloc_entry,
613 asection *input_section,
615 char **error_message)
618 bfd_reloc_status_type flag = bfd_reloc_ok;
619 bfd_size_type octets;
620 bfd_vma output_base = 0;
621 reloc_howto_type *howto = reloc_entry->howto;
622 asection *reloc_target_output_section;
625 symbol = *(reloc_entry->sym_ptr_ptr);
627 /* If we are not producing relocatable output, return an error if
628 the symbol is not defined. An undefined weak symbol is
629 considered to have a value of zero (SVR4 ABI, p. 4-27). */
630 if (bfd_is_und_section (symbol->section)
631 && (symbol->flags & BSF_WEAK) == 0
632 && output_bfd == NULL)
633 flag = bfd_reloc_undefined;
635 /* If there is a function supplied to handle this relocation type,
636 call it. It'll return `bfd_reloc_continue' if further processing
638 if (howto && howto->special_function)
640 bfd_reloc_status_type cont;
642 /* Note - we do not call bfd_reloc_offset_in_range here as the
643 reloc_entry->address field might actually be valid for the
644 backend concerned. It is up to the special_function itself
645 to call bfd_reloc_offset_in_range if needed. */
646 cont = howto->special_function (abfd, reloc_entry, symbol, data,
647 input_section, output_bfd,
649 if (cont != bfd_reloc_continue)
653 if (bfd_is_abs_section (symbol->section)
654 && output_bfd != NULL)
656 reloc_entry->address += input_section->output_offset;
660 /* PR 17512: file: 0f67f69d. */
662 return bfd_reloc_undefined;
664 /* Is the address of the relocation really within the section? */
665 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
666 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
667 return bfd_reloc_outofrange;
669 /* Work out which section the relocation is targeted at and the
670 initial relocation command value. */
672 /* Get symbol value. (Common symbols are special.) */
673 if (bfd_is_com_section (symbol->section))
676 relocation = symbol->value;
678 reloc_target_output_section = symbol->section->output_section;
680 /* Convert input-section-relative symbol value to absolute. */
681 if ((output_bfd && ! howto->partial_inplace)
682 || reloc_target_output_section == NULL)
685 output_base = reloc_target_output_section->vma;
687 relocation += output_base + symbol->section->output_offset;
689 /* Add in supplied addend. */
690 relocation += reloc_entry->addend;
692 /* Here the variable relocation holds the final address of the
693 symbol we are relocating against, plus any addend. */
695 if (howto->pc_relative)
697 /* This is a PC relative relocation. We want to set RELOCATION
698 to the distance between the address of the symbol and the
699 location. RELOCATION is already the address of the symbol.
701 We start by subtracting the address of the section containing
704 If pcrel_offset is set, we must further subtract the position
705 of the location within the section. Some targets arrange for
706 the addend to be the negative of the position of the location
707 within the section; for example, i386-aout does this. For
708 i386-aout, pcrel_offset is FALSE. Some other targets do not
709 include the position of the location; for example, m88kbcs,
710 or ELF. For those targets, pcrel_offset is TRUE.
712 If we are producing relocatable output, then we must ensure
713 that this reloc will be correctly computed when the final
714 relocation is done. If pcrel_offset is FALSE we want to wind
715 up with the negative of the location within the section,
716 which means we must adjust the existing addend by the change
717 in the location within the section. If pcrel_offset is TRUE
718 we do not want to adjust the existing addend at all.
720 FIXME: This seems logical to me, but for the case of
721 producing relocatable output it is not what the code
722 actually does. I don't want to change it, because it seems
723 far too likely that something will break. */
726 input_section->output_section->vma + input_section->output_offset;
728 if (howto->pcrel_offset)
729 relocation -= reloc_entry->address;
732 if (output_bfd != NULL)
734 if (! howto->partial_inplace)
736 /* This is a partial relocation, and we want to apply the relocation
737 to the reloc entry rather than the raw data. Modify the reloc
738 inplace to reflect what we now know. */
739 reloc_entry->addend = relocation;
740 reloc_entry->address += input_section->output_offset;
745 /* This is a partial relocation, but inplace, so modify the
748 If we've relocated with a symbol with a section, change
749 into a ref to the section belonging to the symbol. */
751 reloc_entry->address += input_section->output_offset;
754 if (abfd->xvec->flavour == bfd_target_coff_flavour
755 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
756 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
758 /* For m68k-coff, the addend was being subtracted twice during
759 relocation with -r. Removing the line below this comment
760 fixes that problem; see PR 2953.
762 However, Ian wrote the following, regarding removing the line below,
763 which explains why it is still enabled: --djm
765 If you put a patch like that into BFD you need to check all the COFF
766 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
767 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
768 problem in a different way. There may very well be a reason that the
769 code works as it does.
771 Hmmm. The first obvious point is that bfd_perform_relocation should
772 not have any tests that depend upon the flavour. It's seem like
773 entirely the wrong place for such a thing. The second obvious point
774 is that the current code ignores the reloc addend when producing
775 relocatable output for COFF. That's peculiar. In fact, I really
776 have no idea what the point of the line you want to remove is.
778 A typical COFF reloc subtracts the old value of the symbol and adds in
779 the new value to the location in the object file (if it's a pc
780 relative reloc it adds the difference between the symbol value and the
781 location). When relocating we need to preserve that property.
783 BFD handles this by setting the addend to the negative of the old
784 value of the symbol. Unfortunately it handles common symbols in a
785 non-standard way (it doesn't subtract the old value) but that's a
786 different story (we can't change it without losing backward
787 compatibility with old object files) (coff-i386 does subtract the old
788 value, to be compatible with existing coff-i386 targets, like SCO).
790 So everything works fine when not producing relocatable output. When
791 we are producing relocatable output, logically we should do exactly
792 what we do when not producing relocatable output. Therefore, your
793 patch is correct. In fact, it should probably always just set
794 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
795 add the value into the object file. This won't hurt the COFF code,
796 which doesn't use the addend; I'm not sure what it will do to other
797 formats (the thing to check for would be whether any formats both use
798 the addend and set partial_inplace).
800 When I wanted to make coff-i386 produce relocatable output, I ran
801 into the problem that you are running into: I wanted to remove that
802 line. Rather than risk it, I made the coff-i386 relocs use a special
803 function; it's coff_i386_reloc in coff-i386.c. The function
804 specifically adds the addend field into the object file, knowing that
805 bfd_perform_relocation is not going to. If you remove that line, then
806 coff-i386.c will wind up adding the addend field in twice. It's
807 trivial to fix; it just needs to be done.
809 The problem with removing the line is just that it may break some
810 working code. With BFD it's hard to be sure of anything. The right
811 way to deal with this is simply to build and test at least all the
812 supported COFF targets. It should be straightforward if time and disk
813 space consuming. For each target:
815 2) generate some executable, and link it using -r (I would
816 probably use paranoia.o and link against newlib/libc.a, which
817 for all the supported targets would be available in
818 /usr/cygnus/progressive/H-host/target/lib/libc.a).
819 3) make the change to reloc.c
820 4) rebuild the linker
822 6) if the resulting object files are the same, you have at least
824 7) if they are different you have to figure out which version is
827 relocation -= reloc_entry->addend;
828 reloc_entry->addend = 0;
832 reloc_entry->addend = relocation;
837 /* FIXME: This overflow checking is incomplete, because the value
838 might have overflowed before we get here. For a correct check we
839 need to compute the value in a size larger than bitsize, but we
840 can't reasonably do that for a reloc the same size as a host
842 FIXME: We should also do overflow checking on the result after
843 adding in the value contained in the object file. */
844 if (howto->complain_on_overflow != complain_overflow_dont
845 && flag == bfd_reloc_ok)
846 flag = bfd_check_overflow (howto->complain_on_overflow,
849 bfd_arch_bits_per_address (abfd),
852 /* Either we are relocating all the way, or we don't want to apply
853 the relocation to the reloc entry (probably because there isn't
854 any room in the output format to describe addends to relocs). */
856 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
857 (OSF version 1.3, compiler version 3.11). It miscompiles the
871 x <<= (unsigned long) s.i0;
875 printf ("succeeded (%lx)\n", x);
879 relocation >>= (bfd_vma) howto->rightshift;
881 /* Shift everything up to where it's going to be used. */
882 relocation <<= (bfd_vma) howto->bitpos;
884 /* Wait for the day when all have the mask in them. */
887 i instruction to be left alone
888 o offset within instruction
889 r relocation offset to apply
898 (( i i i i i o o o o o from bfd_get<size>
899 and S S S S S) to get the size offset we want
900 + r r r r r r r r r r) to get the final value to place
901 and D D D D D to chop to right size
902 -----------------------
905 ( i i i i i o o o o o from bfd_get<size>
906 and N N N N N ) get instruction
907 -----------------------
913 -----------------------
914 = R R R R R R R R R R put into bfd_put<size>
918 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
924 char x = bfd_get_8 (abfd, (char *) data + octets);
926 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
932 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
934 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
939 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
941 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
946 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
947 relocation = -relocation;
949 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
955 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
956 relocation = -relocation;
958 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
969 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
971 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
978 return bfd_reloc_other;
986 bfd_install_relocation
989 bfd_reloc_status_type bfd_install_relocation
991 arelent *reloc_entry,
992 void *data, bfd_vma data_start,
993 asection *input_section,
994 char **error_message);
997 This looks remarkably like <<bfd_perform_relocation>>, except it
998 does not expect that the section contents have been filled in.
999 I.e., it's suitable for use when creating, rather than applying
1002 For now, this function should be considered reserved for the
1006 bfd_reloc_status_type
1007 bfd_install_relocation (bfd *abfd,
1008 arelent *reloc_entry,
1010 bfd_vma data_start_offset,
1011 asection *input_section,
1012 char **error_message)
1015 bfd_reloc_status_type flag = bfd_reloc_ok;
1016 bfd_size_type octets;
1017 bfd_vma output_base = 0;
1018 reloc_howto_type *howto = reloc_entry->howto;
1019 asection *reloc_target_output_section;
1023 symbol = *(reloc_entry->sym_ptr_ptr);
1025 /* If there is a function supplied to handle this relocation type,
1026 call it. It'll return `bfd_reloc_continue' if further processing
1028 if (howto && howto->special_function)
1030 bfd_reloc_status_type cont;
1032 /* Note - we do not call bfd_reloc_offset_in_range here as the
1033 reloc_entry->address field might actually be valid for the
1034 backend concerned. It is up to the special_function itself
1035 to call bfd_reloc_offset_in_range if needed. */
1036 /* XXX - The special_function calls haven't been fixed up to deal
1037 with creating new relocations and section contents. */
1038 cont = howto->special_function (abfd, reloc_entry, symbol,
1039 /* XXX - Non-portable! */
1040 ((bfd_byte *) data_start
1041 - data_start_offset),
1042 input_section, abfd, error_message);
1043 if (cont != bfd_reloc_continue)
1047 if (bfd_is_abs_section (symbol->section))
1049 reloc_entry->address += input_section->output_offset;
1050 return bfd_reloc_ok;
1053 /* No need to check for howto != NULL if !bfd_is_abs_section as
1054 it will have been checked in `bfd_perform_relocation already'. */
1056 /* Is the address of the relocation really within the section? */
1057 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
1058 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
1059 return bfd_reloc_outofrange;
1061 /* Work out which section the relocation is targeted at and the
1062 initial relocation command value. */
1064 /* Get symbol value. (Common symbols are special.) */
1065 if (bfd_is_com_section (symbol->section))
1068 relocation = symbol->value;
1070 reloc_target_output_section = symbol->section->output_section;
1072 /* Convert input-section-relative symbol value to absolute. */
1073 if (! howto->partial_inplace)
1076 output_base = reloc_target_output_section->vma;
1078 relocation += output_base + symbol->section->output_offset;
1080 /* Add in supplied addend. */
1081 relocation += reloc_entry->addend;
1083 /* Here the variable relocation holds the final address of the
1084 symbol we are relocating against, plus any addend. */
1086 if (howto->pc_relative)
1088 /* This is a PC relative relocation. We want to set RELOCATION
1089 to the distance between the address of the symbol and the
1090 location. RELOCATION is already the address of the symbol.
1092 We start by subtracting the address of the section containing
1095 If pcrel_offset is set, we must further subtract the position
1096 of the location within the section. Some targets arrange for
1097 the addend to be the negative of the position of the location
1098 within the section; for example, i386-aout does this. For
1099 i386-aout, pcrel_offset is FALSE. Some other targets do not
1100 include the position of the location; for example, m88kbcs,
1101 or ELF. For those targets, pcrel_offset is TRUE.
1103 If we are producing relocatable output, then we must ensure
1104 that this reloc will be correctly computed when the final
1105 relocation is done. If pcrel_offset is FALSE we want to wind
1106 up with the negative of the location within the section,
1107 which means we must adjust the existing addend by the change
1108 in the location within the section. If pcrel_offset is TRUE
1109 we do not want to adjust the existing addend at all.
1111 FIXME: This seems logical to me, but for the case of
1112 producing relocatable output it is not what the code
1113 actually does. I don't want to change it, because it seems
1114 far too likely that something will break. */
1117 input_section->output_section->vma + input_section->output_offset;
1119 if (howto->pcrel_offset && howto->partial_inplace)
1120 relocation -= reloc_entry->address;
1123 if (! howto->partial_inplace)
1125 /* This is a partial relocation, and we want to apply the relocation
1126 to the reloc entry rather than the raw data. Modify the reloc
1127 inplace to reflect what we now know. */
1128 reloc_entry->addend = relocation;
1129 reloc_entry->address += input_section->output_offset;
1134 /* This is a partial relocation, but inplace, so modify the
1137 If we've relocated with a symbol with a section, change
1138 into a ref to the section belonging to the symbol. */
1139 reloc_entry->address += input_section->output_offset;
1142 if (abfd->xvec->flavour == bfd_target_coff_flavour
1143 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1144 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1147 /* For m68k-coff, the addend was being subtracted twice during
1148 relocation with -r. Removing the line below this comment
1149 fixes that problem; see PR 2953.
1151 However, Ian wrote the following, regarding removing the line below,
1152 which explains why it is still enabled: --djm
1154 If you put a patch like that into BFD you need to check all the COFF
1155 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1156 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1157 problem in a different way. There may very well be a reason that the
1158 code works as it does.
1160 Hmmm. The first obvious point is that bfd_install_relocation should
1161 not have any tests that depend upon the flavour. It's seem like
1162 entirely the wrong place for such a thing. The second obvious point
1163 is that the current code ignores the reloc addend when producing
1164 relocatable output for COFF. That's peculiar. In fact, I really
1165 have no idea what the point of the line you want to remove is.
1167 A typical COFF reloc subtracts the old value of the symbol and adds in
1168 the new value to the location in the object file (if it's a pc
1169 relative reloc it adds the difference between the symbol value and the
1170 location). When relocating we need to preserve that property.
1172 BFD handles this by setting the addend to the negative of the old
1173 value of the symbol. Unfortunately it handles common symbols in a
1174 non-standard way (it doesn't subtract the old value) but that's a
1175 different story (we can't change it without losing backward
1176 compatibility with old object files) (coff-i386 does subtract the old
1177 value, to be compatible with existing coff-i386 targets, like SCO).
1179 So everything works fine when not producing relocatable output. When
1180 we are producing relocatable output, logically we should do exactly
1181 what we do when not producing relocatable output. Therefore, your
1182 patch is correct. In fact, it should probably always just set
1183 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1184 add the value into the object file. This won't hurt the COFF code,
1185 which doesn't use the addend; I'm not sure what it will do to other
1186 formats (the thing to check for would be whether any formats both use
1187 the addend and set partial_inplace).
1189 When I wanted to make coff-i386 produce relocatable output, I ran
1190 into the problem that you are running into: I wanted to remove that
1191 line. Rather than risk it, I made the coff-i386 relocs use a special
1192 function; it's coff_i386_reloc in coff-i386.c. The function
1193 specifically adds the addend field into the object file, knowing that
1194 bfd_install_relocation is not going to. If you remove that line, then
1195 coff-i386.c will wind up adding the addend field in twice. It's
1196 trivial to fix; it just needs to be done.
1198 The problem with removing the line is just that it may break some
1199 working code. With BFD it's hard to be sure of anything. The right
1200 way to deal with this is simply to build and test at least all the
1201 supported COFF targets. It should be straightforward if time and disk
1202 space consuming. For each target:
1204 2) generate some executable, and link it using -r (I would
1205 probably use paranoia.o and link against newlib/libc.a, which
1206 for all the supported targets would be available in
1207 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1208 3) make the change to reloc.c
1209 4) rebuild the linker
1211 6) if the resulting object files are the same, you have at least
1213 7) if they are different you have to figure out which version is
1215 relocation -= reloc_entry->addend;
1216 /* FIXME: There should be no target specific code here... */
1217 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1218 reloc_entry->addend = 0;
1222 reloc_entry->addend = relocation;
1226 /* FIXME: This overflow checking is incomplete, because the value
1227 might have overflowed before we get here. For a correct check we
1228 need to compute the value in a size larger than bitsize, but we
1229 can't reasonably do that for a reloc the same size as a host
1231 FIXME: We should also do overflow checking on the result after
1232 adding in the value contained in the object file. */
1233 if (howto->complain_on_overflow != complain_overflow_dont)
1234 flag = bfd_check_overflow (howto->complain_on_overflow,
1237 bfd_arch_bits_per_address (abfd),
1240 /* Either we are relocating all the way, or we don't want to apply
1241 the relocation to the reloc entry (probably because there isn't
1242 any room in the output format to describe addends to relocs). */
1244 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1245 (OSF version 1.3, compiler version 3.11). It miscompiles the
1259 x <<= (unsigned long) s.i0;
1261 printf ("failed\n");
1263 printf ("succeeded (%lx)\n", x);
1267 relocation >>= (bfd_vma) howto->rightshift;
1269 /* Shift everything up to where it's going to be used. */
1270 relocation <<= (bfd_vma) howto->bitpos;
1272 /* Wait for the day when all have the mask in them. */
1275 i instruction to be left alone
1276 o offset within instruction
1277 r relocation offset to apply
1286 (( i i i i i o o o o o from bfd_get<size>
1287 and S S S S S) to get the size offset we want
1288 + r r r r r r r r r r) to get the final value to place
1289 and D D D D D to chop to right size
1290 -----------------------
1293 ( i i i i i o o o o o from bfd_get<size>
1294 and N N N N N ) get instruction
1295 -----------------------
1301 -----------------------
1302 = R R R R R R R R R R put into bfd_put<size>
1306 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1308 data = (bfd_byte *) data_start + (octets - data_start_offset);
1310 switch (howto->size)
1314 char x = bfd_get_8 (abfd, data);
1316 bfd_put_8 (abfd, x, data);
1322 short x = bfd_get_16 (abfd, data);
1324 bfd_put_16 (abfd, (bfd_vma) x, data);
1329 long x = bfd_get_32 (abfd, data);
1331 bfd_put_32 (abfd, (bfd_vma) x, data);
1336 long x = bfd_get_32 (abfd, data);
1337 relocation = -relocation;
1339 bfd_put_32 (abfd, (bfd_vma) x, data);
1349 bfd_vma x = bfd_get_64 (abfd, data);
1351 bfd_put_64 (abfd, x, data);
1355 return bfd_reloc_other;
1361 /* This relocation routine is used by some of the backend linkers.
1362 They do not construct asymbol or arelent structures, so there is no
1363 reason for them to use bfd_perform_relocation. Also,
1364 bfd_perform_relocation is so hacked up it is easier to write a new
1365 function than to try to deal with it.
1367 This routine does a final relocation. Whether it is useful for a
1368 relocatable link depends upon how the object format defines
1371 FIXME: This routine ignores any special_function in the HOWTO,
1372 since the existing special_function values have been written for
1373 bfd_perform_relocation.
1375 HOWTO is the reloc howto information.
1376 INPUT_BFD is the BFD which the reloc applies to.
1377 INPUT_SECTION is the section which the reloc applies to.
1378 CONTENTS is the contents of the section.
1379 ADDRESS is the address of the reloc within INPUT_SECTION.
1380 VALUE is the value of the symbol the reloc refers to.
1381 ADDEND is the addend of the reloc. */
1383 bfd_reloc_status_type
1384 _bfd_final_link_relocate (reloc_howto_type *howto,
1386 asection *input_section,
1393 bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
1395 /* Sanity check the address. */
1396 if (!bfd_reloc_offset_in_range (howto, input_bfd, input_section, octets))
1397 return bfd_reloc_outofrange;
1399 /* This function assumes that we are dealing with a basic relocation
1400 against a symbol. We want to compute the value of the symbol to
1401 relocate to. This is just VALUE, the value of the symbol, plus
1402 ADDEND, any addend associated with the reloc. */
1403 relocation = value + addend;
1405 /* If the relocation is PC relative, we want to set RELOCATION to
1406 the distance between the symbol (currently in RELOCATION) and the
1407 location we are relocating. Some targets (e.g., i386-aout)
1408 arrange for the contents of the section to be the negative of the
1409 offset of the location within the section; for such targets
1410 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1411 simply leave the contents of the section as zero; for such
1412 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1413 need to subtract out the offset of the location within the
1414 section (which is just ADDRESS). */
1415 if (howto->pc_relative)
1417 relocation -= (input_section->output_section->vma
1418 + input_section->output_offset);
1419 if (howto->pcrel_offset)
1420 relocation -= address;
1423 return _bfd_relocate_contents (howto, input_bfd, relocation,
1425 + address * bfd_octets_per_byte (input_bfd));
1428 /* Relocate a given location using a given value and howto. */
1430 bfd_reloc_status_type
1431 _bfd_relocate_contents (reloc_howto_type *howto,
1438 bfd_reloc_status_type flag;
1439 unsigned int rightshift = howto->rightshift;
1440 unsigned int bitpos = howto->bitpos;
1442 /* If the size is negative, negate RELOCATION. This isn't very
1444 if (howto->size < 0)
1445 relocation = -relocation;
1447 /* Get the value we are going to relocate. */
1448 size = bfd_get_reloc_size (howto);
1454 return bfd_reloc_ok;
1456 x = bfd_get_8 (input_bfd, location);
1459 x = bfd_get_16 (input_bfd, location);
1462 x = bfd_get_32 (input_bfd, location);
1466 x = bfd_get_64 (input_bfd, location);
1473 /* Check for overflow. FIXME: We may drop bits during the addition
1474 which we don't check for. We must either check at every single
1475 operation, which would be tedious, or we must do the computations
1476 in a type larger than bfd_vma, which would be inefficient. */
1477 flag = bfd_reloc_ok;
1478 if (howto->complain_on_overflow != complain_overflow_dont)
1480 bfd_vma addrmask, fieldmask, signmask, ss;
1483 /* Get the values to be added together. For signed and unsigned
1484 relocations, we assume that all values should be truncated to
1485 the size of an address. For bitfields, all the bits matter.
1486 See also bfd_check_overflow. */
1487 fieldmask = N_ONES (howto->bitsize);
1488 signmask = ~fieldmask;
1489 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1490 | (fieldmask << rightshift));
1491 a = (relocation & addrmask) >> rightshift;
1492 b = (x & howto->src_mask & addrmask) >> bitpos;
1493 addrmask >>= rightshift;
1495 switch (howto->complain_on_overflow)
1497 case complain_overflow_signed:
1498 /* If any sign bits are set, all sign bits must be set.
1499 That is, A must be a valid negative address after
1501 signmask = ~(fieldmask >> 1);
1504 case complain_overflow_bitfield:
1505 /* Much like the signed check, but for a field one bit
1506 wider. We allow a bitfield to represent numbers in the
1507 range -2**n to 2**n-1, where n is the number of bits in the
1508 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1509 can't overflow, which is exactly what we want. */
1511 if (ss != 0 && ss != (addrmask & signmask))
1512 flag = bfd_reloc_overflow;
1514 /* We only need this next bit of code if the sign bit of B
1515 is below the sign bit of A. This would only happen if
1516 SRC_MASK had fewer bits than BITSIZE. Note that if
1517 SRC_MASK has more bits than BITSIZE, we can get into
1518 trouble; we would need to verify that B is in range, as
1519 we do for A above. */
1520 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1523 /* Set all the bits above the sign bit. */
1526 /* Now we can do the addition. */
1529 /* See if the result has the correct sign. Bits above the
1530 sign bit are junk now; ignore them. If the sum is
1531 positive, make sure we did not have all negative inputs;
1532 if the sum is negative, make sure we did not have all
1533 positive inputs. The test below looks only at the sign
1534 bits, and it really just
1535 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1537 We mask with addrmask here to explicitly allow an address
1538 wrap-around. The Linux kernel relies on it, and it is
1539 the only way to write assembler code which can run when
1540 loaded at a location 0x80000000 away from the location at
1541 which it is linked. */
1542 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1543 flag = bfd_reloc_overflow;
1546 case complain_overflow_unsigned:
1547 /* Checking for an unsigned overflow is relatively easy:
1548 trim the addresses and add, and trim the result as well.
1549 Overflow is normally indicated when the result does not
1550 fit in the field. However, we also need to consider the
1551 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1552 input is 0x80000000, and bfd_vma is only 32 bits; then we
1553 will get sum == 0, but there is an overflow, since the
1554 inputs did not fit in the field. Instead of doing a
1555 separate test, we can check for this by or-ing in the
1556 operands when testing for the sum overflowing its final
1558 sum = (a + b) & addrmask;
1559 if ((a | b | sum) & signmask)
1560 flag = bfd_reloc_overflow;
1568 /* Put RELOCATION in the right bits. */
1569 relocation >>= (bfd_vma) rightshift;
1570 relocation <<= (bfd_vma) bitpos;
1572 /* Add RELOCATION to the right bits of X. */
1573 x = ((x & ~howto->dst_mask)
1574 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1576 /* Put the relocated value back in the object file. */
1582 bfd_put_8 (input_bfd, x, location);
1585 bfd_put_16 (input_bfd, x, location);
1588 bfd_put_32 (input_bfd, x, location);
1592 bfd_put_64 (input_bfd, x, location);
1602 /* Clear a given location using a given howto, by applying a fixed relocation
1603 value and discarding any in-place addend. This is used for fixed-up
1604 relocations against discarded symbols, to make ignorable debug or unwind
1605 information more obvious. */
1608 _bfd_clear_contents (reloc_howto_type *howto,
1610 asection *input_section,
1616 /* Get the value we are going to relocate. */
1617 size = bfd_get_reloc_size (howto);
1625 x = bfd_get_8 (input_bfd, location);
1628 x = bfd_get_16 (input_bfd, location);
1631 x = bfd_get_32 (input_bfd, location);
1635 x = bfd_get_64 (input_bfd, location);
1642 /* Zero out the unwanted bits of X. */
1643 x &= ~howto->dst_mask;
1645 /* For a range list, use 1 instead of 0 as placeholder. 0
1646 would terminate the list, hiding any later entries. */
1647 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1648 ".debug_ranges") == 0
1649 && (howto->dst_mask & 1) != 0)
1652 /* Put the relocated value back in the object file. */
1659 bfd_put_8 (input_bfd, x, location);
1662 bfd_put_16 (input_bfd, x, location);
1665 bfd_put_32 (input_bfd, x, location);
1669 bfd_put_64 (input_bfd, x, location);
1680 howto manager, , typedef arelent, Relocations
1685 When an application wants to create a relocation, but doesn't
1686 know what the target machine might call it, it can find out by
1687 using this bit of code.
1696 The insides of a reloc code. The idea is that, eventually, there
1697 will be one enumerator for every type of relocation we ever do.
1698 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1699 return a howto pointer.
1701 This does mean that the application must determine the correct
1702 enumerator value; you can't get a howto pointer from a random set
1723 Basic absolute relocations of N bits.
1738 PC-relative relocations. Sometimes these are relative to the address
1739 of the relocation itself; sometimes they are relative to the start of
1740 the section containing the relocation. It depends on the specific target.
1742 The 24-bit relocation is used in some Intel 960 configurations.
1747 Section relative relocations. Some targets need this for DWARF2.
1750 BFD_RELOC_32_GOT_PCREL
1752 BFD_RELOC_16_GOT_PCREL
1754 BFD_RELOC_8_GOT_PCREL
1760 BFD_RELOC_LO16_GOTOFF
1762 BFD_RELOC_HI16_GOTOFF
1764 BFD_RELOC_HI16_S_GOTOFF
1768 BFD_RELOC_64_PLT_PCREL
1770 BFD_RELOC_32_PLT_PCREL
1772 BFD_RELOC_24_PLT_PCREL
1774 BFD_RELOC_16_PLT_PCREL
1776 BFD_RELOC_8_PLT_PCREL
1784 BFD_RELOC_LO16_PLTOFF
1786 BFD_RELOC_HI16_PLTOFF
1788 BFD_RELOC_HI16_S_PLTOFF
1802 BFD_RELOC_68K_GLOB_DAT
1804 BFD_RELOC_68K_JMP_SLOT
1806 BFD_RELOC_68K_RELATIVE
1808 BFD_RELOC_68K_TLS_GD32
1810 BFD_RELOC_68K_TLS_GD16
1812 BFD_RELOC_68K_TLS_GD8
1814 BFD_RELOC_68K_TLS_LDM32
1816 BFD_RELOC_68K_TLS_LDM16
1818 BFD_RELOC_68K_TLS_LDM8
1820 BFD_RELOC_68K_TLS_LDO32
1822 BFD_RELOC_68K_TLS_LDO16
1824 BFD_RELOC_68K_TLS_LDO8
1826 BFD_RELOC_68K_TLS_IE32
1828 BFD_RELOC_68K_TLS_IE16
1830 BFD_RELOC_68K_TLS_IE8
1832 BFD_RELOC_68K_TLS_LE32
1834 BFD_RELOC_68K_TLS_LE16
1836 BFD_RELOC_68K_TLS_LE8
1838 Relocations used by 68K ELF.
1841 BFD_RELOC_32_BASEREL
1843 BFD_RELOC_16_BASEREL
1845 BFD_RELOC_LO16_BASEREL
1847 BFD_RELOC_HI16_BASEREL
1849 BFD_RELOC_HI16_S_BASEREL
1855 Linkage-table relative.
1860 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1863 BFD_RELOC_32_PCREL_S2
1865 BFD_RELOC_16_PCREL_S2
1867 BFD_RELOC_23_PCREL_S2
1869 These PC-relative relocations are stored as word displacements --
1870 i.e., byte displacements shifted right two bits. The 30-bit word
1871 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1872 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1873 signed 16-bit displacement is used on the MIPS, and the 23-bit
1874 displacement is used on the Alpha.
1881 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1882 the target word. These are used on the SPARC.
1889 For systems that allocate a Global Pointer register, these are
1890 displacements off that register. These relocation types are
1891 handled specially, because the value the register will have is
1892 decided relatively late.
1895 BFD_RELOC_I960_CALLJ
1897 Reloc types used for i960/b.out.
1902 BFD_RELOC_SPARC_WDISP22
1908 BFD_RELOC_SPARC_GOT10
1910 BFD_RELOC_SPARC_GOT13
1912 BFD_RELOC_SPARC_GOT22
1914 BFD_RELOC_SPARC_PC10
1916 BFD_RELOC_SPARC_PC22
1918 BFD_RELOC_SPARC_WPLT30
1920 BFD_RELOC_SPARC_COPY
1922 BFD_RELOC_SPARC_GLOB_DAT
1924 BFD_RELOC_SPARC_JMP_SLOT
1926 BFD_RELOC_SPARC_RELATIVE
1928 BFD_RELOC_SPARC_UA16
1930 BFD_RELOC_SPARC_UA32
1932 BFD_RELOC_SPARC_UA64
1934 BFD_RELOC_SPARC_GOTDATA_HIX22
1936 BFD_RELOC_SPARC_GOTDATA_LOX10
1938 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1940 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1942 BFD_RELOC_SPARC_GOTDATA_OP
1944 BFD_RELOC_SPARC_JMP_IREL
1946 BFD_RELOC_SPARC_IRELATIVE
1948 SPARC ELF relocations. There is probably some overlap with other
1949 relocation types already defined.
1952 BFD_RELOC_SPARC_BASE13
1954 BFD_RELOC_SPARC_BASE22
1956 I think these are specific to SPARC a.out (e.g., Sun 4).
1966 BFD_RELOC_SPARC_OLO10
1968 BFD_RELOC_SPARC_HH22
1970 BFD_RELOC_SPARC_HM10
1972 BFD_RELOC_SPARC_LM22
1974 BFD_RELOC_SPARC_PC_HH22
1976 BFD_RELOC_SPARC_PC_HM10
1978 BFD_RELOC_SPARC_PC_LM22
1980 BFD_RELOC_SPARC_WDISP16
1982 BFD_RELOC_SPARC_WDISP19
1990 BFD_RELOC_SPARC_DISP64
1993 BFD_RELOC_SPARC_PLT32
1995 BFD_RELOC_SPARC_PLT64
1997 BFD_RELOC_SPARC_HIX22
1999 BFD_RELOC_SPARC_LOX10
2007 BFD_RELOC_SPARC_REGISTER
2011 BFD_RELOC_SPARC_SIZE32
2013 BFD_RELOC_SPARC_SIZE64
2015 BFD_RELOC_SPARC_WDISP10
2020 BFD_RELOC_SPARC_REV32
2022 SPARC little endian relocation
2024 BFD_RELOC_SPARC_TLS_GD_HI22
2026 BFD_RELOC_SPARC_TLS_GD_LO10
2028 BFD_RELOC_SPARC_TLS_GD_ADD
2030 BFD_RELOC_SPARC_TLS_GD_CALL
2032 BFD_RELOC_SPARC_TLS_LDM_HI22
2034 BFD_RELOC_SPARC_TLS_LDM_LO10
2036 BFD_RELOC_SPARC_TLS_LDM_ADD
2038 BFD_RELOC_SPARC_TLS_LDM_CALL
2040 BFD_RELOC_SPARC_TLS_LDO_HIX22
2042 BFD_RELOC_SPARC_TLS_LDO_LOX10
2044 BFD_RELOC_SPARC_TLS_LDO_ADD
2046 BFD_RELOC_SPARC_TLS_IE_HI22
2048 BFD_RELOC_SPARC_TLS_IE_LO10
2050 BFD_RELOC_SPARC_TLS_IE_LD
2052 BFD_RELOC_SPARC_TLS_IE_LDX
2054 BFD_RELOC_SPARC_TLS_IE_ADD
2056 BFD_RELOC_SPARC_TLS_LE_HIX22
2058 BFD_RELOC_SPARC_TLS_LE_LOX10
2060 BFD_RELOC_SPARC_TLS_DTPMOD32
2062 BFD_RELOC_SPARC_TLS_DTPMOD64
2064 BFD_RELOC_SPARC_TLS_DTPOFF32
2066 BFD_RELOC_SPARC_TLS_DTPOFF64
2068 BFD_RELOC_SPARC_TLS_TPOFF32
2070 BFD_RELOC_SPARC_TLS_TPOFF64
2072 SPARC TLS relocations
2081 BFD_RELOC_SPU_IMM10W
2085 BFD_RELOC_SPU_IMM16W
2089 BFD_RELOC_SPU_PCREL9a
2091 BFD_RELOC_SPU_PCREL9b
2093 BFD_RELOC_SPU_PCREL16
2103 BFD_RELOC_SPU_ADD_PIC
2108 BFD_RELOC_ALPHA_GPDISP_HI16
2110 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2111 "addend" in some special way.
2112 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2113 writing; when reading, it will be the absolute section symbol. The
2114 addend is the displacement in bytes of the "lda" instruction from
2115 the "ldah" instruction (which is at the address of this reloc).
2117 BFD_RELOC_ALPHA_GPDISP_LO16
2119 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2120 with GPDISP_HI16 relocs. The addend is ignored when writing the
2121 relocations out, and is filled in with the file's GP value on
2122 reading, for convenience.
2125 BFD_RELOC_ALPHA_GPDISP
2127 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2128 relocation except that there is no accompanying GPDISP_LO16
2132 BFD_RELOC_ALPHA_LITERAL
2134 BFD_RELOC_ALPHA_ELF_LITERAL
2136 BFD_RELOC_ALPHA_LITUSE
2138 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2139 the assembler turns it into a LDQ instruction to load the address of
2140 the symbol, and then fills in a register in the real instruction.
2142 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2143 section symbol. The addend is ignored when writing, but is filled
2144 in with the file's GP value on reading, for convenience, as with the
2147 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2148 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2149 but it generates output not based on the position within the .got
2150 section, but relative to the GP value chosen for the file during the
2153 The LITUSE reloc, on the instruction using the loaded address, gives
2154 information to the linker that it might be able to use to optimize
2155 away some literal section references. The symbol is ignored (read
2156 as the absolute section symbol), and the "addend" indicates the type
2157 of instruction using the register:
2158 1 - "memory" fmt insn
2159 2 - byte-manipulation (byte offset reg)
2160 3 - jsr (target of branch)
2163 BFD_RELOC_ALPHA_HINT
2165 The HINT relocation indicates a value that should be filled into the
2166 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2167 prediction logic which may be provided on some processors.
2170 BFD_RELOC_ALPHA_LINKAGE
2172 The LINKAGE relocation outputs a linkage pair in the object file,
2173 which is filled by the linker.
2176 BFD_RELOC_ALPHA_CODEADDR
2178 The CODEADDR relocation outputs a STO_CA in the object file,
2179 which is filled by the linker.
2182 BFD_RELOC_ALPHA_GPREL_HI16
2184 BFD_RELOC_ALPHA_GPREL_LO16
2186 The GPREL_HI/LO relocations together form a 32-bit offset from the
2190 BFD_RELOC_ALPHA_BRSGP
2192 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2193 share a common GP, and the target address is adjusted for
2194 STO_ALPHA_STD_GPLOAD.
2199 The NOP relocation outputs a NOP if the longword displacement
2200 between two procedure entry points is < 2^21.
2205 The BSR relocation outputs a BSR if the longword displacement
2206 between two procedure entry points is < 2^21.
2211 The LDA relocation outputs a LDA if the longword displacement
2212 between two procedure entry points is < 2^16.
2217 The BOH relocation outputs a BSR if the longword displacement
2218 between two procedure entry points is < 2^21, or else a hint.
2221 BFD_RELOC_ALPHA_TLSGD
2223 BFD_RELOC_ALPHA_TLSLDM
2225 BFD_RELOC_ALPHA_DTPMOD64
2227 BFD_RELOC_ALPHA_GOTDTPREL16
2229 BFD_RELOC_ALPHA_DTPREL64
2231 BFD_RELOC_ALPHA_DTPREL_HI16
2233 BFD_RELOC_ALPHA_DTPREL_LO16
2235 BFD_RELOC_ALPHA_DTPREL16
2237 BFD_RELOC_ALPHA_GOTTPREL16
2239 BFD_RELOC_ALPHA_TPREL64
2241 BFD_RELOC_ALPHA_TPREL_HI16
2243 BFD_RELOC_ALPHA_TPREL_LO16
2245 BFD_RELOC_ALPHA_TPREL16
2247 Alpha thread-local storage relocations.
2252 BFD_RELOC_MICROMIPS_JMP
2254 The MIPS jump instruction.
2257 BFD_RELOC_MIPS16_JMP
2259 The MIPS16 jump instruction.
2262 BFD_RELOC_MIPS16_GPREL
2264 MIPS16 GP relative reloc.
2269 High 16 bits of 32-bit value; simple reloc.
2274 High 16 bits of 32-bit value but the low 16 bits will be sign
2275 extended and added to form the final result. If the low 16
2276 bits form a negative number, we need to add one to the high value
2277 to compensate for the borrow when the low bits are added.
2285 BFD_RELOC_HI16_PCREL
2287 High 16 bits of 32-bit pc-relative value
2289 BFD_RELOC_HI16_S_PCREL
2291 High 16 bits of 32-bit pc-relative value, adjusted
2293 BFD_RELOC_LO16_PCREL
2295 Low 16 bits of pc-relative value
2298 BFD_RELOC_MIPS16_GOT16
2300 BFD_RELOC_MIPS16_CALL16
2302 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2303 16-bit immediate fields
2305 BFD_RELOC_MIPS16_HI16
2307 MIPS16 high 16 bits of 32-bit value.
2309 BFD_RELOC_MIPS16_HI16_S
2311 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2312 extended and added to form the final result. If the low 16
2313 bits form a negative number, we need to add one to the high value
2314 to compensate for the borrow when the low bits are added.
2316 BFD_RELOC_MIPS16_LO16
2321 BFD_RELOC_MIPS16_TLS_GD
2323 BFD_RELOC_MIPS16_TLS_LDM
2325 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2327 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2329 BFD_RELOC_MIPS16_TLS_GOTTPREL
2331 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2333 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2335 MIPS16 TLS relocations
2338 BFD_RELOC_MIPS_LITERAL
2340 BFD_RELOC_MICROMIPS_LITERAL
2342 Relocation against a MIPS literal section.
2345 BFD_RELOC_MICROMIPS_7_PCREL_S1
2347 BFD_RELOC_MICROMIPS_10_PCREL_S1
2349 BFD_RELOC_MICROMIPS_16_PCREL_S1
2351 microMIPS PC-relative relocations.
2354 BFD_RELOC_MIPS16_16_PCREL_S1
2356 MIPS16 PC-relative relocation.
2359 BFD_RELOC_MIPS_21_PCREL_S2
2361 BFD_RELOC_MIPS_26_PCREL_S2
2363 BFD_RELOC_MIPS_18_PCREL_S3
2365 BFD_RELOC_MIPS_19_PCREL_S2
2367 MIPS PC-relative relocations.
2370 BFD_RELOC_MICROMIPS_GPREL16
2372 BFD_RELOC_MICROMIPS_HI16
2374 BFD_RELOC_MICROMIPS_HI16_S
2376 BFD_RELOC_MICROMIPS_LO16
2378 microMIPS versions of generic BFD relocs.
2381 BFD_RELOC_MIPS_GOT16
2383 BFD_RELOC_MICROMIPS_GOT16
2385 BFD_RELOC_MIPS_CALL16
2387 BFD_RELOC_MICROMIPS_CALL16
2389 BFD_RELOC_MIPS_GOT_HI16
2391 BFD_RELOC_MICROMIPS_GOT_HI16
2393 BFD_RELOC_MIPS_GOT_LO16
2395 BFD_RELOC_MICROMIPS_GOT_LO16
2397 BFD_RELOC_MIPS_CALL_HI16
2399 BFD_RELOC_MICROMIPS_CALL_HI16
2401 BFD_RELOC_MIPS_CALL_LO16
2403 BFD_RELOC_MICROMIPS_CALL_LO16
2407 BFD_RELOC_MICROMIPS_SUB
2409 BFD_RELOC_MIPS_GOT_PAGE
2411 BFD_RELOC_MICROMIPS_GOT_PAGE
2413 BFD_RELOC_MIPS_GOT_OFST
2415 BFD_RELOC_MICROMIPS_GOT_OFST
2417 BFD_RELOC_MIPS_GOT_DISP
2419 BFD_RELOC_MICROMIPS_GOT_DISP
2421 BFD_RELOC_MIPS_SHIFT5
2423 BFD_RELOC_MIPS_SHIFT6
2425 BFD_RELOC_MIPS_INSERT_A
2427 BFD_RELOC_MIPS_INSERT_B
2429 BFD_RELOC_MIPS_DELETE
2431 BFD_RELOC_MIPS_HIGHEST
2433 BFD_RELOC_MICROMIPS_HIGHEST
2435 BFD_RELOC_MIPS_HIGHER
2437 BFD_RELOC_MICROMIPS_HIGHER
2439 BFD_RELOC_MIPS_SCN_DISP
2441 BFD_RELOC_MICROMIPS_SCN_DISP
2443 BFD_RELOC_MIPS_REL16
2445 BFD_RELOC_MIPS_RELGOT
2449 BFD_RELOC_MICROMIPS_JALR
2451 BFD_RELOC_MIPS_TLS_DTPMOD32
2453 BFD_RELOC_MIPS_TLS_DTPREL32
2455 BFD_RELOC_MIPS_TLS_DTPMOD64
2457 BFD_RELOC_MIPS_TLS_DTPREL64
2459 BFD_RELOC_MIPS_TLS_GD
2461 BFD_RELOC_MICROMIPS_TLS_GD
2463 BFD_RELOC_MIPS_TLS_LDM
2465 BFD_RELOC_MICROMIPS_TLS_LDM
2467 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2469 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2471 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2473 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2475 BFD_RELOC_MIPS_TLS_GOTTPREL
2477 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2479 BFD_RELOC_MIPS_TLS_TPREL32
2481 BFD_RELOC_MIPS_TLS_TPREL64
2483 BFD_RELOC_MIPS_TLS_TPREL_HI16
2485 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2487 BFD_RELOC_MIPS_TLS_TPREL_LO16
2489 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2493 MIPS ELF relocations.
2499 BFD_RELOC_MIPS_JUMP_SLOT
2501 MIPS ELF relocations (VxWorks and PLT extensions).
2505 BFD_RELOC_MOXIE_10_PCREL
2507 Moxie ELF relocations.
2519 BFD_RELOC_FT32_RELAX
2527 BFD_RELOC_FT32_DIFF32
2529 FT32 ELF relocations.
2533 BFD_RELOC_FRV_LABEL16
2535 BFD_RELOC_FRV_LABEL24
2541 BFD_RELOC_FRV_GPREL12
2543 BFD_RELOC_FRV_GPRELU12
2545 BFD_RELOC_FRV_GPREL32
2547 BFD_RELOC_FRV_GPRELHI
2549 BFD_RELOC_FRV_GPRELLO
2557 BFD_RELOC_FRV_FUNCDESC
2559 BFD_RELOC_FRV_FUNCDESC_GOT12
2561 BFD_RELOC_FRV_FUNCDESC_GOTHI
2563 BFD_RELOC_FRV_FUNCDESC_GOTLO
2565 BFD_RELOC_FRV_FUNCDESC_VALUE
2567 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2569 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2571 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2573 BFD_RELOC_FRV_GOTOFF12
2575 BFD_RELOC_FRV_GOTOFFHI
2577 BFD_RELOC_FRV_GOTOFFLO
2579 BFD_RELOC_FRV_GETTLSOFF
2581 BFD_RELOC_FRV_TLSDESC_VALUE
2583 BFD_RELOC_FRV_GOTTLSDESC12
2585 BFD_RELOC_FRV_GOTTLSDESCHI
2587 BFD_RELOC_FRV_GOTTLSDESCLO
2589 BFD_RELOC_FRV_TLSMOFF12
2591 BFD_RELOC_FRV_TLSMOFFHI
2593 BFD_RELOC_FRV_TLSMOFFLO
2595 BFD_RELOC_FRV_GOTTLSOFF12
2597 BFD_RELOC_FRV_GOTTLSOFFHI
2599 BFD_RELOC_FRV_GOTTLSOFFLO
2601 BFD_RELOC_FRV_TLSOFF
2603 BFD_RELOC_FRV_TLSDESC_RELAX
2605 BFD_RELOC_FRV_GETTLSOFF_RELAX
2607 BFD_RELOC_FRV_TLSOFF_RELAX
2609 BFD_RELOC_FRV_TLSMOFF
2611 Fujitsu Frv Relocations.
2615 BFD_RELOC_MN10300_GOTOFF24
2617 This is a 24bit GOT-relative reloc for the mn10300.
2619 BFD_RELOC_MN10300_GOT32
2621 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2624 BFD_RELOC_MN10300_GOT24
2626 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2629 BFD_RELOC_MN10300_GOT16
2631 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2634 BFD_RELOC_MN10300_COPY
2636 Copy symbol at runtime.
2638 BFD_RELOC_MN10300_GLOB_DAT
2642 BFD_RELOC_MN10300_JMP_SLOT
2646 BFD_RELOC_MN10300_RELATIVE
2648 Adjust by program base.
2650 BFD_RELOC_MN10300_SYM_DIFF
2652 Together with another reloc targeted at the same location,
2653 allows for a value that is the difference of two symbols
2654 in the same section.
2656 BFD_RELOC_MN10300_ALIGN
2658 The addend of this reloc is an alignment power that must
2659 be honoured at the offset's location, regardless of linker
2662 BFD_RELOC_MN10300_TLS_GD
2664 BFD_RELOC_MN10300_TLS_LD
2666 BFD_RELOC_MN10300_TLS_LDO
2668 BFD_RELOC_MN10300_TLS_GOTIE
2670 BFD_RELOC_MN10300_TLS_IE
2672 BFD_RELOC_MN10300_TLS_LE
2674 BFD_RELOC_MN10300_TLS_DTPMOD
2676 BFD_RELOC_MN10300_TLS_DTPOFF
2678 BFD_RELOC_MN10300_TLS_TPOFF
2680 Various TLS-related relocations.
2682 BFD_RELOC_MN10300_32_PCREL
2684 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2687 BFD_RELOC_MN10300_16_PCREL
2689 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2700 BFD_RELOC_386_GLOB_DAT
2702 BFD_RELOC_386_JUMP_SLOT
2704 BFD_RELOC_386_RELATIVE
2706 BFD_RELOC_386_GOTOFF
2710 BFD_RELOC_386_TLS_TPOFF
2712 BFD_RELOC_386_TLS_IE
2714 BFD_RELOC_386_TLS_GOTIE
2716 BFD_RELOC_386_TLS_LE
2718 BFD_RELOC_386_TLS_GD
2720 BFD_RELOC_386_TLS_LDM
2722 BFD_RELOC_386_TLS_LDO_32
2724 BFD_RELOC_386_TLS_IE_32
2726 BFD_RELOC_386_TLS_LE_32
2728 BFD_RELOC_386_TLS_DTPMOD32
2730 BFD_RELOC_386_TLS_DTPOFF32
2732 BFD_RELOC_386_TLS_TPOFF32
2734 BFD_RELOC_386_TLS_GOTDESC
2736 BFD_RELOC_386_TLS_DESC_CALL
2738 BFD_RELOC_386_TLS_DESC
2740 BFD_RELOC_386_IRELATIVE
2742 BFD_RELOC_386_GOT32X
2744 i386/elf relocations
2747 BFD_RELOC_X86_64_GOT32
2749 BFD_RELOC_X86_64_PLT32
2751 BFD_RELOC_X86_64_COPY
2753 BFD_RELOC_X86_64_GLOB_DAT
2755 BFD_RELOC_X86_64_JUMP_SLOT
2757 BFD_RELOC_X86_64_RELATIVE
2759 BFD_RELOC_X86_64_GOTPCREL
2761 BFD_RELOC_X86_64_32S
2763 BFD_RELOC_X86_64_DTPMOD64
2765 BFD_RELOC_X86_64_DTPOFF64
2767 BFD_RELOC_X86_64_TPOFF64
2769 BFD_RELOC_X86_64_TLSGD
2771 BFD_RELOC_X86_64_TLSLD
2773 BFD_RELOC_X86_64_DTPOFF32
2775 BFD_RELOC_X86_64_GOTTPOFF
2777 BFD_RELOC_X86_64_TPOFF32
2779 BFD_RELOC_X86_64_GOTOFF64
2781 BFD_RELOC_X86_64_GOTPC32
2783 BFD_RELOC_X86_64_GOT64
2785 BFD_RELOC_X86_64_GOTPCREL64
2787 BFD_RELOC_X86_64_GOTPC64
2789 BFD_RELOC_X86_64_GOTPLT64
2791 BFD_RELOC_X86_64_PLTOFF64
2793 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2795 BFD_RELOC_X86_64_TLSDESC_CALL
2797 BFD_RELOC_X86_64_TLSDESC
2799 BFD_RELOC_X86_64_IRELATIVE
2801 BFD_RELOC_X86_64_PC32_BND
2803 BFD_RELOC_X86_64_PLT32_BND
2805 BFD_RELOC_X86_64_GOTPCRELX
2807 BFD_RELOC_X86_64_REX_GOTPCRELX
2809 x86-64/elf relocations
2812 BFD_RELOC_NS32K_IMM_8
2814 BFD_RELOC_NS32K_IMM_16
2816 BFD_RELOC_NS32K_IMM_32
2818 BFD_RELOC_NS32K_IMM_8_PCREL
2820 BFD_RELOC_NS32K_IMM_16_PCREL
2822 BFD_RELOC_NS32K_IMM_32_PCREL
2824 BFD_RELOC_NS32K_DISP_8
2826 BFD_RELOC_NS32K_DISP_16
2828 BFD_RELOC_NS32K_DISP_32
2830 BFD_RELOC_NS32K_DISP_8_PCREL
2832 BFD_RELOC_NS32K_DISP_16_PCREL
2834 BFD_RELOC_NS32K_DISP_32_PCREL
2839 BFD_RELOC_PDP11_DISP_8_PCREL
2841 BFD_RELOC_PDP11_DISP_6_PCREL
2846 BFD_RELOC_PJ_CODE_HI16
2848 BFD_RELOC_PJ_CODE_LO16
2850 BFD_RELOC_PJ_CODE_DIR16
2852 BFD_RELOC_PJ_CODE_DIR32
2854 BFD_RELOC_PJ_CODE_REL16
2856 BFD_RELOC_PJ_CODE_REL32
2858 Picojava relocs. Not all of these appear in object files.
2869 BFD_RELOC_PPC_B16_BRTAKEN
2871 BFD_RELOC_PPC_B16_BRNTAKEN
2875 BFD_RELOC_PPC_BA16_BRTAKEN
2877 BFD_RELOC_PPC_BA16_BRNTAKEN
2881 BFD_RELOC_PPC_GLOB_DAT
2883 BFD_RELOC_PPC_JMP_SLOT
2885 BFD_RELOC_PPC_RELATIVE
2887 BFD_RELOC_PPC_LOCAL24PC
2889 BFD_RELOC_PPC_EMB_NADDR32
2891 BFD_RELOC_PPC_EMB_NADDR16
2893 BFD_RELOC_PPC_EMB_NADDR16_LO
2895 BFD_RELOC_PPC_EMB_NADDR16_HI
2897 BFD_RELOC_PPC_EMB_NADDR16_HA
2899 BFD_RELOC_PPC_EMB_SDAI16
2901 BFD_RELOC_PPC_EMB_SDA2I16
2903 BFD_RELOC_PPC_EMB_SDA2REL
2905 BFD_RELOC_PPC_EMB_SDA21
2907 BFD_RELOC_PPC_EMB_MRKREF
2909 BFD_RELOC_PPC_EMB_RELSEC16
2911 BFD_RELOC_PPC_EMB_RELST_LO
2913 BFD_RELOC_PPC_EMB_RELST_HI
2915 BFD_RELOC_PPC_EMB_RELST_HA
2917 BFD_RELOC_PPC_EMB_BIT_FLD
2919 BFD_RELOC_PPC_EMB_RELSDA
2921 BFD_RELOC_PPC_VLE_REL8
2923 BFD_RELOC_PPC_VLE_REL15
2925 BFD_RELOC_PPC_VLE_REL24
2927 BFD_RELOC_PPC_VLE_LO16A
2929 BFD_RELOC_PPC_VLE_LO16D
2931 BFD_RELOC_PPC_VLE_HI16A
2933 BFD_RELOC_PPC_VLE_HI16D
2935 BFD_RELOC_PPC_VLE_HA16A
2937 BFD_RELOC_PPC_VLE_HA16D
2939 BFD_RELOC_PPC_VLE_SDA21
2941 BFD_RELOC_PPC_VLE_SDA21_LO
2943 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2945 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2947 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2949 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2951 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2953 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2955 BFD_RELOC_PPC_16DX_HA
2957 BFD_RELOC_PPC_REL16DX_HA
2959 BFD_RELOC_PPC64_HIGHER
2961 BFD_RELOC_PPC64_HIGHER_S
2963 BFD_RELOC_PPC64_HIGHEST
2965 BFD_RELOC_PPC64_HIGHEST_S
2967 BFD_RELOC_PPC64_TOC16_LO
2969 BFD_RELOC_PPC64_TOC16_HI
2971 BFD_RELOC_PPC64_TOC16_HA
2975 BFD_RELOC_PPC64_PLTGOT16
2977 BFD_RELOC_PPC64_PLTGOT16_LO
2979 BFD_RELOC_PPC64_PLTGOT16_HI
2981 BFD_RELOC_PPC64_PLTGOT16_HA
2983 BFD_RELOC_PPC64_ADDR16_DS
2985 BFD_RELOC_PPC64_ADDR16_LO_DS
2987 BFD_RELOC_PPC64_GOT16_DS
2989 BFD_RELOC_PPC64_GOT16_LO_DS
2991 BFD_RELOC_PPC64_PLT16_LO_DS
2993 BFD_RELOC_PPC64_SECTOFF_DS
2995 BFD_RELOC_PPC64_SECTOFF_LO_DS
2997 BFD_RELOC_PPC64_TOC16_DS
2999 BFD_RELOC_PPC64_TOC16_LO_DS
3001 BFD_RELOC_PPC64_PLTGOT16_DS
3003 BFD_RELOC_PPC64_PLTGOT16_LO_DS
3005 BFD_RELOC_PPC64_ADDR16_HIGH
3007 BFD_RELOC_PPC64_ADDR16_HIGHA
3009 BFD_RELOC_PPC64_ADDR64_LOCAL
3011 BFD_RELOC_PPC64_ENTRY
3013 Power(rs6000) and PowerPC relocations.
3022 BFD_RELOC_PPC_DTPMOD
3024 BFD_RELOC_PPC_TPREL16
3026 BFD_RELOC_PPC_TPREL16_LO
3028 BFD_RELOC_PPC_TPREL16_HI
3030 BFD_RELOC_PPC_TPREL16_HA
3034 BFD_RELOC_PPC_DTPREL16
3036 BFD_RELOC_PPC_DTPREL16_LO
3038 BFD_RELOC_PPC_DTPREL16_HI
3040 BFD_RELOC_PPC_DTPREL16_HA
3042 BFD_RELOC_PPC_DTPREL
3044 BFD_RELOC_PPC_GOT_TLSGD16
3046 BFD_RELOC_PPC_GOT_TLSGD16_LO
3048 BFD_RELOC_PPC_GOT_TLSGD16_HI
3050 BFD_RELOC_PPC_GOT_TLSGD16_HA
3052 BFD_RELOC_PPC_GOT_TLSLD16
3054 BFD_RELOC_PPC_GOT_TLSLD16_LO
3056 BFD_RELOC_PPC_GOT_TLSLD16_HI
3058 BFD_RELOC_PPC_GOT_TLSLD16_HA
3060 BFD_RELOC_PPC_GOT_TPREL16
3062 BFD_RELOC_PPC_GOT_TPREL16_LO
3064 BFD_RELOC_PPC_GOT_TPREL16_HI
3066 BFD_RELOC_PPC_GOT_TPREL16_HA
3068 BFD_RELOC_PPC_GOT_DTPREL16
3070 BFD_RELOC_PPC_GOT_DTPREL16_LO
3072 BFD_RELOC_PPC_GOT_DTPREL16_HI
3074 BFD_RELOC_PPC_GOT_DTPREL16_HA
3076 BFD_RELOC_PPC64_TPREL16_DS
3078 BFD_RELOC_PPC64_TPREL16_LO_DS
3080 BFD_RELOC_PPC64_TPREL16_HIGHER
3082 BFD_RELOC_PPC64_TPREL16_HIGHERA
3084 BFD_RELOC_PPC64_TPREL16_HIGHEST
3086 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3088 BFD_RELOC_PPC64_DTPREL16_DS
3090 BFD_RELOC_PPC64_DTPREL16_LO_DS
3092 BFD_RELOC_PPC64_DTPREL16_HIGHER
3094 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3096 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3098 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3100 BFD_RELOC_PPC64_TPREL16_HIGH
3102 BFD_RELOC_PPC64_TPREL16_HIGHA
3104 BFD_RELOC_PPC64_DTPREL16_HIGH
3106 BFD_RELOC_PPC64_DTPREL16_HIGHA
3108 PowerPC and PowerPC64 thread-local storage relocations.
3113 IBM 370/390 relocations
3118 The type of reloc used to build a constructor table - at the moment
3119 probably a 32 bit wide absolute relocation, but the target can choose.
3120 It generally does map to one of the other relocation types.
3123 BFD_RELOC_ARM_PCREL_BRANCH
3125 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3126 not stored in the instruction.
3128 BFD_RELOC_ARM_PCREL_BLX
3130 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3131 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3132 field in the instruction.
3134 BFD_RELOC_THUMB_PCREL_BLX
3136 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3137 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3138 field in the instruction.
3140 BFD_RELOC_ARM_PCREL_CALL
3142 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3144 BFD_RELOC_ARM_PCREL_JUMP
3146 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3149 BFD_RELOC_THUMB_PCREL_BRANCH7
3151 BFD_RELOC_THUMB_PCREL_BRANCH9
3153 BFD_RELOC_THUMB_PCREL_BRANCH12
3155 BFD_RELOC_THUMB_PCREL_BRANCH20
3157 BFD_RELOC_THUMB_PCREL_BRANCH23
3159 BFD_RELOC_THUMB_PCREL_BRANCH25
3161 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3162 The lowest bit must be zero and is not stored in the instruction.
3163 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3164 "nn" one smaller in all cases. Note further that BRANCH23
3165 corresponds to R_ARM_THM_CALL.
3168 BFD_RELOC_ARM_OFFSET_IMM
3170 12-bit immediate offset, used in ARM-format ldr and str instructions.
3173 BFD_RELOC_ARM_THUMB_OFFSET
3175 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3178 BFD_RELOC_ARM_TARGET1
3180 Pc-relative or absolute relocation depending on target. Used for
3181 entries in .init_array sections.
3183 BFD_RELOC_ARM_ROSEGREL32
3185 Read-only segment base relative address.
3187 BFD_RELOC_ARM_SBREL32
3189 Data segment base relative address.
3191 BFD_RELOC_ARM_TARGET2
3193 This reloc is used for references to RTTI data from exception handling
3194 tables. The actual definition depends on the target. It may be a
3195 pc-relative or some form of GOT-indirect relocation.
3197 BFD_RELOC_ARM_PREL31
3199 31-bit PC relative address.
3205 BFD_RELOC_ARM_MOVW_PCREL
3207 BFD_RELOC_ARM_MOVT_PCREL
3209 BFD_RELOC_ARM_THUMB_MOVW
3211 BFD_RELOC_ARM_THUMB_MOVT
3213 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3215 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3217 Low and High halfword relocations for MOVW and MOVT instructions.
3220 BFD_RELOC_ARM_JUMP_SLOT
3222 BFD_RELOC_ARM_GLOB_DAT
3228 BFD_RELOC_ARM_RELATIVE
3230 BFD_RELOC_ARM_GOTOFF
3234 BFD_RELOC_ARM_GOT_PREL
3236 Relocations for setting up GOTs and PLTs for shared libraries.
3239 BFD_RELOC_ARM_TLS_GD32
3241 BFD_RELOC_ARM_TLS_LDO32
3243 BFD_RELOC_ARM_TLS_LDM32
3245 BFD_RELOC_ARM_TLS_DTPOFF32
3247 BFD_RELOC_ARM_TLS_DTPMOD32
3249 BFD_RELOC_ARM_TLS_TPOFF32
3251 BFD_RELOC_ARM_TLS_IE32
3253 BFD_RELOC_ARM_TLS_LE32
3255 BFD_RELOC_ARM_TLS_GOTDESC
3257 BFD_RELOC_ARM_TLS_CALL
3259 BFD_RELOC_ARM_THM_TLS_CALL
3261 BFD_RELOC_ARM_TLS_DESCSEQ
3263 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3265 BFD_RELOC_ARM_TLS_DESC
3267 ARM thread-local storage relocations.
3270 BFD_RELOC_ARM_ALU_PC_G0_NC
3272 BFD_RELOC_ARM_ALU_PC_G0
3274 BFD_RELOC_ARM_ALU_PC_G1_NC
3276 BFD_RELOC_ARM_ALU_PC_G1
3278 BFD_RELOC_ARM_ALU_PC_G2
3280 BFD_RELOC_ARM_LDR_PC_G0
3282 BFD_RELOC_ARM_LDR_PC_G1
3284 BFD_RELOC_ARM_LDR_PC_G2
3286 BFD_RELOC_ARM_LDRS_PC_G0
3288 BFD_RELOC_ARM_LDRS_PC_G1
3290 BFD_RELOC_ARM_LDRS_PC_G2
3292 BFD_RELOC_ARM_LDC_PC_G0
3294 BFD_RELOC_ARM_LDC_PC_G1
3296 BFD_RELOC_ARM_LDC_PC_G2
3298 BFD_RELOC_ARM_ALU_SB_G0_NC
3300 BFD_RELOC_ARM_ALU_SB_G0
3302 BFD_RELOC_ARM_ALU_SB_G1_NC
3304 BFD_RELOC_ARM_ALU_SB_G1
3306 BFD_RELOC_ARM_ALU_SB_G2
3308 BFD_RELOC_ARM_LDR_SB_G0
3310 BFD_RELOC_ARM_LDR_SB_G1
3312 BFD_RELOC_ARM_LDR_SB_G2
3314 BFD_RELOC_ARM_LDRS_SB_G0
3316 BFD_RELOC_ARM_LDRS_SB_G1
3318 BFD_RELOC_ARM_LDRS_SB_G2
3320 BFD_RELOC_ARM_LDC_SB_G0
3322 BFD_RELOC_ARM_LDC_SB_G1
3324 BFD_RELOC_ARM_LDC_SB_G2
3326 ARM group relocations.
3331 Annotation of BX instructions.
3334 BFD_RELOC_ARM_IRELATIVE
3336 ARM support for STT_GNU_IFUNC.
3339 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3341 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3343 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3345 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3347 Thumb1 relocations to support execute-only code.
3350 BFD_RELOC_ARM_IMMEDIATE
3352 BFD_RELOC_ARM_ADRL_IMMEDIATE
3354 BFD_RELOC_ARM_T32_IMMEDIATE
3356 BFD_RELOC_ARM_T32_ADD_IMM
3358 BFD_RELOC_ARM_T32_IMM12
3360 BFD_RELOC_ARM_T32_ADD_PC12
3362 BFD_RELOC_ARM_SHIFT_IMM
3372 BFD_RELOC_ARM_CP_OFF_IMM
3374 BFD_RELOC_ARM_CP_OFF_IMM_S2
3376 BFD_RELOC_ARM_T32_CP_OFF_IMM
3378 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3380 BFD_RELOC_ARM_ADR_IMM
3382 BFD_RELOC_ARM_LDR_IMM
3384 BFD_RELOC_ARM_LITERAL
3386 BFD_RELOC_ARM_IN_POOL
3388 BFD_RELOC_ARM_OFFSET_IMM8
3390 BFD_RELOC_ARM_T32_OFFSET_U8
3392 BFD_RELOC_ARM_T32_OFFSET_IMM
3394 BFD_RELOC_ARM_HWLITERAL
3396 BFD_RELOC_ARM_THUMB_ADD
3398 BFD_RELOC_ARM_THUMB_IMM
3400 BFD_RELOC_ARM_THUMB_SHIFT
3402 These relocs are only used within the ARM assembler. They are not
3403 (at present) written to any object files.
3406 BFD_RELOC_SH_PCDISP8BY2
3408 BFD_RELOC_SH_PCDISP12BY2
3416 BFD_RELOC_SH_DISP12BY2
3418 BFD_RELOC_SH_DISP12BY4
3420 BFD_RELOC_SH_DISP12BY8
3424 BFD_RELOC_SH_DISP20BY8
3428 BFD_RELOC_SH_IMM4BY2
3430 BFD_RELOC_SH_IMM4BY4
3434 BFD_RELOC_SH_IMM8BY2
3436 BFD_RELOC_SH_IMM8BY4
3438 BFD_RELOC_SH_PCRELIMM8BY2
3440 BFD_RELOC_SH_PCRELIMM8BY4
3442 BFD_RELOC_SH_SWITCH16
3444 BFD_RELOC_SH_SWITCH32
3458 BFD_RELOC_SH_LOOP_START
3460 BFD_RELOC_SH_LOOP_END
3464 BFD_RELOC_SH_GLOB_DAT
3466 BFD_RELOC_SH_JMP_SLOT
3468 BFD_RELOC_SH_RELATIVE
3472 BFD_RELOC_SH_GOT_LOW16
3474 BFD_RELOC_SH_GOT_MEDLOW16
3476 BFD_RELOC_SH_GOT_MEDHI16
3478 BFD_RELOC_SH_GOT_HI16
3480 BFD_RELOC_SH_GOTPLT_LOW16
3482 BFD_RELOC_SH_GOTPLT_MEDLOW16
3484 BFD_RELOC_SH_GOTPLT_MEDHI16
3486 BFD_RELOC_SH_GOTPLT_HI16
3488 BFD_RELOC_SH_PLT_LOW16
3490 BFD_RELOC_SH_PLT_MEDLOW16
3492 BFD_RELOC_SH_PLT_MEDHI16
3494 BFD_RELOC_SH_PLT_HI16
3496 BFD_RELOC_SH_GOTOFF_LOW16
3498 BFD_RELOC_SH_GOTOFF_MEDLOW16
3500 BFD_RELOC_SH_GOTOFF_MEDHI16
3502 BFD_RELOC_SH_GOTOFF_HI16
3504 BFD_RELOC_SH_GOTPC_LOW16
3506 BFD_RELOC_SH_GOTPC_MEDLOW16
3508 BFD_RELOC_SH_GOTPC_MEDHI16
3510 BFD_RELOC_SH_GOTPC_HI16
3514 BFD_RELOC_SH_GLOB_DAT64
3516 BFD_RELOC_SH_JMP_SLOT64
3518 BFD_RELOC_SH_RELATIVE64
3520 BFD_RELOC_SH_GOT10BY4
3522 BFD_RELOC_SH_GOT10BY8
3524 BFD_RELOC_SH_GOTPLT10BY4
3526 BFD_RELOC_SH_GOTPLT10BY8
3528 BFD_RELOC_SH_GOTPLT32
3530 BFD_RELOC_SH_SHMEDIA_CODE
3536 BFD_RELOC_SH_IMMS6BY32
3542 BFD_RELOC_SH_IMMS10BY2
3544 BFD_RELOC_SH_IMMS10BY4
3546 BFD_RELOC_SH_IMMS10BY8
3552 BFD_RELOC_SH_IMM_LOW16
3554 BFD_RELOC_SH_IMM_LOW16_PCREL
3556 BFD_RELOC_SH_IMM_MEDLOW16
3558 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3560 BFD_RELOC_SH_IMM_MEDHI16
3562 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3564 BFD_RELOC_SH_IMM_HI16
3566 BFD_RELOC_SH_IMM_HI16_PCREL
3570 BFD_RELOC_SH_TLS_GD_32
3572 BFD_RELOC_SH_TLS_LD_32
3574 BFD_RELOC_SH_TLS_LDO_32
3576 BFD_RELOC_SH_TLS_IE_32
3578 BFD_RELOC_SH_TLS_LE_32
3580 BFD_RELOC_SH_TLS_DTPMOD32
3582 BFD_RELOC_SH_TLS_DTPOFF32
3584 BFD_RELOC_SH_TLS_TPOFF32
3588 BFD_RELOC_SH_GOTOFF20
3590 BFD_RELOC_SH_GOTFUNCDESC
3592 BFD_RELOC_SH_GOTFUNCDESC20
3594 BFD_RELOC_SH_GOTOFFFUNCDESC
3596 BFD_RELOC_SH_GOTOFFFUNCDESC20
3598 BFD_RELOC_SH_FUNCDESC
3600 Renesas / SuperH SH relocs. Not all of these appear in object files.
3623 BFD_RELOC_ARC_SECTOFF
3625 BFD_RELOC_ARC_S21H_PCREL
3627 BFD_RELOC_ARC_S21W_PCREL
3629 BFD_RELOC_ARC_S25H_PCREL
3631 BFD_RELOC_ARC_S25W_PCREL
3635 BFD_RELOC_ARC_SDA_LDST
3637 BFD_RELOC_ARC_SDA_LDST1
3639 BFD_RELOC_ARC_SDA_LDST2
3641 BFD_RELOC_ARC_SDA16_LD
3643 BFD_RELOC_ARC_SDA16_LD1
3645 BFD_RELOC_ARC_SDA16_LD2
3647 BFD_RELOC_ARC_S13_PCREL
3653 BFD_RELOC_ARC_32_ME_S
3655 BFD_RELOC_ARC_N32_ME
3657 BFD_RELOC_ARC_SECTOFF_ME
3659 BFD_RELOC_ARC_SDA32_ME
3663 BFD_RELOC_AC_SECTOFF_U8
3665 BFD_RELOC_AC_SECTOFF_U8_1
3667 BFD_RELOC_AC_SECTOFF_U8_2
3669 BFD_RELOC_AC_SECTOFF_S9
3671 BFD_RELOC_AC_SECTOFF_S9_1
3673 BFD_RELOC_AC_SECTOFF_S9_2
3675 BFD_RELOC_ARC_SECTOFF_ME_1
3677 BFD_RELOC_ARC_SECTOFF_ME_2
3679 BFD_RELOC_ARC_SECTOFF_1
3681 BFD_RELOC_ARC_SECTOFF_2
3683 BFD_RELOC_ARC_SDA_12
3685 BFD_RELOC_ARC_SDA16_ST2
3687 BFD_RELOC_ARC_32_PCREL
3693 BFD_RELOC_ARC_GOTPC32
3699 BFD_RELOC_ARC_GLOB_DAT
3701 BFD_RELOC_ARC_JMP_SLOT
3703 BFD_RELOC_ARC_RELATIVE
3705 BFD_RELOC_ARC_GOTOFF
3709 BFD_RELOC_ARC_S21W_PCREL_PLT
3711 BFD_RELOC_ARC_S25H_PCREL_PLT
3713 BFD_RELOC_ARC_TLS_DTPMOD
3715 BFD_RELOC_ARC_TLS_TPOFF
3717 BFD_RELOC_ARC_TLS_GD_GOT
3719 BFD_RELOC_ARC_TLS_GD_LD
3721 BFD_RELOC_ARC_TLS_GD_CALL
3723 BFD_RELOC_ARC_TLS_IE_GOT
3725 BFD_RELOC_ARC_TLS_DTPOFF
3727 BFD_RELOC_ARC_TLS_DTPOFF_S9
3729 BFD_RELOC_ARC_TLS_LE_S9
3731 BFD_RELOC_ARC_TLS_LE_32
3733 BFD_RELOC_ARC_S25W_PCREL_PLT
3735 BFD_RELOC_ARC_S21H_PCREL_PLT
3737 BFD_RELOC_ARC_NPS_CMEM16
3739 BFD_RELOC_ARC_JLI_SECTOFF
3744 BFD_RELOC_BFIN_16_IMM
3746 ADI Blackfin 16 bit immediate absolute reloc.
3748 BFD_RELOC_BFIN_16_HIGH
3750 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3752 BFD_RELOC_BFIN_4_PCREL
3754 ADI Blackfin 'a' part of LSETUP.
3756 BFD_RELOC_BFIN_5_PCREL
3760 BFD_RELOC_BFIN_16_LOW
3762 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3764 BFD_RELOC_BFIN_10_PCREL
3768 BFD_RELOC_BFIN_11_PCREL
3770 ADI Blackfin 'b' part of LSETUP.
3772 BFD_RELOC_BFIN_12_PCREL_JUMP
3776 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3778 ADI Blackfin Short jump, pcrel.
3780 BFD_RELOC_BFIN_24_PCREL_CALL_X
3782 ADI Blackfin Call.x not implemented.
3784 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3786 ADI Blackfin Long Jump pcrel.
3788 BFD_RELOC_BFIN_GOT17M4
3790 BFD_RELOC_BFIN_GOTHI
3792 BFD_RELOC_BFIN_GOTLO
3794 BFD_RELOC_BFIN_FUNCDESC
3796 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3798 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3800 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3802 BFD_RELOC_BFIN_FUNCDESC_VALUE
3804 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3806 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3808 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3810 BFD_RELOC_BFIN_GOTOFF17M4
3812 BFD_RELOC_BFIN_GOTOFFHI
3814 BFD_RELOC_BFIN_GOTOFFLO
3816 ADI Blackfin FD-PIC relocations.
3820 ADI Blackfin GOT relocation.
3822 BFD_RELOC_BFIN_PLTPC
3824 ADI Blackfin PLTPC relocation.
3826 BFD_ARELOC_BFIN_PUSH
3828 ADI Blackfin arithmetic relocation.
3830 BFD_ARELOC_BFIN_CONST
3832 ADI Blackfin arithmetic relocation.
3836 ADI Blackfin arithmetic relocation.
3840 ADI Blackfin arithmetic relocation.
3842 BFD_ARELOC_BFIN_MULT
3844 ADI Blackfin arithmetic relocation.
3848 ADI Blackfin arithmetic relocation.
3852 ADI Blackfin arithmetic relocation.
3854 BFD_ARELOC_BFIN_LSHIFT
3856 ADI Blackfin arithmetic relocation.
3858 BFD_ARELOC_BFIN_RSHIFT
3860 ADI Blackfin arithmetic relocation.
3864 ADI Blackfin arithmetic relocation.
3868 ADI Blackfin arithmetic relocation.
3872 ADI Blackfin arithmetic relocation.
3874 BFD_ARELOC_BFIN_LAND
3876 ADI Blackfin arithmetic relocation.
3880 ADI Blackfin arithmetic relocation.
3884 ADI Blackfin arithmetic relocation.
3888 ADI Blackfin arithmetic relocation.
3890 BFD_ARELOC_BFIN_COMP
3892 ADI Blackfin arithmetic relocation.
3894 BFD_ARELOC_BFIN_PAGE
3896 ADI Blackfin arithmetic relocation.
3898 BFD_ARELOC_BFIN_HWPAGE
3900 ADI Blackfin arithmetic relocation.
3902 BFD_ARELOC_BFIN_ADDR
3904 ADI Blackfin arithmetic relocation.
3907 BFD_RELOC_D10V_10_PCREL_R
3909 Mitsubishi D10V relocs.
3910 This is a 10-bit reloc with the right 2 bits
3913 BFD_RELOC_D10V_10_PCREL_L
3915 Mitsubishi D10V relocs.
3916 This is a 10-bit reloc with the right 2 bits
3917 assumed to be 0. This is the same as the previous reloc
3918 except it is in the left container, i.e.,
3919 shifted left 15 bits.
3923 This is an 18-bit reloc with the right 2 bits
3926 BFD_RELOC_D10V_18_PCREL
3928 This is an 18-bit reloc with the right 2 bits
3934 Mitsubishi D30V relocs.
3935 This is a 6-bit absolute reloc.
3937 BFD_RELOC_D30V_9_PCREL
3939 This is a 6-bit pc-relative reloc with
3940 the right 3 bits assumed to be 0.
3942 BFD_RELOC_D30V_9_PCREL_R
3944 This is a 6-bit pc-relative reloc with
3945 the right 3 bits assumed to be 0. Same
3946 as the previous reloc but on the right side
3951 This is a 12-bit absolute reloc with the
3952 right 3 bitsassumed to be 0.
3954 BFD_RELOC_D30V_15_PCREL
3956 This is a 12-bit pc-relative reloc with
3957 the right 3 bits assumed to be 0.
3959 BFD_RELOC_D30V_15_PCREL_R
3961 This is a 12-bit pc-relative reloc with
3962 the right 3 bits assumed to be 0. Same
3963 as the previous reloc but on the right side
3968 This is an 18-bit absolute reloc with
3969 the right 3 bits assumed to be 0.
3971 BFD_RELOC_D30V_21_PCREL
3973 This is an 18-bit pc-relative reloc with
3974 the right 3 bits assumed to be 0.
3976 BFD_RELOC_D30V_21_PCREL_R
3978 This is an 18-bit pc-relative reloc with
3979 the right 3 bits assumed to be 0. Same
3980 as the previous reloc but on the right side
3985 This is a 32-bit absolute reloc.
3987 BFD_RELOC_D30V_32_PCREL
3989 This is a 32-bit pc-relative reloc.
3992 BFD_RELOC_DLX_HI16_S
4007 BFD_RELOC_M32C_RL_JUMP
4009 BFD_RELOC_M32C_RL_1ADDR
4011 BFD_RELOC_M32C_RL_2ADDR
4013 Renesas M16C/M32C Relocations.
4018 Renesas M32R (formerly Mitsubishi M32R) relocs.
4019 This is a 24 bit absolute address.
4021 BFD_RELOC_M32R_10_PCREL
4023 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4025 BFD_RELOC_M32R_18_PCREL
4027 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4029 BFD_RELOC_M32R_26_PCREL
4031 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4033 BFD_RELOC_M32R_HI16_ULO
4035 This is a 16-bit reloc containing the high 16 bits of an address
4036 used when the lower 16 bits are treated as unsigned.
4038 BFD_RELOC_M32R_HI16_SLO
4040 This is a 16-bit reloc containing the high 16 bits of an address
4041 used when the lower 16 bits are treated as signed.
4045 This is a 16-bit reloc containing the lower 16 bits of an address.
4047 BFD_RELOC_M32R_SDA16
4049 This is a 16-bit reloc containing the small data area offset for use in
4050 add3, load, and store instructions.
4052 BFD_RELOC_M32R_GOT24
4054 BFD_RELOC_M32R_26_PLTREL
4058 BFD_RELOC_M32R_GLOB_DAT
4060 BFD_RELOC_M32R_JMP_SLOT
4062 BFD_RELOC_M32R_RELATIVE
4064 BFD_RELOC_M32R_GOTOFF
4066 BFD_RELOC_M32R_GOTOFF_HI_ULO
4068 BFD_RELOC_M32R_GOTOFF_HI_SLO
4070 BFD_RELOC_M32R_GOTOFF_LO
4072 BFD_RELOC_M32R_GOTPC24
4074 BFD_RELOC_M32R_GOT16_HI_ULO
4076 BFD_RELOC_M32R_GOT16_HI_SLO
4078 BFD_RELOC_M32R_GOT16_LO
4080 BFD_RELOC_M32R_GOTPC_HI_ULO
4082 BFD_RELOC_M32R_GOTPC_HI_SLO
4084 BFD_RELOC_M32R_GOTPC_LO
4093 This is a 20 bit absolute address.
4095 BFD_RELOC_NDS32_9_PCREL
4097 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4099 BFD_RELOC_NDS32_WORD_9_PCREL
4101 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4103 BFD_RELOC_NDS32_15_PCREL
4105 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4107 BFD_RELOC_NDS32_17_PCREL
4109 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4111 BFD_RELOC_NDS32_25_PCREL
4113 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4115 BFD_RELOC_NDS32_HI20
4117 This is a 20-bit reloc containing the high 20 bits of an address
4118 used with the lower 12 bits
4120 BFD_RELOC_NDS32_LO12S3
4122 This is a 12-bit reloc containing the lower 12 bits of an address
4123 then shift right by 3. This is used with ldi,sdi...
4125 BFD_RELOC_NDS32_LO12S2
4127 This is a 12-bit reloc containing the lower 12 bits of an address
4128 then shift left by 2. This is used with lwi,swi...
4130 BFD_RELOC_NDS32_LO12S1
4132 This is a 12-bit reloc containing the lower 12 bits of an address
4133 then shift left by 1. This is used with lhi,shi...
4135 BFD_RELOC_NDS32_LO12S0
4137 This is a 12-bit reloc containing the lower 12 bits of an address
4138 then shift left by 0. This is used with lbisbi...
4140 BFD_RELOC_NDS32_LO12S0_ORI
4142 This is a 12-bit reloc containing the lower 12 bits of an address
4143 then shift left by 0. This is only used with branch relaxations
4145 BFD_RELOC_NDS32_SDA15S3
4147 This is a 15-bit reloc containing the small data area 18-bit signed offset
4148 and shift left by 3 for use in ldi, sdi...
4150 BFD_RELOC_NDS32_SDA15S2
4152 This is a 15-bit reloc containing the small data area 17-bit signed offset
4153 and shift left by 2 for use in lwi, swi...
4155 BFD_RELOC_NDS32_SDA15S1
4157 This is a 15-bit reloc containing the small data area 16-bit signed offset
4158 and shift left by 1 for use in lhi, shi...
4160 BFD_RELOC_NDS32_SDA15S0
4162 This is a 15-bit reloc containing the small data area 15-bit signed offset
4163 and shift left by 0 for use in lbi, sbi...
4165 BFD_RELOC_NDS32_SDA16S3
4167 This is a 16-bit reloc containing the small data area 16-bit signed offset
4170 BFD_RELOC_NDS32_SDA17S2
4172 This is a 17-bit reloc containing the small data area 17-bit signed offset
4173 and shift left by 2 for use in lwi.gp, swi.gp...
4175 BFD_RELOC_NDS32_SDA18S1
4177 This is a 18-bit reloc containing the small data area 18-bit signed offset
4178 and shift left by 1 for use in lhi.gp, shi.gp...
4180 BFD_RELOC_NDS32_SDA19S0
4182 This is a 19-bit reloc containing the small data area 19-bit signed offset
4183 and shift left by 0 for use in lbi.gp, sbi.gp...
4185 BFD_RELOC_NDS32_GOT20
4187 BFD_RELOC_NDS32_9_PLTREL
4189 BFD_RELOC_NDS32_25_PLTREL
4191 BFD_RELOC_NDS32_COPY
4193 BFD_RELOC_NDS32_GLOB_DAT
4195 BFD_RELOC_NDS32_JMP_SLOT
4197 BFD_RELOC_NDS32_RELATIVE
4199 BFD_RELOC_NDS32_GOTOFF
4201 BFD_RELOC_NDS32_GOTOFF_HI20
4203 BFD_RELOC_NDS32_GOTOFF_LO12
4205 BFD_RELOC_NDS32_GOTPC20
4207 BFD_RELOC_NDS32_GOT_HI20
4209 BFD_RELOC_NDS32_GOT_LO12
4211 BFD_RELOC_NDS32_GOTPC_HI20
4213 BFD_RELOC_NDS32_GOTPC_LO12
4217 BFD_RELOC_NDS32_INSN16
4219 BFD_RELOC_NDS32_LABEL
4221 BFD_RELOC_NDS32_LONGCALL1
4223 BFD_RELOC_NDS32_LONGCALL2
4225 BFD_RELOC_NDS32_LONGCALL3
4227 BFD_RELOC_NDS32_LONGJUMP1
4229 BFD_RELOC_NDS32_LONGJUMP2
4231 BFD_RELOC_NDS32_LONGJUMP3
4233 BFD_RELOC_NDS32_LOADSTORE
4235 BFD_RELOC_NDS32_9_FIXED
4237 BFD_RELOC_NDS32_15_FIXED
4239 BFD_RELOC_NDS32_17_FIXED
4241 BFD_RELOC_NDS32_25_FIXED
4243 BFD_RELOC_NDS32_LONGCALL4
4245 BFD_RELOC_NDS32_LONGCALL5
4247 BFD_RELOC_NDS32_LONGCALL6
4249 BFD_RELOC_NDS32_LONGJUMP4
4251 BFD_RELOC_NDS32_LONGJUMP5
4253 BFD_RELOC_NDS32_LONGJUMP6
4255 BFD_RELOC_NDS32_LONGJUMP7
4259 BFD_RELOC_NDS32_PLTREL_HI20
4261 BFD_RELOC_NDS32_PLTREL_LO12
4263 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4265 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4269 BFD_RELOC_NDS32_SDA12S2_DP
4271 BFD_RELOC_NDS32_SDA12S2_SP
4273 BFD_RELOC_NDS32_LO12S2_DP
4275 BFD_RELOC_NDS32_LO12S2_SP
4279 BFD_RELOC_NDS32_DWARF2_OP1
4281 BFD_RELOC_NDS32_DWARF2_OP2
4283 BFD_RELOC_NDS32_DWARF2_LEB
4285 for dwarf2 debug_line.
4287 BFD_RELOC_NDS32_UPDATE_TA
4289 for eliminate 16-bit instructions
4291 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4293 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4295 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4297 BFD_RELOC_NDS32_GOT_LO15
4299 BFD_RELOC_NDS32_GOT_LO19
4301 BFD_RELOC_NDS32_GOTOFF_LO15
4303 BFD_RELOC_NDS32_GOTOFF_LO19
4305 BFD_RELOC_NDS32_GOT15S2
4307 BFD_RELOC_NDS32_GOT17S2
4309 for PIC object relaxation
4314 This is a 5 bit absolute address.
4316 BFD_RELOC_NDS32_10_UPCREL
4318 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4320 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4322 If fp were omitted, fp can used as another gp.
4324 BFD_RELOC_NDS32_RELAX_ENTRY
4326 BFD_RELOC_NDS32_GOT_SUFF
4328 BFD_RELOC_NDS32_GOTOFF_SUFF
4330 BFD_RELOC_NDS32_PLT_GOT_SUFF
4332 BFD_RELOC_NDS32_MULCALL_SUFF
4336 BFD_RELOC_NDS32_PTR_COUNT
4338 BFD_RELOC_NDS32_PTR_RESOLVED
4340 BFD_RELOC_NDS32_PLTBLOCK
4342 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4344 BFD_RELOC_NDS32_RELAX_REGION_END
4346 BFD_RELOC_NDS32_MINUEND
4348 BFD_RELOC_NDS32_SUBTRAHEND
4350 BFD_RELOC_NDS32_DIFF8
4352 BFD_RELOC_NDS32_DIFF16
4354 BFD_RELOC_NDS32_DIFF32
4356 BFD_RELOC_NDS32_DIFF_ULEB128
4358 BFD_RELOC_NDS32_EMPTY
4360 relaxation relative relocation types
4362 BFD_RELOC_NDS32_25_ABS
4364 This is a 25 bit absolute address.
4366 BFD_RELOC_NDS32_DATA
4368 BFD_RELOC_NDS32_TRAN
4370 BFD_RELOC_NDS32_17IFC_PCREL
4372 BFD_RELOC_NDS32_10IFCU_PCREL
4374 For ex9 and ifc using.
4376 BFD_RELOC_NDS32_TPOFF
4378 BFD_RELOC_NDS32_TLS_LE_HI20
4380 BFD_RELOC_NDS32_TLS_LE_LO12
4382 BFD_RELOC_NDS32_TLS_LE_ADD
4384 BFD_RELOC_NDS32_TLS_LE_LS
4386 BFD_RELOC_NDS32_GOTTPOFF
4388 BFD_RELOC_NDS32_TLS_IE_HI20
4390 BFD_RELOC_NDS32_TLS_IE_LO12S2
4392 BFD_RELOC_NDS32_TLS_TPOFF
4394 BFD_RELOC_NDS32_TLS_LE_20
4396 BFD_RELOC_NDS32_TLS_LE_15S0
4398 BFD_RELOC_NDS32_TLS_LE_15S1
4400 BFD_RELOC_NDS32_TLS_LE_15S2
4406 BFD_RELOC_V850_9_PCREL
4408 This is a 9-bit reloc
4410 BFD_RELOC_V850_22_PCREL
4412 This is a 22-bit reloc
4415 BFD_RELOC_V850_SDA_16_16_OFFSET
4417 This is a 16 bit offset from the short data area pointer.
4419 BFD_RELOC_V850_SDA_15_16_OFFSET
4421 This is a 16 bit offset (of which only 15 bits are used) from the
4422 short data area pointer.
4424 BFD_RELOC_V850_ZDA_16_16_OFFSET
4426 This is a 16 bit offset from the zero data area pointer.
4428 BFD_RELOC_V850_ZDA_15_16_OFFSET
4430 This is a 16 bit offset (of which only 15 bits are used) from the
4431 zero data area pointer.
4433 BFD_RELOC_V850_TDA_6_8_OFFSET
4435 This is an 8 bit offset (of which only 6 bits are used) from the
4436 tiny data area pointer.
4438 BFD_RELOC_V850_TDA_7_8_OFFSET
4440 This is an 8bit offset (of which only 7 bits are used) from the tiny
4443 BFD_RELOC_V850_TDA_7_7_OFFSET
4445 This is a 7 bit offset from the tiny data area pointer.
4447 BFD_RELOC_V850_TDA_16_16_OFFSET
4449 This is a 16 bit offset from the tiny data area pointer.
4452 BFD_RELOC_V850_TDA_4_5_OFFSET
4454 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4457 BFD_RELOC_V850_TDA_4_4_OFFSET
4459 This is a 4 bit offset from the tiny data area pointer.
4461 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4463 This is a 16 bit offset from the short data area pointer, with the
4464 bits placed non-contiguously in the instruction.
4466 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4468 This is a 16 bit offset from the zero data area pointer, with the
4469 bits placed non-contiguously in the instruction.
4471 BFD_RELOC_V850_CALLT_6_7_OFFSET
4473 This is a 6 bit offset from the call table base pointer.
4475 BFD_RELOC_V850_CALLT_16_16_OFFSET
4477 This is a 16 bit offset from the call table base pointer.
4479 BFD_RELOC_V850_LONGCALL
4481 Used for relaxing indirect function calls.
4483 BFD_RELOC_V850_LONGJUMP
4485 Used for relaxing indirect jumps.
4487 BFD_RELOC_V850_ALIGN
4489 Used to maintain alignment whilst relaxing.
4491 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4493 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4496 BFD_RELOC_V850_16_PCREL
4498 This is a 16-bit reloc.
4500 BFD_RELOC_V850_17_PCREL
4502 This is a 17-bit reloc.
4506 This is a 23-bit reloc.
4508 BFD_RELOC_V850_32_PCREL
4510 This is a 32-bit reloc.
4512 BFD_RELOC_V850_32_ABS
4514 This is a 32-bit reloc.
4516 BFD_RELOC_V850_16_SPLIT_OFFSET
4518 This is a 16-bit reloc.
4520 BFD_RELOC_V850_16_S1
4522 This is a 16-bit reloc.
4524 BFD_RELOC_V850_LO16_S1
4526 Low 16 bits. 16 bit shifted by 1.
4528 BFD_RELOC_V850_CALLT_15_16_OFFSET
4530 This is a 16 bit offset from the call table base pointer.
4532 BFD_RELOC_V850_32_GOTPCREL
4536 BFD_RELOC_V850_16_GOT
4540 BFD_RELOC_V850_32_GOT
4544 BFD_RELOC_V850_22_PLT_PCREL
4548 BFD_RELOC_V850_32_PLT_PCREL
4556 BFD_RELOC_V850_GLOB_DAT
4560 BFD_RELOC_V850_JMP_SLOT
4564 BFD_RELOC_V850_RELATIVE
4568 BFD_RELOC_V850_16_GOTOFF
4572 BFD_RELOC_V850_32_GOTOFF
4587 This is a 8bit DP reloc for the tms320c30, where the most
4588 significant 8 bits of a 24 bit word are placed into the least
4589 significant 8 bits of the opcode.
4592 BFD_RELOC_TIC54X_PARTLS7
4594 This is a 7bit reloc for the tms320c54x, where the least
4595 significant 7 bits of a 16 bit word are placed into the least
4596 significant 7 bits of the opcode.
4599 BFD_RELOC_TIC54X_PARTMS9
4601 This is a 9bit DP reloc for the tms320c54x, where the most
4602 significant 9 bits of a 16 bit word are placed into the least
4603 significant 9 bits of the opcode.
4608 This is an extended address 23-bit reloc for the tms320c54x.
4611 BFD_RELOC_TIC54X_16_OF_23
4613 This is a 16-bit reloc for the tms320c54x, where the least
4614 significant 16 bits of a 23-bit extended address are placed into
4618 BFD_RELOC_TIC54X_MS7_OF_23
4620 This is a reloc for the tms320c54x, where the most
4621 significant 7 bits of a 23-bit extended address are placed into
4625 BFD_RELOC_C6000_PCR_S21
4627 BFD_RELOC_C6000_PCR_S12
4629 BFD_RELOC_C6000_PCR_S10
4631 BFD_RELOC_C6000_PCR_S7
4633 BFD_RELOC_C6000_ABS_S16
4635 BFD_RELOC_C6000_ABS_L16
4637 BFD_RELOC_C6000_ABS_H16
4639 BFD_RELOC_C6000_SBR_U15_B
4641 BFD_RELOC_C6000_SBR_U15_H
4643 BFD_RELOC_C6000_SBR_U15_W
4645 BFD_RELOC_C6000_SBR_S16
4647 BFD_RELOC_C6000_SBR_L16_B
4649 BFD_RELOC_C6000_SBR_L16_H
4651 BFD_RELOC_C6000_SBR_L16_W
4653 BFD_RELOC_C6000_SBR_H16_B
4655 BFD_RELOC_C6000_SBR_H16_H
4657 BFD_RELOC_C6000_SBR_H16_W
4659 BFD_RELOC_C6000_SBR_GOT_U15_W
4661 BFD_RELOC_C6000_SBR_GOT_L16_W
4663 BFD_RELOC_C6000_SBR_GOT_H16_W
4665 BFD_RELOC_C6000_DSBT_INDEX
4667 BFD_RELOC_C6000_PREL31
4669 BFD_RELOC_C6000_COPY
4671 BFD_RELOC_C6000_JUMP_SLOT
4673 BFD_RELOC_C6000_EHTYPE
4675 BFD_RELOC_C6000_PCR_H16
4677 BFD_RELOC_C6000_PCR_L16
4679 BFD_RELOC_C6000_ALIGN
4681 BFD_RELOC_C6000_FPHEAD
4683 BFD_RELOC_C6000_NOCMP
4685 TMS320C6000 relocations.
4690 This is a 48 bit reloc for the FR30 that stores 32 bits.
4694 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4697 BFD_RELOC_FR30_6_IN_4
4699 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4702 BFD_RELOC_FR30_8_IN_8
4704 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4707 BFD_RELOC_FR30_9_IN_8
4709 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4712 BFD_RELOC_FR30_10_IN_8
4714 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4717 BFD_RELOC_FR30_9_PCREL
4719 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4720 short offset into 8 bits.
4722 BFD_RELOC_FR30_12_PCREL
4724 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4725 short offset into 11 bits.
4728 BFD_RELOC_MCORE_PCREL_IMM8BY4
4730 BFD_RELOC_MCORE_PCREL_IMM11BY2
4732 BFD_RELOC_MCORE_PCREL_IMM4BY2
4734 BFD_RELOC_MCORE_PCREL_32
4736 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4740 Motorola Mcore relocations.
4749 BFD_RELOC_MEP_PCREL8A2
4751 BFD_RELOC_MEP_PCREL12A2
4753 BFD_RELOC_MEP_PCREL17A2
4755 BFD_RELOC_MEP_PCREL24A2
4757 BFD_RELOC_MEP_PCABS24A2
4769 BFD_RELOC_MEP_TPREL7
4771 BFD_RELOC_MEP_TPREL7A2
4773 BFD_RELOC_MEP_TPREL7A4
4775 BFD_RELOC_MEP_UIMM24
4777 BFD_RELOC_MEP_ADDR24A4
4779 BFD_RELOC_MEP_GNU_VTINHERIT
4781 BFD_RELOC_MEP_GNU_VTENTRY
4783 Toshiba Media Processor Relocations.
4787 BFD_RELOC_METAG_HIADDR16
4789 BFD_RELOC_METAG_LOADDR16
4791 BFD_RELOC_METAG_RELBRANCH
4793 BFD_RELOC_METAG_GETSETOFF
4795 BFD_RELOC_METAG_HIOG
4797 BFD_RELOC_METAG_LOOG
4799 BFD_RELOC_METAG_REL8
4801 BFD_RELOC_METAG_REL16
4803 BFD_RELOC_METAG_HI16_GOTOFF
4805 BFD_RELOC_METAG_LO16_GOTOFF
4807 BFD_RELOC_METAG_GETSET_GOTOFF
4809 BFD_RELOC_METAG_GETSET_GOT
4811 BFD_RELOC_METAG_HI16_GOTPC
4813 BFD_RELOC_METAG_LO16_GOTPC
4815 BFD_RELOC_METAG_HI16_PLT
4817 BFD_RELOC_METAG_LO16_PLT
4819 BFD_RELOC_METAG_RELBRANCH_PLT
4821 BFD_RELOC_METAG_GOTOFF
4825 BFD_RELOC_METAG_COPY
4827 BFD_RELOC_METAG_JMP_SLOT
4829 BFD_RELOC_METAG_RELATIVE
4831 BFD_RELOC_METAG_GLOB_DAT
4833 BFD_RELOC_METAG_TLS_GD
4835 BFD_RELOC_METAG_TLS_LDM
4837 BFD_RELOC_METAG_TLS_LDO_HI16
4839 BFD_RELOC_METAG_TLS_LDO_LO16
4841 BFD_RELOC_METAG_TLS_LDO
4843 BFD_RELOC_METAG_TLS_IE
4845 BFD_RELOC_METAG_TLS_IENONPIC
4847 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4849 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4851 BFD_RELOC_METAG_TLS_TPOFF
4853 BFD_RELOC_METAG_TLS_DTPMOD
4855 BFD_RELOC_METAG_TLS_DTPOFF
4857 BFD_RELOC_METAG_TLS_LE
4859 BFD_RELOC_METAG_TLS_LE_HI16
4861 BFD_RELOC_METAG_TLS_LE_LO16
4863 Imagination Technologies Meta relocations.
4868 BFD_RELOC_MMIX_GETA_1
4870 BFD_RELOC_MMIX_GETA_2
4872 BFD_RELOC_MMIX_GETA_3
4874 These are relocations for the GETA instruction.
4876 BFD_RELOC_MMIX_CBRANCH
4878 BFD_RELOC_MMIX_CBRANCH_J
4880 BFD_RELOC_MMIX_CBRANCH_1
4882 BFD_RELOC_MMIX_CBRANCH_2
4884 BFD_RELOC_MMIX_CBRANCH_3
4886 These are relocations for a conditional branch instruction.
4888 BFD_RELOC_MMIX_PUSHJ
4890 BFD_RELOC_MMIX_PUSHJ_1
4892 BFD_RELOC_MMIX_PUSHJ_2
4894 BFD_RELOC_MMIX_PUSHJ_3
4896 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4898 These are relocations for the PUSHJ instruction.
4902 BFD_RELOC_MMIX_JMP_1
4904 BFD_RELOC_MMIX_JMP_2
4906 BFD_RELOC_MMIX_JMP_3
4908 These are relocations for the JMP instruction.
4910 BFD_RELOC_MMIX_ADDR19
4912 This is a relocation for a relative address as in a GETA instruction or
4915 BFD_RELOC_MMIX_ADDR27
4917 This is a relocation for a relative address as in a JMP instruction.
4919 BFD_RELOC_MMIX_REG_OR_BYTE
4921 This is a relocation for an instruction field that may be a general
4922 register or a value 0..255.
4926 This is a relocation for an instruction field that may be a general
4929 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4931 This is a relocation for two instruction fields holding a register and
4932 an offset, the equivalent of the relocation.
4934 BFD_RELOC_MMIX_LOCAL
4936 This relocation is an assertion that the expression is not allocated as
4937 a global register. It does not modify contents.
4940 BFD_RELOC_AVR_7_PCREL
4942 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4943 short offset into 7 bits.
4945 BFD_RELOC_AVR_13_PCREL
4947 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4948 short offset into 12 bits.
4952 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4953 program memory address) into 16 bits.
4955 BFD_RELOC_AVR_LO8_LDI
4957 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4958 data memory address) into 8 bit immediate value of LDI insn.
4960 BFD_RELOC_AVR_HI8_LDI
4962 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4963 of data memory address) into 8 bit immediate value of LDI insn.
4965 BFD_RELOC_AVR_HH8_LDI
4967 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4968 of program memory address) into 8 bit immediate value of LDI insn.
4970 BFD_RELOC_AVR_MS8_LDI
4972 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4973 of 32 bit value) into 8 bit immediate value of LDI insn.
4975 BFD_RELOC_AVR_LO8_LDI_NEG
4977 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4978 (usually data memory address) into 8 bit immediate value of SUBI insn.
4980 BFD_RELOC_AVR_HI8_LDI_NEG
4982 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4983 (high 8 bit of data memory address) into 8 bit immediate value of
4986 BFD_RELOC_AVR_HH8_LDI_NEG
4988 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4989 (most high 8 bit of program memory address) into 8 bit immediate value
4990 of LDI or SUBI insn.
4992 BFD_RELOC_AVR_MS8_LDI_NEG
4994 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4995 of 32 bit value) into 8 bit immediate value of LDI insn.
4997 BFD_RELOC_AVR_LO8_LDI_PM
4999 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5000 command address) into 8 bit immediate value of LDI insn.
5002 BFD_RELOC_AVR_LO8_LDI_GS
5004 This is a 16 bit reloc for the AVR that stores 8 bit value
5005 (command address) into 8 bit immediate value of LDI insn. If the address
5006 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5009 BFD_RELOC_AVR_HI8_LDI_PM
5011 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5012 of command address) into 8 bit immediate value of LDI insn.
5014 BFD_RELOC_AVR_HI8_LDI_GS
5016 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5017 of command address) into 8 bit immediate value of LDI insn. If the address
5018 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5021 BFD_RELOC_AVR_HH8_LDI_PM
5023 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5024 of command address) into 8 bit immediate value of LDI insn.
5026 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5028 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5029 (usually command address) into 8 bit immediate value of SUBI insn.
5031 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5033 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5034 (high 8 bit of 16 bit command address) into 8 bit immediate value
5037 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5039 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5040 (high 6 bit of 22 bit command address) into 8 bit immediate
5045 This is a 32 bit reloc for the AVR that stores 23 bit value
5050 This is a 16 bit reloc for the AVR that stores all needed bits
5051 for absolute addressing with ldi with overflow check to linktime
5055 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5058 BFD_RELOC_AVR_6_ADIW
5060 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5065 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5066 in .byte lo8(symbol)
5070 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5071 in .byte hi8(symbol)
5075 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5076 in .byte hlo8(symbol)
5080 BFD_RELOC_AVR_DIFF16
5082 BFD_RELOC_AVR_DIFF32
5084 AVR relocations to mark the difference of two local symbols.
5085 These are only needed to support linker relaxation and can be ignored
5086 when not relaxing. The field is set to the value of the difference
5087 assuming no relaxation. The relocation encodes the position of the
5088 second symbol so the linker can determine whether to adjust the field
5091 BFD_RELOC_AVR_LDS_STS_16
5093 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5094 lds and sts instructions supported only tiny core.
5098 This is a 6 bit reloc for the AVR that stores an I/O register
5099 number for the IN and OUT instructions
5103 This is a 5 bit reloc for the AVR that stores an I/O register
5104 number for the SBIC, SBIS, SBI and CBI instructions
5107 BFD_RELOC_RISCV_HI20
5109 BFD_RELOC_RISCV_PCREL_HI20
5111 BFD_RELOC_RISCV_PCREL_LO12_I
5113 BFD_RELOC_RISCV_PCREL_LO12_S
5115 BFD_RELOC_RISCV_LO12_I
5117 BFD_RELOC_RISCV_LO12_S
5119 BFD_RELOC_RISCV_GPREL12_I
5121 BFD_RELOC_RISCV_GPREL12_S
5123 BFD_RELOC_RISCV_TPREL_HI20
5125 BFD_RELOC_RISCV_TPREL_LO12_I
5127 BFD_RELOC_RISCV_TPREL_LO12_S
5129 BFD_RELOC_RISCV_TPREL_ADD
5131 BFD_RELOC_RISCV_CALL
5133 BFD_RELOC_RISCV_CALL_PLT
5135 BFD_RELOC_RISCV_ADD8
5137 BFD_RELOC_RISCV_ADD16
5139 BFD_RELOC_RISCV_ADD32
5141 BFD_RELOC_RISCV_ADD64
5143 BFD_RELOC_RISCV_SUB8
5145 BFD_RELOC_RISCV_SUB16
5147 BFD_RELOC_RISCV_SUB32
5149 BFD_RELOC_RISCV_SUB64
5151 BFD_RELOC_RISCV_GOT_HI20
5153 BFD_RELOC_RISCV_TLS_GOT_HI20
5155 BFD_RELOC_RISCV_TLS_GD_HI20
5159 BFD_RELOC_RISCV_TLS_DTPMOD32
5161 BFD_RELOC_RISCV_TLS_DTPREL32
5163 BFD_RELOC_RISCV_TLS_DTPMOD64
5165 BFD_RELOC_RISCV_TLS_DTPREL64
5167 BFD_RELOC_RISCV_TLS_TPREL32
5169 BFD_RELOC_RISCV_TLS_TPREL64
5171 BFD_RELOC_RISCV_ALIGN
5173 BFD_RELOC_RISCV_RVC_BRANCH
5175 BFD_RELOC_RISCV_RVC_JUMP
5177 BFD_RELOC_RISCV_RVC_LUI
5179 BFD_RELOC_RISCV_GPREL_I
5181 BFD_RELOC_RISCV_GPREL_S
5183 BFD_RELOC_RISCV_TPREL_I
5185 BFD_RELOC_RISCV_TPREL_S
5187 BFD_RELOC_RISCV_RELAX
5191 BFD_RELOC_RISCV_SUB6
5193 BFD_RELOC_RISCV_SET6
5195 BFD_RELOC_RISCV_SET8
5197 BFD_RELOC_RISCV_SET16
5199 BFD_RELOC_RISCV_SET32
5201 BFD_RELOC_RISCV_32_PCREL
5208 BFD_RELOC_RL78_NEG16
5210 BFD_RELOC_RL78_NEG24
5212 BFD_RELOC_RL78_NEG32
5214 BFD_RELOC_RL78_16_OP
5216 BFD_RELOC_RL78_24_OP
5218 BFD_RELOC_RL78_32_OP
5226 BFD_RELOC_RL78_DIR3U_PCREL
5230 BFD_RELOC_RL78_GPRELB
5232 BFD_RELOC_RL78_GPRELW
5234 BFD_RELOC_RL78_GPRELL
5238 BFD_RELOC_RL78_OP_SUBTRACT
5240 BFD_RELOC_RL78_OP_NEG
5242 BFD_RELOC_RL78_OP_AND
5244 BFD_RELOC_RL78_OP_SHRA
5248 BFD_RELOC_RL78_ABS16
5250 BFD_RELOC_RL78_ABS16_REV
5252 BFD_RELOC_RL78_ABS32
5254 BFD_RELOC_RL78_ABS32_REV
5256 BFD_RELOC_RL78_ABS16U
5258 BFD_RELOC_RL78_ABS16UW
5260 BFD_RELOC_RL78_ABS16UL
5262 BFD_RELOC_RL78_RELAX
5272 BFD_RELOC_RL78_SADDR
5274 Renesas RL78 Relocations.
5297 BFD_RELOC_RX_DIR3U_PCREL
5309 BFD_RELOC_RX_OP_SUBTRACT
5317 BFD_RELOC_RX_ABS16_REV
5321 BFD_RELOC_RX_ABS32_REV
5325 BFD_RELOC_RX_ABS16UW
5327 BFD_RELOC_RX_ABS16UL
5331 Renesas RX Relocations.
5344 32 bit PC relative PLT address.
5348 Copy symbol at runtime.
5350 BFD_RELOC_390_GLOB_DAT
5354 BFD_RELOC_390_JMP_SLOT
5358 BFD_RELOC_390_RELATIVE
5360 Adjust by program base.
5364 32 bit PC relative offset to GOT.
5370 BFD_RELOC_390_PC12DBL
5372 PC relative 12 bit shifted by 1.
5374 BFD_RELOC_390_PLT12DBL
5376 12 bit PC rel. PLT shifted by 1.
5378 BFD_RELOC_390_PC16DBL
5380 PC relative 16 bit shifted by 1.
5382 BFD_RELOC_390_PLT16DBL
5384 16 bit PC rel. PLT shifted by 1.
5386 BFD_RELOC_390_PC24DBL
5388 PC relative 24 bit shifted by 1.
5390 BFD_RELOC_390_PLT24DBL
5392 24 bit PC rel. PLT shifted by 1.
5394 BFD_RELOC_390_PC32DBL
5396 PC relative 32 bit shifted by 1.
5398 BFD_RELOC_390_PLT32DBL
5400 32 bit PC rel. PLT shifted by 1.
5402 BFD_RELOC_390_GOTPCDBL
5404 32 bit PC rel. GOT shifted by 1.
5412 64 bit PC relative PLT address.
5414 BFD_RELOC_390_GOTENT
5416 32 bit rel. offset to GOT entry.
5418 BFD_RELOC_390_GOTOFF64
5420 64 bit offset to GOT.
5422 BFD_RELOC_390_GOTPLT12
5424 12-bit offset to symbol-entry within GOT, with PLT handling.
5426 BFD_RELOC_390_GOTPLT16
5428 16-bit offset to symbol-entry within GOT, with PLT handling.
5430 BFD_RELOC_390_GOTPLT32
5432 32-bit offset to symbol-entry within GOT, with PLT handling.
5434 BFD_RELOC_390_GOTPLT64
5436 64-bit offset to symbol-entry within GOT, with PLT handling.
5438 BFD_RELOC_390_GOTPLTENT
5440 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5442 BFD_RELOC_390_PLTOFF16
5444 16-bit rel. offset from the GOT to a PLT entry.
5446 BFD_RELOC_390_PLTOFF32
5448 32-bit rel. offset from the GOT to a PLT entry.
5450 BFD_RELOC_390_PLTOFF64
5452 64-bit rel. offset from the GOT to a PLT entry.
5455 BFD_RELOC_390_TLS_LOAD
5457 BFD_RELOC_390_TLS_GDCALL
5459 BFD_RELOC_390_TLS_LDCALL
5461 BFD_RELOC_390_TLS_GD32
5463 BFD_RELOC_390_TLS_GD64
5465 BFD_RELOC_390_TLS_GOTIE12
5467 BFD_RELOC_390_TLS_GOTIE32
5469 BFD_RELOC_390_TLS_GOTIE64
5471 BFD_RELOC_390_TLS_LDM32
5473 BFD_RELOC_390_TLS_LDM64
5475 BFD_RELOC_390_TLS_IE32
5477 BFD_RELOC_390_TLS_IE64
5479 BFD_RELOC_390_TLS_IEENT
5481 BFD_RELOC_390_TLS_LE32
5483 BFD_RELOC_390_TLS_LE64
5485 BFD_RELOC_390_TLS_LDO32
5487 BFD_RELOC_390_TLS_LDO64
5489 BFD_RELOC_390_TLS_DTPMOD
5491 BFD_RELOC_390_TLS_DTPOFF
5493 BFD_RELOC_390_TLS_TPOFF
5495 s390 tls relocations.
5502 BFD_RELOC_390_GOTPLT20
5504 BFD_RELOC_390_TLS_GOTIE20
5506 Long displacement extension.
5509 BFD_RELOC_390_IRELATIVE
5511 STT_GNU_IFUNC relocation.
5514 BFD_RELOC_SCORE_GPREL15
5517 Low 16 bit for load/store
5519 BFD_RELOC_SCORE_DUMMY2
5523 This is a 24-bit reloc with the right 1 bit assumed to be 0
5525 BFD_RELOC_SCORE_BRANCH
5527 This is a 19-bit reloc with the right 1 bit assumed to be 0
5529 BFD_RELOC_SCORE_IMM30
5531 This is a 32-bit reloc for 48-bit instructions.
5533 BFD_RELOC_SCORE_IMM32
5535 This is a 32-bit reloc for 48-bit instructions.
5537 BFD_RELOC_SCORE16_JMP
5539 This is a 11-bit reloc with the right 1 bit assumed to be 0
5541 BFD_RELOC_SCORE16_BRANCH
5543 This is a 8-bit reloc with the right 1 bit assumed to be 0
5545 BFD_RELOC_SCORE_BCMP
5547 This is a 9-bit reloc with the right 1 bit assumed to be 0
5549 BFD_RELOC_SCORE_GOT15
5551 BFD_RELOC_SCORE_GOT_LO16
5553 BFD_RELOC_SCORE_CALL15
5555 BFD_RELOC_SCORE_DUMMY_HI16
5557 Undocumented Score relocs
5562 Scenix IP2K - 9-bit register number / data address
5566 Scenix IP2K - 4-bit register/data bank number
5568 BFD_RELOC_IP2K_ADDR16CJP
5570 Scenix IP2K - low 13 bits of instruction word address
5572 BFD_RELOC_IP2K_PAGE3
5574 Scenix IP2K - high 3 bits of instruction word address
5576 BFD_RELOC_IP2K_LO8DATA
5578 BFD_RELOC_IP2K_HI8DATA
5580 BFD_RELOC_IP2K_EX8DATA
5582 Scenix IP2K - ext/low/high 8 bits of data address
5584 BFD_RELOC_IP2K_LO8INSN
5586 BFD_RELOC_IP2K_HI8INSN
5588 Scenix IP2K - low/high 8 bits of instruction word address
5590 BFD_RELOC_IP2K_PC_SKIP
5592 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5596 Scenix IP2K - 16 bit word address in text section.
5598 BFD_RELOC_IP2K_FR_OFFSET
5600 Scenix IP2K - 7-bit sp or dp offset
5602 BFD_RELOC_VPE4KMATH_DATA
5604 BFD_RELOC_VPE4KMATH_INSN
5606 Scenix VPE4K coprocessor - data/insn-space addressing
5609 BFD_RELOC_VTABLE_INHERIT
5611 BFD_RELOC_VTABLE_ENTRY
5613 These two relocations are used by the linker to determine which of
5614 the entries in a C++ virtual function table are actually used. When
5615 the --gc-sections option is given, the linker will zero out the entries
5616 that are not used, so that the code for those functions need not be
5617 included in the output.
5619 VTABLE_INHERIT is a zero-space relocation used to describe to the
5620 linker the inheritance tree of a C++ virtual function table. The
5621 relocation's symbol should be the parent class' vtable, and the
5622 relocation should be located at the child vtable.
5624 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5625 virtual function table entry. The reloc's symbol should refer to the
5626 table of the class mentioned in the code. Off of that base, an offset
5627 describes the entry that is being used. For Rela hosts, this offset
5628 is stored in the reloc's addend. For Rel hosts, we are forced to put
5629 this offset in the reloc's section offset.
5632 BFD_RELOC_IA64_IMM14
5634 BFD_RELOC_IA64_IMM22
5636 BFD_RELOC_IA64_IMM64
5638 BFD_RELOC_IA64_DIR32MSB
5640 BFD_RELOC_IA64_DIR32LSB
5642 BFD_RELOC_IA64_DIR64MSB
5644 BFD_RELOC_IA64_DIR64LSB
5646 BFD_RELOC_IA64_GPREL22
5648 BFD_RELOC_IA64_GPREL64I
5650 BFD_RELOC_IA64_GPREL32MSB
5652 BFD_RELOC_IA64_GPREL32LSB
5654 BFD_RELOC_IA64_GPREL64MSB
5656 BFD_RELOC_IA64_GPREL64LSB
5658 BFD_RELOC_IA64_LTOFF22
5660 BFD_RELOC_IA64_LTOFF64I
5662 BFD_RELOC_IA64_PLTOFF22
5664 BFD_RELOC_IA64_PLTOFF64I
5666 BFD_RELOC_IA64_PLTOFF64MSB
5668 BFD_RELOC_IA64_PLTOFF64LSB
5670 BFD_RELOC_IA64_FPTR64I
5672 BFD_RELOC_IA64_FPTR32MSB
5674 BFD_RELOC_IA64_FPTR32LSB
5676 BFD_RELOC_IA64_FPTR64MSB
5678 BFD_RELOC_IA64_FPTR64LSB
5680 BFD_RELOC_IA64_PCREL21B
5682 BFD_RELOC_IA64_PCREL21BI
5684 BFD_RELOC_IA64_PCREL21M
5686 BFD_RELOC_IA64_PCREL21F
5688 BFD_RELOC_IA64_PCREL22
5690 BFD_RELOC_IA64_PCREL60B
5692 BFD_RELOC_IA64_PCREL64I
5694 BFD_RELOC_IA64_PCREL32MSB
5696 BFD_RELOC_IA64_PCREL32LSB
5698 BFD_RELOC_IA64_PCREL64MSB
5700 BFD_RELOC_IA64_PCREL64LSB
5702 BFD_RELOC_IA64_LTOFF_FPTR22
5704 BFD_RELOC_IA64_LTOFF_FPTR64I
5706 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5708 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5710 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5712 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5714 BFD_RELOC_IA64_SEGREL32MSB
5716 BFD_RELOC_IA64_SEGREL32LSB
5718 BFD_RELOC_IA64_SEGREL64MSB
5720 BFD_RELOC_IA64_SEGREL64LSB
5722 BFD_RELOC_IA64_SECREL32MSB
5724 BFD_RELOC_IA64_SECREL32LSB
5726 BFD_RELOC_IA64_SECREL64MSB
5728 BFD_RELOC_IA64_SECREL64LSB
5730 BFD_RELOC_IA64_REL32MSB
5732 BFD_RELOC_IA64_REL32LSB
5734 BFD_RELOC_IA64_REL64MSB
5736 BFD_RELOC_IA64_REL64LSB
5738 BFD_RELOC_IA64_LTV32MSB
5740 BFD_RELOC_IA64_LTV32LSB
5742 BFD_RELOC_IA64_LTV64MSB
5744 BFD_RELOC_IA64_LTV64LSB
5746 BFD_RELOC_IA64_IPLTMSB
5748 BFD_RELOC_IA64_IPLTLSB
5752 BFD_RELOC_IA64_LTOFF22X
5754 BFD_RELOC_IA64_LDXMOV
5756 BFD_RELOC_IA64_TPREL14
5758 BFD_RELOC_IA64_TPREL22
5760 BFD_RELOC_IA64_TPREL64I
5762 BFD_RELOC_IA64_TPREL64MSB
5764 BFD_RELOC_IA64_TPREL64LSB
5766 BFD_RELOC_IA64_LTOFF_TPREL22
5768 BFD_RELOC_IA64_DTPMOD64MSB
5770 BFD_RELOC_IA64_DTPMOD64LSB
5772 BFD_RELOC_IA64_LTOFF_DTPMOD22
5774 BFD_RELOC_IA64_DTPREL14
5776 BFD_RELOC_IA64_DTPREL22
5778 BFD_RELOC_IA64_DTPREL64I
5780 BFD_RELOC_IA64_DTPREL32MSB
5782 BFD_RELOC_IA64_DTPREL32LSB
5784 BFD_RELOC_IA64_DTPREL64MSB
5786 BFD_RELOC_IA64_DTPREL64LSB
5788 BFD_RELOC_IA64_LTOFF_DTPREL22
5790 Intel IA64 Relocations.
5793 BFD_RELOC_M68HC11_HI8
5795 Motorola 68HC11 reloc.
5796 This is the 8 bit high part of an absolute address.
5798 BFD_RELOC_M68HC11_LO8
5800 Motorola 68HC11 reloc.
5801 This is the 8 bit low part of an absolute address.
5803 BFD_RELOC_M68HC11_3B
5805 Motorola 68HC11 reloc.
5806 This is the 3 bit of a value.
5808 BFD_RELOC_M68HC11_RL_JUMP
5810 Motorola 68HC11 reloc.
5811 This reloc marks the beginning of a jump/call instruction.
5812 It is used for linker relaxation to correctly identify beginning
5813 of instruction and change some branches to use PC-relative
5816 BFD_RELOC_M68HC11_RL_GROUP
5818 Motorola 68HC11 reloc.
5819 This reloc marks a group of several instructions that gcc generates
5820 and for which the linker relaxation pass can modify and/or remove
5823 BFD_RELOC_M68HC11_LO16
5825 Motorola 68HC11 reloc.
5826 This is the 16-bit lower part of an address. It is used for 'call'
5827 instruction to specify the symbol address without any special
5828 transformation (due to memory bank window).
5830 BFD_RELOC_M68HC11_PAGE
5832 Motorola 68HC11 reloc.
5833 This is a 8-bit reloc that specifies the page number of an address.
5834 It is used by 'call' instruction to specify the page number of
5837 BFD_RELOC_M68HC11_24
5839 Motorola 68HC11 reloc.
5840 This is a 24-bit reloc that represents the address with a 16-bit
5841 value and a 8-bit page number. The symbol address is transformed
5842 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5844 BFD_RELOC_M68HC12_5B
5846 Motorola 68HC12 reloc.
5847 This is the 5 bits of a value.
5849 BFD_RELOC_XGATE_RL_JUMP
5851 Freescale XGATE reloc.
5852 This reloc marks the beginning of a bra/jal instruction.
5854 BFD_RELOC_XGATE_RL_GROUP
5856 Freescale XGATE reloc.
5857 This reloc marks a group of several instructions that gcc generates
5858 and for which the linker relaxation pass can modify and/or remove
5861 BFD_RELOC_XGATE_LO16
5863 Freescale XGATE reloc.
5864 This is the 16-bit lower part of an address. It is used for the '16-bit'
5867 BFD_RELOC_XGATE_GPAGE
5869 Freescale XGATE reloc.
5873 Freescale XGATE reloc.
5875 BFD_RELOC_XGATE_PCREL_9
5877 Freescale XGATE reloc.
5878 This is a 9-bit pc-relative reloc.
5880 BFD_RELOC_XGATE_PCREL_10
5882 Freescale XGATE reloc.
5883 This is a 10-bit pc-relative reloc.
5885 BFD_RELOC_XGATE_IMM8_LO
5887 Freescale XGATE reloc.
5888 This is the 16-bit lower part of an address. It is used for the '16-bit'
5891 BFD_RELOC_XGATE_IMM8_HI
5893 Freescale XGATE reloc.
5894 This is the 16-bit higher part of an address. It is used for the '16-bit'
5897 BFD_RELOC_XGATE_IMM3
5899 Freescale XGATE reloc.
5900 This is a 3-bit pc-relative reloc.
5902 BFD_RELOC_XGATE_IMM4
5904 Freescale XGATE reloc.
5905 This is a 4-bit pc-relative reloc.
5907 BFD_RELOC_XGATE_IMM5
5909 Freescale XGATE reloc.
5910 This is a 5-bit pc-relative reloc.
5912 BFD_RELOC_M68HC12_9B
5914 Motorola 68HC12 reloc.
5915 This is the 9 bits of a value.
5917 BFD_RELOC_M68HC12_16B
5919 Motorola 68HC12 reloc.
5920 This is the 16 bits of a value.
5922 BFD_RELOC_M68HC12_9_PCREL
5924 Motorola 68HC12/XGATE reloc.
5925 This is a PCREL9 branch.
5927 BFD_RELOC_M68HC12_10_PCREL
5929 Motorola 68HC12/XGATE reloc.
5930 This is a PCREL10 branch.
5932 BFD_RELOC_M68HC12_LO8XG
5934 Motorola 68HC12/XGATE reloc.
5935 This is the 8 bit low part of an absolute address and immediately precedes
5936 a matching HI8XG part.
5938 BFD_RELOC_M68HC12_HI8XG
5940 Motorola 68HC12/XGATE reloc.
5941 This is the 8 bit high part of an absolute address and immediately follows
5942 a matching LO8XG part.
5946 BFD_RELOC_16C_NUM08_C
5950 BFD_RELOC_16C_NUM16_C
5954 BFD_RELOC_16C_NUM32_C
5956 BFD_RELOC_16C_DISP04
5958 BFD_RELOC_16C_DISP04_C
5960 BFD_RELOC_16C_DISP08
5962 BFD_RELOC_16C_DISP08_C
5964 BFD_RELOC_16C_DISP16
5966 BFD_RELOC_16C_DISP16_C
5968 BFD_RELOC_16C_DISP24
5970 BFD_RELOC_16C_DISP24_C
5972 BFD_RELOC_16C_DISP24a
5974 BFD_RELOC_16C_DISP24a_C
5978 BFD_RELOC_16C_REG04_C
5980 BFD_RELOC_16C_REG04a
5982 BFD_RELOC_16C_REG04a_C
5986 BFD_RELOC_16C_REG14_C
5990 BFD_RELOC_16C_REG16_C
5994 BFD_RELOC_16C_REG20_C
5998 BFD_RELOC_16C_ABS20_C
6002 BFD_RELOC_16C_ABS24_C
6006 BFD_RELOC_16C_IMM04_C
6010 BFD_RELOC_16C_IMM16_C
6014 BFD_RELOC_16C_IMM20_C
6018 BFD_RELOC_16C_IMM24_C
6022 BFD_RELOC_16C_IMM32_C
6024 NS CR16C Relocations.
6029 BFD_RELOC_CR16_NUM16
6031 BFD_RELOC_CR16_NUM32
6033 BFD_RELOC_CR16_NUM32a
6035 BFD_RELOC_CR16_REGREL0
6037 BFD_RELOC_CR16_REGREL4
6039 BFD_RELOC_CR16_REGREL4a
6041 BFD_RELOC_CR16_REGREL14
6043 BFD_RELOC_CR16_REGREL14a
6045 BFD_RELOC_CR16_REGREL16
6047 BFD_RELOC_CR16_REGREL20
6049 BFD_RELOC_CR16_REGREL20a
6051 BFD_RELOC_CR16_ABS20
6053 BFD_RELOC_CR16_ABS24
6059 BFD_RELOC_CR16_IMM16
6061 BFD_RELOC_CR16_IMM20
6063 BFD_RELOC_CR16_IMM24
6065 BFD_RELOC_CR16_IMM32
6067 BFD_RELOC_CR16_IMM32a
6069 BFD_RELOC_CR16_DISP4
6071 BFD_RELOC_CR16_DISP8
6073 BFD_RELOC_CR16_DISP16
6075 BFD_RELOC_CR16_DISP20
6077 BFD_RELOC_CR16_DISP24
6079 BFD_RELOC_CR16_DISP24a
6081 BFD_RELOC_CR16_SWITCH8
6083 BFD_RELOC_CR16_SWITCH16
6085 BFD_RELOC_CR16_SWITCH32
6087 BFD_RELOC_CR16_GOT_REGREL20
6089 BFD_RELOC_CR16_GOTC_REGREL20
6091 BFD_RELOC_CR16_GLOB_DAT
6093 NS CR16 Relocations.
6100 BFD_RELOC_CRX_REL8_CMP
6108 BFD_RELOC_CRX_REGREL12
6110 BFD_RELOC_CRX_REGREL22
6112 BFD_RELOC_CRX_REGREL28
6114 BFD_RELOC_CRX_REGREL32
6130 BFD_RELOC_CRX_SWITCH8
6132 BFD_RELOC_CRX_SWITCH16
6134 BFD_RELOC_CRX_SWITCH32
6139 BFD_RELOC_CRIS_BDISP8
6141 BFD_RELOC_CRIS_UNSIGNED_5
6143 BFD_RELOC_CRIS_SIGNED_6
6145 BFD_RELOC_CRIS_UNSIGNED_6
6147 BFD_RELOC_CRIS_SIGNED_8
6149 BFD_RELOC_CRIS_UNSIGNED_8
6151 BFD_RELOC_CRIS_SIGNED_16
6153 BFD_RELOC_CRIS_UNSIGNED_16
6155 BFD_RELOC_CRIS_LAPCQ_OFFSET
6157 BFD_RELOC_CRIS_UNSIGNED_4
6159 These relocs are only used within the CRIS assembler. They are not
6160 (at present) written to any object files.
6164 BFD_RELOC_CRIS_GLOB_DAT
6166 BFD_RELOC_CRIS_JUMP_SLOT
6168 BFD_RELOC_CRIS_RELATIVE
6170 Relocs used in ELF shared libraries for CRIS.
6172 BFD_RELOC_CRIS_32_GOT
6174 32-bit offset to symbol-entry within GOT.
6176 BFD_RELOC_CRIS_16_GOT
6178 16-bit offset to symbol-entry within GOT.
6180 BFD_RELOC_CRIS_32_GOTPLT
6182 32-bit offset to symbol-entry within GOT, with PLT handling.
6184 BFD_RELOC_CRIS_16_GOTPLT
6186 16-bit offset to symbol-entry within GOT, with PLT handling.
6188 BFD_RELOC_CRIS_32_GOTREL
6190 32-bit offset to symbol, relative to GOT.
6192 BFD_RELOC_CRIS_32_PLT_GOTREL
6194 32-bit offset to symbol with PLT entry, relative to GOT.
6196 BFD_RELOC_CRIS_32_PLT_PCREL
6198 32-bit offset to symbol with PLT entry, relative to this relocation.
6201 BFD_RELOC_CRIS_32_GOT_GD
6203 BFD_RELOC_CRIS_16_GOT_GD
6205 BFD_RELOC_CRIS_32_GD
6209 BFD_RELOC_CRIS_32_DTPREL
6211 BFD_RELOC_CRIS_16_DTPREL
6213 BFD_RELOC_CRIS_32_GOT_TPREL
6215 BFD_RELOC_CRIS_16_GOT_TPREL
6217 BFD_RELOC_CRIS_32_TPREL
6219 BFD_RELOC_CRIS_16_TPREL
6221 BFD_RELOC_CRIS_DTPMOD
6223 BFD_RELOC_CRIS_32_IE
6225 Relocs used in TLS code for CRIS.
6230 BFD_RELOC_860_GLOB_DAT
6232 BFD_RELOC_860_JUMP_SLOT
6234 BFD_RELOC_860_RELATIVE
6244 BFD_RELOC_860_SPLIT0
6248 BFD_RELOC_860_SPLIT1
6252 BFD_RELOC_860_SPLIT2
6256 BFD_RELOC_860_LOGOT0
6258 BFD_RELOC_860_SPGOT0
6260 BFD_RELOC_860_LOGOT1
6262 BFD_RELOC_860_SPGOT1
6264 BFD_RELOC_860_LOGOTOFF0
6266 BFD_RELOC_860_SPGOTOFF0
6268 BFD_RELOC_860_LOGOTOFF1
6270 BFD_RELOC_860_SPGOTOFF1
6272 BFD_RELOC_860_LOGOTOFF2
6274 BFD_RELOC_860_LOGOTOFF3
6278 BFD_RELOC_860_HIGHADJ
6282 BFD_RELOC_860_HAGOTOFF
6290 BFD_RELOC_860_HIGOTOFF
6292 Intel i860 Relocations.
6295 BFD_RELOC_OR1K_REL_26
6297 BFD_RELOC_OR1K_GOTPC_HI16
6299 BFD_RELOC_OR1K_GOTPC_LO16
6301 BFD_RELOC_OR1K_GOT16
6303 BFD_RELOC_OR1K_PLT26
6305 BFD_RELOC_OR1K_GOTOFF_HI16
6307 BFD_RELOC_OR1K_GOTOFF_LO16
6311 BFD_RELOC_OR1K_GLOB_DAT
6313 BFD_RELOC_OR1K_JMP_SLOT
6315 BFD_RELOC_OR1K_RELATIVE
6317 BFD_RELOC_OR1K_TLS_GD_HI16
6319 BFD_RELOC_OR1K_TLS_GD_LO16
6321 BFD_RELOC_OR1K_TLS_LDM_HI16
6323 BFD_RELOC_OR1K_TLS_LDM_LO16
6325 BFD_RELOC_OR1K_TLS_LDO_HI16
6327 BFD_RELOC_OR1K_TLS_LDO_LO16
6329 BFD_RELOC_OR1K_TLS_IE_HI16
6331 BFD_RELOC_OR1K_TLS_IE_LO16
6333 BFD_RELOC_OR1K_TLS_LE_HI16
6335 BFD_RELOC_OR1K_TLS_LE_LO16
6337 BFD_RELOC_OR1K_TLS_TPOFF
6339 BFD_RELOC_OR1K_TLS_DTPOFF
6341 BFD_RELOC_OR1K_TLS_DTPMOD
6343 OpenRISC 1000 Relocations.
6346 BFD_RELOC_H8_DIR16A8
6348 BFD_RELOC_H8_DIR16R8
6350 BFD_RELOC_H8_DIR24A8
6352 BFD_RELOC_H8_DIR24R8
6354 BFD_RELOC_H8_DIR32A16
6356 BFD_RELOC_H8_DISP32A16
6361 BFD_RELOC_XSTORMY16_REL_12
6363 BFD_RELOC_XSTORMY16_12
6365 BFD_RELOC_XSTORMY16_24
6367 BFD_RELOC_XSTORMY16_FPTR16
6369 Sony Xstormy16 Relocations.
6374 Self-describing complex relocations.
6386 Infineon Relocations.
6389 BFD_RELOC_VAX_GLOB_DAT
6391 BFD_RELOC_VAX_JMP_SLOT
6393 BFD_RELOC_VAX_RELATIVE
6395 Relocations used by VAX ELF.
6400 Morpho MT - 16 bit immediate relocation.
6404 Morpho MT - Hi 16 bits of an address.
6408 Morpho MT - Low 16 bits of an address.
6410 BFD_RELOC_MT_GNU_VTINHERIT
6412 Morpho MT - Used to tell the linker which vtable entries are used.
6414 BFD_RELOC_MT_GNU_VTENTRY
6416 Morpho MT - Used to tell the linker which vtable entries are used.
6418 BFD_RELOC_MT_PCINSN8
6420 Morpho MT - 8 bit immediate relocation.
6423 BFD_RELOC_MSP430_10_PCREL
6425 BFD_RELOC_MSP430_16_PCREL
6429 BFD_RELOC_MSP430_16_PCREL_BYTE
6431 BFD_RELOC_MSP430_16_BYTE
6433 BFD_RELOC_MSP430_2X_PCREL
6435 BFD_RELOC_MSP430_RL_PCREL
6437 BFD_RELOC_MSP430_ABS8
6439 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6441 BFD_RELOC_MSP430X_PCR20_EXT_DST
6443 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6445 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6447 BFD_RELOC_MSP430X_ABS20_EXT_DST
6449 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6451 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6453 BFD_RELOC_MSP430X_ABS20_ADR_DST
6455 BFD_RELOC_MSP430X_PCR16
6457 BFD_RELOC_MSP430X_PCR20_CALL
6459 BFD_RELOC_MSP430X_ABS16
6461 BFD_RELOC_MSP430_ABS_HI16
6463 BFD_RELOC_MSP430_PREL31
6465 BFD_RELOC_MSP430_SYM_DIFF
6467 msp430 specific relocation codes
6474 BFD_RELOC_NIOS2_CALL26
6476 BFD_RELOC_NIOS2_IMM5
6478 BFD_RELOC_NIOS2_CACHE_OPX
6480 BFD_RELOC_NIOS2_IMM6
6482 BFD_RELOC_NIOS2_IMM8
6484 BFD_RELOC_NIOS2_HI16
6486 BFD_RELOC_NIOS2_LO16
6488 BFD_RELOC_NIOS2_HIADJ16
6490 BFD_RELOC_NIOS2_GPREL
6492 BFD_RELOC_NIOS2_UJMP
6494 BFD_RELOC_NIOS2_CJMP
6496 BFD_RELOC_NIOS2_CALLR
6498 BFD_RELOC_NIOS2_ALIGN
6500 BFD_RELOC_NIOS2_GOT16
6502 BFD_RELOC_NIOS2_CALL16
6504 BFD_RELOC_NIOS2_GOTOFF_LO
6506 BFD_RELOC_NIOS2_GOTOFF_HA
6508 BFD_RELOC_NIOS2_PCREL_LO
6510 BFD_RELOC_NIOS2_PCREL_HA
6512 BFD_RELOC_NIOS2_TLS_GD16
6514 BFD_RELOC_NIOS2_TLS_LDM16
6516 BFD_RELOC_NIOS2_TLS_LDO16
6518 BFD_RELOC_NIOS2_TLS_IE16
6520 BFD_RELOC_NIOS2_TLS_LE16
6522 BFD_RELOC_NIOS2_TLS_DTPMOD
6524 BFD_RELOC_NIOS2_TLS_DTPREL
6526 BFD_RELOC_NIOS2_TLS_TPREL
6528 BFD_RELOC_NIOS2_COPY
6530 BFD_RELOC_NIOS2_GLOB_DAT
6532 BFD_RELOC_NIOS2_JUMP_SLOT
6534 BFD_RELOC_NIOS2_RELATIVE
6536 BFD_RELOC_NIOS2_GOTOFF
6538 BFD_RELOC_NIOS2_CALL26_NOAT
6540 BFD_RELOC_NIOS2_GOT_LO
6542 BFD_RELOC_NIOS2_GOT_HA
6544 BFD_RELOC_NIOS2_CALL_LO
6546 BFD_RELOC_NIOS2_CALL_HA
6548 BFD_RELOC_NIOS2_R2_S12
6550 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6552 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6554 BFD_RELOC_NIOS2_R2_T1I7_2
6556 BFD_RELOC_NIOS2_R2_T2I4
6558 BFD_RELOC_NIOS2_R2_T2I4_1
6560 BFD_RELOC_NIOS2_R2_T2I4_2
6562 BFD_RELOC_NIOS2_R2_X1I7_2
6564 BFD_RELOC_NIOS2_R2_X2L5
6566 BFD_RELOC_NIOS2_R2_F1I5_2
6568 BFD_RELOC_NIOS2_R2_L5I4X1
6570 BFD_RELOC_NIOS2_R2_T1X1I6
6572 BFD_RELOC_NIOS2_R2_T1X1I6_2
6574 Relocations used by the Altera Nios II core.
6579 PRU LDI 16-bit unsigned data-memory relocation.
6581 BFD_RELOC_PRU_U16_PMEMIMM
6583 PRU LDI 16-bit unsigned instruction-memory relocation.
6587 PRU relocation for two consecutive LDI load instructions that load a
6588 32 bit value into a register. If the higher bits are all zero, then
6589 the second instruction may be relaxed.
6591 BFD_RELOC_PRU_S10_PCREL
6593 PRU QBBx 10-bit signed PC-relative relocation.
6595 BFD_RELOC_PRU_U8_PCREL
6597 PRU 8-bit unsigned relocation used for the LOOP instruction.
6599 BFD_RELOC_PRU_32_PMEM
6601 BFD_RELOC_PRU_16_PMEM
6603 PRU Program Memory relocations. Used to convert from byte addressing to
6604 32-bit word addressing.
6606 BFD_RELOC_PRU_GNU_DIFF8
6608 BFD_RELOC_PRU_GNU_DIFF16
6610 BFD_RELOC_PRU_GNU_DIFF32
6612 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6614 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6616 PRU relocations to mark the difference of two local symbols.
6617 These are only needed to support linker relaxation and can be ignored
6618 when not relaxing. The field is set to the value of the difference
6619 assuming no relaxation. The relocation encodes the position of the
6620 second symbol so the linker can determine whether to adjust the field
6621 value. The PMEM variants encode the word difference, instead of byte
6622 difference between symbols.
6625 BFD_RELOC_IQ2000_OFFSET_16
6627 BFD_RELOC_IQ2000_OFFSET_21
6629 BFD_RELOC_IQ2000_UHI16
6634 BFD_RELOC_XTENSA_RTLD
6636 Special Xtensa relocation used only by PLT entries in ELF shared
6637 objects to indicate that the runtime linker should set the value
6638 to one of its own internal functions or data structures.
6640 BFD_RELOC_XTENSA_GLOB_DAT
6642 BFD_RELOC_XTENSA_JMP_SLOT
6644 BFD_RELOC_XTENSA_RELATIVE
6646 Xtensa relocations for ELF shared objects.
6648 BFD_RELOC_XTENSA_PLT
6650 Xtensa relocation used in ELF object files for symbols that may require
6651 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6653 BFD_RELOC_XTENSA_DIFF8
6655 BFD_RELOC_XTENSA_DIFF16
6657 BFD_RELOC_XTENSA_DIFF32
6659 Xtensa relocations to mark the difference of two local symbols.
6660 These are only needed to support linker relaxation and can be ignored
6661 when not relaxing. The field is set to the value of the difference
6662 assuming no relaxation. The relocation encodes the position of the
6663 first symbol so the linker can determine whether to adjust the field
6666 BFD_RELOC_XTENSA_SLOT0_OP
6668 BFD_RELOC_XTENSA_SLOT1_OP
6670 BFD_RELOC_XTENSA_SLOT2_OP
6672 BFD_RELOC_XTENSA_SLOT3_OP
6674 BFD_RELOC_XTENSA_SLOT4_OP
6676 BFD_RELOC_XTENSA_SLOT5_OP
6678 BFD_RELOC_XTENSA_SLOT6_OP
6680 BFD_RELOC_XTENSA_SLOT7_OP
6682 BFD_RELOC_XTENSA_SLOT8_OP
6684 BFD_RELOC_XTENSA_SLOT9_OP
6686 BFD_RELOC_XTENSA_SLOT10_OP
6688 BFD_RELOC_XTENSA_SLOT11_OP
6690 BFD_RELOC_XTENSA_SLOT12_OP
6692 BFD_RELOC_XTENSA_SLOT13_OP
6694 BFD_RELOC_XTENSA_SLOT14_OP
6696 Generic Xtensa relocations for instruction operands. Only the slot
6697 number is encoded in the relocation. The relocation applies to the
6698 last PC-relative immediate operand, or if there are no PC-relative
6699 immediates, to the last immediate operand.
6701 BFD_RELOC_XTENSA_SLOT0_ALT
6703 BFD_RELOC_XTENSA_SLOT1_ALT
6705 BFD_RELOC_XTENSA_SLOT2_ALT
6707 BFD_RELOC_XTENSA_SLOT3_ALT
6709 BFD_RELOC_XTENSA_SLOT4_ALT
6711 BFD_RELOC_XTENSA_SLOT5_ALT
6713 BFD_RELOC_XTENSA_SLOT6_ALT
6715 BFD_RELOC_XTENSA_SLOT7_ALT
6717 BFD_RELOC_XTENSA_SLOT8_ALT
6719 BFD_RELOC_XTENSA_SLOT9_ALT
6721 BFD_RELOC_XTENSA_SLOT10_ALT
6723 BFD_RELOC_XTENSA_SLOT11_ALT
6725 BFD_RELOC_XTENSA_SLOT12_ALT
6727 BFD_RELOC_XTENSA_SLOT13_ALT
6729 BFD_RELOC_XTENSA_SLOT14_ALT
6731 Alternate Xtensa relocations. Only the slot is encoded in the
6732 relocation. The meaning of these relocations is opcode-specific.
6734 BFD_RELOC_XTENSA_OP0
6736 BFD_RELOC_XTENSA_OP1
6738 BFD_RELOC_XTENSA_OP2
6740 Xtensa relocations for backward compatibility. These have all been
6741 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6743 BFD_RELOC_XTENSA_ASM_EXPAND
6745 Xtensa relocation to mark that the assembler expanded the
6746 instructions from an original target. The expansion size is
6747 encoded in the reloc size.
6749 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6751 Xtensa relocation to mark that the linker should simplify
6752 assembler-expanded instructions. This is commonly used
6753 internally by the linker after analysis of a
6754 BFD_RELOC_XTENSA_ASM_EXPAND.
6756 BFD_RELOC_XTENSA_TLSDESC_FN
6758 BFD_RELOC_XTENSA_TLSDESC_ARG
6760 BFD_RELOC_XTENSA_TLS_DTPOFF
6762 BFD_RELOC_XTENSA_TLS_TPOFF
6764 BFD_RELOC_XTENSA_TLS_FUNC
6766 BFD_RELOC_XTENSA_TLS_ARG
6768 BFD_RELOC_XTENSA_TLS_CALL
6770 Xtensa TLS relocations.
6775 8 bit signed offset in (ix+d) or (iy+d).
6793 BFD_RELOC_LM32_BRANCH
6795 BFD_RELOC_LM32_16_GOT
6797 BFD_RELOC_LM32_GOTOFF_HI16
6799 BFD_RELOC_LM32_GOTOFF_LO16
6803 BFD_RELOC_LM32_GLOB_DAT
6805 BFD_RELOC_LM32_JMP_SLOT
6807 BFD_RELOC_LM32_RELATIVE
6809 Lattice Mico32 relocations.
6812 BFD_RELOC_MACH_O_SECTDIFF
6814 Difference between two section addreses. Must be followed by a
6815 BFD_RELOC_MACH_O_PAIR.
6817 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6819 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6821 BFD_RELOC_MACH_O_PAIR
6823 Pair of relocation. Contains the first symbol.
6825 BFD_RELOC_MACH_O_SUBTRACTOR32
6827 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6829 BFD_RELOC_MACH_O_SUBTRACTOR64
6831 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6834 BFD_RELOC_MACH_O_X86_64_BRANCH32
6836 BFD_RELOC_MACH_O_X86_64_BRANCH8
6838 PCREL relocations. They are marked as branch to create PLT entry if
6841 BFD_RELOC_MACH_O_X86_64_GOT
6843 Used when referencing a GOT entry.
6845 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6847 Used when loading a GOT entry with movq. It is specially marked so that
6848 the linker could optimize the movq to a leaq if possible.
6850 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6852 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6854 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6856 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6858 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6860 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6864 BFD_RELOC_MACH_O_ARM64_ADDEND
6866 Addend for PAGE or PAGEOFF.
6868 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6870 Relative offset to page of GOT slot.
6872 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6874 Relative offset within page of GOT slot.
6876 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6878 Address of a GOT entry.
6881 BFD_RELOC_MICROBLAZE_32_LO
6883 This is a 32 bit reloc for the microblaze that stores the
6884 low 16 bits of a value
6886 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6888 This is a 32 bit pc-relative reloc for the microblaze that
6889 stores the low 16 bits of a value
6891 BFD_RELOC_MICROBLAZE_32_ROSDA
6893 This is a 32 bit reloc for the microblaze that stores a
6894 value relative to the read-only small data area anchor
6896 BFD_RELOC_MICROBLAZE_32_RWSDA
6898 This is a 32 bit reloc for the microblaze that stores a
6899 value relative to the read-write small data area anchor
6901 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6903 This is a 32 bit reloc for the microblaze to handle
6904 expressions of the form "Symbol Op Symbol"
6906 BFD_RELOC_MICROBLAZE_64_NONE
6908 This is a 64 bit reloc that stores the 32 bit pc relative
6909 value in two words (with an imm instruction). No relocation is
6910 done here - only used for relaxing
6912 BFD_RELOC_MICROBLAZE_64_GOTPC
6914 This is a 64 bit reloc that stores the 32 bit pc relative
6915 value in two words (with an imm instruction). The relocation is
6916 PC-relative GOT offset
6918 BFD_RELOC_MICROBLAZE_64_GOT
6920 This is a 64 bit reloc that stores the 32 bit pc relative
6921 value in two words (with an imm instruction). The relocation is
6924 BFD_RELOC_MICROBLAZE_64_PLT
6926 This is a 64 bit reloc that stores the 32 bit pc relative
6927 value in two words (with an imm instruction). The relocation is
6928 PC-relative offset into PLT
6930 BFD_RELOC_MICROBLAZE_64_GOTOFF
6932 This is a 64 bit reloc that stores the 32 bit GOT relative
6933 value in two words (with an imm instruction). The relocation is
6934 relative offset from _GLOBAL_OFFSET_TABLE_
6936 BFD_RELOC_MICROBLAZE_32_GOTOFF
6938 This is a 32 bit reloc that stores the 32 bit GOT relative
6939 value in a word. The relocation is relative offset from
6940 _GLOBAL_OFFSET_TABLE_
6942 BFD_RELOC_MICROBLAZE_COPY
6944 This is used to tell the dynamic linker to copy the value out of
6945 the dynamic object into the runtime process image.
6947 BFD_RELOC_MICROBLAZE_64_TLS
6951 BFD_RELOC_MICROBLAZE_64_TLSGD
6953 This is a 64 bit reloc that stores the 32 bit GOT relative value
6954 of the GOT TLS GD info entry in two words (with an imm instruction). The
6955 relocation is GOT offset.
6957 BFD_RELOC_MICROBLAZE_64_TLSLD
6959 This is a 64 bit reloc that stores the 32 bit GOT relative value
6960 of the GOT TLS LD info entry in two words (with an imm instruction). The
6961 relocation is GOT offset.
6963 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6965 This is a 32 bit reloc that stores the Module ID to GOT(n).
6967 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6969 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6971 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6973 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6976 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6978 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6979 to two words (uses imm instruction).
6981 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6983 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6984 to two words (uses imm instruction).
6987 BFD_RELOC_AARCH64_RELOC_START
6989 AArch64 pseudo relocation code to mark the start of the AArch64
6990 relocation enumerators. N.B. the order of the enumerators is
6991 important as several tables in the AArch64 bfd backend are indexed
6992 by these enumerators; make sure they are all synced.
6994 BFD_RELOC_AARCH64_NULL
6996 Deprecated AArch64 null relocation code.
6998 BFD_RELOC_AARCH64_NONE
7000 AArch64 null relocation code.
7002 BFD_RELOC_AARCH64_64
7004 BFD_RELOC_AARCH64_32
7006 BFD_RELOC_AARCH64_16
7008 Basic absolute relocations of N bits. These are equivalent to
7009 BFD_RELOC_N and they were added to assist the indexing of the howto
7012 BFD_RELOC_AARCH64_64_PCREL
7014 BFD_RELOC_AARCH64_32_PCREL
7016 BFD_RELOC_AARCH64_16_PCREL
7018 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
7019 and they were added to assist the indexing of the howto table.
7021 BFD_RELOC_AARCH64_MOVW_G0
7023 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
7024 of an unsigned address/value.
7026 BFD_RELOC_AARCH64_MOVW_G0_NC
7028 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7029 an address/value. No overflow checking.
7031 BFD_RELOC_AARCH64_MOVW_G1
7033 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7034 of an unsigned address/value.
7036 BFD_RELOC_AARCH64_MOVW_G1_NC
7038 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7039 of an address/value. No overflow checking.
7041 BFD_RELOC_AARCH64_MOVW_G2
7043 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7044 of an unsigned address/value.
7046 BFD_RELOC_AARCH64_MOVW_G2_NC
7048 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7049 of an address/value. No overflow checking.
7051 BFD_RELOC_AARCH64_MOVW_G3
7053 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7054 of a signed or unsigned address/value.
7056 BFD_RELOC_AARCH64_MOVW_G0_S
7058 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7059 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7062 BFD_RELOC_AARCH64_MOVW_G1_S
7064 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7065 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7068 BFD_RELOC_AARCH64_MOVW_G2_S
7070 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7071 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7074 BFD_RELOC_AARCH64_MOVW_PREL_G0
7076 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7077 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7080 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7082 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7083 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7086 BFD_RELOC_AARCH64_MOVW_PREL_G1
7088 AArch64 MOVK instruction with most significant bits 16 to 31
7091 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7093 AArch64 MOVK instruction with most significant bits 16 to 31
7096 BFD_RELOC_AARCH64_MOVW_PREL_G2
7098 AArch64 MOVK instruction with most significant bits 32 to 47
7101 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7103 AArch64 MOVK instruction with most significant bits 32 to 47
7106 BFD_RELOC_AARCH64_MOVW_PREL_G3
7108 AArch64 MOVK instruction with most significant bits 47 to 63
7111 BFD_RELOC_AARCH64_LD_LO19_PCREL
7113 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7114 offset. The lowest two bits must be zero and are not stored in the
7115 instruction, giving a 21 bit signed byte offset.
7117 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7119 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7121 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7123 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7124 offset, giving a 4KB aligned page base address.
7126 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7128 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7129 offset, giving a 4KB aligned page base address, but with no overflow
7132 BFD_RELOC_AARCH64_ADD_LO12
7134 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7135 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7137 BFD_RELOC_AARCH64_LDST8_LO12
7139 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7140 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7142 BFD_RELOC_AARCH64_TSTBR14
7144 AArch64 14 bit pc-relative test bit and branch.
7145 The lowest two bits must be zero and are not stored in the instruction,
7146 giving a 16 bit signed byte offset.
7148 BFD_RELOC_AARCH64_BRANCH19
7150 AArch64 19 bit pc-relative conditional branch and compare & branch.
7151 The lowest two bits must be zero and are not stored in the instruction,
7152 giving a 21 bit signed byte offset.
7154 BFD_RELOC_AARCH64_JUMP26
7156 AArch64 26 bit pc-relative unconditional branch.
7157 The lowest two bits must be zero and are not stored in the instruction,
7158 giving a 28 bit signed byte offset.
7160 BFD_RELOC_AARCH64_CALL26
7162 AArch64 26 bit pc-relative unconditional branch and link.
7163 The lowest two bits must be zero and are not stored in the instruction,
7164 giving a 28 bit signed byte offset.
7166 BFD_RELOC_AARCH64_LDST16_LO12
7168 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7169 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7171 BFD_RELOC_AARCH64_LDST32_LO12
7173 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7174 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7176 BFD_RELOC_AARCH64_LDST64_LO12
7178 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7179 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7181 BFD_RELOC_AARCH64_LDST128_LO12
7183 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7184 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7186 BFD_RELOC_AARCH64_GOT_LD_PREL19
7188 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7189 offset of the global offset table entry for a symbol. The lowest two
7190 bits must be zero and are not stored in the instruction, giving a 21
7191 bit signed byte offset. This relocation type requires signed overflow
7194 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7196 Get to the page base of the global offset table entry for a symbol as
7197 part of an ADRP instruction using a 21 bit PC relative value.Used in
7198 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7200 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7202 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7203 the GOT entry for this symbol. Used in conjunction with
7204 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7206 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7208 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7209 the GOT entry for this symbol. Used in conjunction with
7210 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7212 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7214 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7215 for this symbol. Valid in LP64 ABI only.
7217 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7219 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7220 for this symbol. Valid in LP64 ABI only.
7222 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7224 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7225 the GOT entry for this symbol. Valid in LP64 ABI only.
7227 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7229 Scaled 14 bit byte offset to the page base of the global offset table.
7231 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7233 Scaled 15 bit byte offset to the page base of the global offset table.
7235 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7237 Get to the page base of the global offset table entry for a symbols
7238 tls_index structure as part of an adrp instruction using a 21 bit PC
7239 relative value. Used in conjunction with
7240 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7242 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7244 AArch64 TLS General Dynamic
7246 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7248 Unsigned 12 bit byte offset to global offset table entry for a symbols
7249 tls_index structure. Used in conjunction with
7250 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7252 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7254 AArch64 TLS General Dynamic relocation.
7256 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7258 AArch64 TLS General Dynamic relocation.
7260 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7262 AArch64 TLS INITIAL EXEC relocation.
7264 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7266 AArch64 TLS INITIAL EXEC relocation.
7268 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7270 AArch64 TLS INITIAL EXEC relocation.
7272 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7274 AArch64 TLS INITIAL EXEC relocation.
7276 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7278 AArch64 TLS INITIAL EXEC relocation.
7280 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7282 AArch64 TLS INITIAL EXEC relocation.
7284 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7286 bit[23:12] of byte offset to module TLS base address.
7288 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7290 Unsigned 12 bit byte offset to module TLS base address.
7292 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7294 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7296 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7298 Unsigned 12 bit byte offset to global offset table entry for a symbols
7299 tls_index structure. Used in conjunction with
7300 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7302 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7304 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7307 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7309 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7311 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7313 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7316 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7318 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7320 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7322 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7325 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7327 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7329 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7331 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7334 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7336 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7338 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7340 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7343 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7345 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7347 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7349 bit[15:0] of byte offset to module TLS base address.
7351 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7353 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7355 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7357 bit[31:16] of byte offset to module TLS base address.
7359 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7361 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7363 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7365 bit[47:32] of byte offset to module TLS base address.
7367 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7369 AArch64 TLS LOCAL EXEC relocation.
7371 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7373 AArch64 TLS LOCAL EXEC relocation.
7375 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7377 AArch64 TLS LOCAL EXEC relocation.
7379 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7381 AArch64 TLS LOCAL EXEC relocation.
7383 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7385 AArch64 TLS LOCAL EXEC relocation.
7387 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7389 AArch64 TLS LOCAL EXEC relocation.
7391 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7393 AArch64 TLS LOCAL EXEC relocation.
7395 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7397 AArch64 TLS LOCAL EXEC relocation.
7399 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7401 AArch64 TLS DESC relocation.
7403 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7405 AArch64 TLS DESC relocation.
7407 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7409 AArch64 TLS DESC relocation.
7411 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7413 AArch64 TLS DESC relocation.
7415 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7417 AArch64 TLS DESC relocation.
7419 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7421 AArch64 TLS DESC relocation.
7423 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7425 AArch64 TLS DESC relocation.
7427 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7429 AArch64 TLS DESC relocation.
7431 BFD_RELOC_AARCH64_TLSDESC_LDR
7433 AArch64 TLS DESC relocation.
7435 BFD_RELOC_AARCH64_TLSDESC_ADD
7437 AArch64 TLS DESC relocation.
7439 BFD_RELOC_AARCH64_TLSDESC_CALL
7441 AArch64 TLS DESC relocation.
7443 BFD_RELOC_AARCH64_COPY
7445 AArch64 TLS relocation.
7447 BFD_RELOC_AARCH64_GLOB_DAT
7449 AArch64 TLS relocation.
7451 BFD_RELOC_AARCH64_JUMP_SLOT
7453 AArch64 TLS relocation.
7455 BFD_RELOC_AARCH64_RELATIVE
7457 AArch64 TLS relocation.
7459 BFD_RELOC_AARCH64_TLS_DTPMOD
7461 AArch64 TLS relocation.
7463 BFD_RELOC_AARCH64_TLS_DTPREL
7465 AArch64 TLS relocation.
7467 BFD_RELOC_AARCH64_TLS_TPREL
7469 AArch64 TLS relocation.
7471 BFD_RELOC_AARCH64_TLSDESC
7473 AArch64 TLS relocation.
7475 BFD_RELOC_AARCH64_IRELATIVE
7477 AArch64 support for STT_GNU_IFUNC.
7479 BFD_RELOC_AARCH64_RELOC_END
7481 AArch64 pseudo relocation code to mark the end of the AArch64
7482 relocation enumerators that have direct mapping to ELF reloc codes.
7483 There are a few more enumerators after this one; those are mainly
7484 used by the AArch64 assembler for the internal fixup or to select
7485 one of the above enumerators.
7487 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7489 AArch64 pseudo relocation code to be used internally by the AArch64
7490 assembler and not (currently) written to any object files.
7492 BFD_RELOC_AARCH64_LDST_LO12
7494 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7495 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7497 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7499 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7500 used internally by the AArch64 assembler and not (currently) written to
7503 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7505 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7507 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7509 AArch64 pseudo relocation code to be used internally by the AArch64
7510 assembler and not (currently) written to any object files.
7512 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7514 AArch64 pseudo relocation code to be used internally by the AArch64
7515 assembler and not (currently) written to any object files.
7517 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7519 AArch64 pseudo relocation code to be used internally by the AArch64
7520 assembler and not (currently) written to any object files.
7522 BFD_RELOC_TILEPRO_COPY
7524 BFD_RELOC_TILEPRO_GLOB_DAT
7526 BFD_RELOC_TILEPRO_JMP_SLOT
7528 BFD_RELOC_TILEPRO_RELATIVE
7530 BFD_RELOC_TILEPRO_BROFF_X1
7532 BFD_RELOC_TILEPRO_JOFFLONG_X1
7534 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7536 BFD_RELOC_TILEPRO_IMM8_X0
7538 BFD_RELOC_TILEPRO_IMM8_Y0
7540 BFD_RELOC_TILEPRO_IMM8_X1
7542 BFD_RELOC_TILEPRO_IMM8_Y1
7544 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7546 BFD_RELOC_TILEPRO_MT_IMM15_X1
7548 BFD_RELOC_TILEPRO_MF_IMM15_X1
7550 BFD_RELOC_TILEPRO_IMM16_X0
7552 BFD_RELOC_TILEPRO_IMM16_X1
7554 BFD_RELOC_TILEPRO_IMM16_X0_LO
7556 BFD_RELOC_TILEPRO_IMM16_X1_LO
7558 BFD_RELOC_TILEPRO_IMM16_X0_HI
7560 BFD_RELOC_TILEPRO_IMM16_X1_HI
7562 BFD_RELOC_TILEPRO_IMM16_X0_HA
7564 BFD_RELOC_TILEPRO_IMM16_X1_HA
7566 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7568 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7570 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7572 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7574 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7576 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7578 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7580 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7582 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7584 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7586 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7588 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7590 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7592 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7594 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7596 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7598 BFD_RELOC_TILEPRO_MMSTART_X0
7600 BFD_RELOC_TILEPRO_MMEND_X0
7602 BFD_RELOC_TILEPRO_MMSTART_X1
7604 BFD_RELOC_TILEPRO_MMEND_X1
7606 BFD_RELOC_TILEPRO_SHAMT_X0
7608 BFD_RELOC_TILEPRO_SHAMT_X1
7610 BFD_RELOC_TILEPRO_SHAMT_Y0
7612 BFD_RELOC_TILEPRO_SHAMT_Y1
7614 BFD_RELOC_TILEPRO_TLS_GD_CALL
7616 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7618 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7620 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7622 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7624 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7626 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7628 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7630 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7632 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7634 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7636 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7638 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7640 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7642 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7644 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7646 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7648 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7650 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7652 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7654 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7656 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7658 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7660 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7662 BFD_RELOC_TILEPRO_TLS_TPOFF32
7664 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7666 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7668 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7670 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7672 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7674 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7676 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7678 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7680 Tilera TILEPro Relocations.
7682 BFD_RELOC_TILEGX_HW0
7684 BFD_RELOC_TILEGX_HW1
7686 BFD_RELOC_TILEGX_HW2
7688 BFD_RELOC_TILEGX_HW3
7690 BFD_RELOC_TILEGX_HW0_LAST
7692 BFD_RELOC_TILEGX_HW1_LAST
7694 BFD_RELOC_TILEGX_HW2_LAST
7696 BFD_RELOC_TILEGX_COPY
7698 BFD_RELOC_TILEGX_GLOB_DAT
7700 BFD_RELOC_TILEGX_JMP_SLOT
7702 BFD_RELOC_TILEGX_RELATIVE
7704 BFD_RELOC_TILEGX_BROFF_X1
7706 BFD_RELOC_TILEGX_JUMPOFF_X1
7708 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7710 BFD_RELOC_TILEGX_IMM8_X0
7712 BFD_RELOC_TILEGX_IMM8_Y0
7714 BFD_RELOC_TILEGX_IMM8_X1
7716 BFD_RELOC_TILEGX_IMM8_Y1
7718 BFD_RELOC_TILEGX_DEST_IMM8_X1
7720 BFD_RELOC_TILEGX_MT_IMM14_X1
7722 BFD_RELOC_TILEGX_MF_IMM14_X1
7724 BFD_RELOC_TILEGX_MMSTART_X0
7726 BFD_RELOC_TILEGX_MMEND_X0
7728 BFD_RELOC_TILEGX_SHAMT_X0
7730 BFD_RELOC_TILEGX_SHAMT_X1
7732 BFD_RELOC_TILEGX_SHAMT_Y0
7734 BFD_RELOC_TILEGX_SHAMT_Y1
7736 BFD_RELOC_TILEGX_IMM16_X0_HW0
7738 BFD_RELOC_TILEGX_IMM16_X1_HW0
7740 BFD_RELOC_TILEGX_IMM16_X0_HW1
7742 BFD_RELOC_TILEGX_IMM16_X1_HW1
7744 BFD_RELOC_TILEGX_IMM16_X0_HW2
7746 BFD_RELOC_TILEGX_IMM16_X1_HW2
7748 BFD_RELOC_TILEGX_IMM16_X0_HW3
7750 BFD_RELOC_TILEGX_IMM16_X1_HW3
7752 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7754 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7756 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7758 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7760 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7762 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7764 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7766 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7768 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7770 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7772 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7774 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7776 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7778 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7780 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7782 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7784 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7786 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7788 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7790 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7792 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7794 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7796 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7798 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7800 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7802 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7804 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7806 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7808 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7810 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7812 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7814 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7816 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7818 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7820 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7822 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7824 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7826 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7828 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7830 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7832 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7834 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7836 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7838 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7840 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7842 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7844 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7846 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7848 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7850 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7852 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7854 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7856 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7858 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7860 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7862 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7864 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7866 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7868 BFD_RELOC_TILEGX_TLS_DTPMOD64
7870 BFD_RELOC_TILEGX_TLS_DTPOFF64
7872 BFD_RELOC_TILEGX_TLS_TPOFF64
7874 BFD_RELOC_TILEGX_TLS_DTPMOD32
7876 BFD_RELOC_TILEGX_TLS_DTPOFF32
7878 BFD_RELOC_TILEGX_TLS_TPOFF32
7880 BFD_RELOC_TILEGX_TLS_GD_CALL
7882 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7884 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7886 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7888 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7890 BFD_RELOC_TILEGX_TLS_IE_LOAD
7892 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7894 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7896 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7898 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7900 Tilera TILE-Gx Relocations.
7903 BFD_RELOC_EPIPHANY_SIMM8
7905 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7907 BFD_RELOC_EPIPHANY_SIMM24
7909 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7911 BFD_RELOC_EPIPHANY_HIGH
7913 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7915 BFD_RELOC_EPIPHANY_LOW
7917 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7919 BFD_RELOC_EPIPHANY_SIMM11
7921 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7923 BFD_RELOC_EPIPHANY_IMM11
7925 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7927 BFD_RELOC_EPIPHANY_IMM8
7929 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7932 BFD_RELOC_VISIUM_HI16
7934 BFD_RELOC_VISIUM_LO16
7936 BFD_RELOC_VISIUM_IM16
7938 BFD_RELOC_VISIUM_REL16
7940 BFD_RELOC_VISIUM_HI16_PCREL
7942 BFD_RELOC_VISIUM_LO16_PCREL
7944 BFD_RELOC_VISIUM_IM16_PCREL
7949 BFD_RELOC_WASM32_LEB128
7951 BFD_RELOC_WASM32_LEB128_GOT
7953 BFD_RELOC_WASM32_LEB128_GOT_CODE
7955 BFD_RELOC_WASM32_LEB128_PLT
7957 BFD_RELOC_WASM32_PLT_INDEX
7959 BFD_RELOC_WASM32_ABS32_CODE
7961 BFD_RELOC_WASM32_COPY
7963 BFD_RELOC_WASM32_CODE_POINTER
7965 BFD_RELOC_WASM32_INDEX
7967 BFD_RELOC_WASM32_PLT_SIG
7969 WebAssembly relocations.
7975 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7980 bfd_reloc_type_lookup
7981 bfd_reloc_name_lookup
7984 reloc_howto_type *bfd_reloc_type_lookup
7985 (bfd *abfd, bfd_reloc_code_real_type code);
7986 reloc_howto_type *bfd_reloc_name_lookup
7987 (bfd *abfd, const char *reloc_name);
7990 Return a pointer to a howto structure which, when
7991 invoked, will perform the relocation @var{code} on data from the
7997 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7999 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
8003 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
8005 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
8008 static reloc_howto_type bfd_howto_32 =
8009 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
8013 bfd_default_reloc_type_lookup
8016 reloc_howto_type *bfd_default_reloc_type_lookup
8017 (bfd *abfd, bfd_reloc_code_real_type code);
8020 Provides a default relocation lookup routine for any architecture.
8025 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8029 case BFD_RELOC_CTOR:
8030 /* The type of reloc used in a ctor, which will be as wide as the
8031 address - so either a 64, 32, or 16 bitter. */
8032 switch (bfd_arch_bits_per_address (abfd))
8038 return &bfd_howto_32;
8054 bfd_get_reloc_code_name
8057 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8060 Provides a printable name for the supplied relocation code.
8061 Useful mainly for printing error messages.
8065 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
8067 if (code > BFD_RELOC_UNUSED)
8069 return bfd_reloc_code_real_names[code];
8074 bfd_generic_relax_section
8077 bfd_boolean bfd_generic_relax_section
8080 struct bfd_link_info *,
8084 Provides default handling for relaxing for back ends which
8089 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
8090 asection *section ATTRIBUTE_UNUSED,
8091 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
8094 if (bfd_link_relocatable (link_info))
8095 (*link_info->callbacks->einfo)
8096 (_("%P%F: --relax and -r may not be used together\n"));
8104 bfd_generic_gc_sections
8107 bfd_boolean bfd_generic_gc_sections
8108 (bfd *, struct bfd_link_info *);
8111 Provides default handling for relaxing for back ends which
8112 don't do section gc -- i.e., does nothing.
8116 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
8117 struct bfd_link_info *info ATTRIBUTE_UNUSED)
8124 bfd_generic_lookup_section_flags
8127 bfd_boolean bfd_generic_lookup_section_flags
8128 (struct bfd_link_info *, struct flag_info *, asection *);
8131 Provides default handling for section flags lookup
8132 -- i.e., does nothing.
8133 Returns FALSE if the section should be omitted, otherwise TRUE.
8137 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
8138 struct flag_info *flaginfo,
8139 asection *section ATTRIBUTE_UNUSED)
8141 if (flaginfo != NULL)
8143 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported.\n"));
8151 bfd_generic_merge_sections
8154 bfd_boolean bfd_generic_merge_sections
8155 (bfd *, struct bfd_link_info *);
8158 Provides default handling for SEC_MERGE section merging for back ends
8159 which don't have SEC_MERGE support -- i.e., does nothing.
8163 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
8164 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
8171 bfd_generic_get_relocated_section_contents
8174 bfd_byte *bfd_generic_get_relocated_section_contents
8176 struct bfd_link_info *link_info,
8177 struct bfd_link_order *link_order,
8179 bfd_boolean relocatable,
8183 Provides default handling of relocation effort for back ends
8184 which can't be bothered to do it efficiently.
8189 bfd_generic_get_relocated_section_contents (bfd *abfd,
8190 struct bfd_link_info *link_info,
8191 struct bfd_link_order *link_order,
8193 bfd_boolean relocatable,
8196 bfd *input_bfd = link_order->u.indirect.section->owner;
8197 asection *input_section = link_order->u.indirect.section;
8199 arelent **reloc_vector;
8202 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
8206 /* Read in the section. */
8207 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
8213 if (reloc_size == 0)
8216 reloc_vector = (arelent **) bfd_malloc (reloc_size);
8217 if (reloc_vector == NULL)
8220 reloc_count = bfd_canonicalize_reloc (input_bfd,
8224 if (reloc_count < 0)
8227 if (reloc_count > 0)
8231 for (parent = reloc_vector; *parent != NULL; parent++)
8233 char *error_message = NULL;
8235 bfd_reloc_status_type r;
8237 symbol = *(*parent)->sym_ptr_ptr;
8238 /* PR ld/19628: A specially crafted input file
8239 can result in a NULL symbol pointer here. */
8242 link_info->callbacks->einfo
8243 /* xgettext:c-format */
8244 (_("%X%P: %B(%A): error: relocation for offset %V has no value\n"),
8245 abfd, input_section, (* parent)->address);
8249 if (symbol->section && discarded_section (symbol->section))
8252 static reloc_howto_type none_howto
8253 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
8254 "unused", FALSE, 0, 0, FALSE);
8256 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
8257 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
8259 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
8260 (*parent)->addend = 0;
8261 (*parent)->howto = &none_howto;
8265 r = bfd_perform_relocation (input_bfd,
8269 relocatable ? abfd : NULL,
8274 asection *os = input_section->output_section;
8276 /* A partial link, so keep the relocs. */
8277 os->orelocation[os->reloc_count] = *parent;
8281 if (r != bfd_reloc_ok)
8285 case bfd_reloc_undefined:
8286 (*link_info->callbacks->undefined_symbol)
8287 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8288 input_bfd, input_section, (*parent)->address, TRUE);
8290 case bfd_reloc_dangerous:
8291 BFD_ASSERT (error_message != NULL);
8292 (*link_info->callbacks->reloc_dangerous)
8293 (link_info, error_message,
8294 input_bfd, input_section, (*parent)->address);
8296 case bfd_reloc_overflow:
8297 (*link_info->callbacks->reloc_overflow)
8299 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8300 (*parent)->howto->name, (*parent)->addend,
8301 input_bfd, input_section, (*parent)->address);
8303 case bfd_reloc_outofrange:
8305 This error can result when processing some partially
8306 complete binaries. Do not abort, but issue an error
8308 link_info->callbacks->einfo
8309 /* xgettext:c-format */
8310 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
8311 abfd, input_section, * parent);
8314 case bfd_reloc_notsupported:
8316 This error can result when processing a corrupt binary.
8317 Do not abort. Issue an error message instead. */
8318 link_info->callbacks->einfo
8319 /* xgettext:c-format */
8320 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
8321 abfd, input_section, * parent);
8325 /* PR 17512; file: 90c2a92e.
8326 Report unexpected results, without aborting. */
8327 link_info->callbacks->einfo
8328 /* xgettext:c-format */
8329 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
8330 abfd, input_section, * parent, r);
8338 free (reloc_vector);
8342 free (reloc_vector);
8348 _bfd_generic_set_reloc
8351 void _bfd_generic_set_reloc
8355 unsigned int count);
8358 Installs a new set of internal relocations in SECTION.
8362 _bfd_generic_set_reloc (bfd *abfd ATTRIBUTE_UNUSED,
8367 section->orelocation = relptr;
8368 section->reloc_count = count;
8373 _bfd_unrecognized_reloc
8376 bfd_boolean _bfd_unrecognized_reloc
8379 unsigned int r_type);
8382 Reports an unrecognized reloc.
8383 Written as a function in order to reduce code duplication.
8384 Returns FALSE so that it can be called from a return statement.
8388 _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type)
8390 /* xgettext:c-format */
8391 _bfd_error_handler (_("%B: unrecognized relocation (%#x) in section `%A'"),
8392 abfd, r_type, section);
8394 /* PR 21803: Suggest the most likely cause of this error. */
8395 _bfd_error_handler (_("Is this version of the linker - %s - out of date ?"),
8396 BFD_VERSION_STRING);
8398 bfd_set_error (bfd_error_bad_value);
8403 _bfd_norelocs_bfd_reloc_type_lookup
8405 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED)
8407 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8411 _bfd_norelocs_bfd_reloc_name_lookup (bfd *abfd,
8412 const char *reloc_name ATTRIBUTE_UNUSED)
8414 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8418 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd *abfd,
8419 arelent **relp ATTRIBUTE_UNUSED,
8420 asymbol **symp ATTRIBUTE_UNUSED)
8422 return _bfd_long_bfd_n1_error (abfd);