1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2017 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type *howto)
452 How relocs are tied together in an <<asection>>:
454 .typedef struct relent_chain
457 . struct relent_chain *next;
463 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
464 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
471 bfd_reloc_status_type bfd_check_overflow
472 (enum complain_overflow how,
473 unsigned int bitsize,
474 unsigned int rightshift,
475 unsigned int addrsize,
479 Perform overflow checking on @var{relocation} which has
480 @var{bitsize} significant bits and will be shifted right by
481 @var{rightshift} bits, on a machine with addresses containing
482 @var{addrsize} significant bits. The result is either of
483 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
487 bfd_reloc_status_type
488 bfd_check_overflow (enum complain_overflow how,
489 unsigned int bitsize,
490 unsigned int rightshift,
491 unsigned int addrsize,
494 bfd_vma fieldmask, addrmask, signmask, ss, a;
495 bfd_reloc_status_type flag = bfd_reloc_ok;
497 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
498 we'll be permissive: extra bits in the field mask will
499 automatically extend the address mask for purposes of the
501 fieldmask = N_ONES (bitsize);
502 signmask = ~fieldmask;
503 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
504 a = (relocation & addrmask) >> rightshift;
508 case complain_overflow_dont:
511 case complain_overflow_signed:
512 /* If any sign bits are set, all sign bits must be set. That
513 is, A must be a valid negative address after shifting. */
514 signmask = ~ (fieldmask >> 1);
517 case complain_overflow_bitfield:
518 /* Bitfields are sometimes signed, sometimes unsigned. We
519 explicitly allow an address wrap too, which means a bitfield
520 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
521 if the value has some, but not all, bits set outside the
524 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
525 flag = bfd_reloc_overflow;
528 case complain_overflow_unsigned:
529 /* We have an overflow if the address does not fit in the field. */
530 if ((a & signmask) != 0)
531 flag = bfd_reloc_overflow;
541 /* HOWTO describes a relocation, at offset OCTET. Return whether the
542 relocation field is within SECTION of ABFD. */
545 reloc_offset_in_range (reloc_howto_type *howto, bfd *abfd,
546 asection *section, bfd_size_type octet)
548 bfd_size_type octet_end = bfd_get_section_limit_octets (abfd, section);
549 bfd_size_type reloc_size = bfd_get_reloc_size (howto);
551 /* The reloc field must be contained entirely within the section.
552 Allow zero length fields (marker relocs or NONE relocs where no
553 relocation will be performed) at the end of the section. */
554 return octet <= octet_end && octet + reloc_size <= octet_end;
559 bfd_perform_relocation
562 bfd_reloc_status_type bfd_perform_relocation
564 arelent *reloc_entry,
566 asection *input_section,
568 char **error_message);
571 If @var{output_bfd} is supplied to this function, the
572 generated image will be relocatable; the relocations are
573 copied to the output file after they have been changed to
574 reflect the new state of the world. There are two ways of
575 reflecting the results of partial linkage in an output file:
576 by modifying the output data in place, and by modifying the
577 relocation record. Some native formats (e.g., basic a.out and
578 basic coff) have no way of specifying an addend in the
579 relocation type, so the addend has to go in the output data.
580 This is no big deal since in these formats the output data
581 slot will always be big enough for the addend. Complex reloc
582 types with addends were invented to solve just this problem.
583 The @var{error_message} argument is set to an error message if
584 this return @code{bfd_reloc_dangerous}.
588 bfd_reloc_status_type
589 bfd_perform_relocation (bfd *abfd,
590 arelent *reloc_entry,
592 asection *input_section,
594 char **error_message)
597 bfd_reloc_status_type flag = bfd_reloc_ok;
598 bfd_size_type octets;
599 bfd_vma output_base = 0;
600 reloc_howto_type *howto = reloc_entry->howto;
601 asection *reloc_target_output_section;
604 symbol = *(reloc_entry->sym_ptr_ptr);
606 /* If we are not producing relocatable output, return an error if
607 the symbol is not defined. An undefined weak symbol is
608 considered to have a value of zero (SVR4 ABI, p. 4-27). */
609 if (bfd_is_und_section (symbol->section)
610 && (symbol->flags & BSF_WEAK) == 0
611 && output_bfd == NULL)
612 flag = bfd_reloc_undefined;
614 /* If there is a function supplied to handle this relocation type,
615 call it. It'll return `bfd_reloc_continue' if further processing
617 if (howto && howto->special_function)
619 bfd_reloc_status_type cont;
620 cont = howto->special_function (abfd, reloc_entry, symbol, data,
621 input_section, output_bfd,
623 if (cont != bfd_reloc_continue)
627 if (bfd_is_abs_section (symbol->section)
628 && output_bfd != NULL)
630 reloc_entry->address += input_section->output_offset;
634 /* PR 17512: file: 0f67f69d. */
636 return bfd_reloc_undefined;
638 /* Is the address of the relocation really within the section? */
639 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
640 if (!reloc_offset_in_range (howto, abfd, input_section, octets))
641 return bfd_reloc_outofrange;
643 /* Work out which section the relocation is targeted at and the
644 initial relocation command value. */
646 /* Get symbol value. (Common symbols are special.) */
647 if (bfd_is_com_section (symbol->section))
650 relocation = symbol->value;
652 reloc_target_output_section = symbol->section->output_section;
654 /* Convert input-section-relative symbol value to absolute. */
655 if ((output_bfd && ! howto->partial_inplace)
656 || reloc_target_output_section == NULL)
659 output_base = reloc_target_output_section->vma;
661 relocation += output_base + symbol->section->output_offset;
663 /* Add in supplied addend. */
664 relocation += reloc_entry->addend;
666 /* Here the variable relocation holds the final address of the
667 symbol we are relocating against, plus any addend. */
669 if (howto->pc_relative)
671 /* This is a PC relative relocation. We want to set RELOCATION
672 to the distance between the address of the symbol and the
673 location. RELOCATION is already the address of the symbol.
675 We start by subtracting the address of the section containing
678 If pcrel_offset is set, we must further subtract the position
679 of the location within the section. Some targets arrange for
680 the addend to be the negative of the position of the location
681 within the section; for example, i386-aout does this. For
682 i386-aout, pcrel_offset is FALSE. Some other targets do not
683 include the position of the location; for example, m88kbcs,
684 or ELF. For those targets, pcrel_offset is TRUE.
686 If we are producing relocatable output, then we must ensure
687 that this reloc will be correctly computed when the final
688 relocation is done. If pcrel_offset is FALSE we want to wind
689 up with the negative of the location within the section,
690 which means we must adjust the existing addend by the change
691 in the location within the section. If pcrel_offset is TRUE
692 we do not want to adjust the existing addend at all.
694 FIXME: This seems logical to me, but for the case of
695 producing relocatable output it is not what the code
696 actually does. I don't want to change it, because it seems
697 far too likely that something will break. */
700 input_section->output_section->vma + input_section->output_offset;
702 if (howto->pcrel_offset)
703 relocation -= reloc_entry->address;
706 if (output_bfd != NULL)
708 if (! howto->partial_inplace)
710 /* This is a partial relocation, and we want to apply the relocation
711 to the reloc entry rather than the raw data. Modify the reloc
712 inplace to reflect what we now know. */
713 reloc_entry->addend = relocation;
714 reloc_entry->address += input_section->output_offset;
719 /* This is a partial relocation, but inplace, so modify the
722 If we've relocated with a symbol with a section, change
723 into a ref to the section belonging to the symbol. */
725 reloc_entry->address += input_section->output_offset;
728 if (abfd->xvec->flavour == bfd_target_coff_flavour
729 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
730 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
732 /* For m68k-coff, the addend was being subtracted twice during
733 relocation with -r. Removing the line below this comment
734 fixes that problem; see PR 2953.
736 However, Ian wrote the following, regarding removing the line below,
737 which explains why it is still enabled: --djm
739 If you put a patch like that into BFD you need to check all the COFF
740 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
741 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
742 problem in a different way. There may very well be a reason that the
743 code works as it does.
745 Hmmm. The first obvious point is that bfd_perform_relocation should
746 not have any tests that depend upon the flavour. It's seem like
747 entirely the wrong place for such a thing. The second obvious point
748 is that the current code ignores the reloc addend when producing
749 relocatable output for COFF. That's peculiar. In fact, I really
750 have no idea what the point of the line you want to remove is.
752 A typical COFF reloc subtracts the old value of the symbol and adds in
753 the new value to the location in the object file (if it's a pc
754 relative reloc it adds the difference between the symbol value and the
755 location). When relocating we need to preserve that property.
757 BFD handles this by setting the addend to the negative of the old
758 value of the symbol. Unfortunately it handles common symbols in a
759 non-standard way (it doesn't subtract the old value) but that's a
760 different story (we can't change it without losing backward
761 compatibility with old object files) (coff-i386 does subtract the old
762 value, to be compatible with existing coff-i386 targets, like SCO).
764 So everything works fine when not producing relocatable output. When
765 we are producing relocatable output, logically we should do exactly
766 what we do when not producing relocatable output. Therefore, your
767 patch is correct. In fact, it should probably always just set
768 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
769 add the value into the object file. This won't hurt the COFF code,
770 which doesn't use the addend; I'm not sure what it will do to other
771 formats (the thing to check for would be whether any formats both use
772 the addend and set partial_inplace).
774 When I wanted to make coff-i386 produce relocatable output, I ran
775 into the problem that you are running into: I wanted to remove that
776 line. Rather than risk it, I made the coff-i386 relocs use a special
777 function; it's coff_i386_reloc in coff-i386.c. The function
778 specifically adds the addend field into the object file, knowing that
779 bfd_perform_relocation is not going to. If you remove that line, then
780 coff-i386.c will wind up adding the addend field in twice. It's
781 trivial to fix; it just needs to be done.
783 The problem with removing the line is just that it may break some
784 working code. With BFD it's hard to be sure of anything. The right
785 way to deal with this is simply to build and test at least all the
786 supported COFF targets. It should be straightforward if time and disk
787 space consuming. For each target:
789 2) generate some executable, and link it using -r (I would
790 probably use paranoia.o and link against newlib/libc.a, which
791 for all the supported targets would be available in
792 /usr/cygnus/progressive/H-host/target/lib/libc.a).
793 3) make the change to reloc.c
794 4) rebuild the linker
796 6) if the resulting object files are the same, you have at least
798 7) if they are different you have to figure out which version is
801 relocation -= reloc_entry->addend;
802 reloc_entry->addend = 0;
806 reloc_entry->addend = relocation;
811 /* FIXME: This overflow checking is incomplete, because the value
812 might have overflowed before we get here. For a correct check we
813 need to compute the value in a size larger than bitsize, but we
814 can't reasonably do that for a reloc the same size as a host
816 FIXME: We should also do overflow checking on the result after
817 adding in the value contained in the object file. */
818 if (howto->complain_on_overflow != complain_overflow_dont
819 && flag == bfd_reloc_ok)
820 flag = bfd_check_overflow (howto->complain_on_overflow,
823 bfd_arch_bits_per_address (abfd),
826 /* Either we are relocating all the way, or we don't want to apply
827 the relocation to the reloc entry (probably because there isn't
828 any room in the output format to describe addends to relocs). */
830 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
831 (OSF version 1.3, compiler version 3.11). It miscompiles the
845 x <<= (unsigned long) s.i0;
849 printf ("succeeded (%lx)\n", x);
853 relocation >>= (bfd_vma) howto->rightshift;
855 /* Shift everything up to where it's going to be used. */
856 relocation <<= (bfd_vma) howto->bitpos;
858 /* Wait for the day when all have the mask in them. */
861 i instruction to be left alone
862 o offset within instruction
863 r relocation offset to apply
872 (( i i i i i o o o o o from bfd_get<size>
873 and S S S S S) to get the size offset we want
874 + r r r r r r r r r r) to get the final value to place
875 and D D D D D to chop to right size
876 -----------------------
879 ( i i i i i o o o o o from bfd_get<size>
880 and N N N N N ) get instruction
881 -----------------------
887 -----------------------
888 = R R R R R R R R R R put into bfd_put<size>
892 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
898 char x = bfd_get_8 (abfd, (char *) data + octets);
900 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
906 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
908 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
913 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
915 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
920 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
921 relocation = -relocation;
923 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
929 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
930 relocation = -relocation;
932 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
943 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
945 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
952 return bfd_reloc_other;
960 bfd_install_relocation
963 bfd_reloc_status_type bfd_install_relocation
965 arelent *reloc_entry,
966 void *data, bfd_vma data_start,
967 asection *input_section,
968 char **error_message);
971 This looks remarkably like <<bfd_perform_relocation>>, except it
972 does not expect that the section contents have been filled in.
973 I.e., it's suitable for use when creating, rather than applying
976 For now, this function should be considered reserved for the
980 bfd_reloc_status_type
981 bfd_install_relocation (bfd *abfd,
982 arelent *reloc_entry,
984 bfd_vma data_start_offset,
985 asection *input_section,
986 char **error_message)
989 bfd_reloc_status_type flag = bfd_reloc_ok;
990 bfd_size_type octets;
991 bfd_vma output_base = 0;
992 reloc_howto_type *howto = reloc_entry->howto;
993 asection *reloc_target_output_section;
997 symbol = *(reloc_entry->sym_ptr_ptr);
999 /* If there is a function supplied to handle this relocation type,
1000 call it. It'll return `bfd_reloc_continue' if further processing
1002 if (howto && howto->special_function)
1004 bfd_reloc_status_type cont;
1006 /* XXX - The special_function calls haven't been fixed up to deal
1007 with creating new relocations and section contents. */
1008 cont = howto->special_function (abfd, reloc_entry, symbol,
1009 /* XXX - Non-portable! */
1010 ((bfd_byte *) data_start
1011 - data_start_offset),
1012 input_section, abfd, error_message);
1013 if (cont != bfd_reloc_continue)
1017 if (bfd_is_abs_section (symbol->section))
1019 reloc_entry->address += input_section->output_offset;
1020 return bfd_reloc_ok;
1023 /* No need to check for howto != NULL if !bfd_is_abs_section as
1024 it will have been checked in `bfd_perform_relocation already'. */
1026 /* Is the address of the relocation really within the section? */
1027 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
1028 if (!reloc_offset_in_range (howto, abfd, input_section, octets))
1029 return bfd_reloc_outofrange;
1031 /* Work out which section the relocation is targeted at and the
1032 initial relocation command value. */
1034 /* Get symbol value. (Common symbols are special.) */
1035 if (bfd_is_com_section (symbol->section))
1038 relocation = symbol->value;
1040 reloc_target_output_section = symbol->section->output_section;
1042 /* Convert input-section-relative symbol value to absolute. */
1043 if (! howto->partial_inplace)
1046 output_base = reloc_target_output_section->vma;
1048 relocation += output_base + symbol->section->output_offset;
1050 /* Add in supplied addend. */
1051 relocation += reloc_entry->addend;
1053 /* Here the variable relocation holds the final address of the
1054 symbol we are relocating against, plus any addend. */
1056 if (howto->pc_relative)
1058 /* This is a PC relative relocation. We want to set RELOCATION
1059 to the distance between the address of the symbol and the
1060 location. RELOCATION is already the address of the symbol.
1062 We start by subtracting the address of the section containing
1065 If pcrel_offset is set, we must further subtract the position
1066 of the location within the section. Some targets arrange for
1067 the addend to be the negative of the position of the location
1068 within the section; for example, i386-aout does this. For
1069 i386-aout, pcrel_offset is FALSE. Some other targets do not
1070 include the position of the location; for example, m88kbcs,
1071 or ELF. For those targets, pcrel_offset is TRUE.
1073 If we are producing relocatable output, then we must ensure
1074 that this reloc will be correctly computed when the final
1075 relocation is done. If pcrel_offset is FALSE we want to wind
1076 up with the negative of the location within the section,
1077 which means we must adjust the existing addend by the change
1078 in the location within the section. If pcrel_offset is TRUE
1079 we do not want to adjust the existing addend at all.
1081 FIXME: This seems logical to me, but for the case of
1082 producing relocatable output it is not what the code
1083 actually does. I don't want to change it, because it seems
1084 far too likely that something will break. */
1087 input_section->output_section->vma + input_section->output_offset;
1089 if (howto->pcrel_offset && howto->partial_inplace)
1090 relocation -= reloc_entry->address;
1093 if (! howto->partial_inplace)
1095 /* This is a partial relocation, and we want to apply the relocation
1096 to the reloc entry rather than the raw data. Modify the reloc
1097 inplace to reflect what we now know. */
1098 reloc_entry->addend = relocation;
1099 reloc_entry->address += input_section->output_offset;
1104 /* This is a partial relocation, but inplace, so modify the
1107 If we've relocated with a symbol with a section, change
1108 into a ref to the section belonging to the symbol. */
1109 reloc_entry->address += input_section->output_offset;
1112 if (abfd->xvec->flavour == bfd_target_coff_flavour
1113 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1114 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1117 /* For m68k-coff, the addend was being subtracted twice during
1118 relocation with -r. Removing the line below this comment
1119 fixes that problem; see PR 2953.
1121 However, Ian wrote the following, regarding removing the line below,
1122 which explains why it is still enabled: --djm
1124 If you put a patch like that into BFD you need to check all the COFF
1125 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1126 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1127 problem in a different way. There may very well be a reason that the
1128 code works as it does.
1130 Hmmm. The first obvious point is that bfd_install_relocation should
1131 not have any tests that depend upon the flavour. It's seem like
1132 entirely the wrong place for such a thing. The second obvious point
1133 is that the current code ignores the reloc addend when producing
1134 relocatable output for COFF. That's peculiar. In fact, I really
1135 have no idea what the point of the line you want to remove is.
1137 A typical COFF reloc subtracts the old value of the symbol and adds in
1138 the new value to the location in the object file (if it's a pc
1139 relative reloc it adds the difference between the symbol value and the
1140 location). When relocating we need to preserve that property.
1142 BFD handles this by setting the addend to the negative of the old
1143 value of the symbol. Unfortunately it handles common symbols in a
1144 non-standard way (it doesn't subtract the old value) but that's a
1145 different story (we can't change it without losing backward
1146 compatibility with old object files) (coff-i386 does subtract the old
1147 value, to be compatible with existing coff-i386 targets, like SCO).
1149 So everything works fine when not producing relocatable output. When
1150 we are producing relocatable output, logically we should do exactly
1151 what we do when not producing relocatable output. Therefore, your
1152 patch is correct. In fact, it should probably always just set
1153 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1154 add the value into the object file. This won't hurt the COFF code,
1155 which doesn't use the addend; I'm not sure what it will do to other
1156 formats (the thing to check for would be whether any formats both use
1157 the addend and set partial_inplace).
1159 When I wanted to make coff-i386 produce relocatable output, I ran
1160 into the problem that you are running into: I wanted to remove that
1161 line. Rather than risk it, I made the coff-i386 relocs use a special
1162 function; it's coff_i386_reloc in coff-i386.c. The function
1163 specifically adds the addend field into the object file, knowing that
1164 bfd_install_relocation is not going to. If you remove that line, then
1165 coff-i386.c will wind up adding the addend field in twice. It's
1166 trivial to fix; it just needs to be done.
1168 The problem with removing the line is just that it may break some
1169 working code. With BFD it's hard to be sure of anything. The right
1170 way to deal with this is simply to build and test at least all the
1171 supported COFF targets. It should be straightforward if time and disk
1172 space consuming. For each target:
1174 2) generate some executable, and link it using -r (I would
1175 probably use paranoia.o and link against newlib/libc.a, which
1176 for all the supported targets would be available in
1177 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1178 3) make the change to reloc.c
1179 4) rebuild the linker
1181 6) if the resulting object files are the same, you have at least
1183 7) if they are different you have to figure out which version is
1185 relocation -= reloc_entry->addend;
1186 /* FIXME: There should be no target specific code here... */
1187 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1188 reloc_entry->addend = 0;
1192 reloc_entry->addend = relocation;
1196 /* FIXME: This overflow checking is incomplete, because the value
1197 might have overflowed before we get here. For a correct check we
1198 need to compute the value in a size larger than bitsize, but we
1199 can't reasonably do that for a reloc the same size as a host
1201 FIXME: We should also do overflow checking on the result after
1202 adding in the value contained in the object file. */
1203 if (howto->complain_on_overflow != complain_overflow_dont)
1204 flag = bfd_check_overflow (howto->complain_on_overflow,
1207 bfd_arch_bits_per_address (abfd),
1210 /* Either we are relocating all the way, or we don't want to apply
1211 the relocation to the reloc entry (probably because there isn't
1212 any room in the output format to describe addends to relocs). */
1214 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1215 (OSF version 1.3, compiler version 3.11). It miscompiles the
1229 x <<= (unsigned long) s.i0;
1231 printf ("failed\n");
1233 printf ("succeeded (%lx)\n", x);
1237 relocation >>= (bfd_vma) howto->rightshift;
1239 /* Shift everything up to where it's going to be used. */
1240 relocation <<= (bfd_vma) howto->bitpos;
1242 /* Wait for the day when all have the mask in them. */
1245 i instruction to be left alone
1246 o offset within instruction
1247 r relocation offset to apply
1256 (( i i i i i o o o o o from bfd_get<size>
1257 and S S S S S) to get the size offset we want
1258 + r r r r r r r r r r) to get the final value to place
1259 and D D D D D to chop to right size
1260 -----------------------
1263 ( i i i i i o o o o o from bfd_get<size>
1264 and N N N N N ) get instruction
1265 -----------------------
1271 -----------------------
1272 = R R R R R R R R R R put into bfd_put<size>
1276 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1278 data = (bfd_byte *) data_start + (octets - data_start_offset);
1280 switch (howto->size)
1284 char x = bfd_get_8 (abfd, data);
1286 bfd_put_8 (abfd, x, data);
1292 short x = bfd_get_16 (abfd, data);
1294 bfd_put_16 (abfd, (bfd_vma) x, data);
1299 long x = bfd_get_32 (abfd, data);
1301 bfd_put_32 (abfd, (bfd_vma) x, data);
1306 long x = bfd_get_32 (abfd, data);
1307 relocation = -relocation;
1309 bfd_put_32 (abfd, (bfd_vma) x, data);
1319 bfd_vma x = bfd_get_64 (abfd, data);
1321 bfd_put_64 (abfd, x, data);
1325 return bfd_reloc_other;
1331 /* This relocation routine is used by some of the backend linkers.
1332 They do not construct asymbol or arelent structures, so there is no
1333 reason for them to use bfd_perform_relocation. Also,
1334 bfd_perform_relocation is so hacked up it is easier to write a new
1335 function than to try to deal with it.
1337 This routine does a final relocation. Whether it is useful for a
1338 relocatable link depends upon how the object format defines
1341 FIXME: This routine ignores any special_function in the HOWTO,
1342 since the existing special_function values have been written for
1343 bfd_perform_relocation.
1345 HOWTO is the reloc howto information.
1346 INPUT_BFD is the BFD which the reloc applies to.
1347 INPUT_SECTION is the section which the reloc applies to.
1348 CONTENTS is the contents of the section.
1349 ADDRESS is the address of the reloc within INPUT_SECTION.
1350 VALUE is the value of the symbol the reloc refers to.
1351 ADDEND is the addend of the reloc. */
1353 bfd_reloc_status_type
1354 _bfd_final_link_relocate (reloc_howto_type *howto,
1356 asection *input_section,
1363 bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
1365 /* Sanity check the address. */
1366 if (!reloc_offset_in_range (howto, input_bfd, input_section, octets))
1367 return bfd_reloc_outofrange;
1369 /* This function assumes that we are dealing with a basic relocation
1370 against a symbol. We want to compute the value of the symbol to
1371 relocate to. This is just VALUE, the value of the symbol, plus
1372 ADDEND, any addend associated with the reloc. */
1373 relocation = value + addend;
1375 /* If the relocation is PC relative, we want to set RELOCATION to
1376 the distance between the symbol (currently in RELOCATION) and the
1377 location we are relocating. Some targets (e.g., i386-aout)
1378 arrange for the contents of the section to be the negative of the
1379 offset of the location within the section; for such targets
1380 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1381 simply leave the contents of the section as zero; for such
1382 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1383 need to subtract out the offset of the location within the
1384 section (which is just ADDRESS). */
1385 if (howto->pc_relative)
1387 relocation -= (input_section->output_section->vma
1388 + input_section->output_offset);
1389 if (howto->pcrel_offset)
1390 relocation -= address;
1393 return _bfd_relocate_contents (howto, input_bfd, relocation,
1395 + address * bfd_octets_per_byte (input_bfd));
1398 /* Relocate a given location using a given value and howto. */
1400 bfd_reloc_status_type
1401 _bfd_relocate_contents (reloc_howto_type *howto,
1408 bfd_reloc_status_type flag;
1409 unsigned int rightshift = howto->rightshift;
1410 unsigned int bitpos = howto->bitpos;
1412 /* If the size is negative, negate RELOCATION. This isn't very
1414 if (howto->size < 0)
1415 relocation = -relocation;
1417 /* Get the value we are going to relocate. */
1418 size = bfd_get_reloc_size (howto);
1424 return bfd_reloc_ok;
1426 x = bfd_get_8 (input_bfd, location);
1429 x = bfd_get_16 (input_bfd, location);
1432 x = bfd_get_32 (input_bfd, location);
1436 x = bfd_get_64 (input_bfd, location);
1443 /* Check for overflow. FIXME: We may drop bits during the addition
1444 which we don't check for. We must either check at every single
1445 operation, which would be tedious, or we must do the computations
1446 in a type larger than bfd_vma, which would be inefficient. */
1447 flag = bfd_reloc_ok;
1448 if (howto->complain_on_overflow != complain_overflow_dont)
1450 bfd_vma addrmask, fieldmask, signmask, ss;
1453 /* Get the values to be added together. For signed and unsigned
1454 relocations, we assume that all values should be truncated to
1455 the size of an address. For bitfields, all the bits matter.
1456 See also bfd_check_overflow. */
1457 fieldmask = N_ONES (howto->bitsize);
1458 signmask = ~fieldmask;
1459 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1460 | (fieldmask << rightshift));
1461 a = (relocation & addrmask) >> rightshift;
1462 b = (x & howto->src_mask & addrmask) >> bitpos;
1463 addrmask >>= rightshift;
1465 switch (howto->complain_on_overflow)
1467 case complain_overflow_signed:
1468 /* If any sign bits are set, all sign bits must be set.
1469 That is, A must be a valid negative address after
1471 signmask = ~(fieldmask >> 1);
1474 case complain_overflow_bitfield:
1475 /* Much like the signed check, but for a field one bit
1476 wider. We allow a bitfield to represent numbers in the
1477 range -2**n to 2**n-1, where n is the number of bits in the
1478 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1479 can't overflow, which is exactly what we want. */
1481 if (ss != 0 && ss != (addrmask & signmask))
1482 flag = bfd_reloc_overflow;
1484 /* We only need this next bit of code if the sign bit of B
1485 is below the sign bit of A. This would only happen if
1486 SRC_MASK had fewer bits than BITSIZE. Note that if
1487 SRC_MASK has more bits than BITSIZE, we can get into
1488 trouble; we would need to verify that B is in range, as
1489 we do for A above. */
1490 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1493 /* Set all the bits above the sign bit. */
1496 /* Now we can do the addition. */
1499 /* See if the result has the correct sign. Bits above the
1500 sign bit are junk now; ignore them. If the sum is
1501 positive, make sure we did not have all negative inputs;
1502 if the sum is negative, make sure we did not have all
1503 positive inputs. The test below looks only at the sign
1504 bits, and it really just
1505 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1507 We mask with addrmask here to explicitly allow an address
1508 wrap-around. The Linux kernel relies on it, and it is
1509 the only way to write assembler code which can run when
1510 loaded at a location 0x80000000 away from the location at
1511 which it is linked. */
1512 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1513 flag = bfd_reloc_overflow;
1516 case complain_overflow_unsigned:
1517 /* Checking for an unsigned overflow is relatively easy:
1518 trim the addresses and add, and trim the result as well.
1519 Overflow is normally indicated when the result does not
1520 fit in the field. However, we also need to consider the
1521 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1522 input is 0x80000000, and bfd_vma is only 32 bits; then we
1523 will get sum == 0, but there is an overflow, since the
1524 inputs did not fit in the field. Instead of doing a
1525 separate test, we can check for this by or-ing in the
1526 operands when testing for the sum overflowing its final
1528 sum = (a + b) & addrmask;
1529 if ((a | b | sum) & signmask)
1530 flag = bfd_reloc_overflow;
1538 /* Put RELOCATION in the right bits. */
1539 relocation >>= (bfd_vma) rightshift;
1540 relocation <<= (bfd_vma) bitpos;
1542 /* Add RELOCATION to the right bits of X. */
1543 x = ((x & ~howto->dst_mask)
1544 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1546 /* Put the relocated value back in the object file. */
1552 bfd_put_8 (input_bfd, x, location);
1555 bfd_put_16 (input_bfd, x, location);
1558 bfd_put_32 (input_bfd, x, location);
1562 bfd_put_64 (input_bfd, x, location);
1572 /* Clear a given location using a given howto, by applying a fixed relocation
1573 value and discarding any in-place addend. This is used for fixed-up
1574 relocations against discarded symbols, to make ignorable debug or unwind
1575 information more obvious. */
1578 _bfd_clear_contents (reloc_howto_type *howto,
1580 asection *input_section,
1586 /* Get the value we are going to relocate. */
1587 size = bfd_get_reloc_size (howto);
1595 x = bfd_get_8 (input_bfd, location);
1598 x = bfd_get_16 (input_bfd, location);
1601 x = bfd_get_32 (input_bfd, location);
1605 x = bfd_get_64 (input_bfd, location);
1612 /* Zero out the unwanted bits of X. */
1613 x &= ~howto->dst_mask;
1615 /* For a range list, use 1 instead of 0 as placeholder. 0
1616 would terminate the list, hiding any later entries. */
1617 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1618 ".debug_ranges") == 0
1619 && (howto->dst_mask & 1) != 0)
1622 /* Put the relocated value back in the object file. */
1629 bfd_put_8 (input_bfd, x, location);
1632 bfd_put_16 (input_bfd, x, location);
1635 bfd_put_32 (input_bfd, x, location);
1639 bfd_put_64 (input_bfd, x, location);
1650 howto manager, , typedef arelent, Relocations
1655 When an application wants to create a relocation, but doesn't
1656 know what the target machine might call it, it can find out by
1657 using this bit of code.
1666 The insides of a reloc code. The idea is that, eventually, there
1667 will be one enumerator for every type of relocation we ever do.
1668 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1669 return a howto pointer.
1671 This does mean that the application must determine the correct
1672 enumerator value; you can't get a howto pointer from a random set
1693 Basic absolute relocations of N bits.
1708 PC-relative relocations. Sometimes these are relative to the address
1709 of the relocation itself; sometimes they are relative to the start of
1710 the section containing the relocation. It depends on the specific target.
1712 The 24-bit relocation is used in some Intel 960 configurations.
1717 Section relative relocations. Some targets need this for DWARF2.
1720 BFD_RELOC_32_GOT_PCREL
1722 BFD_RELOC_16_GOT_PCREL
1724 BFD_RELOC_8_GOT_PCREL
1730 BFD_RELOC_LO16_GOTOFF
1732 BFD_RELOC_HI16_GOTOFF
1734 BFD_RELOC_HI16_S_GOTOFF
1738 BFD_RELOC_64_PLT_PCREL
1740 BFD_RELOC_32_PLT_PCREL
1742 BFD_RELOC_24_PLT_PCREL
1744 BFD_RELOC_16_PLT_PCREL
1746 BFD_RELOC_8_PLT_PCREL
1754 BFD_RELOC_LO16_PLTOFF
1756 BFD_RELOC_HI16_PLTOFF
1758 BFD_RELOC_HI16_S_PLTOFF
1772 BFD_RELOC_68K_GLOB_DAT
1774 BFD_RELOC_68K_JMP_SLOT
1776 BFD_RELOC_68K_RELATIVE
1778 BFD_RELOC_68K_TLS_GD32
1780 BFD_RELOC_68K_TLS_GD16
1782 BFD_RELOC_68K_TLS_GD8
1784 BFD_RELOC_68K_TLS_LDM32
1786 BFD_RELOC_68K_TLS_LDM16
1788 BFD_RELOC_68K_TLS_LDM8
1790 BFD_RELOC_68K_TLS_LDO32
1792 BFD_RELOC_68K_TLS_LDO16
1794 BFD_RELOC_68K_TLS_LDO8
1796 BFD_RELOC_68K_TLS_IE32
1798 BFD_RELOC_68K_TLS_IE16
1800 BFD_RELOC_68K_TLS_IE8
1802 BFD_RELOC_68K_TLS_LE32
1804 BFD_RELOC_68K_TLS_LE16
1806 BFD_RELOC_68K_TLS_LE8
1808 Relocations used by 68K ELF.
1811 BFD_RELOC_32_BASEREL
1813 BFD_RELOC_16_BASEREL
1815 BFD_RELOC_LO16_BASEREL
1817 BFD_RELOC_HI16_BASEREL
1819 BFD_RELOC_HI16_S_BASEREL
1825 Linkage-table relative.
1830 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1833 BFD_RELOC_32_PCREL_S2
1835 BFD_RELOC_16_PCREL_S2
1837 BFD_RELOC_23_PCREL_S2
1839 These PC-relative relocations are stored as word displacements --
1840 i.e., byte displacements shifted right two bits. The 30-bit word
1841 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1842 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1843 signed 16-bit displacement is used on the MIPS, and the 23-bit
1844 displacement is used on the Alpha.
1851 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1852 the target word. These are used on the SPARC.
1859 For systems that allocate a Global Pointer register, these are
1860 displacements off that register. These relocation types are
1861 handled specially, because the value the register will have is
1862 decided relatively late.
1865 BFD_RELOC_I960_CALLJ
1867 Reloc types used for i960/b.out.
1872 BFD_RELOC_SPARC_WDISP22
1878 BFD_RELOC_SPARC_GOT10
1880 BFD_RELOC_SPARC_GOT13
1882 BFD_RELOC_SPARC_GOT22
1884 BFD_RELOC_SPARC_PC10
1886 BFD_RELOC_SPARC_PC22
1888 BFD_RELOC_SPARC_WPLT30
1890 BFD_RELOC_SPARC_COPY
1892 BFD_RELOC_SPARC_GLOB_DAT
1894 BFD_RELOC_SPARC_JMP_SLOT
1896 BFD_RELOC_SPARC_RELATIVE
1898 BFD_RELOC_SPARC_UA16
1900 BFD_RELOC_SPARC_UA32
1902 BFD_RELOC_SPARC_UA64
1904 BFD_RELOC_SPARC_GOTDATA_HIX22
1906 BFD_RELOC_SPARC_GOTDATA_LOX10
1908 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1910 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1912 BFD_RELOC_SPARC_GOTDATA_OP
1914 BFD_RELOC_SPARC_JMP_IREL
1916 BFD_RELOC_SPARC_IRELATIVE
1918 SPARC ELF relocations. There is probably some overlap with other
1919 relocation types already defined.
1922 BFD_RELOC_SPARC_BASE13
1924 BFD_RELOC_SPARC_BASE22
1926 I think these are specific to SPARC a.out (e.g., Sun 4).
1936 BFD_RELOC_SPARC_OLO10
1938 BFD_RELOC_SPARC_HH22
1940 BFD_RELOC_SPARC_HM10
1942 BFD_RELOC_SPARC_LM22
1944 BFD_RELOC_SPARC_PC_HH22
1946 BFD_RELOC_SPARC_PC_HM10
1948 BFD_RELOC_SPARC_PC_LM22
1950 BFD_RELOC_SPARC_WDISP16
1952 BFD_RELOC_SPARC_WDISP19
1960 BFD_RELOC_SPARC_DISP64
1963 BFD_RELOC_SPARC_PLT32
1965 BFD_RELOC_SPARC_PLT64
1967 BFD_RELOC_SPARC_HIX22
1969 BFD_RELOC_SPARC_LOX10
1977 BFD_RELOC_SPARC_REGISTER
1981 BFD_RELOC_SPARC_SIZE32
1983 BFD_RELOC_SPARC_SIZE64
1985 BFD_RELOC_SPARC_WDISP10
1990 BFD_RELOC_SPARC_REV32
1992 SPARC little endian relocation
1994 BFD_RELOC_SPARC_TLS_GD_HI22
1996 BFD_RELOC_SPARC_TLS_GD_LO10
1998 BFD_RELOC_SPARC_TLS_GD_ADD
2000 BFD_RELOC_SPARC_TLS_GD_CALL
2002 BFD_RELOC_SPARC_TLS_LDM_HI22
2004 BFD_RELOC_SPARC_TLS_LDM_LO10
2006 BFD_RELOC_SPARC_TLS_LDM_ADD
2008 BFD_RELOC_SPARC_TLS_LDM_CALL
2010 BFD_RELOC_SPARC_TLS_LDO_HIX22
2012 BFD_RELOC_SPARC_TLS_LDO_LOX10
2014 BFD_RELOC_SPARC_TLS_LDO_ADD
2016 BFD_RELOC_SPARC_TLS_IE_HI22
2018 BFD_RELOC_SPARC_TLS_IE_LO10
2020 BFD_RELOC_SPARC_TLS_IE_LD
2022 BFD_RELOC_SPARC_TLS_IE_LDX
2024 BFD_RELOC_SPARC_TLS_IE_ADD
2026 BFD_RELOC_SPARC_TLS_LE_HIX22
2028 BFD_RELOC_SPARC_TLS_LE_LOX10
2030 BFD_RELOC_SPARC_TLS_DTPMOD32
2032 BFD_RELOC_SPARC_TLS_DTPMOD64
2034 BFD_RELOC_SPARC_TLS_DTPOFF32
2036 BFD_RELOC_SPARC_TLS_DTPOFF64
2038 BFD_RELOC_SPARC_TLS_TPOFF32
2040 BFD_RELOC_SPARC_TLS_TPOFF64
2042 SPARC TLS relocations
2051 BFD_RELOC_SPU_IMM10W
2055 BFD_RELOC_SPU_IMM16W
2059 BFD_RELOC_SPU_PCREL9a
2061 BFD_RELOC_SPU_PCREL9b
2063 BFD_RELOC_SPU_PCREL16
2073 BFD_RELOC_SPU_ADD_PIC
2078 BFD_RELOC_ALPHA_GPDISP_HI16
2080 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2081 "addend" in some special way.
2082 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2083 writing; when reading, it will be the absolute section symbol. The
2084 addend is the displacement in bytes of the "lda" instruction from
2085 the "ldah" instruction (which is at the address of this reloc).
2087 BFD_RELOC_ALPHA_GPDISP_LO16
2089 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2090 with GPDISP_HI16 relocs. The addend is ignored when writing the
2091 relocations out, and is filled in with the file's GP value on
2092 reading, for convenience.
2095 BFD_RELOC_ALPHA_GPDISP
2097 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2098 relocation except that there is no accompanying GPDISP_LO16
2102 BFD_RELOC_ALPHA_LITERAL
2104 BFD_RELOC_ALPHA_ELF_LITERAL
2106 BFD_RELOC_ALPHA_LITUSE
2108 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2109 the assembler turns it into a LDQ instruction to load the address of
2110 the symbol, and then fills in a register in the real instruction.
2112 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2113 section symbol. The addend is ignored when writing, but is filled
2114 in with the file's GP value on reading, for convenience, as with the
2117 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2118 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2119 but it generates output not based on the position within the .got
2120 section, but relative to the GP value chosen for the file during the
2123 The LITUSE reloc, on the instruction using the loaded address, gives
2124 information to the linker that it might be able to use to optimize
2125 away some literal section references. The symbol is ignored (read
2126 as the absolute section symbol), and the "addend" indicates the type
2127 of instruction using the register:
2128 1 - "memory" fmt insn
2129 2 - byte-manipulation (byte offset reg)
2130 3 - jsr (target of branch)
2133 BFD_RELOC_ALPHA_HINT
2135 The HINT relocation indicates a value that should be filled into the
2136 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2137 prediction logic which may be provided on some processors.
2140 BFD_RELOC_ALPHA_LINKAGE
2142 The LINKAGE relocation outputs a linkage pair in the object file,
2143 which is filled by the linker.
2146 BFD_RELOC_ALPHA_CODEADDR
2148 The CODEADDR relocation outputs a STO_CA in the object file,
2149 which is filled by the linker.
2152 BFD_RELOC_ALPHA_GPREL_HI16
2154 BFD_RELOC_ALPHA_GPREL_LO16
2156 The GPREL_HI/LO relocations together form a 32-bit offset from the
2160 BFD_RELOC_ALPHA_BRSGP
2162 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2163 share a common GP, and the target address is adjusted for
2164 STO_ALPHA_STD_GPLOAD.
2169 The NOP relocation outputs a NOP if the longword displacement
2170 between two procedure entry points is < 2^21.
2175 The BSR relocation outputs a BSR if the longword displacement
2176 between two procedure entry points is < 2^21.
2181 The LDA relocation outputs a LDA if the longword displacement
2182 between two procedure entry points is < 2^16.
2187 The BOH relocation outputs a BSR if the longword displacement
2188 between two procedure entry points is < 2^21, or else a hint.
2191 BFD_RELOC_ALPHA_TLSGD
2193 BFD_RELOC_ALPHA_TLSLDM
2195 BFD_RELOC_ALPHA_DTPMOD64
2197 BFD_RELOC_ALPHA_GOTDTPREL16
2199 BFD_RELOC_ALPHA_DTPREL64
2201 BFD_RELOC_ALPHA_DTPREL_HI16
2203 BFD_RELOC_ALPHA_DTPREL_LO16
2205 BFD_RELOC_ALPHA_DTPREL16
2207 BFD_RELOC_ALPHA_GOTTPREL16
2209 BFD_RELOC_ALPHA_TPREL64
2211 BFD_RELOC_ALPHA_TPREL_HI16
2213 BFD_RELOC_ALPHA_TPREL_LO16
2215 BFD_RELOC_ALPHA_TPREL16
2217 Alpha thread-local storage relocations.
2222 BFD_RELOC_MICROMIPS_JMP
2224 The MIPS jump instruction.
2227 BFD_RELOC_MIPS16_JMP
2229 The MIPS16 jump instruction.
2232 BFD_RELOC_MIPS16_GPREL
2234 MIPS16 GP relative reloc.
2239 High 16 bits of 32-bit value; simple reloc.
2244 High 16 bits of 32-bit value but the low 16 bits will be sign
2245 extended and added to form the final result. If the low 16
2246 bits form a negative number, we need to add one to the high value
2247 to compensate for the borrow when the low bits are added.
2255 BFD_RELOC_HI16_PCREL
2257 High 16 bits of 32-bit pc-relative value
2259 BFD_RELOC_HI16_S_PCREL
2261 High 16 bits of 32-bit pc-relative value, adjusted
2263 BFD_RELOC_LO16_PCREL
2265 Low 16 bits of pc-relative value
2268 BFD_RELOC_MIPS16_GOT16
2270 BFD_RELOC_MIPS16_CALL16
2272 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2273 16-bit immediate fields
2275 BFD_RELOC_MIPS16_HI16
2277 MIPS16 high 16 bits of 32-bit value.
2279 BFD_RELOC_MIPS16_HI16_S
2281 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2282 extended and added to form the final result. If the low 16
2283 bits form a negative number, we need to add one to the high value
2284 to compensate for the borrow when the low bits are added.
2286 BFD_RELOC_MIPS16_LO16
2291 BFD_RELOC_MIPS16_TLS_GD
2293 BFD_RELOC_MIPS16_TLS_LDM
2295 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2297 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2299 BFD_RELOC_MIPS16_TLS_GOTTPREL
2301 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2303 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2305 MIPS16 TLS relocations
2308 BFD_RELOC_MIPS_LITERAL
2310 BFD_RELOC_MICROMIPS_LITERAL
2312 Relocation against a MIPS literal section.
2315 BFD_RELOC_MICROMIPS_7_PCREL_S1
2317 BFD_RELOC_MICROMIPS_10_PCREL_S1
2319 BFD_RELOC_MICROMIPS_16_PCREL_S1
2321 microMIPS PC-relative relocations.
2324 BFD_RELOC_MIPS16_16_PCREL_S1
2326 MIPS16 PC-relative relocation.
2329 BFD_RELOC_MIPS_21_PCREL_S2
2331 BFD_RELOC_MIPS_26_PCREL_S2
2333 BFD_RELOC_MIPS_18_PCREL_S3
2335 BFD_RELOC_MIPS_19_PCREL_S2
2337 MIPS PC-relative relocations.
2340 BFD_RELOC_MICROMIPS_GPREL16
2342 BFD_RELOC_MICROMIPS_HI16
2344 BFD_RELOC_MICROMIPS_HI16_S
2346 BFD_RELOC_MICROMIPS_LO16
2348 microMIPS versions of generic BFD relocs.
2351 BFD_RELOC_MIPS_GOT16
2353 BFD_RELOC_MICROMIPS_GOT16
2355 BFD_RELOC_MIPS_CALL16
2357 BFD_RELOC_MICROMIPS_CALL16
2359 BFD_RELOC_MIPS_GOT_HI16
2361 BFD_RELOC_MICROMIPS_GOT_HI16
2363 BFD_RELOC_MIPS_GOT_LO16
2365 BFD_RELOC_MICROMIPS_GOT_LO16
2367 BFD_RELOC_MIPS_CALL_HI16
2369 BFD_RELOC_MICROMIPS_CALL_HI16
2371 BFD_RELOC_MIPS_CALL_LO16
2373 BFD_RELOC_MICROMIPS_CALL_LO16
2377 BFD_RELOC_MICROMIPS_SUB
2379 BFD_RELOC_MIPS_GOT_PAGE
2381 BFD_RELOC_MICROMIPS_GOT_PAGE
2383 BFD_RELOC_MIPS_GOT_OFST
2385 BFD_RELOC_MICROMIPS_GOT_OFST
2387 BFD_RELOC_MIPS_GOT_DISP
2389 BFD_RELOC_MICROMIPS_GOT_DISP
2391 BFD_RELOC_MIPS_SHIFT5
2393 BFD_RELOC_MIPS_SHIFT6
2395 BFD_RELOC_MIPS_INSERT_A
2397 BFD_RELOC_MIPS_INSERT_B
2399 BFD_RELOC_MIPS_DELETE
2401 BFD_RELOC_MIPS_HIGHEST
2403 BFD_RELOC_MICROMIPS_HIGHEST
2405 BFD_RELOC_MIPS_HIGHER
2407 BFD_RELOC_MICROMIPS_HIGHER
2409 BFD_RELOC_MIPS_SCN_DISP
2411 BFD_RELOC_MICROMIPS_SCN_DISP
2413 BFD_RELOC_MIPS_REL16
2415 BFD_RELOC_MIPS_RELGOT
2419 BFD_RELOC_MICROMIPS_JALR
2421 BFD_RELOC_MIPS_TLS_DTPMOD32
2423 BFD_RELOC_MIPS_TLS_DTPREL32
2425 BFD_RELOC_MIPS_TLS_DTPMOD64
2427 BFD_RELOC_MIPS_TLS_DTPREL64
2429 BFD_RELOC_MIPS_TLS_GD
2431 BFD_RELOC_MICROMIPS_TLS_GD
2433 BFD_RELOC_MIPS_TLS_LDM
2435 BFD_RELOC_MICROMIPS_TLS_LDM
2437 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2439 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2441 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2443 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2445 BFD_RELOC_MIPS_TLS_GOTTPREL
2447 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2449 BFD_RELOC_MIPS_TLS_TPREL32
2451 BFD_RELOC_MIPS_TLS_TPREL64
2453 BFD_RELOC_MIPS_TLS_TPREL_HI16
2455 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2457 BFD_RELOC_MIPS_TLS_TPREL_LO16
2459 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2463 MIPS ELF relocations.
2469 BFD_RELOC_MIPS_JUMP_SLOT
2471 MIPS ELF relocations (VxWorks and PLT extensions).
2475 BFD_RELOC_MOXIE_10_PCREL
2477 Moxie ELF relocations.
2489 FT32 ELF relocations.
2493 BFD_RELOC_FRV_LABEL16
2495 BFD_RELOC_FRV_LABEL24
2501 BFD_RELOC_FRV_GPREL12
2503 BFD_RELOC_FRV_GPRELU12
2505 BFD_RELOC_FRV_GPREL32
2507 BFD_RELOC_FRV_GPRELHI
2509 BFD_RELOC_FRV_GPRELLO
2517 BFD_RELOC_FRV_FUNCDESC
2519 BFD_RELOC_FRV_FUNCDESC_GOT12
2521 BFD_RELOC_FRV_FUNCDESC_GOTHI
2523 BFD_RELOC_FRV_FUNCDESC_GOTLO
2525 BFD_RELOC_FRV_FUNCDESC_VALUE
2527 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2529 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2531 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2533 BFD_RELOC_FRV_GOTOFF12
2535 BFD_RELOC_FRV_GOTOFFHI
2537 BFD_RELOC_FRV_GOTOFFLO
2539 BFD_RELOC_FRV_GETTLSOFF
2541 BFD_RELOC_FRV_TLSDESC_VALUE
2543 BFD_RELOC_FRV_GOTTLSDESC12
2545 BFD_RELOC_FRV_GOTTLSDESCHI
2547 BFD_RELOC_FRV_GOTTLSDESCLO
2549 BFD_RELOC_FRV_TLSMOFF12
2551 BFD_RELOC_FRV_TLSMOFFHI
2553 BFD_RELOC_FRV_TLSMOFFLO
2555 BFD_RELOC_FRV_GOTTLSOFF12
2557 BFD_RELOC_FRV_GOTTLSOFFHI
2559 BFD_RELOC_FRV_GOTTLSOFFLO
2561 BFD_RELOC_FRV_TLSOFF
2563 BFD_RELOC_FRV_TLSDESC_RELAX
2565 BFD_RELOC_FRV_GETTLSOFF_RELAX
2567 BFD_RELOC_FRV_TLSOFF_RELAX
2569 BFD_RELOC_FRV_TLSMOFF
2571 Fujitsu Frv Relocations.
2575 BFD_RELOC_MN10300_GOTOFF24
2577 This is a 24bit GOT-relative reloc for the mn10300.
2579 BFD_RELOC_MN10300_GOT32
2581 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2584 BFD_RELOC_MN10300_GOT24
2586 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2589 BFD_RELOC_MN10300_GOT16
2591 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2594 BFD_RELOC_MN10300_COPY
2596 Copy symbol at runtime.
2598 BFD_RELOC_MN10300_GLOB_DAT
2602 BFD_RELOC_MN10300_JMP_SLOT
2606 BFD_RELOC_MN10300_RELATIVE
2608 Adjust by program base.
2610 BFD_RELOC_MN10300_SYM_DIFF
2612 Together with another reloc targeted at the same location,
2613 allows for a value that is the difference of two symbols
2614 in the same section.
2616 BFD_RELOC_MN10300_ALIGN
2618 The addend of this reloc is an alignment power that must
2619 be honoured at the offset's location, regardless of linker
2622 BFD_RELOC_MN10300_TLS_GD
2624 BFD_RELOC_MN10300_TLS_LD
2626 BFD_RELOC_MN10300_TLS_LDO
2628 BFD_RELOC_MN10300_TLS_GOTIE
2630 BFD_RELOC_MN10300_TLS_IE
2632 BFD_RELOC_MN10300_TLS_LE
2634 BFD_RELOC_MN10300_TLS_DTPMOD
2636 BFD_RELOC_MN10300_TLS_DTPOFF
2638 BFD_RELOC_MN10300_TLS_TPOFF
2640 Various TLS-related relocations.
2642 BFD_RELOC_MN10300_32_PCREL
2644 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2647 BFD_RELOC_MN10300_16_PCREL
2649 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2660 BFD_RELOC_386_GLOB_DAT
2662 BFD_RELOC_386_JUMP_SLOT
2664 BFD_RELOC_386_RELATIVE
2666 BFD_RELOC_386_GOTOFF
2670 BFD_RELOC_386_TLS_TPOFF
2672 BFD_RELOC_386_TLS_IE
2674 BFD_RELOC_386_TLS_GOTIE
2676 BFD_RELOC_386_TLS_LE
2678 BFD_RELOC_386_TLS_GD
2680 BFD_RELOC_386_TLS_LDM
2682 BFD_RELOC_386_TLS_LDO_32
2684 BFD_RELOC_386_TLS_IE_32
2686 BFD_RELOC_386_TLS_LE_32
2688 BFD_RELOC_386_TLS_DTPMOD32
2690 BFD_RELOC_386_TLS_DTPOFF32
2692 BFD_RELOC_386_TLS_TPOFF32
2694 BFD_RELOC_386_TLS_GOTDESC
2696 BFD_RELOC_386_TLS_DESC_CALL
2698 BFD_RELOC_386_TLS_DESC
2700 BFD_RELOC_386_IRELATIVE
2702 BFD_RELOC_386_GOT32X
2704 i386/elf relocations
2707 BFD_RELOC_X86_64_GOT32
2709 BFD_RELOC_X86_64_PLT32
2711 BFD_RELOC_X86_64_COPY
2713 BFD_RELOC_X86_64_GLOB_DAT
2715 BFD_RELOC_X86_64_JUMP_SLOT
2717 BFD_RELOC_X86_64_RELATIVE
2719 BFD_RELOC_X86_64_GOTPCREL
2721 BFD_RELOC_X86_64_32S
2723 BFD_RELOC_X86_64_DTPMOD64
2725 BFD_RELOC_X86_64_DTPOFF64
2727 BFD_RELOC_X86_64_TPOFF64
2729 BFD_RELOC_X86_64_TLSGD
2731 BFD_RELOC_X86_64_TLSLD
2733 BFD_RELOC_X86_64_DTPOFF32
2735 BFD_RELOC_X86_64_GOTTPOFF
2737 BFD_RELOC_X86_64_TPOFF32
2739 BFD_RELOC_X86_64_GOTOFF64
2741 BFD_RELOC_X86_64_GOTPC32
2743 BFD_RELOC_X86_64_GOT64
2745 BFD_RELOC_X86_64_GOTPCREL64
2747 BFD_RELOC_X86_64_GOTPC64
2749 BFD_RELOC_X86_64_GOTPLT64
2751 BFD_RELOC_X86_64_PLTOFF64
2753 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2755 BFD_RELOC_X86_64_TLSDESC_CALL
2757 BFD_RELOC_X86_64_TLSDESC
2759 BFD_RELOC_X86_64_IRELATIVE
2761 BFD_RELOC_X86_64_PC32_BND
2763 BFD_RELOC_X86_64_PLT32_BND
2765 BFD_RELOC_X86_64_GOTPCRELX
2767 BFD_RELOC_X86_64_REX_GOTPCRELX
2769 x86-64/elf relocations
2772 BFD_RELOC_NS32K_IMM_8
2774 BFD_RELOC_NS32K_IMM_16
2776 BFD_RELOC_NS32K_IMM_32
2778 BFD_RELOC_NS32K_IMM_8_PCREL
2780 BFD_RELOC_NS32K_IMM_16_PCREL
2782 BFD_RELOC_NS32K_IMM_32_PCREL
2784 BFD_RELOC_NS32K_DISP_8
2786 BFD_RELOC_NS32K_DISP_16
2788 BFD_RELOC_NS32K_DISP_32
2790 BFD_RELOC_NS32K_DISP_8_PCREL
2792 BFD_RELOC_NS32K_DISP_16_PCREL
2794 BFD_RELOC_NS32K_DISP_32_PCREL
2799 BFD_RELOC_PDP11_DISP_8_PCREL
2801 BFD_RELOC_PDP11_DISP_6_PCREL
2806 BFD_RELOC_PJ_CODE_HI16
2808 BFD_RELOC_PJ_CODE_LO16
2810 BFD_RELOC_PJ_CODE_DIR16
2812 BFD_RELOC_PJ_CODE_DIR32
2814 BFD_RELOC_PJ_CODE_REL16
2816 BFD_RELOC_PJ_CODE_REL32
2818 Picojava relocs. Not all of these appear in object files.
2829 BFD_RELOC_PPC_B16_BRTAKEN
2831 BFD_RELOC_PPC_B16_BRNTAKEN
2835 BFD_RELOC_PPC_BA16_BRTAKEN
2837 BFD_RELOC_PPC_BA16_BRNTAKEN
2841 BFD_RELOC_PPC_GLOB_DAT
2843 BFD_RELOC_PPC_JMP_SLOT
2845 BFD_RELOC_PPC_RELATIVE
2847 BFD_RELOC_PPC_LOCAL24PC
2849 BFD_RELOC_PPC_EMB_NADDR32
2851 BFD_RELOC_PPC_EMB_NADDR16
2853 BFD_RELOC_PPC_EMB_NADDR16_LO
2855 BFD_RELOC_PPC_EMB_NADDR16_HI
2857 BFD_RELOC_PPC_EMB_NADDR16_HA
2859 BFD_RELOC_PPC_EMB_SDAI16
2861 BFD_RELOC_PPC_EMB_SDA2I16
2863 BFD_RELOC_PPC_EMB_SDA2REL
2865 BFD_RELOC_PPC_EMB_SDA21
2867 BFD_RELOC_PPC_EMB_MRKREF
2869 BFD_RELOC_PPC_EMB_RELSEC16
2871 BFD_RELOC_PPC_EMB_RELST_LO
2873 BFD_RELOC_PPC_EMB_RELST_HI
2875 BFD_RELOC_PPC_EMB_RELST_HA
2877 BFD_RELOC_PPC_EMB_BIT_FLD
2879 BFD_RELOC_PPC_EMB_RELSDA
2881 BFD_RELOC_PPC_VLE_REL8
2883 BFD_RELOC_PPC_VLE_REL15
2885 BFD_RELOC_PPC_VLE_REL24
2887 BFD_RELOC_PPC_VLE_LO16A
2889 BFD_RELOC_PPC_VLE_LO16D
2891 BFD_RELOC_PPC_VLE_HI16A
2893 BFD_RELOC_PPC_VLE_HI16D
2895 BFD_RELOC_PPC_VLE_HA16A
2897 BFD_RELOC_PPC_VLE_HA16D
2899 BFD_RELOC_PPC_VLE_SDA21
2901 BFD_RELOC_PPC_VLE_SDA21_LO
2903 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2905 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2907 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2909 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2911 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2913 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2915 BFD_RELOC_PPC_16DX_HA
2917 BFD_RELOC_PPC_REL16DX_HA
2919 BFD_RELOC_PPC64_HIGHER
2921 BFD_RELOC_PPC64_HIGHER_S
2923 BFD_RELOC_PPC64_HIGHEST
2925 BFD_RELOC_PPC64_HIGHEST_S
2927 BFD_RELOC_PPC64_TOC16_LO
2929 BFD_RELOC_PPC64_TOC16_HI
2931 BFD_RELOC_PPC64_TOC16_HA
2935 BFD_RELOC_PPC64_PLTGOT16
2937 BFD_RELOC_PPC64_PLTGOT16_LO
2939 BFD_RELOC_PPC64_PLTGOT16_HI
2941 BFD_RELOC_PPC64_PLTGOT16_HA
2943 BFD_RELOC_PPC64_ADDR16_DS
2945 BFD_RELOC_PPC64_ADDR16_LO_DS
2947 BFD_RELOC_PPC64_GOT16_DS
2949 BFD_RELOC_PPC64_GOT16_LO_DS
2951 BFD_RELOC_PPC64_PLT16_LO_DS
2953 BFD_RELOC_PPC64_SECTOFF_DS
2955 BFD_RELOC_PPC64_SECTOFF_LO_DS
2957 BFD_RELOC_PPC64_TOC16_DS
2959 BFD_RELOC_PPC64_TOC16_LO_DS
2961 BFD_RELOC_PPC64_PLTGOT16_DS
2963 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2965 BFD_RELOC_PPC64_ADDR16_HIGH
2967 BFD_RELOC_PPC64_ADDR16_HIGHA
2969 BFD_RELOC_PPC64_ADDR64_LOCAL
2971 BFD_RELOC_PPC64_ENTRY
2973 Power(rs6000) and PowerPC relocations.
2982 BFD_RELOC_PPC_DTPMOD
2984 BFD_RELOC_PPC_TPREL16
2986 BFD_RELOC_PPC_TPREL16_LO
2988 BFD_RELOC_PPC_TPREL16_HI
2990 BFD_RELOC_PPC_TPREL16_HA
2994 BFD_RELOC_PPC_DTPREL16
2996 BFD_RELOC_PPC_DTPREL16_LO
2998 BFD_RELOC_PPC_DTPREL16_HI
3000 BFD_RELOC_PPC_DTPREL16_HA
3002 BFD_RELOC_PPC_DTPREL
3004 BFD_RELOC_PPC_GOT_TLSGD16
3006 BFD_RELOC_PPC_GOT_TLSGD16_LO
3008 BFD_RELOC_PPC_GOT_TLSGD16_HI
3010 BFD_RELOC_PPC_GOT_TLSGD16_HA
3012 BFD_RELOC_PPC_GOT_TLSLD16
3014 BFD_RELOC_PPC_GOT_TLSLD16_LO
3016 BFD_RELOC_PPC_GOT_TLSLD16_HI
3018 BFD_RELOC_PPC_GOT_TLSLD16_HA
3020 BFD_RELOC_PPC_GOT_TPREL16
3022 BFD_RELOC_PPC_GOT_TPREL16_LO
3024 BFD_RELOC_PPC_GOT_TPREL16_HI
3026 BFD_RELOC_PPC_GOT_TPREL16_HA
3028 BFD_RELOC_PPC_GOT_DTPREL16
3030 BFD_RELOC_PPC_GOT_DTPREL16_LO
3032 BFD_RELOC_PPC_GOT_DTPREL16_HI
3034 BFD_RELOC_PPC_GOT_DTPREL16_HA
3036 BFD_RELOC_PPC64_TPREL16_DS
3038 BFD_RELOC_PPC64_TPREL16_LO_DS
3040 BFD_RELOC_PPC64_TPREL16_HIGHER
3042 BFD_RELOC_PPC64_TPREL16_HIGHERA
3044 BFD_RELOC_PPC64_TPREL16_HIGHEST
3046 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3048 BFD_RELOC_PPC64_DTPREL16_DS
3050 BFD_RELOC_PPC64_DTPREL16_LO_DS
3052 BFD_RELOC_PPC64_DTPREL16_HIGHER
3054 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3056 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3058 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3060 BFD_RELOC_PPC64_TPREL16_HIGH
3062 BFD_RELOC_PPC64_TPREL16_HIGHA
3064 BFD_RELOC_PPC64_DTPREL16_HIGH
3066 BFD_RELOC_PPC64_DTPREL16_HIGHA
3068 PowerPC and PowerPC64 thread-local storage relocations.
3073 IBM 370/390 relocations
3078 The type of reloc used to build a constructor table - at the moment
3079 probably a 32 bit wide absolute relocation, but the target can choose.
3080 It generally does map to one of the other relocation types.
3083 BFD_RELOC_ARM_PCREL_BRANCH
3085 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3086 not stored in the instruction.
3088 BFD_RELOC_ARM_PCREL_BLX
3090 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3091 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3092 field in the instruction.
3094 BFD_RELOC_THUMB_PCREL_BLX
3096 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3097 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3098 field in the instruction.
3100 BFD_RELOC_ARM_PCREL_CALL
3102 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3104 BFD_RELOC_ARM_PCREL_JUMP
3106 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3109 BFD_RELOC_THUMB_PCREL_BRANCH7
3111 BFD_RELOC_THUMB_PCREL_BRANCH9
3113 BFD_RELOC_THUMB_PCREL_BRANCH12
3115 BFD_RELOC_THUMB_PCREL_BRANCH20
3117 BFD_RELOC_THUMB_PCREL_BRANCH23
3119 BFD_RELOC_THUMB_PCREL_BRANCH25
3121 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3122 The lowest bit must be zero and is not stored in the instruction.
3123 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3124 "nn" one smaller in all cases. Note further that BRANCH23
3125 corresponds to R_ARM_THM_CALL.
3128 BFD_RELOC_ARM_OFFSET_IMM
3130 12-bit immediate offset, used in ARM-format ldr and str instructions.
3133 BFD_RELOC_ARM_THUMB_OFFSET
3135 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3138 BFD_RELOC_ARM_TARGET1
3140 Pc-relative or absolute relocation depending on target. Used for
3141 entries in .init_array sections.
3143 BFD_RELOC_ARM_ROSEGREL32
3145 Read-only segment base relative address.
3147 BFD_RELOC_ARM_SBREL32
3149 Data segment base relative address.
3151 BFD_RELOC_ARM_TARGET2
3153 This reloc is used for references to RTTI data from exception handling
3154 tables. The actual definition depends on the target. It may be a
3155 pc-relative or some form of GOT-indirect relocation.
3157 BFD_RELOC_ARM_PREL31
3159 31-bit PC relative address.
3165 BFD_RELOC_ARM_MOVW_PCREL
3167 BFD_RELOC_ARM_MOVT_PCREL
3169 BFD_RELOC_ARM_THUMB_MOVW
3171 BFD_RELOC_ARM_THUMB_MOVT
3173 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3175 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3177 Low and High halfword relocations for MOVW and MOVT instructions.
3180 BFD_RELOC_ARM_JUMP_SLOT
3182 BFD_RELOC_ARM_GLOB_DAT
3188 BFD_RELOC_ARM_RELATIVE
3190 BFD_RELOC_ARM_GOTOFF
3194 BFD_RELOC_ARM_GOT_PREL
3196 Relocations for setting up GOTs and PLTs for shared libraries.
3199 BFD_RELOC_ARM_TLS_GD32
3201 BFD_RELOC_ARM_TLS_LDO32
3203 BFD_RELOC_ARM_TLS_LDM32
3205 BFD_RELOC_ARM_TLS_DTPOFF32
3207 BFD_RELOC_ARM_TLS_DTPMOD32
3209 BFD_RELOC_ARM_TLS_TPOFF32
3211 BFD_RELOC_ARM_TLS_IE32
3213 BFD_RELOC_ARM_TLS_LE32
3215 BFD_RELOC_ARM_TLS_GOTDESC
3217 BFD_RELOC_ARM_TLS_CALL
3219 BFD_RELOC_ARM_THM_TLS_CALL
3221 BFD_RELOC_ARM_TLS_DESCSEQ
3223 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3225 BFD_RELOC_ARM_TLS_DESC
3227 ARM thread-local storage relocations.
3230 BFD_RELOC_ARM_ALU_PC_G0_NC
3232 BFD_RELOC_ARM_ALU_PC_G0
3234 BFD_RELOC_ARM_ALU_PC_G1_NC
3236 BFD_RELOC_ARM_ALU_PC_G1
3238 BFD_RELOC_ARM_ALU_PC_G2
3240 BFD_RELOC_ARM_LDR_PC_G0
3242 BFD_RELOC_ARM_LDR_PC_G1
3244 BFD_RELOC_ARM_LDR_PC_G2
3246 BFD_RELOC_ARM_LDRS_PC_G0
3248 BFD_RELOC_ARM_LDRS_PC_G1
3250 BFD_RELOC_ARM_LDRS_PC_G2
3252 BFD_RELOC_ARM_LDC_PC_G0
3254 BFD_RELOC_ARM_LDC_PC_G1
3256 BFD_RELOC_ARM_LDC_PC_G2
3258 BFD_RELOC_ARM_ALU_SB_G0_NC
3260 BFD_RELOC_ARM_ALU_SB_G0
3262 BFD_RELOC_ARM_ALU_SB_G1_NC
3264 BFD_RELOC_ARM_ALU_SB_G1
3266 BFD_RELOC_ARM_ALU_SB_G2
3268 BFD_RELOC_ARM_LDR_SB_G0
3270 BFD_RELOC_ARM_LDR_SB_G1
3272 BFD_RELOC_ARM_LDR_SB_G2
3274 BFD_RELOC_ARM_LDRS_SB_G0
3276 BFD_RELOC_ARM_LDRS_SB_G1
3278 BFD_RELOC_ARM_LDRS_SB_G2
3280 BFD_RELOC_ARM_LDC_SB_G0
3282 BFD_RELOC_ARM_LDC_SB_G1
3284 BFD_RELOC_ARM_LDC_SB_G2
3286 ARM group relocations.
3291 Annotation of BX instructions.
3294 BFD_RELOC_ARM_IRELATIVE
3296 ARM support for STT_GNU_IFUNC.
3299 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3301 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3303 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3305 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3307 Thumb1 relocations to support execute-only code.
3310 BFD_RELOC_ARM_IMMEDIATE
3312 BFD_RELOC_ARM_ADRL_IMMEDIATE
3314 BFD_RELOC_ARM_T32_IMMEDIATE
3316 BFD_RELOC_ARM_T32_ADD_IMM
3318 BFD_RELOC_ARM_T32_IMM12
3320 BFD_RELOC_ARM_T32_ADD_PC12
3322 BFD_RELOC_ARM_SHIFT_IMM
3332 BFD_RELOC_ARM_CP_OFF_IMM
3334 BFD_RELOC_ARM_CP_OFF_IMM_S2
3336 BFD_RELOC_ARM_T32_CP_OFF_IMM
3338 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3340 BFD_RELOC_ARM_ADR_IMM
3342 BFD_RELOC_ARM_LDR_IMM
3344 BFD_RELOC_ARM_LITERAL
3346 BFD_RELOC_ARM_IN_POOL
3348 BFD_RELOC_ARM_OFFSET_IMM8
3350 BFD_RELOC_ARM_T32_OFFSET_U8
3352 BFD_RELOC_ARM_T32_OFFSET_IMM
3354 BFD_RELOC_ARM_HWLITERAL
3356 BFD_RELOC_ARM_THUMB_ADD
3358 BFD_RELOC_ARM_THUMB_IMM
3360 BFD_RELOC_ARM_THUMB_SHIFT
3362 These relocs are only used within the ARM assembler. They are not
3363 (at present) written to any object files.
3366 BFD_RELOC_SH_PCDISP8BY2
3368 BFD_RELOC_SH_PCDISP12BY2
3376 BFD_RELOC_SH_DISP12BY2
3378 BFD_RELOC_SH_DISP12BY4
3380 BFD_RELOC_SH_DISP12BY8
3384 BFD_RELOC_SH_DISP20BY8
3388 BFD_RELOC_SH_IMM4BY2
3390 BFD_RELOC_SH_IMM4BY4
3394 BFD_RELOC_SH_IMM8BY2
3396 BFD_RELOC_SH_IMM8BY4
3398 BFD_RELOC_SH_PCRELIMM8BY2
3400 BFD_RELOC_SH_PCRELIMM8BY4
3402 BFD_RELOC_SH_SWITCH16
3404 BFD_RELOC_SH_SWITCH32
3418 BFD_RELOC_SH_LOOP_START
3420 BFD_RELOC_SH_LOOP_END
3424 BFD_RELOC_SH_GLOB_DAT
3426 BFD_RELOC_SH_JMP_SLOT
3428 BFD_RELOC_SH_RELATIVE
3432 BFD_RELOC_SH_GOT_LOW16
3434 BFD_RELOC_SH_GOT_MEDLOW16
3436 BFD_RELOC_SH_GOT_MEDHI16
3438 BFD_RELOC_SH_GOT_HI16
3440 BFD_RELOC_SH_GOTPLT_LOW16
3442 BFD_RELOC_SH_GOTPLT_MEDLOW16
3444 BFD_RELOC_SH_GOTPLT_MEDHI16
3446 BFD_RELOC_SH_GOTPLT_HI16
3448 BFD_RELOC_SH_PLT_LOW16
3450 BFD_RELOC_SH_PLT_MEDLOW16
3452 BFD_RELOC_SH_PLT_MEDHI16
3454 BFD_RELOC_SH_PLT_HI16
3456 BFD_RELOC_SH_GOTOFF_LOW16
3458 BFD_RELOC_SH_GOTOFF_MEDLOW16
3460 BFD_RELOC_SH_GOTOFF_MEDHI16
3462 BFD_RELOC_SH_GOTOFF_HI16
3464 BFD_RELOC_SH_GOTPC_LOW16
3466 BFD_RELOC_SH_GOTPC_MEDLOW16
3468 BFD_RELOC_SH_GOTPC_MEDHI16
3470 BFD_RELOC_SH_GOTPC_HI16
3474 BFD_RELOC_SH_GLOB_DAT64
3476 BFD_RELOC_SH_JMP_SLOT64
3478 BFD_RELOC_SH_RELATIVE64
3480 BFD_RELOC_SH_GOT10BY4
3482 BFD_RELOC_SH_GOT10BY8
3484 BFD_RELOC_SH_GOTPLT10BY4
3486 BFD_RELOC_SH_GOTPLT10BY8
3488 BFD_RELOC_SH_GOTPLT32
3490 BFD_RELOC_SH_SHMEDIA_CODE
3496 BFD_RELOC_SH_IMMS6BY32
3502 BFD_RELOC_SH_IMMS10BY2
3504 BFD_RELOC_SH_IMMS10BY4
3506 BFD_RELOC_SH_IMMS10BY8
3512 BFD_RELOC_SH_IMM_LOW16
3514 BFD_RELOC_SH_IMM_LOW16_PCREL
3516 BFD_RELOC_SH_IMM_MEDLOW16
3518 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3520 BFD_RELOC_SH_IMM_MEDHI16
3522 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3524 BFD_RELOC_SH_IMM_HI16
3526 BFD_RELOC_SH_IMM_HI16_PCREL
3530 BFD_RELOC_SH_TLS_GD_32
3532 BFD_RELOC_SH_TLS_LD_32
3534 BFD_RELOC_SH_TLS_LDO_32
3536 BFD_RELOC_SH_TLS_IE_32
3538 BFD_RELOC_SH_TLS_LE_32
3540 BFD_RELOC_SH_TLS_DTPMOD32
3542 BFD_RELOC_SH_TLS_DTPOFF32
3544 BFD_RELOC_SH_TLS_TPOFF32
3548 BFD_RELOC_SH_GOTOFF20
3550 BFD_RELOC_SH_GOTFUNCDESC
3552 BFD_RELOC_SH_GOTFUNCDESC20
3554 BFD_RELOC_SH_GOTOFFFUNCDESC
3556 BFD_RELOC_SH_GOTOFFFUNCDESC20
3558 BFD_RELOC_SH_FUNCDESC
3560 Renesas / SuperH SH relocs. Not all of these appear in object files.
3583 BFD_RELOC_ARC_SECTOFF
3585 BFD_RELOC_ARC_S21H_PCREL
3587 BFD_RELOC_ARC_S21W_PCREL
3589 BFD_RELOC_ARC_S25H_PCREL
3591 BFD_RELOC_ARC_S25W_PCREL
3595 BFD_RELOC_ARC_SDA_LDST
3597 BFD_RELOC_ARC_SDA_LDST1
3599 BFD_RELOC_ARC_SDA_LDST2
3601 BFD_RELOC_ARC_SDA16_LD
3603 BFD_RELOC_ARC_SDA16_LD1
3605 BFD_RELOC_ARC_SDA16_LD2
3607 BFD_RELOC_ARC_S13_PCREL
3613 BFD_RELOC_ARC_32_ME_S
3615 BFD_RELOC_ARC_N32_ME
3617 BFD_RELOC_ARC_SECTOFF_ME
3619 BFD_RELOC_ARC_SDA32_ME
3623 BFD_RELOC_AC_SECTOFF_U8
3625 BFD_RELOC_AC_SECTOFF_U8_1
3627 BFD_RELOC_AC_SECTOFF_U8_2
3629 BFD_RELOC_AC_SECTOFF_S9
3631 BFD_RELOC_AC_SECTOFF_S9_1
3633 BFD_RELOC_AC_SECTOFF_S9_2
3635 BFD_RELOC_ARC_SECTOFF_ME_1
3637 BFD_RELOC_ARC_SECTOFF_ME_2
3639 BFD_RELOC_ARC_SECTOFF_1
3641 BFD_RELOC_ARC_SECTOFF_2
3643 BFD_RELOC_ARC_SDA_12
3645 BFD_RELOC_ARC_SDA16_ST2
3647 BFD_RELOC_ARC_32_PCREL
3653 BFD_RELOC_ARC_GOTPC32
3659 BFD_RELOC_ARC_GLOB_DAT
3661 BFD_RELOC_ARC_JMP_SLOT
3663 BFD_RELOC_ARC_RELATIVE
3665 BFD_RELOC_ARC_GOTOFF
3669 BFD_RELOC_ARC_S21W_PCREL_PLT
3671 BFD_RELOC_ARC_S25H_PCREL_PLT
3673 BFD_RELOC_ARC_TLS_DTPMOD
3675 BFD_RELOC_ARC_TLS_TPOFF
3677 BFD_RELOC_ARC_TLS_GD_GOT
3679 BFD_RELOC_ARC_TLS_GD_LD
3681 BFD_RELOC_ARC_TLS_GD_CALL
3683 BFD_RELOC_ARC_TLS_IE_GOT
3685 BFD_RELOC_ARC_TLS_DTPOFF
3687 BFD_RELOC_ARC_TLS_DTPOFF_S9
3689 BFD_RELOC_ARC_TLS_LE_S9
3691 BFD_RELOC_ARC_TLS_LE_32
3693 BFD_RELOC_ARC_S25W_PCREL_PLT
3695 BFD_RELOC_ARC_S21H_PCREL_PLT
3697 BFD_RELOC_ARC_NPS_CMEM16
3702 BFD_RELOC_BFIN_16_IMM
3704 ADI Blackfin 16 bit immediate absolute reloc.
3706 BFD_RELOC_BFIN_16_HIGH
3708 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3710 BFD_RELOC_BFIN_4_PCREL
3712 ADI Blackfin 'a' part of LSETUP.
3714 BFD_RELOC_BFIN_5_PCREL
3718 BFD_RELOC_BFIN_16_LOW
3720 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3722 BFD_RELOC_BFIN_10_PCREL
3726 BFD_RELOC_BFIN_11_PCREL
3728 ADI Blackfin 'b' part of LSETUP.
3730 BFD_RELOC_BFIN_12_PCREL_JUMP
3734 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3736 ADI Blackfin Short jump, pcrel.
3738 BFD_RELOC_BFIN_24_PCREL_CALL_X
3740 ADI Blackfin Call.x not implemented.
3742 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3744 ADI Blackfin Long Jump pcrel.
3746 BFD_RELOC_BFIN_GOT17M4
3748 BFD_RELOC_BFIN_GOTHI
3750 BFD_RELOC_BFIN_GOTLO
3752 BFD_RELOC_BFIN_FUNCDESC
3754 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3756 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3758 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3760 BFD_RELOC_BFIN_FUNCDESC_VALUE
3762 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3764 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3766 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3768 BFD_RELOC_BFIN_GOTOFF17M4
3770 BFD_RELOC_BFIN_GOTOFFHI
3772 BFD_RELOC_BFIN_GOTOFFLO
3774 ADI Blackfin FD-PIC relocations.
3778 ADI Blackfin GOT relocation.
3780 BFD_RELOC_BFIN_PLTPC
3782 ADI Blackfin PLTPC relocation.
3784 BFD_ARELOC_BFIN_PUSH
3786 ADI Blackfin arithmetic relocation.
3788 BFD_ARELOC_BFIN_CONST
3790 ADI Blackfin arithmetic relocation.
3794 ADI Blackfin arithmetic relocation.
3798 ADI Blackfin arithmetic relocation.
3800 BFD_ARELOC_BFIN_MULT
3802 ADI Blackfin arithmetic relocation.
3806 ADI Blackfin arithmetic relocation.
3810 ADI Blackfin arithmetic relocation.
3812 BFD_ARELOC_BFIN_LSHIFT
3814 ADI Blackfin arithmetic relocation.
3816 BFD_ARELOC_BFIN_RSHIFT
3818 ADI Blackfin arithmetic relocation.
3822 ADI Blackfin arithmetic relocation.
3826 ADI Blackfin arithmetic relocation.
3830 ADI Blackfin arithmetic relocation.
3832 BFD_ARELOC_BFIN_LAND
3834 ADI Blackfin arithmetic relocation.
3838 ADI Blackfin arithmetic relocation.
3842 ADI Blackfin arithmetic relocation.
3846 ADI Blackfin arithmetic relocation.
3848 BFD_ARELOC_BFIN_COMP
3850 ADI Blackfin arithmetic relocation.
3852 BFD_ARELOC_BFIN_PAGE
3854 ADI Blackfin arithmetic relocation.
3856 BFD_ARELOC_BFIN_HWPAGE
3858 ADI Blackfin arithmetic relocation.
3860 BFD_ARELOC_BFIN_ADDR
3862 ADI Blackfin arithmetic relocation.
3865 BFD_RELOC_D10V_10_PCREL_R
3867 Mitsubishi D10V relocs.
3868 This is a 10-bit reloc with the right 2 bits
3871 BFD_RELOC_D10V_10_PCREL_L
3873 Mitsubishi D10V relocs.
3874 This is a 10-bit reloc with the right 2 bits
3875 assumed to be 0. This is the same as the previous reloc
3876 except it is in the left container, i.e.,
3877 shifted left 15 bits.
3881 This is an 18-bit reloc with the right 2 bits
3884 BFD_RELOC_D10V_18_PCREL
3886 This is an 18-bit reloc with the right 2 bits
3892 Mitsubishi D30V relocs.
3893 This is a 6-bit absolute reloc.
3895 BFD_RELOC_D30V_9_PCREL
3897 This is a 6-bit pc-relative reloc with
3898 the right 3 bits assumed to be 0.
3900 BFD_RELOC_D30V_9_PCREL_R
3902 This is a 6-bit pc-relative reloc with
3903 the right 3 bits assumed to be 0. Same
3904 as the previous reloc but on the right side
3909 This is a 12-bit absolute reloc with the
3910 right 3 bitsassumed to be 0.
3912 BFD_RELOC_D30V_15_PCREL
3914 This is a 12-bit pc-relative reloc with
3915 the right 3 bits assumed to be 0.
3917 BFD_RELOC_D30V_15_PCREL_R
3919 This is a 12-bit pc-relative reloc with
3920 the right 3 bits assumed to be 0. Same
3921 as the previous reloc but on the right side
3926 This is an 18-bit absolute reloc with
3927 the right 3 bits assumed to be 0.
3929 BFD_RELOC_D30V_21_PCREL
3931 This is an 18-bit pc-relative reloc with
3932 the right 3 bits assumed to be 0.
3934 BFD_RELOC_D30V_21_PCREL_R
3936 This is an 18-bit pc-relative reloc with
3937 the right 3 bits assumed to be 0. Same
3938 as the previous reloc but on the right side
3943 This is a 32-bit absolute reloc.
3945 BFD_RELOC_D30V_32_PCREL
3947 This is a 32-bit pc-relative reloc.
3950 BFD_RELOC_DLX_HI16_S
3965 BFD_RELOC_M32C_RL_JUMP
3967 BFD_RELOC_M32C_RL_1ADDR
3969 BFD_RELOC_M32C_RL_2ADDR
3971 Renesas M16C/M32C Relocations.
3976 Renesas M32R (formerly Mitsubishi M32R) relocs.
3977 This is a 24 bit absolute address.
3979 BFD_RELOC_M32R_10_PCREL
3981 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3983 BFD_RELOC_M32R_18_PCREL
3985 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3987 BFD_RELOC_M32R_26_PCREL
3989 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3991 BFD_RELOC_M32R_HI16_ULO
3993 This is a 16-bit reloc containing the high 16 bits of an address
3994 used when the lower 16 bits are treated as unsigned.
3996 BFD_RELOC_M32R_HI16_SLO
3998 This is a 16-bit reloc containing the high 16 bits of an address
3999 used when the lower 16 bits are treated as signed.
4003 This is a 16-bit reloc containing the lower 16 bits of an address.
4005 BFD_RELOC_M32R_SDA16
4007 This is a 16-bit reloc containing the small data area offset for use in
4008 add3, load, and store instructions.
4010 BFD_RELOC_M32R_GOT24
4012 BFD_RELOC_M32R_26_PLTREL
4016 BFD_RELOC_M32R_GLOB_DAT
4018 BFD_RELOC_M32R_JMP_SLOT
4020 BFD_RELOC_M32R_RELATIVE
4022 BFD_RELOC_M32R_GOTOFF
4024 BFD_RELOC_M32R_GOTOFF_HI_ULO
4026 BFD_RELOC_M32R_GOTOFF_HI_SLO
4028 BFD_RELOC_M32R_GOTOFF_LO
4030 BFD_RELOC_M32R_GOTPC24
4032 BFD_RELOC_M32R_GOT16_HI_ULO
4034 BFD_RELOC_M32R_GOT16_HI_SLO
4036 BFD_RELOC_M32R_GOT16_LO
4038 BFD_RELOC_M32R_GOTPC_HI_ULO
4040 BFD_RELOC_M32R_GOTPC_HI_SLO
4042 BFD_RELOC_M32R_GOTPC_LO
4051 This is a 20 bit absolute address.
4053 BFD_RELOC_NDS32_9_PCREL
4055 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4057 BFD_RELOC_NDS32_WORD_9_PCREL
4059 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4061 BFD_RELOC_NDS32_15_PCREL
4063 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4065 BFD_RELOC_NDS32_17_PCREL
4067 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4069 BFD_RELOC_NDS32_25_PCREL
4071 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4073 BFD_RELOC_NDS32_HI20
4075 This is a 20-bit reloc containing the high 20 bits of an address
4076 used with the lower 12 bits
4078 BFD_RELOC_NDS32_LO12S3
4080 This is a 12-bit reloc containing the lower 12 bits of an address
4081 then shift right by 3. This is used with ldi,sdi...
4083 BFD_RELOC_NDS32_LO12S2
4085 This is a 12-bit reloc containing the lower 12 bits of an address
4086 then shift left by 2. This is used with lwi,swi...
4088 BFD_RELOC_NDS32_LO12S1
4090 This is a 12-bit reloc containing the lower 12 bits of an address
4091 then shift left by 1. This is used with lhi,shi...
4093 BFD_RELOC_NDS32_LO12S0
4095 This is a 12-bit reloc containing the lower 12 bits of an address
4096 then shift left by 0. This is used with lbisbi...
4098 BFD_RELOC_NDS32_LO12S0_ORI
4100 This is a 12-bit reloc containing the lower 12 bits of an address
4101 then shift left by 0. This is only used with branch relaxations
4103 BFD_RELOC_NDS32_SDA15S3
4105 This is a 15-bit reloc containing the small data area 18-bit signed offset
4106 and shift left by 3 for use in ldi, sdi...
4108 BFD_RELOC_NDS32_SDA15S2
4110 This is a 15-bit reloc containing the small data area 17-bit signed offset
4111 and shift left by 2 for use in lwi, swi...
4113 BFD_RELOC_NDS32_SDA15S1
4115 This is a 15-bit reloc containing the small data area 16-bit signed offset
4116 and shift left by 1 for use in lhi, shi...
4118 BFD_RELOC_NDS32_SDA15S0
4120 This is a 15-bit reloc containing the small data area 15-bit signed offset
4121 and shift left by 0 for use in lbi, sbi...
4123 BFD_RELOC_NDS32_SDA16S3
4125 This is a 16-bit reloc containing the small data area 16-bit signed offset
4128 BFD_RELOC_NDS32_SDA17S2
4130 This is a 17-bit reloc containing the small data area 17-bit signed offset
4131 and shift left by 2 for use in lwi.gp, swi.gp...
4133 BFD_RELOC_NDS32_SDA18S1
4135 This is a 18-bit reloc containing the small data area 18-bit signed offset
4136 and shift left by 1 for use in lhi.gp, shi.gp...
4138 BFD_RELOC_NDS32_SDA19S0
4140 This is a 19-bit reloc containing the small data area 19-bit signed offset
4141 and shift left by 0 for use in lbi.gp, sbi.gp...
4143 BFD_RELOC_NDS32_GOT20
4145 BFD_RELOC_NDS32_9_PLTREL
4147 BFD_RELOC_NDS32_25_PLTREL
4149 BFD_RELOC_NDS32_COPY
4151 BFD_RELOC_NDS32_GLOB_DAT
4153 BFD_RELOC_NDS32_JMP_SLOT
4155 BFD_RELOC_NDS32_RELATIVE
4157 BFD_RELOC_NDS32_GOTOFF
4159 BFD_RELOC_NDS32_GOTOFF_HI20
4161 BFD_RELOC_NDS32_GOTOFF_LO12
4163 BFD_RELOC_NDS32_GOTPC20
4165 BFD_RELOC_NDS32_GOT_HI20
4167 BFD_RELOC_NDS32_GOT_LO12
4169 BFD_RELOC_NDS32_GOTPC_HI20
4171 BFD_RELOC_NDS32_GOTPC_LO12
4175 BFD_RELOC_NDS32_INSN16
4177 BFD_RELOC_NDS32_LABEL
4179 BFD_RELOC_NDS32_LONGCALL1
4181 BFD_RELOC_NDS32_LONGCALL2
4183 BFD_RELOC_NDS32_LONGCALL3
4185 BFD_RELOC_NDS32_LONGJUMP1
4187 BFD_RELOC_NDS32_LONGJUMP2
4189 BFD_RELOC_NDS32_LONGJUMP3
4191 BFD_RELOC_NDS32_LOADSTORE
4193 BFD_RELOC_NDS32_9_FIXED
4195 BFD_RELOC_NDS32_15_FIXED
4197 BFD_RELOC_NDS32_17_FIXED
4199 BFD_RELOC_NDS32_25_FIXED
4201 BFD_RELOC_NDS32_LONGCALL4
4203 BFD_RELOC_NDS32_LONGCALL5
4205 BFD_RELOC_NDS32_LONGCALL6
4207 BFD_RELOC_NDS32_LONGJUMP4
4209 BFD_RELOC_NDS32_LONGJUMP5
4211 BFD_RELOC_NDS32_LONGJUMP6
4213 BFD_RELOC_NDS32_LONGJUMP7
4217 BFD_RELOC_NDS32_PLTREL_HI20
4219 BFD_RELOC_NDS32_PLTREL_LO12
4221 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4223 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4227 BFD_RELOC_NDS32_SDA12S2_DP
4229 BFD_RELOC_NDS32_SDA12S2_SP
4231 BFD_RELOC_NDS32_LO12S2_DP
4233 BFD_RELOC_NDS32_LO12S2_SP
4237 BFD_RELOC_NDS32_DWARF2_OP1
4239 BFD_RELOC_NDS32_DWARF2_OP2
4241 BFD_RELOC_NDS32_DWARF2_LEB
4243 for dwarf2 debug_line.
4245 BFD_RELOC_NDS32_UPDATE_TA
4247 for eliminate 16-bit instructions
4249 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4251 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4253 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4255 BFD_RELOC_NDS32_GOT_LO15
4257 BFD_RELOC_NDS32_GOT_LO19
4259 BFD_RELOC_NDS32_GOTOFF_LO15
4261 BFD_RELOC_NDS32_GOTOFF_LO19
4263 BFD_RELOC_NDS32_GOT15S2
4265 BFD_RELOC_NDS32_GOT17S2
4267 for PIC object relaxation
4272 This is a 5 bit absolute address.
4274 BFD_RELOC_NDS32_10_UPCREL
4276 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4278 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4280 If fp were omitted, fp can used as another gp.
4282 BFD_RELOC_NDS32_RELAX_ENTRY
4284 BFD_RELOC_NDS32_GOT_SUFF
4286 BFD_RELOC_NDS32_GOTOFF_SUFF
4288 BFD_RELOC_NDS32_PLT_GOT_SUFF
4290 BFD_RELOC_NDS32_MULCALL_SUFF
4294 BFD_RELOC_NDS32_PTR_COUNT
4296 BFD_RELOC_NDS32_PTR_RESOLVED
4298 BFD_RELOC_NDS32_PLTBLOCK
4300 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4302 BFD_RELOC_NDS32_RELAX_REGION_END
4304 BFD_RELOC_NDS32_MINUEND
4306 BFD_RELOC_NDS32_SUBTRAHEND
4308 BFD_RELOC_NDS32_DIFF8
4310 BFD_RELOC_NDS32_DIFF16
4312 BFD_RELOC_NDS32_DIFF32
4314 BFD_RELOC_NDS32_DIFF_ULEB128
4316 BFD_RELOC_NDS32_EMPTY
4318 relaxation relative relocation types
4320 BFD_RELOC_NDS32_25_ABS
4322 This is a 25 bit absolute address.
4324 BFD_RELOC_NDS32_DATA
4326 BFD_RELOC_NDS32_TRAN
4328 BFD_RELOC_NDS32_17IFC_PCREL
4330 BFD_RELOC_NDS32_10IFCU_PCREL
4332 For ex9 and ifc using.
4334 BFD_RELOC_NDS32_TPOFF
4336 BFD_RELOC_NDS32_TLS_LE_HI20
4338 BFD_RELOC_NDS32_TLS_LE_LO12
4340 BFD_RELOC_NDS32_TLS_LE_ADD
4342 BFD_RELOC_NDS32_TLS_LE_LS
4344 BFD_RELOC_NDS32_GOTTPOFF
4346 BFD_RELOC_NDS32_TLS_IE_HI20
4348 BFD_RELOC_NDS32_TLS_IE_LO12S2
4350 BFD_RELOC_NDS32_TLS_TPOFF
4352 BFD_RELOC_NDS32_TLS_LE_20
4354 BFD_RELOC_NDS32_TLS_LE_15S0
4356 BFD_RELOC_NDS32_TLS_LE_15S1
4358 BFD_RELOC_NDS32_TLS_LE_15S2
4364 BFD_RELOC_V850_9_PCREL
4366 This is a 9-bit reloc
4368 BFD_RELOC_V850_22_PCREL
4370 This is a 22-bit reloc
4373 BFD_RELOC_V850_SDA_16_16_OFFSET
4375 This is a 16 bit offset from the short data area pointer.
4377 BFD_RELOC_V850_SDA_15_16_OFFSET
4379 This is a 16 bit offset (of which only 15 bits are used) from the
4380 short data area pointer.
4382 BFD_RELOC_V850_ZDA_16_16_OFFSET
4384 This is a 16 bit offset from the zero data area pointer.
4386 BFD_RELOC_V850_ZDA_15_16_OFFSET
4388 This is a 16 bit offset (of which only 15 bits are used) from the
4389 zero data area pointer.
4391 BFD_RELOC_V850_TDA_6_8_OFFSET
4393 This is an 8 bit offset (of which only 6 bits are used) from the
4394 tiny data area pointer.
4396 BFD_RELOC_V850_TDA_7_8_OFFSET
4398 This is an 8bit offset (of which only 7 bits are used) from the tiny
4401 BFD_RELOC_V850_TDA_7_7_OFFSET
4403 This is a 7 bit offset from the tiny data area pointer.
4405 BFD_RELOC_V850_TDA_16_16_OFFSET
4407 This is a 16 bit offset from the tiny data area pointer.
4410 BFD_RELOC_V850_TDA_4_5_OFFSET
4412 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4415 BFD_RELOC_V850_TDA_4_4_OFFSET
4417 This is a 4 bit offset from the tiny data area pointer.
4419 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4421 This is a 16 bit offset from the short data area pointer, with the
4422 bits placed non-contiguously in the instruction.
4424 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4426 This is a 16 bit offset from the zero data area pointer, with the
4427 bits placed non-contiguously in the instruction.
4429 BFD_RELOC_V850_CALLT_6_7_OFFSET
4431 This is a 6 bit offset from the call table base pointer.
4433 BFD_RELOC_V850_CALLT_16_16_OFFSET
4435 This is a 16 bit offset from the call table base pointer.
4437 BFD_RELOC_V850_LONGCALL
4439 Used for relaxing indirect function calls.
4441 BFD_RELOC_V850_LONGJUMP
4443 Used for relaxing indirect jumps.
4445 BFD_RELOC_V850_ALIGN
4447 Used to maintain alignment whilst relaxing.
4449 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4451 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4454 BFD_RELOC_V850_16_PCREL
4456 This is a 16-bit reloc.
4458 BFD_RELOC_V850_17_PCREL
4460 This is a 17-bit reloc.
4464 This is a 23-bit reloc.
4466 BFD_RELOC_V850_32_PCREL
4468 This is a 32-bit reloc.
4470 BFD_RELOC_V850_32_ABS
4472 This is a 32-bit reloc.
4474 BFD_RELOC_V850_16_SPLIT_OFFSET
4476 This is a 16-bit reloc.
4478 BFD_RELOC_V850_16_S1
4480 This is a 16-bit reloc.
4482 BFD_RELOC_V850_LO16_S1
4484 Low 16 bits. 16 bit shifted by 1.
4486 BFD_RELOC_V850_CALLT_15_16_OFFSET
4488 This is a 16 bit offset from the call table base pointer.
4490 BFD_RELOC_V850_32_GOTPCREL
4494 BFD_RELOC_V850_16_GOT
4498 BFD_RELOC_V850_32_GOT
4502 BFD_RELOC_V850_22_PLT_PCREL
4506 BFD_RELOC_V850_32_PLT_PCREL
4514 BFD_RELOC_V850_GLOB_DAT
4518 BFD_RELOC_V850_JMP_SLOT
4522 BFD_RELOC_V850_RELATIVE
4526 BFD_RELOC_V850_16_GOTOFF
4530 BFD_RELOC_V850_32_GOTOFF
4545 This is a 8bit DP reloc for the tms320c30, where the most
4546 significant 8 bits of a 24 bit word are placed into the least
4547 significant 8 bits of the opcode.
4550 BFD_RELOC_TIC54X_PARTLS7
4552 This is a 7bit reloc for the tms320c54x, where the least
4553 significant 7 bits of a 16 bit word are placed into the least
4554 significant 7 bits of the opcode.
4557 BFD_RELOC_TIC54X_PARTMS9
4559 This is a 9bit DP reloc for the tms320c54x, where the most
4560 significant 9 bits of a 16 bit word are placed into the least
4561 significant 9 bits of the opcode.
4566 This is an extended address 23-bit reloc for the tms320c54x.
4569 BFD_RELOC_TIC54X_16_OF_23
4571 This is a 16-bit reloc for the tms320c54x, where the least
4572 significant 16 bits of a 23-bit extended address are placed into
4576 BFD_RELOC_TIC54X_MS7_OF_23
4578 This is a reloc for the tms320c54x, where the most
4579 significant 7 bits of a 23-bit extended address are placed into
4583 BFD_RELOC_C6000_PCR_S21
4585 BFD_RELOC_C6000_PCR_S12
4587 BFD_RELOC_C6000_PCR_S10
4589 BFD_RELOC_C6000_PCR_S7
4591 BFD_RELOC_C6000_ABS_S16
4593 BFD_RELOC_C6000_ABS_L16
4595 BFD_RELOC_C6000_ABS_H16
4597 BFD_RELOC_C6000_SBR_U15_B
4599 BFD_RELOC_C6000_SBR_U15_H
4601 BFD_RELOC_C6000_SBR_U15_W
4603 BFD_RELOC_C6000_SBR_S16
4605 BFD_RELOC_C6000_SBR_L16_B
4607 BFD_RELOC_C6000_SBR_L16_H
4609 BFD_RELOC_C6000_SBR_L16_W
4611 BFD_RELOC_C6000_SBR_H16_B
4613 BFD_RELOC_C6000_SBR_H16_H
4615 BFD_RELOC_C6000_SBR_H16_W
4617 BFD_RELOC_C6000_SBR_GOT_U15_W
4619 BFD_RELOC_C6000_SBR_GOT_L16_W
4621 BFD_RELOC_C6000_SBR_GOT_H16_W
4623 BFD_RELOC_C6000_DSBT_INDEX
4625 BFD_RELOC_C6000_PREL31
4627 BFD_RELOC_C6000_COPY
4629 BFD_RELOC_C6000_JUMP_SLOT
4631 BFD_RELOC_C6000_EHTYPE
4633 BFD_RELOC_C6000_PCR_H16
4635 BFD_RELOC_C6000_PCR_L16
4637 BFD_RELOC_C6000_ALIGN
4639 BFD_RELOC_C6000_FPHEAD
4641 BFD_RELOC_C6000_NOCMP
4643 TMS320C6000 relocations.
4648 This is a 48 bit reloc for the FR30 that stores 32 bits.
4652 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4655 BFD_RELOC_FR30_6_IN_4
4657 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4660 BFD_RELOC_FR30_8_IN_8
4662 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4665 BFD_RELOC_FR30_9_IN_8
4667 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4670 BFD_RELOC_FR30_10_IN_8
4672 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4675 BFD_RELOC_FR30_9_PCREL
4677 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4678 short offset into 8 bits.
4680 BFD_RELOC_FR30_12_PCREL
4682 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4683 short offset into 11 bits.
4686 BFD_RELOC_MCORE_PCREL_IMM8BY4
4688 BFD_RELOC_MCORE_PCREL_IMM11BY2
4690 BFD_RELOC_MCORE_PCREL_IMM4BY2
4692 BFD_RELOC_MCORE_PCREL_32
4694 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4698 Motorola Mcore relocations.
4707 BFD_RELOC_MEP_PCREL8A2
4709 BFD_RELOC_MEP_PCREL12A2
4711 BFD_RELOC_MEP_PCREL17A2
4713 BFD_RELOC_MEP_PCREL24A2
4715 BFD_RELOC_MEP_PCABS24A2
4727 BFD_RELOC_MEP_TPREL7
4729 BFD_RELOC_MEP_TPREL7A2
4731 BFD_RELOC_MEP_TPREL7A4
4733 BFD_RELOC_MEP_UIMM24
4735 BFD_RELOC_MEP_ADDR24A4
4737 BFD_RELOC_MEP_GNU_VTINHERIT
4739 BFD_RELOC_MEP_GNU_VTENTRY
4741 Toshiba Media Processor Relocations.
4745 BFD_RELOC_METAG_HIADDR16
4747 BFD_RELOC_METAG_LOADDR16
4749 BFD_RELOC_METAG_RELBRANCH
4751 BFD_RELOC_METAG_GETSETOFF
4753 BFD_RELOC_METAG_HIOG
4755 BFD_RELOC_METAG_LOOG
4757 BFD_RELOC_METAG_REL8
4759 BFD_RELOC_METAG_REL16
4761 BFD_RELOC_METAG_HI16_GOTOFF
4763 BFD_RELOC_METAG_LO16_GOTOFF
4765 BFD_RELOC_METAG_GETSET_GOTOFF
4767 BFD_RELOC_METAG_GETSET_GOT
4769 BFD_RELOC_METAG_HI16_GOTPC
4771 BFD_RELOC_METAG_LO16_GOTPC
4773 BFD_RELOC_METAG_HI16_PLT
4775 BFD_RELOC_METAG_LO16_PLT
4777 BFD_RELOC_METAG_RELBRANCH_PLT
4779 BFD_RELOC_METAG_GOTOFF
4783 BFD_RELOC_METAG_COPY
4785 BFD_RELOC_METAG_JMP_SLOT
4787 BFD_RELOC_METAG_RELATIVE
4789 BFD_RELOC_METAG_GLOB_DAT
4791 BFD_RELOC_METAG_TLS_GD
4793 BFD_RELOC_METAG_TLS_LDM
4795 BFD_RELOC_METAG_TLS_LDO_HI16
4797 BFD_RELOC_METAG_TLS_LDO_LO16
4799 BFD_RELOC_METAG_TLS_LDO
4801 BFD_RELOC_METAG_TLS_IE
4803 BFD_RELOC_METAG_TLS_IENONPIC
4805 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4807 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4809 BFD_RELOC_METAG_TLS_TPOFF
4811 BFD_RELOC_METAG_TLS_DTPMOD
4813 BFD_RELOC_METAG_TLS_DTPOFF
4815 BFD_RELOC_METAG_TLS_LE
4817 BFD_RELOC_METAG_TLS_LE_HI16
4819 BFD_RELOC_METAG_TLS_LE_LO16
4821 Imagination Technologies Meta relocations.
4826 BFD_RELOC_MMIX_GETA_1
4828 BFD_RELOC_MMIX_GETA_2
4830 BFD_RELOC_MMIX_GETA_3
4832 These are relocations for the GETA instruction.
4834 BFD_RELOC_MMIX_CBRANCH
4836 BFD_RELOC_MMIX_CBRANCH_J
4838 BFD_RELOC_MMIX_CBRANCH_1
4840 BFD_RELOC_MMIX_CBRANCH_2
4842 BFD_RELOC_MMIX_CBRANCH_3
4844 These are relocations for a conditional branch instruction.
4846 BFD_RELOC_MMIX_PUSHJ
4848 BFD_RELOC_MMIX_PUSHJ_1
4850 BFD_RELOC_MMIX_PUSHJ_2
4852 BFD_RELOC_MMIX_PUSHJ_3
4854 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4856 These are relocations for the PUSHJ instruction.
4860 BFD_RELOC_MMIX_JMP_1
4862 BFD_RELOC_MMIX_JMP_2
4864 BFD_RELOC_MMIX_JMP_3
4866 These are relocations for the JMP instruction.
4868 BFD_RELOC_MMIX_ADDR19
4870 This is a relocation for a relative address as in a GETA instruction or
4873 BFD_RELOC_MMIX_ADDR27
4875 This is a relocation for a relative address as in a JMP instruction.
4877 BFD_RELOC_MMIX_REG_OR_BYTE
4879 This is a relocation for an instruction field that may be a general
4880 register or a value 0..255.
4884 This is a relocation for an instruction field that may be a general
4887 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4889 This is a relocation for two instruction fields holding a register and
4890 an offset, the equivalent of the relocation.
4892 BFD_RELOC_MMIX_LOCAL
4894 This relocation is an assertion that the expression is not allocated as
4895 a global register. It does not modify contents.
4898 BFD_RELOC_AVR_7_PCREL
4900 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4901 short offset into 7 bits.
4903 BFD_RELOC_AVR_13_PCREL
4905 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4906 short offset into 12 bits.
4910 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4911 program memory address) into 16 bits.
4913 BFD_RELOC_AVR_LO8_LDI
4915 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4916 data memory address) into 8 bit immediate value of LDI insn.
4918 BFD_RELOC_AVR_HI8_LDI
4920 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4921 of data memory address) into 8 bit immediate value of LDI insn.
4923 BFD_RELOC_AVR_HH8_LDI
4925 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4926 of program memory address) into 8 bit immediate value of LDI insn.
4928 BFD_RELOC_AVR_MS8_LDI
4930 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4931 of 32 bit value) into 8 bit immediate value of LDI insn.
4933 BFD_RELOC_AVR_LO8_LDI_NEG
4935 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4936 (usually data memory address) into 8 bit immediate value of SUBI insn.
4938 BFD_RELOC_AVR_HI8_LDI_NEG
4940 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4941 (high 8 bit of data memory address) into 8 bit immediate value of
4944 BFD_RELOC_AVR_HH8_LDI_NEG
4946 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4947 (most high 8 bit of program memory address) into 8 bit immediate value
4948 of LDI or SUBI insn.
4950 BFD_RELOC_AVR_MS8_LDI_NEG
4952 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4953 of 32 bit value) into 8 bit immediate value of LDI insn.
4955 BFD_RELOC_AVR_LO8_LDI_PM
4957 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4958 command address) into 8 bit immediate value of LDI insn.
4960 BFD_RELOC_AVR_LO8_LDI_GS
4962 This is a 16 bit reloc for the AVR that stores 8 bit value
4963 (command address) into 8 bit immediate value of LDI insn. If the address
4964 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4967 BFD_RELOC_AVR_HI8_LDI_PM
4969 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4970 of command address) into 8 bit immediate value of LDI insn.
4972 BFD_RELOC_AVR_HI8_LDI_GS
4974 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4975 of command address) into 8 bit immediate value of LDI insn. If the address
4976 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4979 BFD_RELOC_AVR_HH8_LDI_PM
4981 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4982 of command address) into 8 bit immediate value of LDI insn.
4984 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4986 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4987 (usually command address) into 8 bit immediate value of SUBI insn.
4989 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4991 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4992 (high 8 bit of 16 bit command address) into 8 bit immediate value
4995 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4997 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4998 (high 6 bit of 22 bit command address) into 8 bit immediate
5003 This is a 32 bit reloc for the AVR that stores 23 bit value
5008 This is a 16 bit reloc for the AVR that stores all needed bits
5009 for absolute addressing with ldi with overflow check to linktime
5013 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5016 BFD_RELOC_AVR_6_ADIW
5018 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5023 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5024 in .byte lo8(symbol)
5028 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5029 in .byte hi8(symbol)
5033 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5034 in .byte hlo8(symbol)
5038 BFD_RELOC_AVR_DIFF16
5040 BFD_RELOC_AVR_DIFF32
5042 AVR relocations to mark the difference of two local symbols.
5043 These are only needed to support linker relaxation and can be ignored
5044 when not relaxing. The field is set to the value of the difference
5045 assuming no relaxation. The relocation encodes the position of the
5046 second symbol so the linker can determine whether to adjust the field
5049 BFD_RELOC_AVR_LDS_STS_16
5051 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5052 lds and sts instructions supported only tiny core.
5056 This is a 6 bit reloc for the AVR that stores an I/O register
5057 number for the IN and OUT instructions
5061 This is a 5 bit reloc for the AVR that stores an I/O register
5062 number for the SBIC, SBIS, SBI and CBI instructions
5065 BFD_RELOC_RISCV_HI20
5067 BFD_RELOC_RISCV_PCREL_HI20
5069 BFD_RELOC_RISCV_PCREL_LO12_I
5071 BFD_RELOC_RISCV_PCREL_LO12_S
5073 BFD_RELOC_RISCV_LO12_I
5075 BFD_RELOC_RISCV_LO12_S
5077 BFD_RELOC_RISCV_GPREL12_I
5079 BFD_RELOC_RISCV_GPREL12_S
5081 BFD_RELOC_RISCV_TPREL_HI20
5083 BFD_RELOC_RISCV_TPREL_LO12_I
5085 BFD_RELOC_RISCV_TPREL_LO12_S
5087 BFD_RELOC_RISCV_TPREL_ADD
5089 BFD_RELOC_RISCV_CALL
5091 BFD_RELOC_RISCV_CALL_PLT
5093 BFD_RELOC_RISCV_ADD8
5095 BFD_RELOC_RISCV_ADD16
5097 BFD_RELOC_RISCV_ADD32
5099 BFD_RELOC_RISCV_ADD64
5101 BFD_RELOC_RISCV_SUB8
5103 BFD_RELOC_RISCV_SUB16
5105 BFD_RELOC_RISCV_SUB32
5107 BFD_RELOC_RISCV_SUB64
5109 BFD_RELOC_RISCV_GOT_HI20
5111 BFD_RELOC_RISCV_TLS_GOT_HI20
5113 BFD_RELOC_RISCV_TLS_GD_HI20
5117 BFD_RELOC_RISCV_TLS_DTPMOD32
5119 BFD_RELOC_RISCV_TLS_DTPREL32
5121 BFD_RELOC_RISCV_TLS_DTPMOD64
5123 BFD_RELOC_RISCV_TLS_DTPREL64
5125 BFD_RELOC_RISCV_TLS_TPREL32
5127 BFD_RELOC_RISCV_TLS_TPREL64
5129 BFD_RELOC_RISCV_ALIGN
5131 BFD_RELOC_RISCV_RVC_BRANCH
5133 BFD_RELOC_RISCV_RVC_JUMP
5135 BFD_RELOC_RISCV_RVC_LUI
5137 BFD_RELOC_RISCV_GPREL_I
5139 BFD_RELOC_RISCV_GPREL_S
5141 BFD_RELOC_RISCV_TPREL_I
5143 BFD_RELOC_RISCV_TPREL_S
5145 BFD_RELOC_RISCV_RELAX
5149 BFD_RELOC_RISCV_SUB6
5151 BFD_RELOC_RISCV_SET6
5153 BFD_RELOC_RISCV_SET8
5155 BFD_RELOC_RISCV_SET16
5157 BFD_RELOC_RISCV_SET32
5164 BFD_RELOC_RL78_NEG16
5166 BFD_RELOC_RL78_NEG24
5168 BFD_RELOC_RL78_NEG32
5170 BFD_RELOC_RL78_16_OP
5172 BFD_RELOC_RL78_24_OP
5174 BFD_RELOC_RL78_32_OP
5182 BFD_RELOC_RL78_DIR3U_PCREL
5186 BFD_RELOC_RL78_GPRELB
5188 BFD_RELOC_RL78_GPRELW
5190 BFD_RELOC_RL78_GPRELL
5194 BFD_RELOC_RL78_OP_SUBTRACT
5196 BFD_RELOC_RL78_OP_NEG
5198 BFD_RELOC_RL78_OP_AND
5200 BFD_RELOC_RL78_OP_SHRA
5204 BFD_RELOC_RL78_ABS16
5206 BFD_RELOC_RL78_ABS16_REV
5208 BFD_RELOC_RL78_ABS32
5210 BFD_RELOC_RL78_ABS32_REV
5212 BFD_RELOC_RL78_ABS16U
5214 BFD_RELOC_RL78_ABS16UW
5216 BFD_RELOC_RL78_ABS16UL
5218 BFD_RELOC_RL78_RELAX
5228 BFD_RELOC_RL78_SADDR
5230 Renesas RL78 Relocations.
5253 BFD_RELOC_RX_DIR3U_PCREL
5265 BFD_RELOC_RX_OP_SUBTRACT
5273 BFD_RELOC_RX_ABS16_REV
5277 BFD_RELOC_RX_ABS32_REV
5281 BFD_RELOC_RX_ABS16UW
5283 BFD_RELOC_RX_ABS16UL
5287 Renesas RX Relocations.
5300 32 bit PC relative PLT address.
5304 Copy symbol at runtime.
5306 BFD_RELOC_390_GLOB_DAT
5310 BFD_RELOC_390_JMP_SLOT
5314 BFD_RELOC_390_RELATIVE
5316 Adjust by program base.
5320 32 bit PC relative offset to GOT.
5326 BFD_RELOC_390_PC12DBL
5328 PC relative 12 bit shifted by 1.
5330 BFD_RELOC_390_PLT12DBL
5332 12 bit PC rel. PLT shifted by 1.
5334 BFD_RELOC_390_PC16DBL
5336 PC relative 16 bit shifted by 1.
5338 BFD_RELOC_390_PLT16DBL
5340 16 bit PC rel. PLT shifted by 1.
5342 BFD_RELOC_390_PC24DBL
5344 PC relative 24 bit shifted by 1.
5346 BFD_RELOC_390_PLT24DBL
5348 24 bit PC rel. PLT shifted by 1.
5350 BFD_RELOC_390_PC32DBL
5352 PC relative 32 bit shifted by 1.
5354 BFD_RELOC_390_PLT32DBL
5356 32 bit PC rel. PLT shifted by 1.
5358 BFD_RELOC_390_GOTPCDBL
5360 32 bit PC rel. GOT shifted by 1.
5368 64 bit PC relative PLT address.
5370 BFD_RELOC_390_GOTENT
5372 32 bit rel. offset to GOT entry.
5374 BFD_RELOC_390_GOTOFF64
5376 64 bit offset to GOT.
5378 BFD_RELOC_390_GOTPLT12
5380 12-bit offset to symbol-entry within GOT, with PLT handling.
5382 BFD_RELOC_390_GOTPLT16
5384 16-bit offset to symbol-entry within GOT, with PLT handling.
5386 BFD_RELOC_390_GOTPLT32
5388 32-bit offset to symbol-entry within GOT, with PLT handling.
5390 BFD_RELOC_390_GOTPLT64
5392 64-bit offset to symbol-entry within GOT, with PLT handling.
5394 BFD_RELOC_390_GOTPLTENT
5396 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5398 BFD_RELOC_390_PLTOFF16
5400 16-bit rel. offset from the GOT to a PLT entry.
5402 BFD_RELOC_390_PLTOFF32
5404 32-bit rel. offset from the GOT to a PLT entry.
5406 BFD_RELOC_390_PLTOFF64
5408 64-bit rel. offset from the GOT to a PLT entry.
5411 BFD_RELOC_390_TLS_LOAD
5413 BFD_RELOC_390_TLS_GDCALL
5415 BFD_RELOC_390_TLS_LDCALL
5417 BFD_RELOC_390_TLS_GD32
5419 BFD_RELOC_390_TLS_GD64
5421 BFD_RELOC_390_TLS_GOTIE12
5423 BFD_RELOC_390_TLS_GOTIE32
5425 BFD_RELOC_390_TLS_GOTIE64
5427 BFD_RELOC_390_TLS_LDM32
5429 BFD_RELOC_390_TLS_LDM64
5431 BFD_RELOC_390_TLS_IE32
5433 BFD_RELOC_390_TLS_IE64
5435 BFD_RELOC_390_TLS_IEENT
5437 BFD_RELOC_390_TLS_LE32
5439 BFD_RELOC_390_TLS_LE64
5441 BFD_RELOC_390_TLS_LDO32
5443 BFD_RELOC_390_TLS_LDO64
5445 BFD_RELOC_390_TLS_DTPMOD
5447 BFD_RELOC_390_TLS_DTPOFF
5449 BFD_RELOC_390_TLS_TPOFF
5451 s390 tls relocations.
5458 BFD_RELOC_390_GOTPLT20
5460 BFD_RELOC_390_TLS_GOTIE20
5462 Long displacement extension.
5465 BFD_RELOC_390_IRELATIVE
5467 STT_GNU_IFUNC relocation.
5470 BFD_RELOC_SCORE_GPREL15
5473 Low 16 bit for load/store
5475 BFD_RELOC_SCORE_DUMMY2
5479 This is a 24-bit reloc with the right 1 bit assumed to be 0
5481 BFD_RELOC_SCORE_BRANCH
5483 This is a 19-bit reloc with the right 1 bit assumed to be 0
5485 BFD_RELOC_SCORE_IMM30
5487 This is a 32-bit reloc for 48-bit instructions.
5489 BFD_RELOC_SCORE_IMM32
5491 This is a 32-bit reloc for 48-bit instructions.
5493 BFD_RELOC_SCORE16_JMP
5495 This is a 11-bit reloc with the right 1 bit assumed to be 0
5497 BFD_RELOC_SCORE16_BRANCH
5499 This is a 8-bit reloc with the right 1 bit assumed to be 0
5501 BFD_RELOC_SCORE_BCMP
5503 This is a 9-bit reloc with the right 1 bit assumed to be 0
5505 BFD_RELOC_SCORE_GOT15
5507 BFD_RELOC_SCORE_GOT_LO16
5509 BFD_RELOC_SCORE_CALL15
5511 BFD_RELOC_SCORE_DUMMY_HI16
5513 Undocumented Score relocs
5518 Scenix IP2K - 9-bit register number / data address
5522 Scenix IP2K - 4-bit register/data bank number
5524 BFD_RELOC_IP2K_ADDR16CJP
5526 Scenix IP2K - low 13 bits of instruction word address
5528 BFD_RELOC_IP2K_PAGE3
5530 Scenix IP2K - high 3 bits of instruction word address
5532 BFD_RELOC_IP2K_LO8DATA
5534 BFD_RELOC_IP2K_HI8DATA
5536 BFD_RELOC_IP2K_EX8DATA
5538 Scenix IP2K - ext/low/high 8 bits of data address
5540 BFD_RELOC_IP2K_LO8INSN
5542 BFD_RELOC_IP2K_HI8INSN
5544 Scenix IP2K - low/high 8 bits of instruction word address
5546 BFD_RELOC_IP2K_PC_SKIP
5548 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5552 Scenix IP2K - 16 bit word address in text section.
5554 BFD_RELOC_IP2K_FR_OFFSET
5556 Scenix IP2K - 7-bit sp or dp offset
5558 BFD_RELOC_VPE4KMATH_DATA
5560 BFD_RELOC_VPE4KMATH_INSN
5562 Scenix VPE4K coprocessor - data/insn-space addressing
5565 BFD_RELOC_VTABLE_INHERIT
5567 BFD_RELOC_VTABLE_ENTRY
5569 These two relocations are used by the linker to determine which of
5570 the entries in a C++ virtual function table are actually used. When
5571 the --gc-sections option is given, the linker will zero out the entries
5572 that are not used, so that the code for those functions need not be
5573 included in the output.
5575 VTABLE_INHERIT is a zero-space relocation used to describe to the
5576 linker the inheritance tree of a C++ virtual function table. The
5577 relocation's symbol should be the parent class' vtable, and the
5578 relocation should be located at the child vtable.
5580 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5581 virtual function table entry. The reloc's symbol should refer to the
5582 table of the class mentioned in the code. Off of that base, an offset
5583 describes the entry that is being used. For Rela hosts, this offset
5584 is stored in the reloc's addend. For Rel hosts, we are forced to put
5585 this offset in the reloc's section offset.
5588 BFD_RELOC_IA64_IMM14
5590 BFD_RELOC_IA64_IMM22
5592 BFD_RELOC_IA64_IMM64
5594 BFD_RELOC_IA64_DIR32MSB
5596 BFD_RELOC_IA64_DIR32LSB
5598 BFD_RELOC_IA64_DIR64MSB
5600 BFD_RELOC_IA64_DIR64LSB
5602 BFD_RELOC_IA64_GPREL22
5604 BFD_RELOC_IA64_GPREL64I
5606 BFD_RELOC_IA64_GPREL32MSB
5608 BFD_RELOC_IA64_GPREL32LSB
5610 BFD_RELOC_IA64_GPREL64MSB
5612 BFD_RELOC_IA64_GPREL64LSB
5614 BFD_RELOC_IA64_LTOFF22
5616 BFD_RELOC_IA64_LTOFF64I
5618 BFD_RELOC_IA64_PLTOFF22
5620 BFD_RELOC_IA64_PLTOFF64I
5622 BFD_RELOC_IA64_PLTOFF64MSB
5624 BFD_RELOC_IA64_PLTOFF64LSB
5626 BFD_RELOC_IA64_FPTR64I
5628 BFD_RELOC_IA64_FPTR32MSB
5630 BFD_RELOC_IA64_FPTR32LSB
5632 BFD_RELOC_IA64_FPTR64MSB
5634 BFD_RELOC_IA64_FPTR64LSB
5636 BFD_RELOC_IA64_PCREL21B
5638 BFD_RELOC_IA64_PCREL21BI
5640 BFD_RELOC_IA64_PCREL21M
5642 BFD_RELOC_IA64_PCREL21F
5644 BFD_RELOC_IA64_PCREL22
5646 BFD_RELOC_IA64_PCREL60B
5648 BFD_RELOC_IA64_PCREL64I
5650 BFD_RELOC_IA64_PCREL32MSB
5652 BFD_RELOC_IA64_PCREL32LSB
5654 BFD_RELOC_IA64_PCREL64MSB
5656 BFD_RELOC_IA64_PCREL64LSB
5658 BFD_RELOC_IA64_LTOFF_FPTR22
5660 BFD_RELOC_IA64_LTOFF_FPTR64I
5662 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5664 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5666 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5668 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5670 BFD_RELOC_IA64_SEGREL32MSB
5672 BFD_RELOC_IA64_SEGREL32LSB
5674 BFD_RELOC_IA64_SEGREL64MSB
5676 BFD_RELOC_IA64_SEGREL64LSB
5678 BFD_RELOC_IA64_SECREL32MSB
5680 BFD_RELOC_IA64_SECREL32LSB
5682 BFD_RELOC_IA64_SECREL64MSB
5684 BFD_RELOC_IA64_SECREL64LSB
5686 BFD_RELOC_IA64_REL32MSB
5688 BFD_RELOC_IA64_REL32LSB
5690 BFD_RELOC_IA64_REL64MSB
5692 BFD_RELOC_IA64_REL64LSB
5694 BFD_RELOC_IA64_LTV32MSB
5696 BFD_RELOC_IA64_LTV32LSB
5698 BFD_RELOC_IA64_LTV64MSB
5700 BFD_RELOC_IA64_LTV64LSB
5702 BFD_RELOC_IA64_IPLTMSB
5704 BFD_RELOC_IA64_IPLTLSB
5708 BFD_RELOC_IA64_LTOFF22X
5710 BFD_RELOC_IA64_LDXMOV
5712 BFD_RELOC_IA64_TPREL14
5714 BFD_RELOC_IA64_TPREL22
5716 BFD_RELOC_IA64_TPREL64I
5718 BFD_RELOC_IA64_TPREL64MSB
5720 BFD_RELOC_IA64_TPREL64LSB
5722 BFD_RELOC_IA64_LTOFF_TPREL22
5724 BFD_RELOC_IA64_DTPMOD64MSB
5726 BFD_RELOC_IA64_DTPMOD64LSB
5728 BFD_RELOC_IA64_LTOFF_DTPMOD22
5730 BFD_RELOC_IA64_DTPREL14
5732 BFD_RELOC_IA64_DTPREL22
5734 BFD_RELOC_IA64_DTPREL64I
5736 BFD_RELOC_IA64_DTPREL32MSB
5738 BFD_RELOC_IA64_DTPREL32LSB
5740 BFD_RELOC_IA64_DTPREL64MSB
5742 BFD_RELOC_IA64_DTPREL64LSB
5744 BFD_RELOC_IA64_LTOFF_DTPREL22
5746 Intel IA64 Relocations.
5749 BFD_RELOC_M68HC11_HI8
5751 Motorola 68HC11 reloc.
5752 This is the 8 bit high part of an absolute address.
5754 BFD_RELOC_M68HC11_LO8
5756 Motorola 68HC11 reloc.
5757 This is the 8 bit low part of an absolute address.
5759 BFD_RELOC_M68HC11_3B
5761 Motorola 68HC11 reloc.
5762 This is the 3 bit of a value.
5764 BFD_RELOC_M68HC11_RL_JUMP
5766 Motorola 68HC11 reloc.
5767 This reloc marks the beginning of a jump/call instruction.
5768 It is used for linker relaxation to correctly identify beginning
5769 of instruction and change some branches to use PC-relative
5772 BFD_RELOC_M68HC11_RL_GROUP
5774 Motorola 68HC11 reloc.
5775 This reloc marks a group of several instructions that gcc generates
5776 and for which the linker relaxation pass can modify and/or remove
5779 BFD_RELOC_M68HC11_LO16
5781 Motorola 68HC11 reloc.
5782 This is the 16-bit lower part of an address. It is used for 'call'
5783 instruction to specify the symbol address without any special
5784 transformation (due to memory bank window).
5786 BFD_RELOC_M68HC11_PAGE
5788 Motorola 68HC11 reloc.
5789 This is a 8-bit reloc that specifies the page number of an address.
5790 It is used by 'call' instruction to specify the page number of
5793 BFD_RELOC_M68HC11_24
5795 Motorola 68HC11 reloc.
5796 This is a 24-bit reloc that represents the address with a 16-bit
5797 value and a 8-bit page number. The symbol address is transformed
5798 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5800 BFD_RELOC_M68HC12_5B
5802 Motorola 68HC12 reloc.
5803 This is the 5 bits of a value.
5805 BFD_RELOC_XGATE_RL_JUMP
5807 Freescale XGATE reloc.
5808 This reloc marks the beginning of a bra/jal instruction.
5810 BFD_RELOC_XGATE_RL_GROUP
5812 Freescale XGATE reloc.
5813 This reloc marks a group of several instructions that gcc generates
5814 and for which the linker relaxation pass can modify and/or remove
5817 BFD_RELOC_XGATE_LO16
5819 Freescale XGATE reloc.
5820 This is the 16-bit lower part of an address. It is used for the '16-bit'
5823 BFD_RELOC_XGATE_GPAGE
5825 Freescale XGATE reloc.
5829 Freescale XGATE reloc.
5831 BFD_RELOC_XGATE_PCREL_9
5833 Freescale XGATE reloc.
5834 This is a 9-bit pc-relative reloc.
5836 BFD_RELOC_XGATE_PCREL_10
5838 Freescale XGATE reloc.
5839 This is a 10-bit pc-relative reloc.
5841 BFD_RELOC_XGATE_IMM8_LO
5843 Freescale XGATE reloc.
5844 This is the 16-bit lower part of an address. It is used for the '16-bit'
5847 BFD_RELOC_XGATE_IMM8_HI
5849 Freescale XGATE reloc.
5850 This is the 16-bit higher part of an address. It is used for the '16-bit'
5853 BFD_RELOC_XGATE_IMM3
5855 Freescale XGATE reloc.
5856 This is a 3-bit pc-relative reloc.
5858 BFD_RELOC_XGATE_IMM4
5860 Freescale XGATE reloc.
5861 This is a 4-bit pc-relative reloc.
5863 BFD_RELOC_XGATE_IMM5
5865 Freescale XGATE reloc.
5866 This is a 5-bit pc-relative reloc.
5868 BFD_RELOC_M68HC12_9B
5870 Motorola 68HC12 reloc.
5871 This is the 9 bits of a value.
5873 BFD_RELOC_M68HC12_16B
5875 Motorola 68HC12 reloc.
5876 This is the 16 bits of a value.
5878 BFD_RELOC_M68HC12_9_PCREL
5880 Motorola 68HC12/XGATE reloc.
5881 This is a PCREL9 branch.
5883 BFD_RELOC_M68HC12_10_PCREL
5885 Motorola 68HC12/XGATE reloc.
5886 This is a PCREL10 branch.
5888 BFD_RELOC_M68HC12_LO8XG
5890 Motorola 68HC12/XGATE reloc.
5891 This is the 8 bit low part of an absolute address and immediately precedes
5892 a matching HI8XG part.
5894 BFD_RELOC_M68HC12_HI8XG
5896 Motorola 68HC12/XGATE reloc.
5897 This is the 8 bit high part of an absolute address and immediately follows
5898 a matching LO8XG part.
5902 BFD_RELOC_16C_NUM08_C
5906 BFD_RELOC_16C_NUM16_C
5910 BFD_RELOC_16C_NUM32_C
5912 BFD_RELOC_16C_DISP04
5914 BFD_RELOC_16C_DISP04_C
5916 BFD_RELOC_16C_DISP08
5918 BFD_RELOC_16C_DISP08_C
5920 BFD_RELOC_16C_DISP16
5922 BFD_RELOC_16C_DISP16_C
5924 BFD_RELOC_16C_DISP24
5926 BFD_RELOC_16C_DISP24_C
5928 BFD_RELOC_16C_DISP24a
5930 BFD_RELOC_16C_DISP24a_C
5934 BFD_RELOC_16C_REG04_C
5936 BFD_RELOC_16C_REG04a
5938 BFD_RELOC_16C_REG04a_C
5942 BFD_RELOC_16C_REG14_C
5946 BFD_RELOC_16C_REG16_C
5950 BFD_RELOC_16C_REG20_C
5954 BFD_RELOC_16C_ABS20_C
5958 BFD_RELOC_16C_ABS24_C
5962 BFD_RELOC_16C_IMM04_C
5966 BFD_RELOC_16C_IMM16_C
5970 BFD_RELOC_16C_IMM20_C
5974 BFD_RELOC_16C_IMM24_C
5978 BFD_RELOC_16C_IMM32_C
5980 NS CR16C Relocations.
5985 BFD_RELOC_CR16_NUM16
5987 BFD_RELOC_CR16_NUM32
5989 BFD_RELOC_CR16_NUM32a
5991 BFD_RELOC_CR16_REGREL0
5993 BFD_RELOC_CR16_REGREL4
5995 BFD_RELOC_CR16_REGREL4a
5997 BFD_RELOC_CR16_REGREL14
5999 BFD_RELOC_CR16_REGREL14a
6001 BFD_RELOC_CR16_REGREL16
6003 BFD_RELOC_CR16_REGREL20
6005 BFD_RELOC_CR16_REGREL20a
6007 BFD_RELOC_CR16_ABS20
6009 BFD_RELOC_CR16_ABS24
6015 BFD_RELOC_CR16_IMM16
6017 BFD_RELOC_CR16_IMM20
6019 BFD_RELOC_CR16_IMM24
6021 BFD_RELOC_CR16_IMM32
6023 BFD_RELOC_CR16_IMM32a
6025 BFD_RELOC_CR16_DISP4
6027 BFD_RELOC_CR16_DISP8
6029 BFD_RELOC_CR16_DISP16
6031 BFD_RELOC_CR16_DISP20
6033 BFD_RELOC_CR16_DISP24
6035 BFD_RELOC_CR16_DISP24a
6037 BFD_RELOC_CR16_SWITCH8
6039 BFD_RELOC_CR16_SWITCH16
6041 BFD_RELOC_CR16_SWITCH32
6043 BFD_RELOC_CR16_GOT_REGREL20
6045 BFD_RELOC_CR16_GOTC_REGREL20
6047 BFD_RELOC_CR16_GLOB_DAT
6049 NS CR16 Relocations.
6056 BFD_RELOC_CRX_REL8_CMP
6064 BFD_RELOC_CRX_REGREL12
6066 BFD_RELOC_CRX_REGREL22
6068 BFD_RELOC_CRX_REGREL28
6070 BFD_RELOC_CRX_REGREL32
6086 BFD_RELOC_CRX_SWITCH8
6088 BFD_RELOC_CRX_SWITCH16
6090 BFD_RELOC_CRX_SWITCH32
6095 BFD_RELOC_CRIS_BDISP8
6097 BFD_RELOC_CRIS_UNSIGNED_5
6099 BFD_RELOC_CRIS_SIGNED_6
6101 BFD_RELOC_CRIS_UNSIGNED_6
6103 BFD_RELOC_CRIS_SIGNED_8
6105 BFD_RELOC_CRIS_UNSIGNED_8
6107 BFD_RELOC_CRIS_SIGNED_16
6109 BFD_RELOC_CRIS_UNSIGNED_16
6111 BFD_RELOC_CRIS_LAPCQ_OFFSET
6113 BFD_RELOC_CRIS_UNSIGNED_4
6115 These relocs are only used within the CRIS assembler. They are not
6116 (at present) written to any object files.
6120 BFD_RELOC_CRIS_GLOB_DAT
6122 BFD_RELOC_CRIS_JUMP_SLOT
6124 BFD_RELOC_CRIS_RELATIVE
6126 Relocs used in ELF shared libraries for CRIS.
6128 BFD_RELOC_CRIS_32_GOT
6130 32-bit offset to symbol-entry within GOT.
6132 BFD_RELOC_CRIS_16_GOT
6134 16-bit offset to symbol-entry within GOT.
6136 BFD_RELOC_CRIS_32_GOTPLT
6138 32-bit offset to symbol-entry within GOT, with PLT handling.
6140 BFD_RELOC_CRIS_16_GOTPLT
6142 16-bit offset to symbol-entry within GOT, with PLT handling.
6144 BFD_RELOC_CRIS_32_GOTREL
6146 32-bit offset to symbol, relative to GOT.
6148 BFD_RELOC_CRIS_32_PLT_GOTREL
6150 32-bit offset to symbol with PLT entry, relative to GOT.
6152 BFD_RELOC_CRIS_32_PLT_PCREL
6154 32-bit offset to symbol with PLT entry, relative to this relocation.
6157 BFD_RELOC_CRIS_32_GOT_GD
6159 BFD_RELOC_CRIS_16_GOT_GD
6161 BFD_RELOC_CRIS_32_GD
6165 BFD_RELOC_CRIS_32_DTPREL
6167 BFD_RELOC_CRIS_16_DTPREL
6169 BFD_RELOC_CRIS_32_GOT_TPREL
6171 BFD_RELOC_CRIS_16_GOT_TPREL
6173 BFD_RELOC_CRIS_32_TPREL
6175 BFD_RELOC_CRIS_16_TPREL
6177 BFD_RELOC_CRIS_DTPMOD
6179 BFD_RELOC_CRIS_32_IE
6181 Relocs used in TLS code for CRIS.
6186 BFD_RELOC_860_GLOB_DAT
6188 BFD_RELOC_860_JUMP_SLOT
6190 BFD_RELOC_860_RELATIVE
6200 BFD_RELOC_860_SPLIT0
6204 BFD_RELOC_860_SPLIT1
6208 BFD_RELOC_860_SPLIT2
6212 BFD_RELOC_860_LOGOT0
6214 BFD_RELOC_860_SPGOT0
6216 BFD_RELOC_860_LOGOT1
6218 BFD_RELOC_860_SPGOT1
6220 BFD_RELOC_860_LOGOTOFF0
6222 BFD_RELOC_860_SPGOTOFF0
6224 BFD_RELOC_860_LOGOTOFF1
6226 BFD_RELOC_860_SPGOTOFF1
6228 BFD_RELOC_860_LOGOTOFF2
6230 BFD_RELOC_860_LOGOTOFF3
6234 BFD_RELOC_860_HIGHADJ
6238 BFD_RELOC_860_HAGOTOFF
6246 BFD_RELOC_860_HIGOTOFF
6248 Intel i860 Relocations.
6251 BFD_RELOC_OR1K_REL_26
6253 BFD_RELOC_OR1K_GOTPC_HI16
6255 BFD_RELOC_OR1K_GOTPC_LO16
6257 BFD_RELOC_OR1K_GOT16
6259 BFD_RELOC_OR1K_PLT26
6261 BFD_RELOC_OR1K_GOTOFF_HI16
6263 BFD_RELOC_OR1K_GOTOFF_LO16
6267 BFD_RELOC_OR1K_GLOB_DAT
6269 BFD_RELOC_OR1K_JMP_SLOT
6271 BFD_RELOC_OR1K_RELATIVE
6273 BFD_RELOC_OR1K_TLS_GD_HI16
6275 BFD_RELOC_OR1K_TLS_GD_LO16
6277 BFD_RELOC_OR1K_TLS_LDM_HI16
6279 BFD_RELOC_OR1K_TLS_LDM_LO16
6281 BFD_RELOC_OR1K_TLS_LDO_HI16
6283 BFD_RELOC_OR1K_TLS_LDO_LO16
6285 BFD_RELOC_OR1K_TLS_IE_HI16
6287 BFD_RELOC_OR1K_TLS_IE_LO16
6289 BFD_RELOC_OR1K_TLS_LE_HI16
6291 BFD_RELOC_OR1K_TLS_LE_LO16
6293 BFD_RELOC_OR1K_TLS_TPOFF
6295 BFD_RELOC_OR1K_TLS_DTPOFF
6297 BFD_RELOC_OR1K_TLS_DTPMOD
6299 OpenRISC 1000 Relocations.
6302 BFD_RELOC_H8_DIR16A8
6304 BFD_RELOC_H8_DIR16R8
6306 BFD_RELOC_H8_DIR24A8
6308 BFD_RELOC_H8_DIR24R8
6310 BFD_RELOC_H8_DIR32A16
6312 BFD_RELOC_H8_DISP32A16
6317 BFD_RELOC_XSTORMY16_REL_12
6319 BFD_RELOC_XSTORMY16_12
6321 BFD_RELOC_XSTORMY16_24
6323 BFD_RELOC_XSTORMY16_FPTR16
6325 Sony Xstormy16 Relocations.
6330 Self-describing complex relocations.
6342 Infineon Relocations.
6345 BFD_RELOC_VAX_GLOB_DAT
6347 BFD_RELOC_VAX_JMP_SLOT
6349 BFD_RELOC_VAX_RELATIVE
6351 Relocations used by VAX ELF.
6356 Morpho MT - 16 bit immediate relocation.
6360 Morpho MT - Hi 16 bits of an address.
6364 Morpho MT - Low 16 bits of an address.
6366 BFD_RELOC_MT_GNU_VTINHERIT
6368 Morpho MT - Used to tell the linker which vtable entries are used.
6370 BFD_RELOC_MT_GNU_VTENTRY
6372 Morpho MT - Used to tell the linker which vtable entries are used.
6374 BFD_RELOC_MT_PCINSN8
6376 Morpho MT - 8 bit immediate relocation.
6379 BFD_RELOC_MSP430_10_PCREL
6381 BFD_RELOC_MSP430_16_PCREL
6385 BFD_RELOC_MSP430_16_PCREL_BYTE
6387 BFD_RELOC_MSP430_16_BYTE
6389 BFD_RELOC_MSP430_2X_PCREL
6391 BFD_RELOC_MSP430_RL_PCREL
6393 BFD_RELOC_MSP430_ABS8
6395 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6397 BFD_RELOC_MSP430X_PCR20_EXT_DST
6399 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6401 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6403 BFD_RELOC_MSP430X_ABS20_EXT_DST
6405 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6407 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6409 BFD_RELOC_MSP430X_ABS20_ADR_DST
6411 BFD_RELOC_MSP430X_PCR16
6413 BFD_RELOC_MSP430X_PCR20_CALL
6415 BFD_RELOC_MSP430X_ABS16
6417 BFD_RELOC_MSP430_ABS_HI16
6419 BFD_RELOC_MSP430_PREL31
6421 BFD_RELOC_MSP430_SYM_DIFF
6423 msp430 specific relocation codes
6430 BFD_RELOC_NIOS2_CALL26
6432 BFD_RELOC_NIOS2_IMM5
6434 BFD_RELOC_NIOS2_CACHE_OPX
6436 BFD_RELOC_NIOS2_IMM6
6438 BFD_RELOC_NIOS2_IMM8
6440 BFD_RELOC_NIOS2_HI16
6442 BFD_RELOC_NIOS2_LO16
6444 BFD_RELOC_NIOS2_HIADJ16
6446 BFD_RELOC_NIOS2_GPREL
6448 BFD_RELOC_NIOS2_UJMP
6450 BFD_RELOC_NIOS2_CJMP
6452 BFD_RELOC_NIOS2_CALLR
6454 BFD_RELOC_NIOS2_ALIGN
6456 BFD_RELOC_NIOS2_GOT16
6458 BFD_RELOC_NIOS2_CALL16
6460 BFD_RELOC_NIOS2_GOTOFF_LO
6462 BFD_RELOC_NIOS2_GOTOFF_HA
6464 BFD_RELOC_NIOS2_PCREL_LO
6466 BFD_RELOC_NIOS2_PCREL_HA
6468 BFD_RELOC_NIOS2_TLS_GD16
6470 BFD_RELOC_NIOS2_TLS_LDM16
6472 BFD_RELOC_NIOS2_TLS_LDO16
6474 BFD_RELOC_NIOS2_TLS_IE16
6476 BFD_RELOC_NIOS2_TLS_LE16
6478 BFD_RELOC_NIOS2_TLS_DTPMOD
6480 BFD_RELOC_NIOS2_TLS_DTPREL
6482 BFD_RELOC_NIOS2_TLS_TPREL
6484 BFD_RELOC_NIOS2_COPY
6486 BFD_RELOC_NIOS2_GLOB_DAT
6488 BFD_RELOC_NIOS2_JUMP_SLOT
6490 BFD_RELOC_NIOS2_RELATIVE
6492 BFD_RELOC_NIOS2_GOTOFF
6494 BFD_RELOC_NIOS2_CALL26_NOAT
6496 BFD_RELOC_NIOS2_GOT_LO
6498 BFD_RELOC_NIOS2_GOT_HA
6500 BFD_RELOC_NIOS2_CALL_LO
6502 BFD_RELOC_NIOS2_CALL_HA
6504 BFD_RELOC_NIOS2_R2_S12
6506 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6508 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6510 BFD_RELOC_NIOS2_R2_T1I7_2
6512 BFD_RELOC_NIOS2_R2_T2I4
6514 BFD_RELOC_NIOS2_R2_T2I4_1
6516 BFD_RELOC_NIOS2_R2_T2I4_2
6518 BFD_RELOC_NIOS2_R2_X1I7_2
6520 BFD_RELOC_NIOS2_R2_X2L5
6522 BFD_RELOC_NIOS2_R2_F1I5_2
6524 BFD_RELOC_NIOS2_R2_L5I4X1
6526 BFD_RELOC_NIOS2_R2_T1X1I6
6528 BFD_RELOC_NIOS2_R2_T1X1I6_2
6530 Relocations used by the Altera Nios II core.
6535 PRU LDI 16-bit unsigned data-memory relocation.
6537 BFD_RELOC_PRU_U16_PMEMIMM
6539 PRU LDI 16-bit unsigned instruction-memory relocation.
6543 PRU relocation for two consecutive LDI load instructions that load a
6544 32 bit value into a register. If the higher bits are all zero, then
6545 the second instruction may be relaxed.
6547 BFD_RELOC_PRU_S10_PCREL
6549 PRU QBBx 10-bit signed PC-relative relocation.
6551 BFD_RELOC_PRU_U8_PCREL
6553 PRU 8-bit unsigned relocation used for the LOOP instruction.
6555 BFD_RELOC_PRU_32_PMEM
6557 BFD_RELOC_PRU_16_PMEM
6559 PRU Program Memory relocations. Used to convert from byte addressing to
6560 32-bit word addressing.
6562 BFD_RELOC_PRU_GNU_DIFF8
6564 BFD_RELOC_PRU_GNU_DIFF16
6566 BFD_RELOC_PRU_GNU_DIFF32
6568 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6570 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6572 PRU relocations to mark the difference of two local symbols.
6573 These are only needed to support linker relaxation and can be ignored
6574 when not relaxing. The field is set to the value of the difference
6575 assuming no relaxation. The relocation encodes the position of the
6576 second symbol so the linker can determine whether to adjust the field
6577 value. The PMEM variants encode the word difference, instead of byte
6578 difference between symbols.
6581 BFD_RELOC_IQ2000_OFFSET_16
6583 BFD_RELOC_IQ2000_OFFSET_21
6585 BFD_RELOC_IQ2000_UHI16
6590 BFD_RELOC_XTENSA_RTLD
6592 Special Xtensa relocation used only by PLT entries in ELF shared
6593 objects to indicate that the runtime linker should set the value
6594 to one of its own internal functions or data structures.
6596 BFD_RELOC_XTENSA_GLOB_DAT
6598 BFD_RELOC_XTENSA_JMP_SLOT
6600 BFD_RELOC_XTENSA_RELATIVE
6602 Xtensa relocations for ELF shared objects.
6604 BFD_RELOC_XTENSA_PLT
6606 Xtensa relocation used in ELF object files for symbols that may require
6607 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6609 BFD_RELOC_XTENSA_DIFF8
6611 BFD_RELOC_XTENSA_DIFF16
6613 BFD_RELOC_XTENSA_DIFF32
6615 Xtensa relocations to mark the difference of two local symbols.
6616 These are only needed to support linker relaxation and can be ignored
6617 when not relaxing. The field is set to the value of the difference
6618 assuming no relaxation. The relocation encodes the position of the
6619 first symbol so the linker can determine whether to adjust the field
6622 BFD_RELOC_XTENSA_SLOT0_OP
6624 BFD_RELOC_XTENSA_SLOT1_OP
6626 BFD_RELOC_XTENSA_SLOT2_OP
6628 BFD_RELOC_XTENSA_SLOT3_OP
6630 BFD_RELOC_XTENSA_SLOT4_OP
6632 BFD_RELOC_XTENSA_SLOT5_OP
6634 BFD_RELOC_XTENSA_SLOT6_OP
6636 BFD_RELOC_XTENSA_SLOT7_OP
6638 BFD_RELOC_XTENSA_SLOT8_OP
6640 BFD_RELOC_XTENSA_SLOT9_OP
6642 BFD_RELOC_XTENSA_SLOT10_OP
6644 BFD_RELOC_XTENSA_SLOT11_OP
6646 BFD_RELOC_XTENSA_SLOT12_OP
6648 BFD_RELOC_XTENSA_SLOT13_OP
6650 BFD_RELOC_XTENSA_SLOT14_OP
6652 Generic Xtensa relocations for instruction operands. Only the slot
6653 number is encoded in the relocation. The relocation applies to the
6654 last PC-relative immediate operand, or if there are no PC-relative
6655 immediates, to the last immediate operand.
6657 BFD_RELOC_XTENSA_SLOT0_ALT
6659 BFD_RELOC_XTENSA_SLOT1_ALT
6661 BFD_RELOC_XTENSA_SLOT2_ALT
6663 BFD_RELOC_XTENSA_SLOT3_ALT
6665 BFD_RELOC_XTENSA_SLOT4_ALT
6667 BFD_RELOC_XTENSA_SLOT5_ALT
6669 BFD_RELOC_XTENSA_SLOT6_ALT
6671 BFD_RELOC_XTENSA_SLOT7_ALT
6673 BFD_RELOC_XTENSA_SLOT8_ALT
6675 BFD_RELOC_XTENSA_SLOT9_ALT
6677 BFD_RELOC_XTENSA_SLOT10_ALT
6679 BFD_RELOC_XTENSA_SLOT11_ALT
6681 BFD_RELOC_XTENSA_SLOT12_ALT
6683 BFD_RELOC_XTENSA_SLOT13_ALT
6685 BFD_RELOC_XTENSA_SLOT14_ALT
6687 Alternate Xtensa relocations. Only the slot is encoded in the
6688 relocation. The meaning of these relocations is opcode-specific.
6690 BFD_RELOC_XTENSA_OP0
6692 BFD_RELOC_XTENSA_OP1
6694 BFD_RELOC_XTENSA_OP2
6696 Xtensa relocations for backward compatibility. These have all been
6697 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6699 BFD_RELOC_XTENSA_ASM_EXPAND
6701 Xtensa relocation to mark that the assembler expanded the
6702 instructions from an original target. The expansion size is
6703 encoded in the reloc size.
6705 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6707 Xtensa relocation to mark that the linker should simplify
6708 assembler-expanded instructions. This is commonly used
6709 internally by the linker after analysis of a
6710 BFD_RELOC_XTENSA_ASM_EXPAND.
6712 BFD_RELOC_XTENSA_TLSDESC_FN
6714 BFD_RELOC_XTENSA_TLSDESC_ARG
6716 BFD_RELOC_XTENSA_TLS_DTPOFF
6718 BFD_RELOC_XTENSA_TLS_TPOFF
6720 BFD_RELOC_XTENSA_TLS_FUNC
6722 BFD_RELOC_XTENSA_TLS_ARG
6724 BFD_RELOC_XTENSA_TLS_CALL
6726 Xtensa TLS relocations.
6731 8 bit signed offset in (ix+d) or (iy+d).
6749 BFD_RELOC_LM32_BRANCH
6751 BFD_RELOC_LM32_16_GOT
6753 BFD_RELOC_LM32_GOTOFF_HI16
6755 BFD_RELOC_LM32_GOTOFF_LO16
6759 BFD_RELOC_LM32_GLOB_DAT
6761 BFD_RELOC_LM32_JMP_SLOT
6763 BFD_RELOC_LM32_RELATIVE
6765 Lattice Mico32 relocations.
6768 BFD_RELOC_MACH_O_SECTDIFF
6770 Difference between two section addreses. Must be followed by a
6771 BFD_RELOC_MACH_O_PAIR.
6773 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6775 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6777 BFD_RELOC_MACH_O_PAIR
6779 Pair of relocation. Contains the first symbol.
6781 BFD_RELOC_MACH_O_SUBTRACTOR32
6783 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6785 BFD_RELOC_MACH_O_SUBTRACTOR64
6787 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6790 BFD_RELOC_MACH_O_X86_64_BRANCH32
6792 BFD_RELOC_MACH_O_X86_64_BRANCH8
6794 PCREL relocations. They are marked as branch to create PLT entry if
6797 BFD_RELOC_MACH_O_X86_64_GOT
6799 Used when referencing a GOT entry.
6801 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6803 Used when loading a GOT entry with movq. It is specially marked so that
6804 the linker could optimize the movq to a leaq if possible.
6806 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6808 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6810 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6812 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6814 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6816 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6820 BFD_RELOC_MACH_O_ARM64_ADDEND
6822 Addend for PAGE or PAGEOFF.
6824 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6826 Relative offset to page of GOT slot.
6828 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6830 Relative offset within page of GOT slot.
6832 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6834 Address of a GOT entry.
6837 BFD_RELOC_MICROBLAZE_32_LO
6839 This is a 32 bit reloc for the microblaze that stores the
6840 low 16 bits of a value
6842 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6844 This is a 32 bit pc-relative reloc for the microblaze that
6845 stores the low 16 bits of a value
6847 BFD_RELOC_MICROBLAZE_32_ROSDA
6849 This is a 32 bit reloc for the microblaze that stores a
6850 value relative to the read-only small data area anchor
6852 BFD_RELOC_MICROBLAZE_32_RWSDA
6854 This is a 32 bit reloc for the microblaze that stores a
6855 value relative to the read-write small data area anchor
6857 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6859 This is a 32 bit reloc for the microblaze to handle
6860 expressions of the form "Symbol Op Symbol"
6862 BFD_RELOC_MICROBLAZE_64_NONE
6864 This is a 64 bit reloc that stores the 32 bit pc relative
6865 value in two words (with an imm instruction). No relocation is
6866 done here - only used for relaxing
6868 BFD_RELOC_MICROBLAZE_64_GOTPC
6870 This is a 64 bit reloc that stores the 32 bit pc relative
6871 value in two words (with an imm instruction). The relocation is
6872 PC-relative GOT offset
6874 BFD_RELOC_MICROBLAZE_64_GOT
6876 This is a 64 bit reloc that stores the 32 bit pc relative
6877 value in two words (with an imm instruction). The relocation is
6880 BFD_RELOC_MICROBLAZE_64_PLT
6882 This is a 64 bit reloc that stores the 32 bit pc relative
6883 value in two words (with an imm instruction). The relocation is
6884 PC-relative offset into PLT
6886 BFD_RELOC_MICROBLAZE_64_GOTOFF
6888 This is a 64 bit reloc that stores the 32 bit GOT relative
6889 value in two words (with an imm instruction). The relocation is
6890 relative offset from _GLOBAL_OFFSET_TABLE_
6892 BFD_RELOC_MICROBLAZE_32_GOTOFF
6894 This is a 32 bit reloc that stores the 32 bit GOT relative
6895 value in a word. The relocation is relative offset from
6896 _GLOBAL_OFFSET_TABLE_
6898 BFD_RELOC_MICROBLAZE_COPY
6900 This is used to tell the dynamic linker to copy the value out of
6901 the dynamic object into the runtime process image.
6903 BFD_RELOC_MICROBLAZE_64_TLS
6907 BFD_RELOC_MICROBLAZE_64_TLSGD
6909 This is a 64 bit reloc that stores the 32 bit GOT relative value
6910 of the GOT TLS GD info entry in two words (with an imm instruction). The
6911 relocation is GOT offset.
6913 BFD_RELOC_MICROBLAZE_64_TLSLD
6915 This is a 64 bit reloc that stores the 32 bit GOT relative value
6916 of the GOT TLS LD info entry in two words (with an imm instruction). The
6917 relocation is GOT offset.
6919 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6921 This is a 32 bit reloc that stores the Module ID to GOT(n).
6923 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6925 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6927 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6929 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6932 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6934 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6935 to two words (uses imm instruction).
6937 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6939 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6940 to two words (uses imm instruction).
6943 BFD_RELOC_AARCH64_RELOC_START
6945 AArch64 pseudo relocation code to mark the start of the AArch64
6946 relocation enumerators. N.B. the order of the enumerators is
6947 important as several tables in the AArch64 bfd backend are indexed
6948 by these enumerators; make sure they are all synced.
6950 BFD_RELOC_AARCH64_NULL
6952 Deprecated AArch64 null relocation code.
6954 BFD_RELOC_AARCH64_NONE
6956 AArch64 null relocation code.
6958 BFD_RELOC_AARCH64_64
6960 BFD_RELOC_AARCH64_32
6962 BFD_RELOC_AARCH64_16
6964 Basic absolute relocations of N bits. These are equivalent to
6965 BFD_RELOC_N and they were added to assist the indexing of the howto
6968 BFD_RELOC_AARCH64_64_PCREL
6970 BFD_RELOC_AARCH64_32_PCREL
6972 BFD_RELOC_AARCH64_16_PCREL
6974 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6975 and they were added to assist the indexing of the howto table.
6977 BFD_RELOC_AARCH64_MOVW_G0
6979 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6980 of an unsigned address/value.
6982 BFD_RELOC_AARCH64_MOVW_G0_NC
6984 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6985 an address/value. No overflow checking.
6987 BFD_RELOC_AARCH64_MOVW_G1
6989 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6990 of an unsigned address/value.
6992 BFD_RELOC_AARCH64_MOVW_G1_NC
6994 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6995 of an address/value. No overflow checking.
6997 BFD_RELOC_AARCH64_MOVW_G2
6999 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7000 of an unsigned address/value.
7002 BFD_RELOC_AARCH64_MOVW_G2_NC
7004 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7005 of an address/value. No overflow checking.
7007 BFD_RELOC_AARCH64_MOVW_G3
7009 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7010 of a signed or unsigned address/value.
7012 BFD_RELOC_AARCH64_MOVW_G0_S
7014 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7015 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7018 BFD_RELOC_AARCH64_MOVW_G1_S
7020 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7021 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7024 BFD_RELOC_AARCH64_MOVW_G2_S
7026 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7027 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7030 BFD_RELOC_AARCH64_LD_LO19_PCREL
7032 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7033 offset. The lowest two bits must be zero and are not stored in the
7034 instruction, giving a 21 bit signed byte offset.
7036 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7038 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7040 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7042 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7043 offset, giving a 4KB aligned page base address.
7045 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7047 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7048 offset, giving a 4KB aligned page base address, but with no overflow
7051 BFD_RELOC_AARCH64_ADD_LO12
7053 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7054 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7056 BFD_RELOC_AARCH64_LDST8_LO12
7058 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7059 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7061 BFD_RELOC_AARCH64_TSTBR14
7063 AArch64 14 bit pc-relative test bit and branch.
7064 The lowest two bits must be zero and are not stored in the instruction,
7065 giving a 16 bit signed byte offset.
7067 BFD_RELOC_AARCH64_BRANCH19
7069 AArch64 19 bit pc-relative conditional branch and compare & branch.
7070 The lowest two bits must be zero and are not stored in the instruction,
7071 giving a 21 bit signed byte offset.
7073 BFD_RELOC_AARCH64_JUMP26
7075 AArch64 26 bit pc-relative unconditional branch.
7076 The lowest two bits must be zero and are not stored in the instruction,
7077 giving a 28 bit signed byte offset.
7079 BFD_RELOC_AARCH64_CALL26
7081 AArch64 26 bit pc-relative unconditional branch and link.
7082 The lowest two bits must be zero and are not stored in the instruction,
7083 giving a 28 bit signed byte offset.
7085 BFD_RELOC_AARCH64_LDST16_LO12
7087 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7088 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7090 BFD_RELOC_AARCH64_LDST32_LO12
7092 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7093 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7095 BFD_RELOC_AARCH64_LDST64_LO12
7097 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7098 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7100 BFD_RELOC_AARCH64_LDST128_LO12
7102 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7103 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7105 BFD_RELOC_AARCH64_GOT_LD_PREL19
7107 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7108 offset of the global offset table entry for a symbol. The lowest two
7109 bits must be zero and are not stored in the instruction, giving a 21
7110 bit signed byte offset. This relocation type requires signed overflow
7113 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7115 Get to the page base of the global offset table entry for a symbol as
7116 part of an ADRP instruction using a 21 bit PC relative value.Used in
7117 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7119 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7121 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7122 the GOT entry for this symbol. Used in conjunction with
7123 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
7125 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7127 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7128 the GOT entry for this symbol. Used in conjunction with
7129 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
7131 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7133 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7134 for this symbol. Valid in LP64 ABI only.
7136 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7138 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7139 for this symbol. Valid in LP64 ABI only.
7141 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7143 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7144 the GOT entry for this symbol. Valid in LP64 ABI only.
7146 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7148 Scaled 14 bit byte offset to the page base of the global offset table.
7150 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7152 Scaled 15 bit byte offset to the page base of the global offset table.
7154 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7156 Get to the page base of the global offset table entry for a symbols
7157 tls_index structure as part of an adrp instruction using a 21 bit PC
7158 relative value. Used in conjunction with
7159 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7161 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7163 AArch64 TLS General Dynamic
7165 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7167 Unsigned 12 bit byte offset to global offset table entry for a symbols
7168 tls_index structure. Used in conjunction with
7169 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7171 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7173 AArch64 TLS General Dynamic relocation.
7175 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7177 AArch64 TLS General Dynamic relocation.
7179 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7181 AArch64 TLS INITIAL EXEC relocation.
7183 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7185 AArch64 TLS INITIAL EXEC relocation.
7187 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7189 AArch64 TLS INITIAL EXEC relocation.
7191 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7193 AArch64 TLS INITIAL EXEC relocation.
7195 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7197 AArch64 TLS INITIAL EXEC relocation.
7199 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7201 AArch64 TLS INITIAL EXEC relocation.
7203 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7205 bit[23:12] of byte offset to module TLS base address.
7207 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7209 Unsigned 12 bit byte offset to module TLS base address.
7211 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7213 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7215 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7217 Unsigned 12 bit byte offset to global offset table entry for a symbols
7218 tls_index structure. Used in conjunction with
7219 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7221 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7223 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7226 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7228 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7230 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7232 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7235 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7237 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7239 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7241 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7244 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7246 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7248 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7250 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7253 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7255 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7257 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7259 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7262 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7264 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7266 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7268 bit[15:0] of byte offset to module TLS base address.
7270 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7272 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7274 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7276 bit[31:16] of byte offset to module TLS base address.
7278 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7280 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7282 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7284 bit[47:32] of byte offset to module TLS base address.
7286 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7288 AArch64 TLS LOCAL EXEC relocation.
7290 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7292 AArch64 TLS LOCAL EXEC relocation.
7294 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7296 AArch64 TLS LOCAL EXEC relocation.
7298 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7300 AArch64 TLS LOCAL EXEC relocation.
7302 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7304 AArch64 TLS LOCAL EXEC relocation.
7306 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7308 AArch64 TLS LOCAL EXEC relocation.
7310 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7312 AArch64 TLS LOCAL EXEC relocation.
7314 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7316 AArch64 TLS LOCAL EXEC relocation.
7318 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7320 AArch64 TLS DESC relocation.
7322 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7324 AArch64 TLS DESC relocation.
7326 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7328 AArch64 TLS DESC relocation.
7330 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7332 AArch64 TLS DESC relocation.
7334 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7336 AArch64 TLS DESC relocation.
7338 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7340 AArch64 TLS DESC relocation.
7342 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7344 AArch64 TLS DESC relocation.
7346 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7348 AArch64 TLS DESC relocation.
7350 BFD_RELOC_AARCH64_TLSDESC_LDR
7352 AArch64 TLS DESC relocation.
7354 BFD_RELOC_AARCH64_TLSDESC_ADD
7356 AArch64 TLS DESC relocation.
7358 BFD_RELOC_AARCH64_TLSDESC_CALL
7360 AArch64 TLS DESC relocation.
7362 BFD_RELOC_AARCH64_COPY
7364 AArch64 TLS relocation.
7366 BFD_RELOC_AARCH64_GLOB_DAT
7368 AArch64 TLS relocation.
7370 BFD_RELOC_AARCH64_JUMP_SLOT
7372 AArch64 TLS relocation.
7374 BFD_RELOC_AARCH64_RELATIVE
7376 AArch64 TLS relocation.
7378 BFD_RELOC_AARCH64_TLS_DTPMOD
7380 AArch64 TLS relocation.
7382 BFD_RELOC_AARCH64_TLS_DTPREL
7384 AArch64 TLS relocation.
7386 BFD_RELOC_AARCH64_TLS_TPREL
7388 AArch64 TLS relocation.
7390 BFD_RELOC_AARCH64_TLSDESC
7392 AArch64 TLS relocation.
7394 BFD_RELOC_AARCH64_IRELATIVE
7396 AArch64 support for STT_GNU_IFUNC.
7398 BFD_RELOC_AARCH64_RELOC_END
7400 AArch64 pseudo relocation code to mark the end of the AArch64
7401 relocation enumerators that have direct mapping to ELF reloc codes.
7402 There are a few more enumerators after this one; those are mainly
7403 used by the AArch64 assembler for the internal fixup or to select
7404 one of the above enumerators.
7406 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7408 AArch64 pseudo relocation code to be used internally by the AArch64
7409 assembler and not (currently) written to any object files.
7411 BFD_RELOC_AARCH64_LDST_LO12
7413 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7414 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7416 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7418 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7419 used internally by the AArch64 assembler and not (currently) written to
7422 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7424 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7426 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7428 AArch64 pseudo relocation code to be used internally by the AArch64
7429 assembler and not (currently) written to any object files.
7431 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7433 AArch64 pseudo relocation code to be used internally by the AArch64
7434 assembler and not (currently) written to any object files.
7436 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7438 AArch64 pseudo relocation code to be used internally by the AArch64
7439 assembler and not (currently) written to any object files.
7441 BFD_RELOC_TILEPRO_COPY
7443 BFD_RELOC_TILEPRO_GLOB_DAT
7445 BFD_RELOC_TILEPRO_JMP_SLOT
7447 BFD_RELOC_TILEPRO_RELATIVE
7449 BFD_RELOC_TILEPRO_BROFF_X1
7451 BFD_RELOC_TILEPRO_JOFFLONG_X1
7453 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7455 BFD_RELOC_TILEPRO_IMM8_X0
7457 BFD_RELOC_TILEPRO_IMM8_Y0
7459 BFD_RELOC_TILEPRO_IMM8_X1
7461 BFD_RELOC_TILEPRO_IMM8_Y1
7463 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7465 BFD_RELOC_TILEPRO_MT_IMM15_X1
7467 BFD_RELOC_TILEPRO_MF_IMM15_X1
7469 BFD_RELOC_TILEPRO_IMM16_X0
7471 BFD_RELOC_TILEPRO_IMM16_X1
7473 BFD_RELOC_TILEPRO_IMM16_X0_LO
7475 BFD_RELOC_TILEPRO_IMM16_X1_LO
7477 BFD_RELOC_TILEPRO_IMM16_X0_HI
7479 BFD_RELOC_TILEPRO_IMM16_X1_HI
7481 BFD_RELOC_TILEPRO_IMM16_X0_HA
7483 BFD_RELOC_TILEPRO_IMM16_X1_HA
7485 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7487 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7489 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7491 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7493 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7495 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7497 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7499 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7501 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7503 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7505 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7507 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7509 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7511 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7513 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7515 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7517 BFD_RELOC_TILEPRO_MMSTART_X0
7519 BFD_RELOC_TILEPRO_MMEND_X0
7521 BFD_RELOC_TILEPRO_MMSTART_X1
7523 BFD_RELOC_TILEPRO_MMEND_X1
7525 BFD_RELOC_TILEPRO_SHAMT_X0
7527 BFD_RELOC_TILEPRO_SHAMT_X1
7529 BFD_RELOC_TILEPRO_SHAMT_Y0
7531 BFD_RELOC_TILEPRO_SHAMT_Y1
7533 BFD_RELOC_TILEPRO_TLS_GD_CALL
7535 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7537 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7539 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7541 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7543 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7545 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7547 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7549 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7551 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7553 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7555 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7557 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7559 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7561 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7563 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7565 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7567 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7569 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7571 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7573 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7575 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7577 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7579 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7581 BFD_RELOC_TILEPRO_TLS_TPOFF32
7583 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7585 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7587 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7589 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7591 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7593 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7595 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7597 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7599 Tilera TILEPro Relocations.
7601 BFD_RELOC_TILEGX_HW0
7603 BFD_RELOC_TILEGX_HW1
7605 BFD_RELOC_TILEGX_HW2
7607 BFD_RELOC_TILEGX_HW3
7609 BFD_RELOC_TILEGX_HW0_LAST
7611 BFD_RELOC_TILEGX_HW1_LAST
7613 BFD_RELOC_TILEGX_HW2_LAST
7615 BFD_RELOC_TILEGX_COPY
7617 BFD_RELOC_TILEGX_GLOB_DAT
7619 BFD_RELOC_TILEGX_JMP_SLOT
7621 BFD_RELOC_TILEGX_RELATIVE
7623 BFD_RELOC_TILEGX_BROFF_X1
7625 BFD_RELOC_TILEGX_JUMPOFF_X1
7627 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7629 BFD_RELOC_TILEGX_IMM8_X0
7631 BFD_RELOC_TILEGX_IMM8_Y0
7633 BFD_RELOC_TILEGX_IMM8_X1
7635 BFD_RELOC_TILEGX_IMM8_Y1
7637 BFD_RELOC_TILEGX_DEST_IMM8_X1
7639 BFD_RELOC_TILEGX_MT_IMM14_X1
7641 BFD_RELOC_TILEGX_MF_IMM14_X1
7643 BFD_RELOC_TILEGX_MMSTART_X0
7645 BFD_RELOC_TILEGX_MMEND_X0
7647 BFD_RELOC_TILEGX_SHAMT_X0
7649 BFD_RELOC_TILEGX_SHAMT_X1
7651 BFD_RELOC_TILEGX_SHAMT_Y0
7653 BFD_RELOC_TILEGX_SHAMT_Y1
7655 BFD_RELOC_TILEGX_IMM16_X0_HW0
7657 BFD_RELOC_TILEGX_IMM16_X1_HW0
7659 BFD_RELOC_TILEGX_IMM16_X0_HW1
7661 BFD_RELOC_TILEGX_IMM16_X1_HW1
7663 BFD_RELOC_TILEGX_IMM16_X0_HW2
7665 BFD_RELOC_TILEGX_IMM16_X1_HW2
7667 BFD_RELOC_TILEGX_IMM16_X0_HW3
7669 BFD_RELOC_TILEGX_IMM16_X1_HW3
7671 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7673 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7675 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7677 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7679 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7681 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7683 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7685 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7687 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7689 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7691 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7693 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7695 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7697 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7699 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7701 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7703 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7705 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7707 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7709 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7711 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7713 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7715 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7717 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7719 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7721 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7723 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7725 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7727 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7729 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7731 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7733 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7735 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7737 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7739 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7741 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7743 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7745 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7747 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7749 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7751 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7753 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7755 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7757 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7759 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7761 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7763 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7765 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7767 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7769 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7771 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7773 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7775 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7777 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7779 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7781 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7783 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7785 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7787 BFD_RELOC_TILEGX_TLS_DTPMOD64
7789 BFD_RELOC_TILEGX_TLS_DTPOFF64
7791 BFD_RELOC_TILEGX_TLS_TPOFF64
7793 BFD_RELOC_TILEGX_TLS_DTPMOD32
7795 BFD_RELOC_TILEGX_TLS_DTPOFF32
7797 BFD_RELOC_TILEGX_TLS_TPOFF32
7799 BFD_RELOC_TILEGX_TLS_GD_CALL
7801 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7803 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7805 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7807 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7809 BFD_RELOC_TILEGX_TLS_IE_LOAD
7811 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7813 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7815 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7817 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7819 Tilera TILE-Gx Relocations.
7822 BFD_RELOC_EPIPHANY_SIMM8
7824 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7826 BFD_RELOC_EPIPHANY_SIMM24
7828 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7830 BFD_RELOC_EPIPHANY_HIGH
7832 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7834 BFD_RELOC_EPIPHANY_LOW
7836 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7838 BFD_RELOC_EPIPHANY_SIMM11
7840 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7842 BFD_RELOC_EPIPHANY_IMM11
7844 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7846 BFD_RELOC_EPIPHANY_IMM8
7848 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7851 BFD_RELOC_VISIUM_HI16
7853 BFD_RELOC_VISIUM_LO16
7855 BFD_RELOC_VISIUM_IM16
7857 BFD_RELOC_VISIUM_REL16
7859 BFD_RELOC_VISIUM_HI16_PCREL
7861 BFD_RELOC_VISIUM_LO16_PCREL
7863 BFD_RELOC_VISIUM_IM16_PCREL
7868 BFD_RELOC_WASM32_LEB128
7870 BFD_RELOC_WASM32_LEB128_GOT
7872 BFD_RELOC_WASM32_LEB128_GOT_CODE
7874 BFD_RELOC_WASM32_LEB128_PLT
7876 BFD_RELOC_WASM32_PLT_INDEX
7878 BFD_RELOC_WASM32_ABS32_CODE
7880 BFD_RELOC_WASM32_COPY
7882 BFD_RELOC_WASM32_CODE_POINTER
7884 BFD_RELOC_WASM32_INDEX
7886 BFD_RELOC_WASM32_PLT_SIG
7888 WebAssembly relocations.
7894 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7899 bfd_reloc_type_lookup
7900 bfd_reloc_name_lookup
7903 reloc_howto_type *bfd_reloc_type_lookup
7904 (bfd *abfd, bfd_reloc_code_real_type code);
7905 reloc_howto_type *bfd_reloc_name_lookup
7906 (bfd *abfd, const char *reloc_name);
7909 Return a pointer to a howto structure which, when
7910 invoked, will perform the relocation @var{code} on data from the
7916 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7918 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
7922 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
7924 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
7927 static reloc_howto_type bfd_howto_32 =
7928 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
7932 bfd_default_reloc_type_lookup
7935 reloc_howto_type *bfd_default_reloc_type_lookup
7936 (bfd *abfd, bfd_reloc_code_real_type code);
7939 Provides a default relocation lookup routine for any architecture.
7944 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7948 case BFD_RELOC_CTOR:
7949 /* The type of reloc used in a ctor, which will be as wide as the
7950 address - so either a 64, 32, or 16 bitter. */
7951 switch (bfd_arch_bits_per_address (abfd))
7957 return &bfd_howto_32;
7973 bfd_get_reloc_code_name
7976 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7979 Provides a printable name for the supplied relocation code.
7980 Useful mainly for printing error messages.
7984 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
7986 if (code > BFD_RELOC_UNUSED)
7988 return bfd_reloc_code_real_names[code];
7993 bfd_generic_relax_section
7996 bfd_boolean bfd_generic_relax_section
7999 struct bfd_link_info *,
8003 Provides default handling for relaxing for back ends which
8008 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
8009 asection *section ATTRIBUTE_UNUSED,
8010 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
8013 if (bfd_link_relocatable (link_info))
8014 (*link_info->callbacks->einfo)
8015 (_("%P%F: --relax and -r may not be used together\n"));
8023 bfd_generic_gc_sections
8026 bfd_boolean bfd_generic_gc_sections
8027 (bfd *, struct bfd_link_info *);
8030 Provides default handling for relaxing for back ends which
8031 don't do section gc -- i.e., does nothing.
8035 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
8036 struct bfd_link_info *info ATTRIBUTE_UNUSED)
8043 bfd_generic_lookup_section_flags
8046 bfd_boolean bfd_generic_lookup_section_flags
8047 (struct bfd_link_info *, struct flag_info *, asection *);
8050 Provides default handling for section flags lookup
8051 -- i.e., does nothing.
8052 Returns FALSE if the section should be omitted, otherwise TRUE.
8056 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
8057 struct flag_info *flaginfo,
8058 asection *section ATTRIBUTE_UNUSED)
8060 if (flaginfo != NULL)
8062 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported.\n"));
8070 bfd_generic_merge_sections
8073 bfd_boolean bfd_generic_merge_sections
8074 (bfd *, struct bfd_link_info *);
8077 Provides default handling for SEC_MERGE section merging for back ends
8078 which don't have SEC_MERGE support -- i.e., does nothing.
8082 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
8083 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
8090 bfd_generic_get_relocated_section_contents
8093 bfd_byte *bfd_generic_get_relocated_section_contents
8095 struct bfd_link_info *link_info,
8096 struct bfd_link_order *link_order,
8098 bfd_boolean relocatable,
8102 Provides default handling of relocation effort for back ends
8103 which can't be bothered to do it efficiently.
8108 bfd_generic_get_relocated_section_contents (bfd *abfd,
8109 struct bfd_link_info *link_info,
8110 struct bfd_link_order *link_order,
8112 bfd_boolean relocatable,
8115 bfd *input_bfd = link_order->u.indirect.section->owner;
8116 asection *input_section = link_order->u.indirect.section;
8118 arelent **reloc_vector;
8121 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
8125 /* Read in the section. */
8126 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
8129 if (reloc_size == 0)
8132 reloc_vector = (arelent **) bfd_malloc (reloc_size);
8133 if (reloc_vector == NULL)
8136 reloc_count = bfd_canonicalize_reloc (input_bfd,
8140 if (reloc_count < 0)
8143 if (reloc_count > 0)
8147 for (parent = reloc_vector; *parent != NULL; parent++)
8149 char *error_message = NULL;
8151 bfd_reloc_status_type r;
8153 symbol = *(*parent)->sym_ptr_ptr;
8154 /* PR ld/19628: A specially crafted input file
8155 can result in a NULL symbol pointer here. */
8158 link_info->callbacks->einfo
8159 /* xgettext:c-format */
8160 (_("%X%P: %B(%A): error: relocation for offset %V has no value\n"),
8161 abfd, input_section, (* parent)->address);
8165 if (symbol->section && discarded_section (symbol->section))
8168 static reloc_howto_type none_howto
8169 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
8170 "unused", FALSE, 0, 0, FALSE);
8172 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
8173 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
8175 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
8176 (*parent)->addend = 0;
8177 (*parent)->howto = &none_howto;
8181 r = bfd_perform_relocation (input_bfd,
8185 relocatable ? abfd : NULL,
8190 asection *os = input_section->output_section;
8192 /* A partial link, so keep the relocs. */
8193 os->orelocation[os->reloc_count] = *parent;
8197 if (r != bfd_reloc_ok)
8201 case bfd_reloc_undefined:
8202 (*link_info->callbacks->undefined_symbol)
8203 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8204 input_bfd, input_section, (*parent)->address, TRUE);
8206 case bfd_reloc_dangerous:
8207 BFD_ASSERT (error_message != NULL);
8208 (*link_info->callbacks->reloc_dangerous)
8209 (link_info, error_message,
8210 input_bfd, input_section, (*parent)->address);
8212 case bfd_reloc_overflow:
8213 (*link_info->callbacks->reloc_overflow)
8215 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8216 (*parent)->howto->name, (*parent)->addend,
8217 input_bfd, input_section, (*parent)->address);
8219 case bfd_reloc_outofrange:
8221 This error can result when processing some partially
8222 complete binaries. Do not abort, but issue an error
8224 link_info->callbacks->einfo
8225 /* xgettext:c-format */
8226 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
8227 abfd, input_section, * parent);
8230 case bfd_reloc_notsupported:
8232 This error can result when processing a corrupt binary.
8233 Do not abort. Issue an error message instead. */
8234 link_info->callbacks->einfo
8235 /* xgettext:c-format */
8236 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
8237 abfd, input_section, * parent);
8241 /* PR 17512; file: 90c2a92e.
8242 Report unexpected results, without aborting. */
8243 link_info->callbacks->einfo
8244 /* xgettext:c-format */
8245 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
8246 abfd, input_section, * parent, r);
8254 free (reloc_vector);
8258 free (reloc_vector);