1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2017 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok - presently
91 . generated only when linking i960 coff files with i960 b.out
92 . symbols. If this type is returned, the error_message argument
93 . to bfd_perform_relocation will be set. *}
96 . bfd_reloc_status_type;
99 .typedef struct reloc_cache_entry
101 . {* A pointer into the canonical table of pointers. *}
102 . struct bfd_symbol **sym_ptr_ptr;
104 . {* offset in section. *}
105 . bfd_size_type address;
107 . {* addend for relocation value. *}
110 . {* Pointer to how to perform the required relocation. *}
111 . reloc_howto_type *howto;
121 Here is a description of each of the fields within an <<arelent>>:
125 The symbol table pointer points to a pointer to the symbol
126 associated with the relocation request. It is the pointer
127 into the table returned by the back end's
128 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
129 referenced through a pointer to a pointer so that tools like
130 the linker can fix up all the symbols of the same name by
131 modifying only one pointer. The relocation routine looks in
132 the symbol and uses the base of the section the symbol is
133 attached to and the value of the symbol as the initial
134 relocation offset. If the symbol pointer is zero, then the
135 section provided is looked up.
139 The <<address>> field gives the offset in bytes from the base of
140 the section data which owns the relocation record to the first
141 byte of relocatable information. The actual data relocated
142 will be relative to this point; for example, a relocation
143 type which modifies the bottom two bytes of a four byte word
144 would not touch the first byte pointed to in a big endian
149 The <<addend>> is a value provided by the back end to be added (!)
150 to the relocation offset. Its interpretation is dependent upon
151 the howto. For example, on the 68k the code:
156 | return foo[0x12345678];
159 Could be compiled into:
162 | moveb @@#12345678,d0
167 This could create a reloc pointing to <<foo>>, but leave the
168 offset in the data, something like:
170 |RELOCATION RECORDS FOR [.text]:
174 |00000000 4e56 fffc ; linkw fp,#-4
175 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
176 |0000000a 49c0 ; extbl d0
177 |0000000c 4e5e ; unlk fp
180 Using coff and an 88k, some instructions don't have enough
181 space in them to represent the full address range, and
182 pointers have to be loaded in two parts. So you'd get something like:
184 | or.u r13,r0,hi16(_foo+0x12345678)
185 | ld.b r2,r13,lo16(_foo+0x12345678)
188 This should create two relocs, both pointing to <<_foo>>, and with
189 0x12340000 in their addend field. The data would consist of:
191 |RELOCATION RECORDS FOR [.text]:
193 |00000002 HVRT16 _foo+0x12340000
194 |00000006 LVRT16 _foo+0x12340000
196 |00000000 5da05678 ; or.u r13,r0,0x5678
197 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
198 |00000008 f400c001 ; jmp r1
200 The relocation routine digs out the value from the data, adds
201 it to the addend to get the original offset, and then adds the
202 value of <<_foo>>. Note that all 32 bits have to be kept around
203 somewhere, to cope with carry from bit 15 to bit 16.
205 One further example is the sparc and the a.out format. The
206 sparc has a similar problem to the 88k, in that some
207 instructions don't have room for an entire offset, but on the
208 sparc the parts are created in odd sized lumps. The designers of
209 the a.out format chose to not use the data within the section
210 for storing part of the offset; all the offset is kept within
211 the reloc. Anything in the data should be ignored.
214 | sethi %hi(_foo+0x12345678),%g2
215 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
219 Both relocs contain a pointer to <<foo>>, and the offsets
222 |RELOCATION RECORDS FOR [.text]:
224 |00000004 HI22 _foo+0x12345678
225 |00000008 LO10 _foo+0x12345678
227 |00000000 9de3bf90 ; save %sp,-112,%sp
228 |00000004 05000000 ; sethi %hi(_foo+0),%g2
229 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
230 |0000000c 81c7e008 ; ret
231 |00000010 81e80000 ; restore
235 The <<howto>> field can be imagined as a
236 relocation instruction. It is a pointer to a structure which
237 contains information on what to do with all of the other
238 information in the reloc record and data section. A back end
239 would normally have a relocation instruction set and turn
240 relocations into pointers to the correct structure on input -
241 but it would be possible to create each howto field on demand.
247 <<enum complain_overflow>>
249 Indicates what sort of overflow checking should be done when
250 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct bfd_symbol; {* Forward declaration. *}
285 .struct reloc_howto_struct
287 . {* The type field has mainly a documentary use - the back end can
288 . do what it wants with it, though normally the back end's
289 . external idea of what a reloc number is stored
290 . in this field. For example, a PC relative word relocation
291 . in a coff environment has the type 023 - because that's
292 . what the outside world calls a R_PCRWORD reloc. *}
295 . {* The value the final relocation is shifted right by. This drops
296 . unwanted data from the relocation. *}
297 . unsigned int rightshift;
299 . {* The size of the item to be relocated. This is *not* a
300 . power-of-two measure. To get the number of bytes operated
301 . on by a type of relocation, use bfd_get_reloc_size. *}
304 . {* The number of bits in the item to be relocated. This is used
305 . when doing overflow checking. *}
306 . unsigned int bitsize;
308 . {* The relocation is relative to the field being relocated. *}
309 . bfd_boolean pc_relative;
311 . {* The bit position of the reloc value in the destination.
312 . The relocated value is left shifted by this amount. *}
313 . unsigned int bitpos;
315 . {* What type of overflow error should be checked for when
317 . enum complain_overflow complain_on_overflow;
319 . {* If this field is non null, then the supplied function is
320 . called rather than the normal function. This allows really
321 . strange relocation methods to be accommodated (e.g., i960 callj
323 . bfd_reloc_status_type (*special_function)
324 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
327 . {* The textual name of the relocation type. *}
330 . {* Some formats record a relocation addend in the section contents
331 . rather than with the relocation. For ELF formats this is the
332 . distinction between USE_REL and USE_RELA (though the code checks
333 . for USE_REL == 1/0). The value of this field is TRUE if the
334 . addend is recorded with the section contents; when performing a
335 . partial link (ld -r) the section contents (the data) will be
336 . modified. The value of this field is FALSE if addends are
337 . recorded with the relocation (in arelent.addend); when performing
338 . a partial link the relocation will be modified.
339 . All relocations for all ELF USE_RELA targets should set this field
340 . to FALSE (values of TRUE should be looked on with suspicion).
341 . However, the converse is not true: not all relocations of all ELF
342 . USE_REL targets set this field to TRUE. Why this is so is peculiar
343 . to each particular target. For relocs that aren't used in partial
344 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
345 . bfd_boolean partial_inplace;
347 . {* src_mask selects the part of the instruction (or data) to be used
348 . in the relocation sum. If the target relocations don't have an
349 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
350 . dst_mask to extract the addend from the section contents. If
351 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
352 . field should be zero. Non-zero values for ELF USE_RELA targets are
353 . bogus as in those cases the value in the dst_mask part of the
354 . section contents should be treated as garbage. *}
357 . {* dst_mask selects which parts of the instruction (or data) are
358 . replaced with a relocated value. *}
361 . {* When some formats create PC relative instructions, they leave
362 . the value of the pc of the place being relocated in the offset
363 . slot of the instruction, so that a PC relative relocation can
364 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
365 . Some formats leave the displacement part of an instruction
366 . empty (e.g., m88k bcs); this flag signals the fact. *}
367 . bfd_boolean pcrel_offset;
377 The HOWTO define is horrible and will go away.
379 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
380 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
383 And will be replaced with the totally magic way. But for the
384 moment, we are compatible, so do it this way.
386 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
387 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
388 . NAME, FALSE, 0, 0, IN)
392 This is used to fill in an empty howto entry in an array.
394 .#define EMPTY_HOWTO(C) \
395 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
396 . NULL, FALSE, 0, 0, FALSE)
400 Helper routine to turn a symbol into a relocation value.
402 .#define HOWTO_PREPARE(relocation, symbol) \
404 . if (symbol != NULL) \
406 . if (bfd_is_com_section (symbol->section)) \
412 . relocation = symbol->value; \
424 unsigned int bfd_get_reloc_size (reloc_howto_type *);
427 For a reloc_howto_type that operates on a fixed number of bytes,
428 this returns the number of bytes operated on.
432 bfd_get_reloc_size (reloc_howto_type *howto)
454 How relocs are tied together in an <<asection>>:
456 .typedef struct relent_chain
459 . struct relent_chain *next;
465 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
466 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
473 bfd_reloc_status_type bfd_check_overflow
474 (enum complain_overflow how,
475 unsigned int bitsize,
476 unsigned int rightshift,
477 unsigned int addrsize,
481 Perform overflow checking on @var{relocation} which has
482 @var{bitsize} significant bits and will be shifted right by
483 @var{rightshift} bits, on a machine with addresses containing
484 @var{addrsize} significant bits. The result is either of
485 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
489 bfd_reloc_status_type
490 bfd_check_overflow (enum complain_overflow how,
491 unsigned int bitsize,
492 unsigned int rightshift,
493 unsigned int addrsize,
496 bfd_vma fieldmask, addrmask, signmask, ss, a;
497 bfd_reloc_status_type flag = bfd_reloc_ok;
499 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
500 we'll be permissive: extra bits in the field mask will
501 automatically extend the address mask for purposes of the
503 fieldmask = N_ONES (bitsize);
504 signmask = ~fieldmask;
505 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
506 a = (relocation & addrmask) >> rightshift;
510 case complain_overflow_dont:
513 case complain_overflow_signed:
514 /* If any sign bits are set, all sign bits must be set. That
515 is, A must be a valid negative address after shifting. */
516 signmask = ~ (fieldmask >> 1);
519 case complain_overflow_bitfield:
520 /* Bitfields are sometimes signed, sometimes unsigned. We
521 explicitly allow an address wrap too, which means a bitfield
522 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
523 if the value has some, but not all, bits set outside the
526 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
527 flag = bfd_reloc_overflow;
530 case complain_overflow_unsigned:
531 /* We have an overflow if the address does not fit in the field. */
532 if ((a & signmask) != 0)
533 flag = bfd_reloc_overflow;
543 /* HOWTO describes a relocation, at offset OCTET. Return whether the
544 relocation field is within SECTION of ABFD. */
547 reloc_offset_in_range (reloc_howto_type *howto, bfd *abfd,
548 asection *section, bfd_size_type octet)
550 bfd_size_type octet_end = bfd_get_section_limit_octets (abfd, section);
551 bfd_size_type reloc_size = bfd_get_reloc_size (howto);
553 /* The reloc field must be contained entirely within the section.
554 Allow zero length fields (marker relocs or NONE relocs where no
555 relocation will be performed) at the end of the section. */
556 return octet <= octet_end && octet + reloc_size <= octet_end;
561 bfd_perform_relocation
564 bfd_reloc_status_type bfd_perform_relocation
566 arelent *reloc_entry,
568 asection *input_section,
570 char **error_message);
573 If @var{output_bfd} is supplied to this function, the
574 generated image will be relocatable; the relocations are
575 copied to the output file after they have been changed to
576 reflect the new state of the world. There are two ways of
577 reflecting the results of partial linkage in an output file:
578 by modifying the output data in place, and by modifying the
579 relocation record. Some native formats (e.g., basic a.out and
580 basic coff) have no way of specifying an addend in the
581 relocation type, so the addend has to go in the output data.
582 This is no big deal since in these formats the output data
583 slot will always be big enough for the addend. Complex reloc
584 types with addends were invented to solve just this problem.
585 The @var{error_message} argument is set to an error message if
586 this return @code{bfd_reloc_dangerous}.
590 bfd_reloc_status_type
591 bfd_perform_relocation (bfd *abfd,
592 arelent *reloc_entry,
594 asection *input_section,
596 char **error_message)
599 bfd_reloc_status_type flag = bfd_reloc_ok;
600 bfd_size_type octets;
601 bfd_vma output_base = 0;
602 reloc_howto_type *howto = reloc_entry->howto;
603 asection *reloc_target_output_section;
606 symbol = *(reloc_entry->sym_ptr_ptr);
608 /* If we are not producing relocatable output, return an error if
609 the symbol is not defined. An undefined weak symbol is
610 considered to have a value of zero (SVR4 ABI, p. 4-27). */
611 if (bfd_is_und_section (symbol->section)
612 && (symbol->flags & BSF_WEAK) == 0
613 && output_bfd == NULL)
614 flag = bfd_reloc_undefined;
616 /* If there is a function supplied to handle this relocation type,
617 call it. It'll return `bfd_reloc_continue' if further processing
619 if (howto && howto->special_function)
621 bfd_reloc_status_type cont;
622 cont = howto->special_function (abfd, reloc_entry, symbol, data,
623 input_section, output_bfd,
625 if (cont != bfd_reloc_continue)
629 if (bfd_is_abs_section (symbol->section)
630 && output_bfd != NULL)
632 reloc_entry->address += input_section->output_offset;
636 /* PR 17512: file: 0f67f69d. */
638 return bfd_reloc_undefined;
640 /* Is the address of the relocation really within the section? */
641 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
642 if (!reloc_offset_in_range (howto, abfd, input_section, octets))
643 return bfd_reloc_outofrange;
645 /* Work out which section the relocation is targeted at and the
646 initial relocation command value. */
648 /* Get symbol value. (Common symbols are special.) */
649 if (bfd_is_com_section (symbol->section))
652 relocation = symbol->value;
654 reloc_target_output_section = symbol->section->output_section;
656 /* Convert input-section-relative symbol value to absolute. */
657 if ((output_bfd && ! howto->partial_inplace)
658 || reloc_target_output_section == NULL)
661 output_base = reloc_target_output_section->vma;
663 relocation += output_base + symbol->section->output_offset;
665 /* Add in supplied addend. */
666 relocation += reloc_entry->addend;
668 /* Here the variable relocation holds the final address of the
669 symbol we are relocating against, plus any addend. */
671 if (howto->pc_relative)
673 /* This is a PC relative relocation. We want to set RELOCATION
674 to the distance between the address of the symbol and the
675 location. RELOCATION is already the address of the symbol.
677 We start by subtracting the address of the section containing
680 If pcrel_offset is set, we must further subtract the position
681 of the location within the section. Some targets arrange for
682 the addend to be the negative of the position of the location
683 within the section; for example, i386-aout does this. For
684 i386-aout, pcrel_offset is FALSE. Some other targets do not
685 include the position of the location; for example, m88kbcs,
686 or ELF. For those targets, pcrel_offset is TRUE.
688 If we are producing relocatable output, then we must ensure
689 that this reloc will be correctly computed when the final
690 relocation is done. If pcrel_offset is FALSE we want to wind
691 up with the negative of the location within the section,
692 which means we must adjust the existing addend by the change
693 in the location within the section. If pcrel_offset is TRUE
694 we do not want to adjust the existing addend at all.
696 FIXME: This seems logical to me, but for the case of
697 producing relocatable output it is not what the code
698 actually does. I don't want to change it, because it seems
699 far too likely that something will break. */
702 input_section->output_section->vma + input_section->output_offset;
704 if (howto->pcrel_offset)
705 relocation -= reloc_entry->address;
708 if (output_bfd != NULL)
710 if (! howto->partial_inplace)
712 /* This is a partial relocation, and we want to apply the relocation
713 to the reloc entry rather than the raw data. Modify the reloc
714 inplace to reflect what we now know. */
715 reloc_entry->addend = relocation;
716 reloc_entry->address += input_section->output_offset;
721 /* This is a partial relocation, but inplace, so modify the
724 If we've relocated with a symbol with a section, change
725 into a ref to the section belonging to the symbol. */
727 reloc_entry->address += input_section->output_offset;
730 if (abfd->xvec->flavour == bfd_target_coff_flavour
731 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
732 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
734 /* For m68k-coff, the addend was being subtracted twice during
735 relocation with -r. Removing the line below this comment
736 fixes that problem; see PR 2953.
738 However, Ian wrote the following, regarding removing the line below,
739 which explains why it is still enabled: --djm
741 If you put a patch like that into BFD you need to check all the COFF
742 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
743 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
744 problem in a different way. There may very well be a reason that the
745 code works as it does.
747 Hmmm. The first obvious point is that bfd_perform_relocation should
748 not have any tests that depend upon the flavour. It's seem like
749 entirely the wrong place for such a thing. The second obvious point
750 is that the current code ignores the reloc addend when producing
751 relocatable output for COFF. That's peculiar. In fact, I really
752 have no idea what the point of the line you want to remove is.
754 A typical COFF reloc subtracts the old value of the symbol and adds in
755 the new value to the location in the object file (if it's a pc
756 relative reloc it adds the difference between the symbol value and the
757 location). When relocating we need to preserve that property.
759 BFD handles this by setting the addend to the negative of the old
760 value of the symbol. Unfortunately it handles common symbols in a
761 non-standard way (it doesn't subtract the old value) but that's a
762 different story (we can't change it without losing backward
763 compatibility with old object files) (coff-i386 does subtract the old
764 value, to be compatible with existing coff-i386 targets, like SCO).
766 So everything works fine when not producing relocatable output. When
767 we are producing relocatable output, logically we should do exactly
768 what we do when not producing relocatable output. Therefore, your
769 patch is correct. In fact, it should probably always just set
770 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
771 add the value into the object file. This won't hurt the COFF code,
772 which doesn't use the addend; I'm not sure what it will do to other
773 formats (the thing to check for would be whether any formats both use
774 the addend and set partial_inplace).
776 When I wanted to make coff-i386 produce relocatable output, I ran
777 into the problem that you are running into: I wanted to remove that
778 line. Rather than risk it, I made the coff-i386 relocs use a special
779 function; it's coff_i386_reloc in coff-i386.c. The function
780 specifically adds the addend field into the object file, knowing that
781 bfd_perform_relocation is not going to. If you remove that line, then
782 coff-i386.c will wind up adding the addend field in twice. It's
783 trivial to fix; it just needs to be done.
785 The problem with removing the line is just that it may break some
786 working code. With BFD it's hard to be sure of anything. The right
787 way to deal with this is simply to build and test at least all the
788 supported COFF targets. It should be straightforward if time and disk
789 space consuming. For each target:
791 2) generate some executable, and link it using -r (I would
792 probably use paranoia.o and link against newlib/libc.a, which
793 for all the supported targets would be available in
794 /usr/cygnus/progressive/H-host/target/lib/libc.a).
795 3) make the change to reloc.c
796 4) rebuild the linker
798 6) if the resulting object files are the same, you have at least
800 7) if they are different you have to figure out which version is
803 relocation -= reloc_entry->addend;
804 reloc_entry->addend = 0;
808 reloc_entry->addend = relocation;
813 /* FIXME: This overflow checking is incomplete, because the value
814 might have overflowed before we get here. For a correct check we
815 need to compute the value in a size larger than bitsize, but we
816 can't reasonably do that for a reloc the same size as a host
818 FIXME: We should also do overflow checking on the result after
819 adding in the value contained in the object file. */
820 if (howto->complain_on_overflow != complain_overflow_dont
821 && flag == bfd_reloc_ok)
822 flag = bfd_check_overflow (howto->complain_on_overflow,
825 bfd_arch_bits_per_address (abfd),
828 /* Either we are relocating all the way, or we don't want to apply
829 the relocation to the reloc entry (probably because there isn't
830 any room in the output format to describe addends to relocs). */
832 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
833 (OSF version 1.3, compiler version 3.11). It miscompiles the
847 x <<= (unsigned long) s.i0;
851 printf ("succeeded (%lx)\n", x);
855 relocation >>= (bfd_vma) howto->rightshift;
857 /* Shift everything up to where it's going to be used. */
858 relocation <<= (bfd_vma) howto->bitpos;
860 /* Wait for the day when all have the mask in them. */
863 i instruction to be left alone
864 o offset within instruction
865 r relocation offset to apply
874 (( i i i i i o o o o o from bfd_get<size>
875 and S S S S S) to get the size offset we want
876 + r r r r r r r r r r) to get the final value to place
877 and D D D D D to chop to right size
878 -----------------------
881 ( i i i i i o o o o o from bfd_get<size>
882 and N N N N N ) get instruction
883 -----------------------
889 -----------------------
890 = R R R R R R R R R R put into bfd_put<size>
894 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
900 char x = bfd_get_8 (abfd, (char *) data + octets);
902 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
908 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
910 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
915 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
917 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
922 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
923 relocation = -relocation;
925 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
931 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
932 relocation = -relocation;
934 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
945 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
947 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
954 return bfd_reloc_other;
962 bfd_install_relocation
965 bfd_reloc_status_type bfd_install_relocation
967 arelent *reloc_entry,
968 void *data, bfd_vma data_start,
969 asection *input_section,
970 char **error_message);
973 This looks remarkably like <<bfd_perform_relocation>>, except it
974 does not expect that the section contents have been filled in.
975 I.e., it's suitable for use when creating, rather than applying
978 For now, this function should be considered reserved for the
982 bfd_reloc_status_type
983 bfd_install_relocation (bfd *abfd,
984 arelent *reloc_entry,
986 bfd_vma data_start_offset,
987 asection *input_section,
988 char **error_message)
991 bfd_reloc_status_type flag = bfd_reloc_ok;
992 bfd_size_type octets;
993 bfd_vma output_base = 0;
994 reloc_howto_type *howto = reloc_entry->howto;
995 asection *reloc_target_output_section;
999 symbol = *(reloc_entry->sym_ptr_ptr);
1001 /* If there is a function supplied to handle this relocation type,
1002 call it. It'll return `bfd_reloc_continue' if further processing
1004 if (howto && howto->special_function)
1006 bfd_reloc_status_type cont;
1008 /* XXX - The special_function calls haven't been fixed up to deal
1009 with creating new relocations and section contents. */
1010 cont = howto->special_function (abfd, reloc_entry, symbol,
1011 /* XXX - Non-portable! */
1012 ((bfd_byte *) data_start
1013 - data_start_offset),
1014 input_section, abfd, error_message);
1015 if (cont != bfd_reloc_continue)
1019 if (bfd_is_abs_section (symbol->section))
1021 reloc_entry->address += input_section->output_offset;
1022 return bfd_reloc_ok;
1025 /* No need to check for howto != NULL if !bfd_is_abs_section as
1026 it will have been checked in `bfd_perform_relocation already'. */
1028 /* Is the address of the relocation really within the section? */
1029 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
1030 if (!reloc_offset_in_range (howto, abfd, input_section, octets))
1031 return bfd_reloc_outofrange;
1033 /* Work out which section the relocation is targeted at and the
1034 initial relocation command value. */
1036 /* Get symbol value. (Common symbols are special.) */
1037 if (bfd_is_com_section (symbol->section))
1040 relocation = symbol->value;
1042 reloc_target_output_section = symbol->section->output_section;
1044 /* Convert input-section-relative symbol value to absolute. */
1045 if (! howto->partial_inplace)
1048 output_base = reloc_target_output_section->vma;
1050 relocation += output_base + symbol->section->output_offset;
1052 /* Add in supplied addend. */
1053 relocation += reloc_entry->addend;
1055 /* Here the variable relocation holds the final address of the
1056 symbol we are relocating against, plus any addend. */
1058 if (howto->pc_relative)
1060 /* This is a PC relative relocation. We want to set RELOCATION
1061 to the distance between the address of the symbol and the
1062 location. RELOCATION is already the address of the symbol.
1064 We start by subtracting the address of the section containing
1067 If pcrel_offset is set, we must further subtract the position
1068 of the location within the section. Some targets arrange for
1069 the addend to be the negative of the position of the location
1070 within the section; for example, i386-aout does this. For
1071 i386-aout, pcrel_offset is FALSE. Some other targets do not
1072 include the position of the location; for example, m88kbcs,
1073 or ELF. For those targets, pcrel_offset is TRUE.
1075 If we are producing relocatable output, then we must ensure
1076 that this reloc will be correctly computed when the final
1077 relocation is done. If pcrel_offset is FALSE we want to wind
1078 up with the negative of the location within the section,
1079 which means we must adjust the existing addend by the change
1080 in the location within the section. If pcrel_offset is TRUE
1081 we do not want to adjust the existing addend at all.
1083 FIXME: This seems logical to me, but for the case of
1084 producing relocatable output it is not what the code
1085 actually does. I don't want to change it, because it seems
1086 far too likely that something will break. */
1089 input_section->output_section->vma + input_section->output_offset;
1091 if (howto->pcrel_offset && howto->partial_inplace)
1092 relocation -= reloc_entry->address;
1095 if (! howto->partial_inplace)
1097 /* This is a partial relocation, and we want to apply the relocation
1098 to the reloc entry rather than the raw data. Modify the reloc
1099 inplace to reflect what we now know. */
1100 reloc_entry->addend = relocation;
1101 reloc_entry->address += input_section->output_offset;
1106 /* This is a partial relocation, but inplace, so modify the
1109 If we've relocated with a symbol with a section, change
1110 into a ref to the section belonging to the symbol. */
1111 reloc_entry->address += input_section->output_offset;
1114 if (abfd->xvec->flavour == bfd_target_coff_flavour
1115 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1116 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1119 /* For m68k-coff, the addend was being subtracted twice during
1120 relocation with -r. Removing the line below this comment
1121 fixes that problem; see PR 2953.
1123 However, Ian wrote the following, regarding removing the line below,
1124 which explains why it is still enabled: --djm
1126 If you put a patch like that into BFD you need to check all the COFF
1127 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1128 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1129 problem in a different way. There may very well be a reason that the
1130 code works as it does.
1132 Hmmm. The first obvious point is that bfd_install_relocation should
1133 not have any tests that depend upon the flavour. It's seem like
1134 entirely the wrong place for such a thing. The second obvious point
1135 is that the current code ignores the reloc addend when producing
1136 relocatable output for COFF. That's peculiar. In fact, I really
1137 have no idea what the point of the line you want to remove is.
1139 A typical COFF reloc subtracts the old value of the symbol and adds in
1140 the new value to the location in the object file (if it's a pc
1141 relative reloc it adds the difference between the symbol value and the
1142 location). When relocating we need to preserve that property.
1144 BFD handles this by setting the addend to the negative of the old
1145 value of the symbol. Unfortunately it handles common symbols in a
1146 non-standard way (it doesn't subtract the old value) but that's a
1147 different story (we can't change it without losing backward
1148 compatibility with old object files) (coff-i386 does subtract the old
1149 value, to be compatible with existing coff-i386 targets, like SCO).
1151 So everything works fine when not producing relocatable output. When
1152 we are producing relocatable output, logically we should do exactly
1153 what we do when not producing relocatable output. Therefore, your
1154 patch is correct. In fact, it should probably always just set
1155 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1156 add the value into the object file. This won't hurt the COFF code,
1157 which doesn't use the addend; I'm not sure what it will do to other
1158 formats (the thing to check for would be whether any formats both use
1159 the addend and set partial_inplace).
1161 When I wanted to make coff-i386 produce relocatable output, I ran
1162 into the problem that you are running into: I wanted to remove that
1163 line. Rather than risk it, I made the coff-i386 relocs use a special
1164 function; it's coff_i386_reloc in coff-i386.c. The function
1165 specifically adds the addend field into the object file, knowing that
1166 bfd_install_relocation is not going to. If you remove that line, then
1167 coff-i386.c will wind up adding the addend field in twice. It's
1168 trivial to fix; it just needs to be done.
1170 The problem with removing the line is just that it may break some
1171 working code. With BFD it's hard to be sure of anything. The right
1172 way to deal with this is simply to build and test at least all the
1173 supported COFF targets. It should be straightforward if time and disk
1174 space consuming. For each target:
1176 2) generate some executable, and link it using -r (I would
1177 probably use paranoia.o and link against newlib/libc.a, which
1178 for all the supported targets would be available in
1179 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1180 3) make the change to reloc.c
1181 4) rebuild the linker
1183 6) if the resulting object files are the same, you have at least
1185 7) if they are different you have to figure out which version is
1187 relocation -= reloc_entry->addend;
1188 /* FIXME: There should be no target specific code here... */
1189 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1190 reloc_entry->addend = 0;
1194 reloc_entry->addend = relocation;
1198 /* FIXME: This overflow checking is incomplete, because the value
1199 might have overflowed before we get here. For a correct check we
1200 need to compute the value in a size larger than bitsize, but we
1201 can't reasonably do that for a reloc the same size as a host
1203 FIXME: We should also do overflow checking on the result after
1204 adding in the value contained in the object file. */
1205 if (howto->complain_on_overflow != complain_overflow_dont)
1206 flag = bfd_check_overflow (howto->complain_on_overflow,
1209 bfd_arch_bits_per_address (abfd),
1212 /* Either we are relocating all the way, or we don't want to apply
1213 the relocation to the reloc entry (probably because there isn't
1214 any room in the output format to describe addends to relocs). */
1216 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1217 (OSF version 1.3, compiler version 3.11). It miscompiles the
1231 x <<= (unsigned long) s.i0;
1233 printf ("failed\n");
1235 printf ("succeeded (%lx)\n", x);
1239 relocation >>= (bfd_vma) howto->rightshift;
1241 /* Shift everything up to where it's going to be used. */
1242 relocation <<= (bfd_vma) howto->bitpos;
1244 /* Wait for the day when all have the mask in them. */
1247 i instruction to be left alone
1248 o offset within instruction
1249 r relocation offset to apply
1258 (( i i i i i o o o o o from bfd_get<size>
1259 and S S S S S) to get the size offset we want
1260 + r r r r r r r r r r) to get the final value to place
1261 and D D D D D to chop to right size
1262 -----------------------
1265 ( i i i i i o o o o o from bfd_get<size>
1266 and N N N N N ) get instruction
1267 -----------------------
1273 -----------------------
1274 = R R R R R R R R R R put into bfd_put<size>
1278 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1280 data = (bfd_byte *) data_start + (octets - data_start_offset);
1282 switch (howto->size)
1286 char x = bfd_get_8 (abfd, data);
1288 bfd_put_8 (abfd, x, data);
1294 short x = bfd_get_16 (abfd, data);
1296 bfd_put_16 (abfd, (bfd_vma) x, data);
1301 long x = bfd_get_32 (abfd, data);
1303 bfd_put_32 (abfd, (bfd_vma) x, data);
1308 long x = bfd_get_32 (abfd, data);
1309 relocation = -relocation;
1311 bfd_put_32 (abfd, (bfd_vma) x, data);
1321 bfd_vma x = bfd_get_64 (abfd, data);
1323 bfd_put_64 (abfd, x, data);
1327 return bfd_reloc_other;
1333 /* This relocation routine is used by some of the backend linkers.
1334 They do not construct asymbol or arelent structures, so there is no
1335 reason for them to use bfd_perform_relocation. Also,
1336 bfd_perform_relocation is so hacked up it is easier to write a new
1337 function than to try to deal with it.
1339 This routine does a final relocation. Whether it is useful for a
1340 relocatable link depends upon how the object format defines
1343 FIXME: This routine ignores any special_function in the HOWTO,
1344 since the existing special_function values have been written for
1345 bfd_perform_relocation.
1347 HOWTO is the reloc howto information.
1348 INPUT_BFD is the BFD which the reloc applies to.
1349 INPUT_SECTION is the section which the reloc applies to.
1350 CONTENTS is the contents of the section.
1351 ADDRESS is the address of the reloc within INPUT_SECTION.
1352 VALUE is the value of the symbol the reloc refers to.
1353 ADDEND is the addend of the reloc. */
1355 bfd_reloc_status_type
1356 _bfd_final_link_relocate (reloc_howto_type *howto,
1358 asection *input_section,
1365 bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
1367 /* Sanity check the address. */
1368 if (!reloc_offset_in_range (howto, input_bfd, input_section, octets))
1369 return bfd_reloc_outofrange;
1371 /* This function assumes that we are dealing with a basic relocation
1372 against a symbol. We want to compute the value of the symbol to
1373 relocate to. This is just VALUE, the value of the symbol, plus
1374 ADDEND, any addend associated with the reloc. */
1375 relocation = value + addend;
1377 /* If the relocation is PC relative, we want to set RELOCATION to
1378 the distance between the symbol (currently in RELOCATION) and the
1379 location we are relocating. Some targets (e.g., i386-aout)
1380 arrange for the contents of the section to be the negative of the
1381 offset of the location within the section; for such targets
1382 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1383 simply leave the contents of the section as zero; for such
1384 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1385 need to subtract out the offset of the location within the
1386 section (which is just ADDRESS). */
1387 if (howto->pc_relative)
1389 relocation -= (input_section->output_section->vma
1390 + input_section->output_offset);
1391 if (howto->pcrel_offset)
1392 relocation -= address;
1395 return _bfd_relocate_contents (howto, input_bfd, relocation,
1397 + address * bfd_octets_per_byte (input_bfd));
1400 /* Relocate a given location using a given value and howto. */
1402 bfd_reloc_status_type
1403 _bfd_relocate_contents (reloc_howto_type *howto,
1410 bfd_reloc_status_type flag;
1411 unsigned int rightshift = howto->rightshift;
1412 unsigned int bitpos = howto->bitpos;
1414 /* If the size is negative, negate RELOCATION. This isn't very
1416 if (howto->size < 0)
1417 relocation = -relocation;
1419 /* Get the value we are going to relocate. */
1420 size = bfd_get_reloc_size (howto);
1426 return bfd_reloc_ok;
1428 x = bfd_get_8 (input_bfd, location);
1431 x = bfd_get_16 (input_bfd, location);
1434 x = bfd_get_32 (input_bfd, location);
1438 x = bfd_get_64 (input_bfd, location);
1445 /* Check for overflow. FIXME: We may drop bits during the addition
1446 which we don't check for. We must either check at every single
1447 operation, which would be tedious, or we must do the computations
1448 in a type larger than bfd_vma, which would be inefficient. */
1449 flag = bfd_reloc_ok;
1450 if (howto->complain_on_overflow != complain_overflow_dont)
1452 bfd_vma addrmask, fieldmask, signmask, ss;
1455 /* Get the values to be added together. For signed and unsigned
1456 relocations, we assume that all values should be truncated to
1457 the size of an address. For bitfields, all the bits matter.
1458 See also bfd_check_overflow. */
1459 fieldmask = N_ONES (howto->bitsize);
1460 signmask = ~fieldmask;
1461 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1462 | (fieldmask << rightshift));
1463 a = (relocation & addrmask) >> rightshift;
1464 b = (x & howto->src_mask & addrmask) >> bitpos;
1465 addrmask >>= rightshift;
1467 switch (howto->complain_on_overflow)
1469 case complain_overflow_signed:
1470 /* If any sign bits are set, all sign bits must be set.
1471 That is, A must be a valid negative address after
1473 signmask = ~(fieldmask >> 1);
1476 case complain_overflow_bitfield:
1477 /* Much like the signed check, but for a field one bit
1478 wider. We allow a bitfield to represent numbers in the
1479 range -2**n to 2**n-1, where n is the number of bits in the
1480 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1481 can't overflow, which is exactly what we want. */
1483 if (ss != 0 && ss != (addrmask & signmask))
1484 flag = bfd_reloc_overflow;
1486 /* We only need this next bit of code if the sign bit of B
1487 is below the sign bit of A. This would only happen if
1488 SRC_MASK had fewer bits than BITSIZE. Note that if
1489 SRC_MASK has more bits than BITSIZE, we can get into
1490 trouble; we would need to verify that B is in range, as
1491 we do for A above. */
1492 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1495 /* Set all the bits above the sign bit. */
1498 /* Now we can do the addition. */
1501 /* See if the result has the correct sign. Bits above the
1502 sign bit are junk now; ignore them. If the sum is
1503 positive, make sure we did not have all negative inputs;
1504 if the sum is negative, make sure we did not have all
1505 positive inputs. The test below looks only at the sign
1506 bits, and it really just
1507 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1509 We mask with addrmask here to explicitly allow an address
1510 wrap-around. The Linux kernel relies on it, and it is
1511 the only way to write assembler code which can run when
1512 loaded at a location 0x80000000 away from the location at
1513 which it is linked. */
1514 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1515 flag = bfd_reloc_overflow;
1518 case complain_overflow_unsigned:
1519 /* Checking for an unsigned overflow is relatively easy:
1520 trim the addresses and add, and trim the result as well.
1521 Overflow is normally indicated when the result does not
1522 fit in the field. However, we also need to consider the
1523 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1524 input is 0x80000000, and bfd_vma is only 32 bits; then we
1525 will get sum == 0, but there is an overflow, since the
1526 inputs did not fit in the field. Instead of doing a
1527 separate test, we can check for this by or-ing in the
1528 operands when testing for the sum overflowing its final
1530 sum = (a + b) & addrmask;
1531 if ((a | b | sum) & signmask)
1532 flag = bfd_reloc_overflow;
1540 /* Put RELOCATION in the right bits. */
1541 relocation >>= (bfd_vma) rightshift;
1542 relocation <<= (bfd_vma) bitpos;
1544 /* Add RELOCATION to the right bits of X. */
1545 x = ((x & ~howto->dst_mask)
1546 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1548 /* Put the relocated value back in the object file. */
1554 bfd_put_8 (input_bfd, x, location);
1557 bfd_put_16 (input_bfd, x, location);
1560 bfd_put_32 (input_bfd, x, location);
1564 bfd_put_64 (input_bfd, x, location);
1574 /* Clear a given location using a given howto, by applying a fixed relocation
1575 value and discarding any in-place addend. This is used for fixed-up
1576 relocations against discarded symbols, to make ignorable debug or unwind
1577 information more obvious. */
1580 _bfd_clear_contents (reloc_howto_type *howto,
1582 asection *input_section,
1588 /* Get the value we are going to relocate. */
1589 size = bfd_get_reloc_size (howto);
1597 x = bfd_get_8 (input_bfd, location);
1600 x = bfd_get_16 (input_bfd, location);
1603 x = bfd_get_32 (input_bfd, location);
1607 x = bfd_get_64 (input_bfd, location);
1614 /* Zero out the unwanted bits of X. */
1615 x &= ~howto->dst_mask;
1617 /* For a range list, use 1 instead of 0 as placeholder. 0
1618 would terminate the list, hiding any later entries. */
1619 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1620 ".debug_ranges") == 0
1621 && (howto->dst_mask & 1) != 0)
1624 /* Put the relocated value back in the object file. */
1631 bfd_put_8 (input_bfd, x, location);
1634 bfd_put_16 (input_bfd, x, location);
1637 bfd_put_32 (input_bfd, x, location);
1641 bfd_put_64 (input_bfd, x, location);
1652 howto manager, , typedef arelent, Relocations
1657 When an application wants to create a relocation, but doesn't
1658 know what the target machine might call it, it can find out by
1659 using this bit of code.
1668 The insides of a reloc code. The idea is that, eventually, there
1669 will be one enumerator for every type of relocation we ever do.
1670 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1671 return a howto pointer.
1673 This does mean that the application must determine the correct
1674 enumerator value; you can't get a howto pointer from a random set
1695 Basic absolute relocations of N bits.
1710 PC-relative relocations. Sometimes these are relative to the address
1711 of the relocation itself; sometimes they are relative to the start of
1712 the section containing the relocation. It depends on the specific target.
1714 The 24-bit relocation is used in some Intel 960 configurations.
1719 Section relative relocations. Some targets need this for DWARF2.
1722 BFD_RELOC_32_GOT_PCREL
1724 BFD_RELOC_16_GOT_PCREL
1726 BFD_RELOC_8_GOT_PCREL
1732 BFD_RELOC_LO16_GOTOFF
1734 BFD_RELOC_HI16_GOTOFF
1736 BFD_RELOC_HI16_S_GOTOFF
1740 BFD_RELOC_64_PLT_PCREL
1742 BFD_RELOC_32_PLT_PCREL
1744 BFD_RELOC_24_PLT_PCREL
1746 BFD_RELOC_16_PLT_PCREL
1748 BFD_RELOC_8_PLT_PCREL
1756 BFD_RELOC_LO16_PLTOFF
1758 BFD_RELOC_HI16_PLTOFF
1760 BFD_RELOC_HI16_S_PLTOFF
1774 BFD_RELOC_68K_GLOB_DAT
1776 BFD_RELOC_68K_JMP_SLOT
1778 BFD_RELOC_68K_RELATIVE
1780 BFD_RELOC_68K_TLS_GD32
1782 BFD_RELOC_68K_TLS_GD16
1784 BFD_RELOC_68K_TLS_GD8
1786 BFD_RELOC_68K_TLS_LDM32
1788 BFD_RELOC_68K_TLS_LDM16
1790 BFD_RELOC_68K_TLS_LDM8
1792 BFD_RELOC_68K_TLS_LDO32
1794 BFD_RELOC_68K_TLS_LDO16
1796 BFD_RELOC_68K_TLS_LDO8
1798 BFD_RELOC_68K_TLS_IE32
1800 BFD_RELOC_68K_TLS_IE16
1802 BFD_RELOC_68K_TLS_IE8
1804 BFD_RELOC_68K_TLS_LE32
1806 BFD_RELOC_68K_TLS_LE16
1808 BFD_RELOC_68K_TLS_LE8
1810 Relocations used by 68K ELF.
1813 BFD_RELOC_32_BASEREL
1815 BFD_RELOC_16_BASEREL
1817 BFD_RELOC_LO16_BASEREL
1819 BFD_RELOC_HI16_BASEREL
1821 BFD_RELOC_HI16_S_BASEREL
1827 Linkage-table relative.
1832 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1835 BFD_RELOC_32_PCREL_S2
1837 BFD_RELOC_16_PCREL_S2
1839 BFD_RELOC_23_PCREL_S2
1841 These PC-relative relocations are stored as word displacements --
1842 i.e., byte displacements shifted right two bits. The 30-bit word
1843 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1844 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1845 signed 16-bit displacement is used on the MIPS, and the 23-bit
1846 displacement is used on the Alpha.
1853 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1854 the target word. These are used on the SPARC.
1861 For systems that allocate a Global Pointer register, these are
1862 displacements off that register. These relocation types are
1863 handled specially, because the value the register will have is
1864 decided relatively late.
1867 BFD_RELOC_I960_CALLJ
1869 Reloc types used for i960/b.out.
1874 BFD_RELOC_SPARC_WDISP22
1880 BFD_RELOC_SPARC_GOT10
1882 BFD_RELOC_SPARC_GOT13
1884 BFD_RELOC_SPARC_GOT22
1886 BFD_RELOC_SPARC_PC10
1888 BFD_RELOC_SPARC_PC22
1890 BFD_RELOC_SPARC_WPLT30
1892 BFD_RELOC_SPARC_COPY
1894 BFD_RELOC_SPARC_GLOB_DAT
1896 BFD_RELOC_SPARC_JMP_SLOT
1898 BFD_RELOC_SPARC_RELATIVE
1900 BFD_RELOC_SPARC_UA16
1902 BFD_RELOC_SPARC_UA32
1904 BFD_RELOC_SPARC_UA64
1906 BFD_RELOC_SPARC_GOTDATA_HIX22
1908 BFD_RELOC_SPARC_GOTDATA_LOX10
1910 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1912 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1914 BFD_RELOC_SPARC_GOTDATA_OP
1916 BFD_RELOC_SPARC_JMP_IREL
1918 BFD_RELOC_SPARC_IRELATIVE
1920 SPARC ELF relocations. There is probably some overlap with other
1921 relocation types already defined.
1924 BFD_RELOC_SPARC_BASE13
1926 BFD_RELOC_SPARC_BASE22
1928 I think these are specific to SPARC a.out (e.g., Sun 4).
1938 BFD_RELOC_SPARC_OLO10
1940 BFD_RELOC_SPARC_HH22
1942 BFD_RELOC_SPARC_HM10
1944 BFD_RELOC_SPARC_LM22
1946 BFD_RELOC_SPARC_PC_HH22
1948 BFD_RELOC_SPARC_PC_HM10
1950 BFD_RELOC_SPARC_PC_LM22
1952 BFD_RELOC_SPARC_WDISP16
1954 BFD_RELOC_SPARC_WDISP19
1962 BFD_RELOC_SPARC_DISP64
1965 BFD_RELOC_SPARC_PLT32
1967 BFD_RELOC_SPARC_PLT64
1969 BFD_RELOC_SPARC_HIX22
1971 BFD_RELOC_SPARC_LOX10
1979 BFD_RELOC_SPARC_REGISTER
1983 BFD_RELOC_SPARC_SIZE32
1985 BFD_RELOC_SPARC_SIZE64
1987 BFD_RELOC_SPARC_WDISP10
1992 BFD_RELOC_SPARC_REV32
1994 SPARC little endian relocation
1996 BFD_RELOC_SPARC_TLS_GD_HI22
1998 BFD_RELOC_SPARC_TLS_GD_LO10
2000 BFD_RELOC_SPARC_TLS_GD_ADD
2002 BFD_RELOC_SPARC_TLS_GD_CALL
2004 BFD_RELOC_SPARC_TLS_LDM_HI22
2006 BFD_RELOC_SPARC_TLS_LDM_LO10
2008 BFD_RELOC_SPARC_TLS_LDM_ADD
2010 BFD_RELOC_SPARC_TLS_LDM_CALL
2012 BFD_RELOC_SPARC_TLS_LDO_HIX22
2014 BFD_RELOC_SPARC_TLS_LDO_LOX10
2016 BFD_RELOC_SPARC_TLS_LDO_ADD
2018 BFD_RELOC_SPARC_TLS_IE_HI22
2020 BFD_RELOC_SPARC_TLS_IE_LO10
2022 BFD_RELOC_SPARC_TLS_IE_LD
2024 BFD_RELOC_SPARC_TLS_IE_LDX
2026 BFD_RELOC_SPARC_TLS_IE_ADD
2028 BFD_RELOC_SPARC_TLS_LE_HIX22
2030 BFD_RELOC_SPARC_TLS_LE_LOX10
2032 BFD_RELOC_SPARC_TLS_DTPMOD32
2034 BFD_RELOC_SPARC_TLS_DTPMOD64
2036 BFD_RELOC_SPARC_TLS_DTPOFF32
2038 BFD_RELOC_SPARC_TLS_DTPOFF64
2040 BFD_RELOC_SPARC_TLS_TPOFF32
2042 BFD_RELOC_SPARC_TLS_TPOFF64
2044 SPARC TLS relocations
2053 BFD_RELOC_SPU_IMM10W
2057 BFD_RELOC_SPU_IMM16W
2061 BFD_RELOC_SPU_PCREL9a
2063 BFD_RELOC_SPU_PCREL9b
2065 BFD_RELOC_SPU_PCREL16
2075 BFD_RELOC_SPU_ADD_PIC
2080 BFD_RELOC_ALPHA_GPDISP_HI16
2082 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2083 "addend" in some special way.
2084 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2085 writing; when reading, it will be the absolute section symbol. The
2086 addend is the displacement in bytes of the "lda" instruction from
2087 the "ldah" instruction (which is at the address of this reloc).
2089 BFD_RELOC_ALPHA_GPDISP_LO16
2091 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2092 with GPDISP_HI16 relocs. The addend is ignored when writing the
2093 relocations out, and is filled in with the file's GP value on
2094 reading, for convenience.
2097 BFD_RELOC_ALPHA_GPDISP
2099 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2100 relocation except that there is no accompanying GPDISP_LO16
2104 BFD_RELOC_ALPHA_LITERAL
2106 BFD_RELOC_ALPHA_ELF_LITERAL
2108 BFD_RELOC_ALPHA_LITUSE
2110 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2111 the assembler turns it into a LDQ instruction to load the address of
2112 the symbol, and then fills in a register in the real instruction.
2114 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2115 section symbol. The addend is ignored when writing, but is filled
2116 in with the file's GP value on reading, for convenience, as with the
2119 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2120 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2121 but it generates output not based on the position within the .got
2122 section, but relative to the GP value chosen for the file during the
2125 The LITUSE reloc, on the instruction using the loaded address, gives
2126 information to the linker that it might be able to use to optimize
2127 away some literal section references. The symbol is ignored (read
2128 as the absolute section symbol), and the "addend" indicates the type
2129 of instruction using the register:
2130 1 - "memory" fmt insn
2131 2 - byte-manipulation (byte offset reg)
2132 3 - jsr (target of branch)
2135 BFD_RELOC_ALPHA_HINT
2137 The HINT relocation indicates a value that should be filled into the
2138 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2139 prediction logic which may be provided on some processors.
2142 BFD_RELOC_ALPHA_LINKAGE
2144 The LINKAGE relocation outputs a linkage pair in the object file,
2145 which is filled by the linker.
2148 BFD_RELOC_ALPHA_CODEADDR
2150 The CODEADDR relocation outputs a STO_CA in the object file,
2151 which is filled by the linker.
2154 BFD_RELOC_ALPHA_GPREL_HI16
2156 BFD_RELOC_ALPHA_GPREL_LO16
2158 The GPREL_HI/LO relocations together form a 32-bit offset from the
2162 BFD_RELOC_ALPHA_BRSGP
2164 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2165 share a common GP, and the target address is adjusted for
2166 STO_ALPHA_STD_GPLOAD.
2171 The NOP relocation outputs a NOP if the longword displacement
2172 between two procedure entry points is < 2^21.
2177 The BSR relocation outputs a BSR if the longword displacement
2178 between two procedure entry points is < 2^21.
2183 The LDA relocation outputs a LDA if the longword displacement
2184 between two procedure entry points is < 2^16.
2189 The BOH relocation outputs a BSR if the longword displacement
2190 between two procedure entry points is < 2^21, or else a hint.
2193 BFD_RELOC_ALPHA_TLSGD
2195 BFD_RELOC_ALPHA_TLSLDM
2197 BFD_RELOC_ALPHA_DTPMOD64
2199 BFD_RELOC_ALPHA_GOTDTPREL16
2201 BFD_RELOC_ALPHA_DTPREL64
2203 BFD_RELOC_ALPHA_DTPREL_HI16
2205 BFD_RELOC_ALPHA_DTPREL_LO16
2207 BFD_RELOC_ALPHA_DTPREL16
2209 BFD_RELOC_ALPHA_GOTTPREL16
2211 BFD_RELOC_ALPHA_TPREL64
2213 BFD_RELOC_ALPHA_TPREL_HI16
2215 BFD_RELOC_ALPHA_TPREL_LO16
2217 BFD_RELOC_ALPHA_TPREL16
2219 Alpha thread-local storage relocations.
2224 BFD_RELOC_MICROMIPS_JMP
2226 The MIPS jump instruction.
2229 BFD_RELOC_MIPS16_JMP
2231 The MIPS16 jump instruction.
2234 BFD_RELOC_MIPS16_GPREL
2236 MIPS16 GP relative reloc.
2241 High 16 bits of 32-bit value; simple reloc.
2246 High 16 bits of 32-bit value but the low 16 bits will be sign
2247 extended and added to form the final result. If the low 16
2248 bits form a negative number, we need to add one to the high value
2249 to compensate for the borrow when the low bits are added.
2257 BFD_RELOC_HI16_PCREL
2259 High 16 bits of 32-bit pc-relative value
2261 BFD_RELOC_HI16_S_PCREL
2263 High 16 bits of 32-bit pc-relative value, adjusted
2265 BFD_RELOC_LO16_PCREL
2267 Low 16 bits of pc-relative value
2270 BFD_RELOC_MIPS16_GOT16
2272 BFD_RELOC_MIPS16_CALL16
2274 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2275 16-bit immediate fields
2277 BFD_RELOC_MIPS16_HI16
2279 MIPS16 high 16 bits of 32-bit value.
2281 BFD_RELOC_MIPS16_HI16_S
2283 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2284 extended and added to form the final result. If the low 16
2285 bits form a negative number, we need to add one to the high value
2286 to compensate for the borrow when the low bits are added.
2288 BFD_RELOC_MIPS16_LO16
2293 BFD_RELOC_MIPS16_TLS_GD
2295 BFD_RELOC_MIPS16_TLS_LDM
2297 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2299 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2301 BFD_RELOC_MIPS16_TLS_GOTTPREL
2303 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2305 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2307 MIPS16 TLS relocations
2310 BFD_RELOC_MIPS_LITERAL
2312 BFD_RELOC_MICROMIPS_LITERAL
2314 Relocation against a MIPS literal section.
2317 BFD_RELOC_MICROMIPS_7_PCREL_S1
2319 BFD_RELOC_MICROMIPS_10_PCREL_S1
2321 BFD_RELOC_MICROMIPS_16_PCREL_S1
2323 microMIPS PC-relative relocations.
2326 BFD_RELOC_MIPS16_16_PCREL_S1
2328 MIPS16 PC-relative relocation.
2331 BFD_RELOC_MIPS_21_PCREL_S2
2333 BFD_RELOC_MIPS_26_PCREL_S2
2335 BFD_RELOC_MIPS_18_PCREL_S3
2337 BFD_RELOC_MIPS_19_PCREL_S2
2339 MIPS PC-relative relocations.
2342 BFD_RELOC_MICROMIPS_GPREL16
2344 BFD_RELOC_MICROMIPS_HI16
2346 BFD_RELOC_MICROMIPS_HI16_S
2348 BFD_RELOC_MICROMIPS_LO16
2350 microMIPS versions of generic BFD relocs.
2353 BFD_RELOC_MIPS_GOT16
2355 BFD_RELOC_MICROMIPS_GOT16
2357 BFD_RELOC_MIPS_CALL16
2359 BFD_RELOC_MICROMIPS_CALL16
2361 BFD_RELOC_MIPS_GOT_HI16
2363 BFD_RELOC_MICROMIPS_GOT_HI16
2365 BFD_RELOC_MIPS_GOT_LO16
2367 BFD_RELOC_MICROMIPS_GOT_LO16
2369 BFD_RELOC_MIPS_CALL_HI16
2371 BFD_RELOC_MICROMIPS_CALL_HI16
2373 BFD_RELOC_MIPS_CALL_LO16
2375 BFD_RELOC_MICROMIPS_CALL_LO16
2379 BFD_RELOC_MICROMIPS_SUB
2381 BFD_RELOC_MIPS_GOT_PAGE
2383 BFD_RELOC_MICROMIPS_GOT_PAGE
2385 BFD_RELOC_MIPS_GOT_OFST
2387 BFD_RELOC_MICROMIPS_GOT_OFST
2389 BFD_RELOC_MIPS_GOT_DISP
2391 BFD_RELOC_MICROMIPS_GOT_DISP
2393 BFD_RELOC_MIPS_SHIFT5
2395 BFD_RELOC_MIPS_SHIFT6
2397 BFD_RELOC_MIPS_INSERT_A
2399 BFD_RELOC_MIPS_INSERT_B
2401 BFD_RELOC_MIPS_DELETE
2403 BFD_RELOC_MIPS_HIGHEST
2405 BFD_RELOC_MICROMIPS_HIGHEST
2407 BFD_RELOC_MIPS_HIGHER
2409 BFD_RELOC_MICROMIPS_HIGHER
2411 BFD_RELOC_MIPS_SCN_DISP
2413 BFD_RELOC_MICROMIPS_SCN_DISP
2415 BFD_RELOC_MIPS_REL16
2417 BFD_RELOC_MIPS_RELGOT
2421 BFD_RELOC_MICROMIPS_JALR
2423 BFD_RELOC_MIPS_TLS_DTPMOD32
2425 BFD_RELOC_MIPS_TLS_DTPREL32
2427 BFD_RELOC_MIPS_TLS_DTPMOD64
2429 BFD_RELOC_MIPS_TLS_DTPREL64
2431 BFD_RELOC_MIPS_TLS_GD
2433 BFD_RELOC_MICROMIPS_TLS_GD
2435 BFD_RELOC_MIPS_TLS_LDM
2437 BFD_RELOC_MICROMIPS_TLS_LDM
2439 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2441 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2443 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2445 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2447 BFD_RELOC_MIPS_TLS_GOTTPREL
2449 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2451 BFD_RELOC_MIPS_TLS_TPREL32
2453 BFD_RELOC_MIPS_TLS_TPREL64
2455 BFD_RELOC_MIPS_TLS_TPREL_HI16
2457 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2459 BFD_RELOC_MIPS_TLS_TPREL_LO16
2461 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2465 MIPS ELF relocations.
2471 BFD_RELOC_MIPS_JUMP_SLOT
2473 MIPS ELF relocations (VxWorks and PLT extensions).
2477 BFD_RELOC_MOXIE_10_PCREL
2479 Moxie ELF relocations.
2491 BFD_RELOC_FT32_RELAX
2499 BFD_RELOC_FT32_DIFF32
2501 FT32 ELF relocations.
2505 BFD_RELOC_FRV_LABEL16
2507 BFD_RELOC_FRV_LABEL24
2513 BFD_RELOC_FRV_GPREL12
2515 BFD_RELOC_FRV_GPRELU12
2517 BFD_RELOC_FRV_GPREL32
2519 BFD_RELOC_FRV_GPRELHI
2521 BFD_RELOC_FRV_GPRELLO
2529 BFD_RELOC_FRV_FUNCDESC
2531 BFD_RELOC_FRV_FUNCDESC_GOT12
2533 BFD_RELOC_FRV_FUNCDESC_GOTHI
2535 BFD_RELOC_FRV_FUNCDESC_GOTLO
2537 BFD_RELOC_FRV_FUNCDESC_VALUE
2539 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2541 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2543 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2545 BFD_RELOC_FRV_GOTOFF12
2547 BFD_RELOC_FRV_GOTOFFHI
2549 BFD_RELOC_FRV_GOTOFFLO
2551 BFD_RELOC_FRV_GETTLSOFF
2553 BFD_RELOC_FRV_TLSDESC_VALUE
2555 BFD_RELOC_FRV_GOTTLSDESC12
2557 BFD_RELOC_FRV_GOTTLSDESCHI
2559 BFD_RELOC_FRV_GOTTLSDESCLO
2561 BFD_RELOC_FRV_TLSMOFF12
2563 BFD_RELOC_FRV_TLSMOFFHI
2565 BFD_RELOC_FRV_TLSMOFFLO
2567 BFD_RELOC_FRV_GOTTLSOFF12
2569 BFD_RELOC_FRV_GOTTLSOFFHI
2571 BFD_RELOC_FRV_GOTTLSOFFLO
2573 BFD_RELOC_FRV_TLSOFF
2575 BFD_RELOC_FRV_TLSDESC_RELAX
2577 BFD_RELOC_FRV_GETTLSOFF_RELAX
2579 BFD_RELOC_FRV_TLSOFF_RELAX
2581 BFD_RELOC_FRV_TLSMOFF
2583 Fujitsu Frv Relocations.
2587 BFD_RELOC_MN10300_GOTOFF24
2589 This is a 24bit GOT-relative reloc for the mn10300.
2591 BFD_RELOC_MN10300_GOT32
2593 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2596 BFD_RELOC_MN10300_GOT24
2598 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2601 BFD_RELOC_MN10300_GOT16
2603 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2606 BFD_RELOC_MN10300_COPY
2608 Copy symbol at runtime.
2610 BFD_RELOC_MN10300_GLOB_DAT
2614 BFD_RELOC_MN10300_JMP_SLOT
2618 BFD_RELOC_MN10300_RELATIVE
2620 Adjust by program base.
2622 BFD_RELOC_MN10300_SYM_DIFF
2624 Together with another reloc targeted at the same location,
2625 allows for a value that is the difference of two symbols
2626 in the same section.
2628 BFD_RELOC_MN10300_ALIGN
2630 The addend of this reloc is an alignment power that must
2631 be honoured at the offset's location, regardless of linker
2634 BFD_RELOC_MN10300_TLS_GD
2636 BFD_RELOC_MN10300_TLS_LD
2638 BFD_RELOC_MN10300_TLS_LDO
2640 BFD_RELOC_MN10300_TLS_GOTIE
2642 BFD_RELOC_MN10300_TLS_IE
2644 BFD_RELOC_MN10300_TLS_LE
2646 BFD_RELOC_MN10300_TLS_DTPMOD
2648 BFD_RELOC_MN10300_TLS_DTPOFF
2650 BFD_RELOC_MN10300_TLS_TPOFF
2652 Various TLS-related relocations.
2654 BFD_RELOC_MN10300_32_PCREL
2656 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2659 BFD_RELOC_MN10300_16_PCREL
2661 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2672 BFD_RELOC_386_GLOB_DAT
2674 BFD_RELOC_386_JUMP_SLOT
2676 BFD_RELOC_386_RELATIVE
2678 BFD_RELOC_386_GOTOFF
2682 BFD_RELOC_386_TLS_TPOFF
2684 BFD_RELOC_386_TLS_IE
2686 BFD_RELOC_386_TLS_GOTIE
2688 BFD_RELOC_386_TLS_LE
2690 BFD_RELOC_386_TLS_GD
2692 BFD_RELOC_386_TLS_LDM
2694 BFD_RELOC_386_TLS_LDO_32
2696 BFD_RELOC_386_TLS_IE_32
2698 BFD_RELOC_386_TLS_LE_32
2700 BFD_RELOC_386_TLS_DTPMOD32
2702 BFD_RELOC_386_TLS_DTPOFF32
2704 BFD_RELOC_386_TLS_TPOFF32
2706 BFD_RELOC_386_TLS_GOTDESC
2708 BFD_RELOC_386_TLS_DESC_CALL
2710 BFD_RELOC_386_TLS_DESC
2712 BFD_RELOC_386_IRELATIVE
2714 BFD_RELOC_386_GOT32X
2716 i386/elf relocations
2719 BFD_RELOC_X86_64_GOT32
2721 BFD_RELOC_X86_64_PLT32
2723 BFD_RELOC_X86_64_COPY
2725 BFD_RELOC_X86_64_GLOB_DAT
2727 BFD_RELOC_X86_64_JUMP_SLOT
2729 BFD_RELOC_X86_64_RELATIVE
2731 BFD_RELOC_X86_64_GOTPCREL
2733 BFD_RELOC_X86_64_32S
2735 BFD_RELOC_X86_64_DTPMOD64
2737 BFD_RELOC_X86_64_DTPOFF64
2739 BFD_RELOC_X86_64_TPOFF64
2741 BFD_RELOC_X86_64_TLSGD
2743 BFD_RELOC_X86_64_TLSLD
2745 BFD_RELOC_X86_64_DTPOFF32
2747 BFD_RELOC_X86_64_GOTTPOFF
2749 BFD_RELOC_X86_64_TPOFF32
2751 BFD_RELOC_X86_64_GOTOFF64
2753 BFD_RELOC_X86_64_GOTPC32
2755 BFD_RELOC_X86_64_GOT64
2757 BFD_RELOC_X86_64_GOTPCREL64
2759 BFD_RELOC_X86_64_GOTPC64
2761 BFD_RELOC_X86_64_GOTPLT64
2763 BFD_RELOC_X86_64_PLTOFF64
2765 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2767 BFD_RELOC_X86_64_TLSDESC_CALL
2769 BFD_RELOC_X86_64_TLSDESC
2771 BFD_RELOC_X86_64_IRELATIVE
2773 BFD_RELOC_X86_64_PC32_BND
2775 BFD_RELOC_X86_64_PLT32_BND
2777 BFD_RELOC_X86_64_GOTPCRELX
2779 BFD_RELOC_X86_64_REX_GOTPCRELX
2781 x86-64/elf relocations
2784 BFD_RELOC_NS32K_IMM_8
2786 BFD_RELOC_NS32K_IMM_16
2788 BFD_RELOC_NS32K_IMM_32
2790 BFD_RELOC_NS32K_IMM_8_PCREL
2792 BFD_RELOC_NS32K_IMM_16_PCREL
2794 BFD_RELOC_NS32K_IMM_32_PCREL
2796 BFD_RELOC_NS32K_DISP_8
2798 BFD_RELOC_NS32K_DISP_16
2800 BFD_RELOC_NS32K_DISP_32
2802 BFD_RELOC_NS32K_DISP_8_PCREL
2804 BFD_RELOC_NS32K_DISP_16_PCREL
2806 BFD_RELOC_NS32K_DISP_32_PCREL
2811 BFD_RELOC_PDP11_DISP_8_PCREL
2813 BFD_RELOC_PDP11_DISP_6_PCREL
2818 BFD_RELOC_PJ_CODE_HI16
2820 BFD_RELOC_PJ_CODE_LO16
2822 BFD_RELOC_PJ_CODE_DIR16
2824 BFD_RELOC_PJ_CODE_DIR32
2826 BFD_RELOC_PJ_CODE_REL16
2828 BFD_RELOC_PJ_CODE_REL32
2830 Picojava relocs. Not all of these appear in object files.
2841 BFD_RELOC_PPC_B16_BRTAKEN
2843 BFD_RELOC_PPC_B16_BRNTAKEN
2847 BFD_RELOC_PPC_BA16_BRTAKEN
2849 BFD_RELOC_PPC_BA16_BRNTAKEN
2853 BFD_RELOC_PPC_GLOB_DAT
2855 BFD_RELOC_PPC_JMP_SLOT
2857 BFD_RELOC_PPC_RELATIVE
2859 BFD_RELOC_PPC_LOCAL24PC
2861 BFD_RELOC_PPC_EMB_NADDR32
2863 BFD_RELOC_PPC_EMB_NADDR16
2865 BFD_RELOC_PPC_EMB_NADDR16_LO
2867 BFD_RELOC_PPC_EMB_NADDR16_HI
2869 BFD_RELOC_PPC_EMB_NADDR16_HA
2871 BFD_RELOC_PPC_EMB_SDAI16
2873 BFD_RELOC_PPC_EMB_SDA2I16
2875 BFD_RELOC_PPC_EMB_SDA2REL
2877 BFD_RELOC_PPC_EMB_SDA21
2879 BFD_RELOC_PPC_EMB_MRKREF
2881 BFD_RELOC_PPC_EMB_RELSEC16
2883 BFD_RELOC_PPC_EMB_RELST_LO
2885 BFD_RELOC_PPC_EMB_RELST_HI
2887 BFD_RELOC_PPC_EMB_RELST_HA
2889 BFD_RELOC_PPC_EMB_BIT_FLD
2891 BFD_RELOC_PPC_EMB_RELSDA
2893 BFD_RELOC_PPC_VLE_REL8
2895 BFD_RELOC_PPC_VLE_REL15
2897 BFD_RELOC_PPC_VLE_REL24
2899 BFD_RELOC_PPC_VLE_LO16A
2901 BFD_RELOC_PPC_VLE_LO16D
2903 BFD_RELOC_PPC_VLE_HI16A
2905 BFD_RELOC_PPC_VLE_HI16D
2907 BFD_RELOC_PPC_VLE_HA16A
2909 BFD_RELOC_PPC_VLE_HA16D
2911 BFD_RELOC_PPC_VLE_SDA21
2913 BFD_RELOC_PPC_VLE_SDA21_LO
2915 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2917 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2919 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2921 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2923 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2925 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2927 BFD_RELOC_PPC_16DX_HA
2929 BFD_RELOC_PPC_REL16DX_HA
2931 BFD_RELOC_PPC64_HIGHER
2933 BFD_RELOC_PPC64_HIGHER_S
2935 BFD_RELOC_PPC64_HIGHEST
2937 BFD_RELOC_PPC64_HIGHEST_S
2939 BFD_RELOC_PPC64_TOC16_LO
2941 BFD_RELOC_PPC64_TOC16_HI
2943 BFD_RELOC_PPC64_TOC16_HA
2947 BFD_RELOC_PPC64_PLTGOT16
2949 BFD_RELOC_PPC64_PLTGOT16_LO
2951 BFD_RELOC_PPC64_PLTGOT16_HI
2953 BFD_RELOC_PPC64_PLTGOT16_HA
2955 BFD_RELOC_PPC64_ADDR16_DS
2957 BFD_RELOC_PPC64_ADDR16_LO_DS
2959 BFD_RELOC_PPC64_GOT16_DS
2961 BFD_RELOC_PPC64_GOT16_LO_DS
2963 BFD_RELOC_PPC64_PLT16_LO_DS
2965 BFD_RELOC_PPC64_SECTOFF_DS
2967 BFD_RELOC_PPC64_SECTOFF_LO_DS
2969 BFD_RELOC_PPC64_TOC16_DS
2971 BFD_RELOC_PPC64_TOC16_LO_DS
2973 BFD_RELOC_PPC64_PLTGOT16_DS
2975 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2977 BFD_RELOC_PPC64_ADDR16_HIGH
2979 BFD_RELOC_PPC64_ADDR16_HIGHA
2981 BFD_RELOC_PPC64_ADDR64_LOCAL
2983 BFD_RELOC_PPC64_ENTRY
2985 Power(rs6000) and PowerPC relocations.
2994 BFD_RELOC_PPC_DTPMOD
2996 BFD_RELOC_PPC_TPREL16
2998 BFD_RELOC_PPC_TPREL16_LO
3000 BFD_RELOC_PPC_TPREL16_HI
3002 BFD_RELOC_PPC_TPREL16_HA
3006 BFD_RELOC_PPC_DTPREL16
3008 BFD_RELOC_PPC_DTPREL16_LO
3010 BFD_RELOC_PPC_DTPREL16_HI
3012 BFD_RELOC_PPC_DTPREL16_HA
3014 BFD_RELOC_PPC_DTPREL
3016 BFD_RELOC_PPC_GOT_TLSGD16
3018 BFD_RELOC_PPC_GOT_TLSGD16_LO
3020 BFD_RELOC_PPC_GOT_TLSGD16_HI
3022 BFD_RELOC_PPC_GOT_TLSGD16_HA
3024 BFD_RELOC_PPC_GOT_TLSLD16
3026 BFD_RELOC_PPC_GOT_TLSLD16_LO
3028 BFD_RELOC_PPC_GOT_TLSLD16_HI
3030 BFD_RELOC_PPC_GOT_TLSLD16_HA
3032 BFD_RELOC_PPC_GOT_TPREL16
3034 BFD_RELOC_PPC_GOT_TPREL16_LO
3036 BFD_RELOC_PPC_GOT_TPREL16_HI
3038 BFD_RELOC_PPC_GOT_TPREL16_HA
3040 BFD_RELOC_PPC_GOT_DTPREL16
3042 BFD_RELOC_PPC_GOT_DTPREL16_LO
3044 BFD_RELOC_PPC_GOT_DTPREL16_HI
3046 BFD_RELOC_PPC_GOT_DTPREL16_HA
3048 BFD_RELOC_PPC64_TPREL16_DS
3050 BFD_RELOC_PPC64_TPREL16_LO_DS
3052 BFD_RELOC_PPC64_TPREL16_HIGHER
3054 BFD_RELOC_PPC64_TPREL16_HIGHERA
3056 BFD_RELOC_PPC64_TPREL16_HIGHEST
3058 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3060 BFD_RELOC_PPC64_DTPREL16_DS
3062 BFD_RELOC_PPC64_DTPREL16_LO_DS
3064 BFD_RELOC_PPC64_DTPREL16_HIGHER
3066 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3068 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3070 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3072 BFD_RELOC_PPC64_TPREL16_HIGH
3074 BFD_RELOC_PPC64_TPREL16_HIGHA
3076 BFD_RELOC_PPC64_DTPREL16_HIGH
3078 BFD_RELOC_PPC64_DTPREL16_HIGHA
3080 PowerPC and PowerPC64 thread-local storage relocations.
3085 IBM 370/390 relocations
3090 The type of reloc used to build a constructor table - at the moment
3091 probably a 32 bit wide absolute relocation, but the target can choose.
3092 It generally does map to one of the other relocation types.
3095 BFD_RELOC_ARM_PCREL_BRANCH
3097 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3098 not stored in the instruction.
3100 BFD_RELOC_ARM_PCREL_BLX
3102 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3103 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3104 field in the instruction.
3106 BFD_RELOC_THUMB_PCREL_BLX
3108 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3109 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3110 field in the instruction.
3112 BFD_RELOC_ARM_PCREL_CALL
3114 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3116 BFD_RELOC_ARM_PCREL_JUMP
3118 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3121 BFD_RELOC_THUMB_PCREL_BRANCH7
3123 BFD_RELOC_THUMB_PCREL_BRANCH9
3125 BFD_RELOC_THUMB_PCREL_BRANCH12
3127 BFD_RELOC_THUMB_PCREL_BRANCH20
3129 BFD_RELOC_THUMB_PCREL_BRANCH23
3131 BFD_RELOC_THUMB_PCREL_BRANCH25
3133 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3134 The lowest bit must be zero and is not stored in the instruction.
3135 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3136 "nn" one smaller in all cases. Note further that BRANCH23
3137 corresponds to R_ARM_THM_CALL.
3140 BFD_RELOC_ARM_OFFSET_IMM
3142 12-bit immediate offset, used in ARM-format ldr and str instructions.
3145 BFD_RELOC_ARM_THUMB_OFFSET
3147 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3150 BFD_RELOC_ARM_TARGET1
3152 Pc-relative or absolute relocation depending on target. Used for
3153 entries in .init_array sections.
3155 BFD_RELOC_ARM_ROSEGREL32
3157 Read-only segment base relative address.
3159 BFD_RELOC_ARM_SBREL32
3161 Data segment base relative address.
3163 BFD_RELOC_ARM_TARGET2
3165 This reloc is used for references to RTTI data from exception handling
3166 tables. The actual definition depends on the target. It may be a
3167 pc-relative or some form of GOT-indirect relocation.
3169 BFD_RELOC_ARM_PREL31
3171 31-bit PC relative address.
3177 BFD_RELOC_ARM_MOVW_PCREL
3179 BFD_RELOC_ARM_MOVT_PCREL
3181 BFD_RELOC_ARM_THUMB_MOVW
3183 BFD_RELOC_ARM_THUMB_MOVT
3185 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3187 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3189 Low and High halfword relocations for MOVW and MOVT instructions.
3192 BFD_RELOC_ARM_JUMP_SLOT
3194 BFD_RELOC_ARM_GLOB_DAT
3200 BFD_RELOC_ARM_RELATIVE
3202 BFD_RELOC_ARM_GOTOFF
3206 BFD_RELOC_ARM_GOT_PREL
3208 Relocations for setting up GOTs and PLTs for shared libraries.
3211 BFD_RELOC_ARM_TLS_GD32
3213 BFD_RELOC_ARM_TLS_LDO32
3215 BFD_RELOC_ARM_TLS_LDM32
3217 BFD_RELOC_ARM_TLS_DTPOFF32
3219 BFD_RELOC_ARM_TLS_DTPMOD32
3221 BFD_RELOC_ARM_TLS_TPOFF32
3223 BFD_RELOC_ARM_TLS_IE32
3225 BFD_RELOC_ARM_TLS_LE32
3227 BFD_RELOC_ARM_TLS_GOTDESC
3229 BFD_RELOC_ARM_TLS_CALL
3231 BFD_RELOC_ARM_THM_TLS_CALL
3233 BFD_RELOC_ARM_TLS_DESCSEQ
3235 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3237 BFD_RELOC_ARM_TLS_DESC
3239 ARM thread-local storage relocations.
3242 BFD_RELOC_ARM_ALU_PC_G0_NC
3244 BFD_RELOC_ARM_ALU_PC_G0
3246 BFD_RELOC_ARM_ALU_PC_G1_NC
3248 BFD_RELOC_ARM_ALU_PC_G1
3250 BFD_RELOC_ARM_ALU_PC_G2
3252 BFD_RELOC_ARM_LDR_PC_G0
3254 BFD_RELOC_ARM_LDR_PC_G1
3256 BFD_RELOC_ARM_LDR_PC_G2
3258 BFD_RELOC_ARM_LDRS_PC_G0
3260 BFD_RELOC_ARM_LDRS_PC_G1
3262 BFD_RELOC_ARM_LDRS_PC_G2
3264 BFD_RELOC_ARM_LDC_PC_G0
3266 BFD_RELOC_ARM_LDC_PC_G1
3268 BFD_RELOC_ARM_LDC_PC_G2
3270 BFD_RELOC_ARM_ALU_SB_G0_NC
3272 BFD_RELOC_ARM_ALU_SB_G0
3274 BFD_RELOC_ARM_ALU_SB_G1_NC
3276 BFD_RELOC_ARM_ALU_SB_G1
3278 BFD_RELOC_ARM_ALU_SB_G2
3280 BFD_RELOC_ARM_LDR_SB_G0
3282 BFD_RELOC_ARM_LDR_SB_G1
3284 BFD_RELOC_ARM_LDR_SB_G2
3286 BFD_RELOC_ARM_LDRS_SB_G0
3288 BFD_RELOC_ARM_LDRS_SB_G1
3290 BFD_RELOC_ARM_LDRS_SB_G2
3292 BFD_RELOC_ARM_LDC_SB_G0
3294 BFD_RELOC_ARM_LDC_SB_G1
3296 BFD_RELOC_ARM_LDC_SB_G2
3298 ARM group relocations.
3303 Annotation of BX instructions.
3306 BFD_RELOC_ARM_IRELATIVE
3308 ARM support for STT_GNU_IFUNC.
3311 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3313 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3315 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3317 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3319 Thumb1 relocations to support execute-only code.
3322 BFD_RELOC_ARM_IMMEDIATE
3324 BFD_RELOC_ARM_ADRL_IMMEDIATE
3326 BFD_RELOC_ARM_T32_IMMEDIATE
3328 BFD_RELOC_ARM_T32_ADD_IMM
3330 BFD_RELOC_ARM_T32_IMM12
3332 BFD_RELOC_ARM_T32_ADD_PC12
3334 BFD_RELOC_ARM_SHIFT_IMM
3344 BFD_RELOC_ARM_CP_OFF_IMM
3346 BFD_RELOC_ARM_CP_OFF_IMM_S2
3348 BFD_RELOC_ARM_T32_CP_OFF_IMM
3350 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3352 BFD_RELOC_ARM_ADR_IMM
3354 BFD_RELOC_ARM_LDR_IMM
3356 BFD_RELOC_ARM_LITERAL
3358 BFD_RELOC_ARM_IN_POOL
3360 BFD_RELOC_ARM_OFFSET_IMM8
3362 BFD_RELOC_ARM_T32_OFFSET_U8
3364 BFD_RELOC_ARM_T32_OFFSET_IMM
3366 BFD_RELOC_ARM_HWLITERAL
3368 BFD_RELOC_ARM_THUMB_ADD
3370 BFD_RELOC_ARM_THUMB_IMM
3372 BFD_RELOC_ARM_THUMB_SHIFT
3374 These relocs are only used within the ARM assembler. They are not
3375 (at present) written to any object files.
3378 BFD_RELOC_SH_PCDISP8BY2
3380 BFD_RELOC_SH_PCDISP12BY2
3388 BFD_RELOC_SH_DISP12BY2
3390 BFD_RELOC_SH_DISP12BY4
3392 BFD_RELOC_SH_DISP12BY8
3396 BFD_RELOC_SH_DISP20BY8
3400 BFD_RELOC_SH_IMM4BY2
3402 BFD_RELOC_SH_IMM4BY4
3406 BFD_RELOC_SH_IMM8BY2
3408 BFD_RELOC_SH_IMM8BY4
3410 BFD_RELOC_SH_PCRELIMM8BY2
3412 BFD_RELOC_SH_PCRELIMM8BY4
3414 BFD_RELOC_SH_SWITCH16
3416 BFD_RELOC_SH_SWITCH32
3430 BFD_RELOC_SH_LOOP_START
3432 BFD_RELOC_SH_LOOP_END
3436 BFD_RELOC_SH_GLOB_DAT
3438 BFD_RELOC_SH_JMP_SLOT
3440 BFD_RELOC_SH_RELATIVE
3444 BFD_RELOC_SH_GOT_LOW16
3446 BFD_RELOC_SH_GOT_MEDLOW16
3448 BFD_RELOC_SH_GOT_MEDHI16
3450 BFD_RELOC_SH_GOT_HI16
3452 BFD_RELOC_SH_GOTPLT_LOW16
3454 BFD_RELOC_SH_GOTPLT_MEDLOW16
3456 BFD_RELOC_SH_GOTPLT_MEDHI16
3458 BFD_RELOC_SH_GOTPLT_HI16
3460 BFD_RELOC_SH_PLT_LOW16
3462 BFD_RELOC_SH_PLT_MEDLOW16
3464 BFD_RELOC_SH_PLT_MEDHI16
3466 BFD_RELOC_SH_PLT_HI16
3468 BFD_RELOC_SH_GOTOFF_LOW16
3470 BFD_RELOC_SH_GOTOFF_MEDLOW16
3472 BFD_RELOC_SH_GOTOFF_MEDHI16
3474 BFD_RELOC_SH_GOTOFF_HI16
3476 BFD_RELOC_SH_GOTPC_LOW16
3478 BFD_RELOC_SH_GOTPC_MEDLOW16
3480 BFD_RELOC_SH_GOTPC_MEDHI16
3482 BFD_RELOC_SH_GOTPC_HI16
3486 BFD_RELOC_SH_GLOB_DAT64
3488 BFD_RELOC_SH_JMP_SLOT64
3490 BFD_RELOC_SH_RELATIVE64
3492 BFD_RELOC_SH_GOT10BY4
3494 BFD_RELOC_SH_GOT10BY8
3496 BFD_RELOC_SH_GOTPLT10BY4
3498 BFD_RELOC_SH_GOTPLT10BY8
3500 BFD_RELOC_SH_GOTPLT32
3502 BFD_RELOC_SH_SHMEDIA_CODE
3508 BFD_RELOC_SH_IMMS6BY32
3514 BFD_RELOC_SH_IMMS10BY2
3516 BFD_RELOC_SH_IMMS10BY4
3518 BFD_RELOC_SH_IMMS10BY8
3524 BFD_RELOC_SH_IMM_LOW16
3526 BFD_RELOC_SH_IMM_LOW16_PCREL
3528 BFD_RELOC_SH_IMM_MEDLOW16
3530 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3532 BFD_RELOC_SH_IMM_MEDHI16
3534 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3536 BFD_RELOC_SH_IMM_HI16
3538 BFD_RELOC_SH_IMM_HI16_PCREL
3542 BFD_RELOC_SH_TLS_GD_32
3544 BFD_RELOC_SH_TLS_LD_32
3546 BFD_RELOC_SH_TLS_LDO_32
3548 BFD_RELOC_SH_TLS_IE_32
3550 BFD_RELOC_SH_TLS_LE_32
3552 BFD_RELOC_SH_TLS_DTPMOD32
3554 BFD_RELOC_SH_TLS_DTPOFF32
3556 BFD_RELOC_SH_TLS_TPOFF32
3560 BFD_RELOC_SH_GOTOFF20
3562 BFD_RELOC_SH_GOTFUNCDESC
3564 BFD_RELOC_SH_GOTFUNCDESC20
3566 BFD_RELOC_SH_GOTOFFFUNCDESC
3568 BFD_RELOC_SH_GOTOFFFUNCDESC20
3570 BFD_RELOC_SH_FUNCDESC
3572 Renesas / SuperH SH relocs. Not all of these appear in object files.
3595 BFD_RELOC_ARC_SECTOFF
3597 BFD_RELOC_ARC_S21H_PCREL
3599 BFD_RELOC_ARC_S21W_PCREL
3601 BFD_RELOC_ARC_S25H_PCREL
3603 BFD_RELOC_ARC_S25W_PCREL
3607 BFD_RELOC_ARC_SDA_LDST
3609 BFD_RELOC_ARC_SDA_LDST1
3611 BFD_RELOC_ARC_SDA_LDST2
3613 BFD_RELOC_ARC_SDA16_LD
3615 BFD_RELOC_ARC_SDA16_LD1
3617 BFD_RELOC_ARC_SDA16_LD2
3619 BFD_RELOC_ARC_S13_PCREL
3625 BFD_RELOC_ARC_32_ME_S
3627 BFD_RELOC_ARC_N32_ME
3629 BFD_RELOC_ARC_SECTOFF_ME
3631 BFD_RELOC_ARC_SDA32_ME
3635 BFD_RELOC_AC_SECTOFF_U8
3637 BFD_RELOC_AC_SECTOFF_U8_1
3639 BFD_RELOC_AC_SECTOFF_U8_2
3641 BFD_RELOC_AC_SECTOFF_S9
3643 BFD_RELOC_AC_SECTOFF_S9_1
3645 BFD_RELOC_AC_SECTOFF_S9_2
3647 BFD_RELOC_ARC_SECTOFF_ME_1
3649 BFD_RELOC_ARC_SECTOFF_ME_2
3651 BFD_RELOC_ARC_SECTOFF_1
3653 BFD_RELOC_ARC_SECTOFF_2
3655 BFD_RELOC_ARC_SDA_12
3657 BFD_RELOC_ARC_SDA16_ST2
3659 BFD_RELOC_ARC_32_PCREL
3665 BFD_RELOC_ARC_GOTPC32
3671 BFD_RELOC_ARC_GLOB_DAT
3673 BFD_RELOC_ARC_JMP_SLOT
3675 BFD_RELOC_ARC_RELATIVE
3677 BFD_RELOC_ARC_GOTOFF
3681 BFD_RELOC_ARC_S21W_PCREL_PLT
3683 BFD_RELOC_ARC_S25H_PCREL_PLT
3685 BFD_RELOC_ARC_TLS_DTPMOD
3687 BFD_RELOC_ARC_TLS_TPOFF
3689 BFD_RELOC_ARC_TLS_GD_GOT
3691 BFD_RELOC_ARC_TLS_GD_LD
3693 BFD_RELOC_ARC_TLS_GD_CALL
3695 BFD_RELOC_ARC_TLS_IE_GOT
3697 BFD_RELOC_ARC_TLS_DTPOFF
3699 BFD_RELOC_ARC_TLS_DTPOFF_S9
3701 BFD_RELOC_ARC_TLS_LE_S9
3703 BFD_RELOC_ARC_TLS_LE_32
3705 BFD_RELOC_ARC_S25W_PCREL_PLT
3707 BFD_RELOC_ARC_S21H_PCREL_PLT
3709 BFD_RELOC_ARC_NPS_CMEM16
3711 BFD_RELOC_ARC_JLI_SECTOFF
3716 BFD_RELOC_BFIN_16_IMM
3718 ADI Blackfin 16 bit immediate absolute reloc.
3720 BFD_RELOC_BFIN_16_HIGH
3722 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3724 BFD_RELOC_BFIN_4_PCREL
3726 ADI Blackfin 'a' part of LSETUP.
3728 BFD_RELOC_BFIN_5_PCREL
3732 BFD_RELOC_BFIN_16_LOW
3734 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3736 BFD_RELOC_BFIN_10_PCREL
3740 BFD_RELOC_BFIN_11_PCREL
3742 ADI Blackfin 'b' part of LSETUP.
3744 BFD_RELOC_BFIN_12_PCREL_JUMP
3748 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3750 ADI Blackfin Short jump, pcrel.
3752 BFD_RELOC_BFIN_24_PCREL_CALL_X
3754 ADI Blackfin Call.x not implemented.
3756 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3758 ADI Blackfin Long Jump pcrel.
3760 BFD_RELOC_BFIN_GOT17M4
3762 BFD_RELOC_BFIN_GOTHI
3764 BFD_RELOC_BFIN_GOTLO
3766 BFD_RELOC_BFIN_FUNCDESC
3768 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3770 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3772 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3774 BFD_RELOC_BFIN_FUNCDESC_VALUE
3776 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3778 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3780 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3782 BFD_RELOC_BFIN_GOTOFF17M4
3784 BFD_RELOC_BFIN_GOTOFFHI
3786 BFD_RELOC_BFIN_GOTOFFLO
3788 ADI Blackfin FD-PIC relocations.
3792 ADI Blackfin GOT relocation.
3794 BFD_RELOC_BFIN_PLTPC
3796 ADI Blackfin PLTPC relocation.
3798 BFD_ARELOC_BFIN_PUSH
3800 ADI Blackfin arithmetic relocation.
3802 BFD_ARELOC_BFIN_CONST
3804 ADI Blackfin arithmetic relocation.
3808 ADI Blackfin arithmetic relocation.
3812 ADI Blackfin arithmetic relocation.
3814 BFD_ARELOC_BFIN_MULT
3816 ADI Blackfin arithmetic relocation.
3820 ADI Blackfin arithmetic relocation.
3824 ADI Blackfin arithmetic relocation.
3826 BFD_ARELOC_BFIN_LSHIFT
3828 ADI Blackfin arithmetic relocation.
3830 BFD_ARELOC_BFIN_RSHIFT
3832 ADI Blackfin arithmetic relocation.
3836 ADI Blackfin arithmetic relocation.
3840 ADI Blackfin arithmetic relocation.
3844 ADI Blackfin arithmetic relocation.
3846 BFD_ARELOC_BFIN_LAND
3848 ADI Blackfin arithmetic relocation.
3852 ADI Blackfin arithmetic relocation.
3856 ADI Blackfin arithmetic relocation.
3860 ADI Blackfin arithmetic relocation.
3862 BFD_ARELOC_BFIN_COMP
3864 ADI Blackfin arithmetic relocation.
3866 BFD_ARELOC_BFIN_PAGE
3868 ADI Blackfin arithmetic relocation.
3870 BFD_ARELOC_BFIN_HWPAGE
3872 ADI Blackfin arithmetic relocation.
3874 BFD_ARELOC_BFIN_ADDR
3876 ADI Blackfin arithmetic relocation.
3879 BFD_RELOC_D10V_10_PCREL_R
3881 Mitsubishi D10V relocs.
3882 This is a 10-bit reloc with the right 2 bits
3885 BFD_RELOC_D10V_10_PCREL_L
3887 Mitsubishi D10V relocs.
3888 This is a 10-bit reloc with the right 2 bits
3889 assumed to be 0. This is the same as the previous reloc
3890 except it is in the left container, i.e.,
3891 shifted left 15 bits.
3895 This is an 18-bit reloc with the right 2 bits
3898 BFD_RELOC_D10V_18_PCREL
3900 This is an 18-bit reloc with the right 2 bits
3906 Mitsubishi D30V relocs.
3907 This is a 6-bit absolute reloc.
3909 BFD_RELOC_D30V_9_PCREL
3911 This is a 6-bit pc-relative reloc with
3912 the right 3 bits assumed to be 0.
3914 BFD_RELOC_D30V_9_PCREL_R
3916 This is a 6-bit pc-relative reloc with
3917 the right 3 bits assumed to be 0. Same
3918 as the previous reloc but on the right side
3923 This is a 12-bit absolute reloc with the
3924 right 3 bitsassumed to be 0.
3926 BFD_RELOC_D30V_15_PCREL
3928 This is a 12-bit pc-relative reloc with
3929 the right 3 bits assumed to be 0.
3931 BFD_RELOC_D30V_15_PCREL_R
3933 This is a 12-bit pc-relative reloc with
3934 the right 3 bits assumed to be 0. Same
3935 as the previous reloc but on the right side
3940 This is an 18-bit absolute reloc with
3941 the right 3 bits assumed to be 0.
3943 BFD_RELOC_D30V_21_PCREL
3945 This is an 18-bit pc-relative reloc with
3946 the right 3 bits assumed to be 0.
3948 BFD_RELOC_D30V_21_PCREL_R
3950 This is an 18-bit pc-relative reloc with
3951 the right 3 bits assumed to be 0. Same
3952 as the previous reloc but on the right side
3957 This is a 32-bit absolute reloc.
3959 BFD_RELOC_D30V_32_PCREL
3961 This is a 32-bit pc-relative reloc.
3964 BFD_RELOC_DLX_HI16_S
3979 BFD_RELOC_M32C_RL_JUMP
3981 BFD_RELOC_M32C_RL_1ADDR
3983 BFD_RELOC_M32C_RL_2ADDR
3985 Renesas M16C/M32C Relocations.
3990 Renesas M32R (formerly Mitsubishi M32R) relocs.
3991 This is a 24 bit absolute address.
3993 BFD_RELOC_M32R_10_PCREL
3995 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3997 BFD_RELOC_M32R_18_PCREL
3999 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4001 BFD_RELOC_M32R_26_PCREL
4003 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4005 BFD_RELOC_M32R_HI16_ULO
4007 This is a 16-bit reloc containing the high 16 bits of an address
4008 used when the lower 16 bits are treated as unsigned.
4010 BFD_RELOC_M32R_HI16_SLO
4012 This is a 16-bit reloc containing the high 16 bits of an address
4013 used when the lower 16 bits are treated as signed.
4017 This is a 16-bit reloc containing the lower 16 bits of an address.
4019 BFD_RELOC_M32R_SDA16
4021 This is a 16-bit reloc containing the small data area offset for use in
4022 add3, load, and store instructions.
4024 BFD_RELOC_M32R_GOT24
4026 BFD_RELOC_M32R_26_PLTREL
4030 BFD_RELOC_M32R_GLOB_DAT
4032 BFD_RELOC_M32R_JMP_SLOT
4034 BFD_RELOC_M32R_RELATIVE
4036 BFD_RELOC_M32R_GOTOFF
4038 BFD_RELOC_M32R_GOTOFF_HI_ULO
4040 BFD_RELOC_M32R_GOTOFF_HI_SLO
4042 BFD_RELOC_M32R_GOTOFF_LO
4044 BFD_RELOC_M32R_GOTPC24
4046 BFD_RELOC_M32R_GOT16_HI_ULO
4048 BFD_RELOC_M32R_GOT16_HI_SLO
4050 BFD_RELOC_M32R_GOT16_LO
4052 BFD_RELOC_M32R_GOTPC_HI_ULO
4054 BFD_RELOC_M32R_GOTPC_HI_SLO
4056 BFD_RELOC_M32R_GOTPC_LO
4065 This is a 20 bit absolute address.
4067 BFD_RELOC_NDS32_9_PCREL
4069 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4071 BFD_RELOC_NDS32_WORD_9_PCREL
4073 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4075 BFD_RELOC_NDS32_15_PCREL
4077 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4079 BFD_RELOC_NDS32_17_PCREL
4081 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4083 BFD_RELOC_NDS32_25_PCREL
4085 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4087 BFD_RELOC_NDS32_HI20
4089 This is a 20-bit reloc containing the high 20 bits of an address
4090 used with the lower 12 bits
4092 BFD_RELOC_NDS32_LO12S3
4094 This is a 12-bit reloc containing the lower 12 bits of an address
4095 then shift right by 3. This is used with ldi,sdi...
4097 BFD_RELOC_NDS32_LO12S2
4099 This is a 12-bit reloc containing the lower 12 bits of an address
4100 then shift left by 2. This is used with lwi,swi...
4102 BFD_RELOC_NDS32_LO12S1
4104 This is a 12-bit reloc containing the lower 12 bits of an address
4105 then shift left by 1. This is used with lhi,shi...
4107 BFD_RELOC_NDS32_LO12S0
4109 This is a 12-bit reloc containing the lower 12 bits of an address
4110 then shift left by 0. This is used with lbisbi...
4112 BFD_RELOC_NDS32_LO12S0_ORI
4114 This is a 12-bit reloc containing the lower 12 bits of an address
4115 then shift left by 0. This is only used with branch relaxations
4117 BFD_RELOC_NDS32_SDA15S3
4119 This is a 15-bit reloc containing the small data area 18-bit signed offset
4120 and shift left by 3 for use in ldi, sdi...
4122 BFD_RELOC_NDS32_SDA15S2
4124 This is a 15-bit reloc containing the small data area 17-bit signed offset
4125 and shift left by 2 for use in lwi, swi...
4127 BFD_RELOC_NDS32_SDA15S1
4129 This is a 15-bit reloc containing the small data area 16-bit signed offset
4130 and shift left by 1 for use in lhi, shi...
4132 BFD_RELOC_NDS32_SDA15S0
4134 This is a 15-bit reloc containing the small data area 15-bit signed offset
4135 and shift left by 0 for use in lbi, sbi...
4137 BFD_RELOC_NDS32_SDA16S3
4139 This is a 16-bit reloc containing the small data area 16-bit signed offset
4142 BFD_RELOC_NDS32_SDA17S2
4144 This is a 17-bit reloc containing the small data area 17-bit signed offset
4145 and shift left by 2 for use in lwi.gp, swi.gp...
4147 BFD_RELOC_NDS32_SDA18S1
4149 This is a 18-bit reloc containing the small data area 18-bit signed offset
4150 and shift left by 1 for use in lhi.gp, shi.gp...
4152 BFD_RELOC_NDS32_SDA19S0
4154 This is a 19-bit reloc containing the small data area 19-bit signed offset
4155 and shift left by 0 for use in lbi.gp, sbi.gp...
4157 BFD_RELOC_NDS32_GOT20
4159 BFD_RELOC_NDS32_9_PLTREL
4161 BFD_RELOC_NDS32_25_PLTREL
4163 BFD_RELOC_NDS32_COPY
4165 BFD_RELOC_NDS32_GLOB_DAT
4167 BFD_RELOC_NDS32_JMP_SLOT
4169 BFD_RELOC_NDS32_RELATIVE
4171 BFD_RELOC_NDS32_GOTOFF
4173 BFD_RELOC_NDS32_GOTOFF_HI20
4175 BFD_RELOC_NDS32_GOTOFF_LO12
4177 BFD_RELOC_NDS32_GOTPC20
4179 BFD_RELOC_NDS32_GOT_HI20
4181 BFD_RELOC_NDS32_GOT_LO12
4183 BFD_RELOC_NDS32_GOTPC_HI20
4185 BFD_RELOC_NDS32_GOTPC_LO12
4189 BFD_RELOC_NDS32_INSN16
4191 BFD_RELOC_NDS32_LABEL
4193 BFD_RELOC_NDS32_LONGCALL1
4195 BFD_RELOC_NDS32_LONGCALL2
4197 BFD_RELOC_NDS32_LONGCALL3
4199 BFD_RELOC_NDS32_LONGJUMP1
4201 BFD_RELOC_NDS32_LONGJUMP2
4203 BFD_RELOC_NDS32_LONGJUMP3
4205 BFD_RELOC_NDS32_LOADSTORE
4207 BFD_RELOC_NDS32_9_FIXED
4209 BFD_RELOC_NDS32_15_FIXED
4211 BFD_RELOC_NDS32_17_FIXED
4213 BFD_RELOC_NDS32_25_FIXED
4215 BFD_RELOC_NDS32_LONGCALL4
4217 BFD_RELOC_NDS32_LONGCALL5
4219 BFD_RELOC_NDS32_LONGCALL6
4221 BFD_RELOC_NDS32_LONGJUMP4
4223 BFD_RELOC_NDS32_LONGJUMP5
4225 BFD_RELOC_NDS32_LONGJUMP6
4227 BFD_RELOC_NDS32_LONGJUMP7
4231 BFD_RELOC_NDS32_PLTREL_HI20
4233 BFD_RELOC_NDS32_PLTREL_LO12
4235 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4237 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4241 BFD_RELOC_NDS32_SDA12S2_DP
4243 BFD_RELOC_NDS32_SDA12S2_SP
4245 BFD_RELOC_NDS32_LO12S2_DP
4247 BFD_RELOC_NDS32_LO12S2_SP
4251 BFD_RELOC_NDS32_DWARF2_OP1
4253 BFD_RELOC_NDS32_DWARF2_OP2
4255 BFD_RELOC_NDS32_DWARF2_LEB
4257 for dwarf2 debug_line.
4259 BFD_RELOC_NDS32_UPDATE_TA
4261 for eliminate 16-bit instructions
4263 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4265 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4267 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4269 BFD_RELOC_NDS32_GOT_LO15
4271 BFD_RELOC_NDS32_GOT_LO19
4273 BFD_RELOC_NDS32_GOTOFF_LO15
4275 BFD_RELOC_NDS32_GOTOFF_LO19
4277 BFD_RELOC_NDS32_GOT15S2
4279 BFD_RELOC_NDS32_GOT17S2
4281 for PIC object relaxation
4286 This is a 5 bit absolute address.
4288 BFD_RELOC_NDS32_10_UPCREL
4290 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4292 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4294 If fp were omitted, fp can used as another gp.
4296 BFD_RELOC_NDS32_RELAX_ENTRY
4298 BFD_RELOC_NDS32_GOT_SUFF
4300 BFD_RELOC_NDS32_GOTOFF_SUFF
4302 BFD_RELOC_NDS32_PLT_GOT_SUFF
4304 BFD_RELOC_NDS32_MULCALL_SUFF
4308 BFD_RELOC_NDS32_PTR_COUNT
4310 BFD_RELOC_NDS32_PTR_RESOLVED
4312 BFD_RELOC_NDS32_PLTBLOCK
4314 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4316 BFD_RELOC_NDS32_RELAX_REGION_END
4318 BFD_RELOC_NDS32_MINUEND
4320 BFD_RELOC_NDS32_SUBTRAHEND
4322 BFD_RELOC_NDS32_DIFF8
4324 BFD_RELOC_NDS32_DIFF16
4326 BFD_RELOC_NDS32_DIFF32
4328 BFD_RELOC_NDS32_DIFF_ULEB128
4330 BFD_RELOC_NDS32_EMPTY
4332 relaxation relative relocation types
4334 BFD_RELOC_NDS32_25_ABS
4336 This is a 25 bit absolute address.
4338 BFD_RELOC_NDS32_DATA
4340 BFD_RELOC_NDS32_TRAN
4342 BFD_RELOC_NDS32_17IFC_PCREL
4344 BFD_RELOC_NDS32_10IFCU_PCREL
4346 For ex9 and ifc using.
4348 BFD_RELOC_NDS32_TPOFF
4350 BFD_RELOC_NDS32_TLS_LE_HI20
4352 BFD_RELOC_NDS32_TLS_LE_LO12
4354 BFD_RELOC_NDS32_TLS_LE_ADD
4356 BFD_RELOC_NDS32_TLS_LE_LS
4358 BFD_RELOC_NDS32_GOTTPOFF
4360 BFD_RELOC_NDS32_TLS_IE_HI20
4362 BFD_RELOC_NDS32_TLS_IE_LO12S2
4364 BFD_RELOC_NDS32_TLS_TPOFF
4366 BFD_RELOC_NDS32_TLS_LE_20
4368 BFD_RELOC_NDS32_TLS_LE_15S0
4370 BFD_RELOC_NDS32_TLS_LE_15S1
4372 BFD_RELOC_NDS32_TLS_LE_15S2
4378 BFD_RELOC_V850_9_PCREL
4380 This is a 9-bit reloc
4382 BFD_RELOC_V850_22_PCREL
4384 This is a 22-bit reloc
4387 BFD_RELOC_V850_SDA_16_16_OFFSET
4389 This is a 16 bit offset from the short data area pointer.
4391 BFD_RELOC_V850_SDA_15_16_OFFSET
4393 This is a 16 bit offset (of which only 15 bits are used) from the
4394 short data area pointer.
4396 BFD_RELOC_V850_ZDA_16_16_OFFSET
4398 This is a 16 bit offset from the zero data area pointer.
4400 BFD_RELOC_V850_ZDA_15_16_OFFSET
4402 This is a 16 bit offset (of which only 15 bits are used) from the
4403 zero data area pointer.
4405 BFD_RELOC_V850_TDA_6_8_OFFSET
4407 This is an 8 bit offset (of which only 6 bits are used) from the
4408 tiny data area pointer.
4410 BFD_RELOC_V850_TDA_7_8_OFFSET
4412 This is an 8bit offset (of which only 7 bits are used) from the tiny
4415 BFD_RELOC_V850_TDA_7_7_OFFSET
4417 This is a 7 bit offset from the tiny data area pointer.
4419 BFD_RELOC_V850_TDA_16_16_OFFSET
4421 This is a 16 bit offset from the tiny data area pointer.
4424 BFD_RELOC_V850_TDA_4_5_OFFSET
4426 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4429 BFD_RELOC_V850_TDA_4_4_OFFSET
4431 This is a 4 bit offset from the tiny data area pointer.
4433 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4435 This is a 16 bit offset from the short data area pointer, with the
4436 bits placed non-contiguously in the instruction.
4438 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4440 This is a 16 bit offset from the zero data area pointer, with the
4441 bits placed non-contiguously in the instruction.
4443 BFD_RELOC_V850_CALLT_6_7_OFFSET
4445 This is a 6 bit offset from the call table base pointer.
4447 BFD_RELOC_V850_CALLT_16_16_OFFSET
4449 This is a 16 bit offset from the call table base pointer.
4451 BFD_RELOC_V850_LONGCALL
4453 Used for relaxing indirect function calls.
4455 BFD_RELOC_V850_LONGJUMP
4457 Used for relaxing indirect jumps.
4459 BFD_RELOC_V850_ALIGN
4461 Used to maintain alignment whilst relaxing.
4463 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4465 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4468 BFD_RELOC_V850_16_PCREL
4470 This is a 16-bit reloc.
4472 BFD_RELOC_V850_17_PCREL
4474 This is a 17-bit reloc.
4478 This is a 23-bit reloc.
4480 BFD_RELOC_V850_32_PCREL
4482 This is a 32-bit reloc.
4484 BFD_RELOC_V850_32_ABS
4486 This is a 32-bit reloc.
4488 BFD_RELOC_V850_16_SPLIT_OFFSET
4490 This is a 16-bit reloc.
4492 BFD_RELOC_V850_16_S1
4494 This is a 16-bit reloc.
4496 BFD_RELOC_V850_LO16_S1
4498 Low 16 bits. 16 bit shifted by 1.
4500 BFD_RELOC_V850_CALLT_15_16_OFFSET
4502 This is a 16 bit offset from the call table base pointer.
4504 BFD_RELOC_V850_32_GOTPCREL
4508 BFD_RELOC_V850_16_GOT
4512 BFD_RELOC_V850_32_GOT
4516 BFD_RELOC_V850_22_PLT_PCREL
4520 BFD_RELOC_V850_32_PLT_PCREL
4528 BFD_RELOC_V850_GLOB_DAT
4532 BFD_RELOC_V850_JMP_SLOT
4536 BFD_RELOC_V850_RELATIVE
4540 BFD_RELOC_V850_16_GOTOFF
4544 BFD_RELOC_V850_32_GOTOFF
4559 This is a 8bit DP reloc for the tms320c30, where the most
4560 significant 8 bits of a 24 bit word are placed into the least
4561 significant 8 bits of the opcode.
4564 BFD_RELOC_TIC54X_PARTLS7
4566 This is a 7bit reloc for the tms320c54x, where the least
4567 significant 7 bits of a 16 bit word are placed into the least
4568 significant 7 bits of the opcode.
4571 BFD_RELOC_TIC54X_PARTMS9
4573 This is a 9bit DP reloc for the tms320c54x, where the most
4574 significant 9 bits of a 16 bit word are placed into the least
4575 significant 9 bits of the opcode.
4580 This is an extended address 23-bit reloc for the tms320c54x.
4583 BFD_RELOC_TIC54X_16_OF_23
4585 This is a 16-bit reloc for the tms320c54x, where the least
4586 significant 16 bits of a 23-bit extended address are placed into
4590 BFD_RELOC_TIC54X_MS7_OF_23
4592 This is a reloc for the tms320c54x, where the most
4593 significant 7 bits of a 23-bit extended address are placed into
4597 BFD_RELOC_C6000_PCR_S21
4599 BFD_RELOC_C6000_PCR_S12
4601 BFD_RELOC_C6000_PCR_S10
4603 BFD_RELOC_C6000_PCR_S7
4605 BFD_RELOC_C6000_ABS_S16
4607 BFD_RELOC_C6000_ABS_L16
4609 BFD_RELOC_C6000_ABS_H16
4611 BFD_RELOC_C6000_SBR_U15_B
4613 BFD_RELOC_C6000_SBR_U15_H
4615 BFD_RELOC_C6000_SBR_U15_W
4617 BFD_RELOC_C6000_SBR_S16
4619 BFD_RELOC_C6000_SBR_L16_B
4621 BFD_RELOC_C6000_SBR_L16_H
4623 BFD_RELOC_C6000_SBR_L16_W
4625 BFD_RELOC_C6000_SBR_H16_B
4627 BFD_RELOC_C6000_SBR_H16_H
4629 BFD_RELOC_C6000_SBR_H16_W
4631 BFD_RELOC_C6000_SBR_GOT_U15_W
4633 BFD_RELOC_C6000_SBR_GOT_L16_W
4635 BFD_RELOC_C6000_SBR_GOT_H16_W
4637 BFD_RELOC_C6000_DSBT_INDEX
4639 BFD_RELOC_C6000_PREL31
4641 BFD_RELOC_C6000_COPY
4643 BFD_RELOC_C6000_JUMP_SLOT
4645 BFD_RELOC_C6000_EHTYPE
4647 BFD_RELOC_C6000_PCR_H16
4649 BFD_RELOC_C6000_PCR_L16
4651 BFD_RELOC_C6000_ALIGN
4653 BFD_RELOC_C6000_FPHEAD
4655 BFD_RELOC_C6000_NOCMP
4657 TMS320C6000 relocations.
4662 This is a 48 bit reloc for the FR30 that stores 32 bits.
4666 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4669 BFD_RELOC_FR30_6_IN_4
4671 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4674 BFD_RELOC_FR30_8_IN_8
4676 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4679 BFD_RELOC_FR30_9_IN_8
4681 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4684 BFD_RELOC_FR30_10_IN_8
4686 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4689 BFD_RELOC_FR30_9_PCREL
4691 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4692 short offset into 8 bits.
4694 BFD_RELOC_FR30_12_PCREL
4696 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4697 short offset into 11 bits.
4700 BFD_RELOC_MCORE_PCREL_IMM8BY4
4702 BFD_RELOC_MCORE_PCREL_IMM11BY2
4704 BFD_RELOC_MCORE_PCREL_IMM4BY2
4706 BFD_RELOC_MCORE_PCREL_32
4708 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4712 Motorola Mcore relocations.
4721 BFD_RELOC_MEP_PCREL8A2
4723 BFD_RELOC_MEP_PCREL12A2
4725 BFD_RELOC_MEP_PCREL17A2
4727 BFD_RELOC_MEP_PCREL24A2
4729 BFD_RELOC_MEP_PCABS24A2
4741 BFD_RELOC_MEP_TPREL7
4743 BFD_RELOC_MEP_TPREL7A2
4745 BFD_RELOC_MEP_TPREL7A4
4747 BFD_RELOC_MEP_UIMM24
4749 BFD_RELOC_MEP_ADDR24A4
4751 BFD_RELOC_MEP_GNU_VTINHERIT
4753 BFD_RELOC_MEP_GNU_VTENTRY
4755 Toshiba Media Processor Relocations.
4759 BFD_RELOC_METAG_HIADDR16
4761 BFD_RELOC_METAG_LOADDR16
4763 BFD_RELOC_METAG_RELBRANCH
4765 BFD_RELOC_METAG_GETSETOFF
4767 BFD_RELOC_METAG_HIOG
4769 BFD_RELOC_METAG_LOOG
4771 BFD_RELOC_METAG_REL8
4773 BFD_RELOC_METAG_REL16
4775 BFD_RELOC_METAG_HI16_GOTOFF
4777 BFD_RELOC_METAG_LO16_GOTOFF
4779 BFD_RELOC_METAG_GETSET_GOTOFF
4781 BFD_RELOC_METAG_GETSET_GOT
4783 BFD_RELOC_METAG_HI16_GOTPC
4785 BFD_RELOC_METAG_LO16_GOTPC
4787 BFD_RELOC_METAG_HI16_PLT
4789 BFD_RELOC_METAG_LO16_PLT
4791 BFD_RELOC_METAG_RELBRANCH_PLT
4793 BFD_RELOC_METAG_GOTOFF
4797 BFD_RELOC_METAG_COPY
4799 BFD_RELOC_METAG_JMP_SLOT
4801 BFD_RELOC_METAG_RELATIVE
4803 BFD_RELOC_METAG_GLOB_DAT
4805 BFD_RELOC_METAG_TLS_GD
4807 BFD_RELOC_METAG_TLS_LDM
4809 BFD_RELOC_METAG_TLS_LDO_HI16
4811 BFD_RELOC_METAG_TLS_LDO_LO16
4813 BFD_RELOC_METAG_TLS_LDO
4815 BFD_RELOC_METAG_TLS_IE
4817 BFD_RELOC_METAG_TLS_IENONPIC
4819 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4821 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4823 BFD_RELOC_METAG_TLS_TPOFF
4825 BFD_RELOC_METAG_TLS_DTPMOD
4827 BFD_RELOC_METAG_TLS_DTPOFF
4829 BFD_RELOC_METAG_TLS_LE
4831 BFD_RELOC_METAG_TLS_LE_HI16
4833 BFD_RELOC_METAG_TLS_LE_LO16
4835 Imagination Technologies Meta relocations.
4840 BFD_RELOC_MMIX_GETA_1
4842 BFD_RELOC_MMIX_GETA_2
4844 BFD_RELOC_MMIX_GETA_3
4846 These are relocations for the GETA instruction.
4848 BFD_RELOC_MMIX_CBRANCH
4850 BFD_RELOC_MMIX_CBRANCH_J
4852 BFD_RELOC_MMIX_CBRANCH_1
4854 BFD_RELOC_MMIX_CBRANCH_2
4856 BFD_RELOC_MMIX_CBRANCH_3
4858 These are relocations for a conditional branch instruction.
4860 BFD_RELOC_MMIX_PUSHJ
4862 BFD_RELOC_MMIX_PUSHJ_1
4864 BFD_RELOC_MMIX_PUSHJ_2
4866 BFD_RELOC_MMIX_PUSHJ_3
4868 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4870 These are relocations for the PUSHJ instruction.
4874 BFD_RELOC_MMIX_JMP_1
4876 BFD_RELOC_MMIX_JMP_2
4878 BFD_RELOC_MMIX_JMP_3
4880 These are relocations for the JMP instruction.
4882 BFD_RELOC_MMIX_ADDR19
4884 This is a relocation for a relative address as in a GETA instruction or
4887 BFD_RELOC_MMIX_ADDR27
4889 This is a relocation for a relative address as in a JMP instruction.
4891 BFD_RELOC_MMIX_REG_OR_BYTE
4893 This is a relocation for an instruction field that may be a general
4894 register or a value 0..255.
4898 This is a relocation for an instruction field that may be a general
4901 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4903 This is a relocation for two instruction fields holding a register and
4904 an offset, the equivalent of the relocation.
4906 BFD_RELOC_MMIX_LOCAL
4908 This relocation is an assertion that the expression is not allocated as
4909 a global register. It does not modify contents.
4912 BFD_RELOC_AVR_7_PCREL
4914 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4915 short offset into 7 bits.
4917 BFD_RELOC_AVR_13_PCREL
4919 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4920 short offset into 12 bits.
4924 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4925 program memory address) into 16 bits.
4927 BFD_RELOC_AVR_LO8_LDI
4929 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4930 data memory address) into 8 bit immediate value of LDI insn.
4932 BFD_RELOC_AVR_HI8_LDI
4934 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4935 of data memory address) into 8 bit immediate value of LDI insn.
4937 BFD_RELOC_AVR_HH8_LDI
4939 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4940 of program memory address) into 8 bit immediate value of LDI insn.
4942 BFD_RELOC_AVR_MS8_LDI
4944 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4945 of 32 bit value) into 8 bit immediate value of LDI insn.
4947 BFD_RELOC_AVR_LO8_LDI_NEG
4949 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4950 (usually data memory address) into 8 bit immediate value of SUBI insn.
4952 BFD_RELOC_AVR_HI8_LDI_NEG
4954 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4955 (high 8 bit of data memory address) into 8 bit immediate value of
4958 BFD_RELOC_AVR_HH8_LDI_NEG
4960 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4961 (most high 8 bit of program memory address) into 8 bit immediate value
4962 of LDI or SUBI insn.
4964 BFD_RELOC_AVR_MS8_LDI_NEG
4966 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4967 of 32 bit value) into 8 bit immediate value of LDI insn.
4969 BFD_RELOC_AVR_LO8_LDI_PM
4971 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4972 command address) into 8 bit immediate value of LDI insn.
4974 BFD_RELOC_AVR_LO8_LDI_GS
4976 This is a 16 bit reloc for the AVR that stores 8 bit value
4977 (command address) into 8 bit immediate value of LDI insn. If the address
4978 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4981 BFD_RELOC_AVR_HI8_LDI_PM
4983 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4984 of command address) into 8 bit immediate value of LDI insn.
4986 BFD_RELOC_AVR_HI8_LDI_GS
4988 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4989 of command address) into 8 bit immediate value of LDI insn. If the address
4990 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4993 BFD_RELOC_AVR_HH8_LDI_PM
4995 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4996 of command address) into 8 bit immediate value of LDI insn.
4998 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5000 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5001 (usually command address) into 8 bit immediate value of SUBI insn.
5003 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5005 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5006 (high 8 bit of 16 bit command address) into 8 bit immediate value
5009 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5011 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5012 (high 6 bit of 22 bit command address) into 8 bit immediate
5017 This is a 32 bit reloc for the AVR that stores 23 bit value
5022 This is a 16 bit reloc for the AVR that stores all needed bits
5023 for absolute addressing with ldi with overflow check to linktime
5027 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5030 BFD_RELOC_AVR_6_ADIW
5032 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5037 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5038 in .byte lo8(symbol)
5042 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5043 in .byte hi8(symbol)
5047 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5048 in .byte hlo8(symbol)
5052 BFD_RELOC_AVR_DIFF16
5054 BFD_RELOC_AVR_DIFF32
5056 AVR relocations to mark the difference of two local symbols.
5057 These are only needed to support linker relaxation and can be ignored
5058 when not relaxing. The field is set to the value of the difference
5059 assuming no relaxation. The relocation encodes the position of the
5060 second symbol so the linker can determine whether to adjust the field
5063 BFD_RELOC_AVR_LDS_STS_16
5065 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5066 lds and sts instructions supported only tiny core.
5070 This is a 6 bit reloc for the AVR that stores an I/O register
5071 number for the IN and OUT instructions
5075 This is a 5 bit reloc for the AVR that stores an I/O register
5076 number for the SBIC, SBIS, SBI and CBI instructions
5079 BFD_RELOC_RISCV_HI20
5081 BFD_RELOC_RISCV_PCREL_HI20
5083 BFD_RELOC_RISCV_PCREL_LO12_I
5085 BFD_RELOC_RISCV_PCREL_LO12_S
5087 BFD_RELOC_RISCV_LO12_I
5089 BFD_RELOC_RISCV_LO12_S
5091 BFD_RELOC_RISCV_GPREL12_I
5093 BFD_RELOC_RISCV_GPREL12_S
5095 BFD_RELOC_RISCV_TPREL_HI20
5097 BFD_RELOC_RISCV_TPREL_LO12_I
5099 BFD_RELOC_RISCV_TPREL_LO12_S
5101 BFD_RELOC_RISCV_TPREL_ADD
5103 BFD_RELOC_RISCV_CALL
5105 BFD_RELOC_RISCV_CALL_PLT
5107 BFD_RELOC_RISCV_ADD8
5109 BFD_RELOC_RISCV_ADD16
5111 BFD_RELOC_RISCV_ADD32
5113 BFD_RELOC_RISCV_ADD64
5115 BFD_RELOC_RISCV_SUB8
5117 BFD_RELOC_RISCV_SUB16
5119 BFD_RELOC_RISCV_SUB32
5121 BFD_RELOC_RISCV_SUB64
5123 BFD_RELOC_RISCV_GOT_HI20
5125 BFD_RELOC_RISCV_TLS_GOT_HI20
5127 BFD_RELOC_RISCV_TLS_GD_HI20
5131 BFD_RELOC_RISCV_TLS_DTPMOD32
5133 BFD_RELOC_RISCV_TLS_DTPREL32
5135 BFD_RELOC_RISCV_TLS_DTPMOD64
5137 BFD_RELOC_RISCV_TLS_DTPREL64
5139 BFD_RELOC_RISCV_TLS_TPREL32
5141 BFD_RELOC_RISCV_TLS_TPREL64
5143 BFD_RELOC_RISCV_ALIGN
5145 BFD_RELOC_RISCV_RVC_BRANCH
5147 BFD_RELOC_RISCV_RVC_JUMP
5149 BFD_RELOC_RISCV_RVC_LUI
5151 BFD_RELOC_RISCV_GPREL_I
5153 BFD_RELOC_RISCV_GPREL_S
5155 BFD_RELOC_RISCV_TPREL_I
5157 BFD_RELOC_RISCV_TPREL_S
5159 BFD_RELOC_RISCV_RELAX
5163 BFD_RELOC_RISCV_SUB6
5165 BFD_RELOC_RISCV_SET6
5167 BFD_RELOC_RISCV_SET8
5169 BFD_RELOC_RISCV_SET16
5171 BFD_RELOC_RISCV_SET32
5173 BFD_RELOC_RISCV_32_PCREL
5180 BFD_RELOC_RL78_NEG16
5182 BFD_RELOC_RL78_NEG24
5184 BFD_RELOC_RL78_NEG32
5186 BFD_RELOC_RL78_16_OP
5188 BFD_RELOC_RL78_24_OP
5190 BFD_RELOC_RL78_32_OP
5198 BFD_RELOC_RL78_DIR3U_PCREL
5202 BFD_RELOC_RL78_GPRELB
5204 BFD_RELOC_RL78_GPRELW
5206 BFD_RELOC_RL78_GPRELL
5210 BFD_RELOC_RL78_OP_SUBTRACT
5212 BFD_RELOC_RL78_OP_NEG
5214 BFD_RELOC_RL78_OP_AND
5216 BFD_RELOC_RL78_OP_SHRA
5220 BFD_RELOC_RL78_ABS16
5222 BFD_RELOC_RL78_ABS16_REV
5224 BFD_RELOC_RL78_ABS32
5226 BFD_RELOC_RL78_ABS32_REV
5228 BFD_RELOC_RL78_ABS16U
5230 BFD_RELOC_RL78_ABS16UW
5232 BFD_RELOC_RL78_ABS16UL
5234 BFD_RELOC_RL78_RELAX
5244 BFD_RELOC_RL78_SADDR
5246 Renesas RL78 Relocations.
5269 BFD_RELOC_RX_DIR3U_PCREL
5281 BFD_RELOC_RX_OP_SUBTRACT
5289 BFD_RELOC_RX_ABS16_REV
5293 BFD_RELOC_RX_ABS32_REV
5297 BFD_RELOC_RX_ABS16UW
5299 BFD_RELOC_RX_ABS16UL
5303 Renesas RX Relocations.
5316 32 bit PC relative PLT address.
5320 Copy symbol at runtime.
5322 BFD_RELOC_390_GLOB_DAT
5326 BFD_RELOC_390_JMP_SLOT
5330 BFD_RELOC_390_RELATIVE
5332 Adjust by program base.
5336 32 bit PC relative offset to GOT.
5342 BFD_RELOC_390_PC12DBL
5344 PC relative 12 bit shifted by 1.
5346 BFD_RELOC_390_PLT12DBL
5348 12 bit PC rel. PLT shifted by 1.
5350 BFD_RELOC_390_PC16DBL
5352 PC relative 16 bit shifted by 1.
5354 BFD_RELOC_390_PLT16DBL
5356 16 bit PC rel. PLT shifted by 1.
5358 BFD_RELOC_390_PC24DBL
5360 PC relative 24 bit shifted by 1.
5362 BFD_RELOC_390_PLT24DBL
5364 24 bit PC rel. PLT shifted by 1.
5366 BFD_RELOC_390_PC32DBL
5368 PC relative 32 bit shifted by 1.
5370 BFD_RELOC_390_PLT32DBL
5372 32 bit PC rel. PLT shifted by 1.
5374 BFD_RELOC_390_GOTPCDBL
5376 32 bit PC rel. GOT shifted by 1.
5384 64 bit PC relative PLT address.
5386 BFD_RELOC_390_GOTENT
5388 32 bit rel. offset to GOT entry.
5390 BFD_RELOC_390_GOTOFF64
5392 64 bit offset to GOT.
5394 BFD_RELOC_390_GOTPLT12
5396 12-bit offset to symbol-entry within GOT, with PLT handling.
5398 BFD_RELOC_390_GOTPLT16
5400 16-bit offset to symbol-entry within GOT, with PLT handling.
5402 BFD_RELOC_390_GOTPLT32
5404 32-bit offset to symbol-entry within GOT, with PLT handling.
5406 BFD_RELOC_390_GOTPLT64
5408 64-bit offset to symbol-entry within GOT, with PLT handling.
5410 BFD_RELOC_390_GOTPLTENT
5412 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5414 BFD_RELOC_390_PLTOFF16
5416 16-bit rel. offset from the GOT to a PLT entry.
5418 BFD_RELOC_390_PLTOFF32
5420 32-bit rel. offset from the GOT to a PLT entry.
5422 BFD_RELOC_390_PLTOFF64
5424 64-bit rel. offset from the GOT to a PLT entry.
5427 BFD_RELOC_390_TLS_LOAD
5429 BFD_RELOC_390_TLS_GDCALL
5431 BFD_RELOC_390_TLS_LDCALL
5433 BFD_RELOC_390_TLS_GD32
5435 BFD_RELOC_390_TLS_GD64
5437 BFD_RELOC_390_TLS_GOTIE12
5439 BFD_RELOC_390_TLS_GOTIE32
5441 BFD_RELOC_390_TLS_GOTIE64
5443 BFD_RELOC_390_TLS_LDM32
5445 BFD_RELOC_390_TLS_LDM64
5447 BFD_RELOC_390_TLS_IE32
5449 BFD_RELOC_390_TLS_IE64
5451 BFD_RELOC_390_TLS_IEENT
5453 BFD_RELOC_390_TLS_LE32
5455 BFD_RELOC_390_TLS_LE64
5457 BFD_RELOC_390_TLS_LDO32
5459 BFD_RELOC_390_TLS_LDO64
5461 BFD_RELOC_390_TLS_DTPMOD
5463 BFD_RELOC_390_TLS_DTPOFF
5465 BFD_RELOC_390_TLS_TPOFF
5467 s390 tls relocations.
5474 BFD_RELOC_390_GOTPLT20
5476 BFD_RELOC_390_TLS_GOTIE20
5478 Long displacement extension.
5481 BFD_RELOC_390_IRELATIVE
5483 STT_GNU_IFUNC relocation.
5486 BFD_RELOC_SCORE_GPREL15
5489 Low 16 bit for load/store
5491 BFD_RELOC_SCORE_DUMMY2
5495 This is a 24-bit reloc with the right 1 bit assumed to be 0
5497 BFD_RELOC_SCORE_BRANCH
5499 This is a 19-bit reloc with the right 1 bit assumed to be 0
5501 BFD_RELOC_SCORE_IMM30
5503 This is a 32-bit reloc for 48-bit instructions.
5505 BFD_RELOC_SCORE_IMM32
5507 This is a 32-bit reloc for 48-bit instructions.
5509 BFD_RELOC_SCORE16_JMP
5511 This is a 11-bit reloc with the right 1 bit assumed to be 0
5513 BFD_RELOC_SCORE16_BRANCH
5515 This is a 8-bit reloc with the right 1 bit assumed to be 0
5517 BFD_RELOC_SCORE_BCMP
5519 This is a 9-bit reloc with the right 1 bit assumed to be 0
5521 BFD_RELOC_SCORE_GOT15
5523 BFD_RELOC_SCORE_GOT_LO16
5525 BFD_RELOC_SCORE_CALL15
5527 BFD_RELOC_SCORE_DUMMY_HI16
5529 Undocumented Score relocs
5534 Scenix IP2K - 9-bit register number / data address
5538 Scenix IP2K - 4-bit register/data bank number
5540 BFD_RELOC_IP2K_ADDR16CJP
5542 Scenix IP2K - low 13 bits of instruction word address
5544 BFD_RELOC_IP2K_PAGE3
5546 Scenix IP2K - high 3 bits of instruction word address
5548 BFD_RELOC_IP2K_LO8DATA
5550 BFD_RELOC_IP2K_HI8DATA
5552 BFD_RELOC_IP2K_EX8DATA
5554 Scenix IP2K - ext/low/high 8 bits of data address
5556 BFD_RELOC_IP2K_LO8INSN
5558 BFD_RELOC_IP2K_HI8INSN
5560 Scenix IP2K - low/high 8 bits of instruction word address
5562 BFD_RELOC_IP2K_PC_SKIP
5564 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5568 Scenix IP2K - 16 bit word address in text section.
5570 BFD_RELOC_IP2K_FR_OFFSET
5572 Scenix IP2K - 7-bit sp or dp offset
5574 BFD_RELOC_VPE4KMATH_DATA
5576 BFD_RELOC_VPE4KMATH_INSN
5578 Scenix VPE4K coprocessor - data/insn-space addressing
5581 BFD_RELOC_VTABLE_INHERIT
5583 BFD_RELOC_VTABLE_ENTRY
5585 These two relocations are used by the linker to determine which of
5586 the entries in a C++ virtual function table are actually used. When
5587 the --gc-sections option is given, the linker will zero out the entries
5588 that are not used, so that the code for those functions need not be
5589 included in the output.
5591 VTABLE_INHERIT is a zero-space relocation used to describe to the
5592 linker the inheritance tree of a C++ virtual function table. The
5593 relocation's symbol should be the parent class' vtable, and the
5594 relocation should be located at the child vtable.
5596 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5597 virtual function table entry. The reloc's symbol should refer to the
5598 table of the class mentioned in the code. Off of that base, an offset
5599 describes the entry that is being used. For Rela hosts, this offset
5600 is stored in the reloc's addend. For Rel hosts, we are forced to put
5601 this offset in the reloc's section offset.
5604 BFD_RELOC_IA64_IMM14
5606 BFD_RELOC_IA64_IMM22
5608 BFD_RELOC_IA64_IMM64
5610 BFD_RELOC_IA64_DIR32MSB
5612 BFD_RELOC_IA64_DIR32LSB
5614 BFD_RELOC_IA64_DIR64MSB
5616 BFD_RELOC_IA64_DIR64LSB
5618 BFD_RELOC_IA64_GPREL22
5620 BFD_RELOC_IA64_GPREL64I
5622 BFD_RELOC_IA64_GPREL32MSB
5624 BFD_RELOC_IA64_GPREL32LSB
5626 BFD_RELOC_IA64_GPREL64MSB
5628 BFD_RELOC_IA64_GPREL64LSB
5630 BFD_RELOC_IA64_LTOFF22
5632 BFD_RELOC_IA64_LTOFF64I
5634 BFD_RELOC_IA64_PLTOFF22
5636 BFD_RELOC_IA64_PLTOFF64I
5638 BFD_RELOC_IA64_PLTOFF64MSB
5640 BFD_RELOC_IA64_PLTOFF64LSB
5642 BFD_RELOC_IA64_FPTR64I
5644 BFD_RELOC_IA64_FPTR32MSB
5646 BFD_RELOC_IA64_FPTR32LSB
5648 BFD_RELOC_IA64_FPTR64MSB
5650 BFD_RELOC_IA64_FPTR64LSB
5652 BFD_RELOC_IA64_PCREL21B
5654 BFD_RELOC_IA64_PCREL21BI
5656 BFD_RELOC_IA64_PCREL21M
5658 BFD_RELOC_IA64_PCREL21F
5660 BFD_RELOC_IA64_PCREL22
5662 BFD_RELOC_IA64_PCREL60B
5664 BFD_RELOC_IA64_PCREL64I
5666 BFD_RELOC_IA64_PCREL32MSB
5668 BFD_RELOC_IA64_PCREL32LSB
5670 BFD_RELOC_IA64_PCREL64MSB
5672 BFD_RELOC_IA64_PCREL64LSB
5674 BFD_RELOC_IA64_LTOFF_FPTR22
5676 BFD_RELOC_IA64_LTOFF_FPTR64I
5678 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5680 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5682 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5684 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5686 BFD_RELOC_IA64_SEGREL32MSB
5688 BFD_RELOC_IA64_SEGREL32LSB
5690 BFD_RELOC_IA64_SEGREL64MSB
5692 BFD_RELOC_IA64_SEGREL64LSB
5694 BFD_RELOC_IA64_SECREL32MSB
5696 BFD_RELOC_IA64_SECREL32LSB
5698 BFD_RELOC_IA64_SECREL64MSB
5700 BFD_RELOC_IA64_SECREL64LSB
5702 BFD_RELOC_IA64_REL32MSB
5704 BFD_RELOC_IA64_REL32LSB
5706 BFD_RELOC_IA64_REL64MSB
5708 BFD_RELOC_IA64_REL64LSB
5710 BFD_RELOC_IA64_LTV32MSB
5712 BFD_RELOC_IA64_LTV32LSB
5714 BFD_RELOC_IA64_LTV64MSB
5716 BFD_RELOC_IA64_LTV64LSB
5718 BFD_RELOC_IA64_IPLTMSB
5720 BFD_RELOC_IA64_IPLTLSB
5724 BFD_RELOC_IA64_LTOFF22X
5726 BFD_RELOC_IA64_LDXMOV
5728 BFD_RELOC_IA64_TPREL14
5730 BFD_RELOC_IA64_TPREL22
5732 BFD_RELOC_IA64_TPREL64I
5734 BFD_RELOC_IA64_TPREL64MSB
5736 BFD_RELOC_IA64_TPREL64LSB
5738 BFD_RELOC_IA64_LTOFF_TPREL22
5740 BFD_RELOC_IA64_DTPMOD64MSB
5742 BFD_RELOC_IA64_DTPMOD64LSB
5744 BFD_RELOC_IA64_LTOFF_DTPMOD22
5746 BFD_RELOC_IA64_DTPREL14
5748 BFD_RELOC_IA64_DTPREL22
5750 BFD_RELOC_IA64_DTPREL64I
5752 BFD_RELOC_IA64_DTPREL32MSB
5754 BFD_RELOC_IA64_DTPREL32LSB
5756 BFD_RELOC_IA64_DTPREL64MSB
5758 BFD_RELOC_IA64_DTPREL64LSB
5760 BFD_RELOC_IA64_LTOFF_DTPREL22
5762 Intel IA64 Relocations.
5765 BFD_RELOC_M68HC11_HI8
5767 Motorola 68HC11 reloc.
5768 This is the 8 bit high part of an absolute address.
5770 BFD_RELOC_M68HC11_LO8
5772 Motorola 68HC11 reloc.
5773 This is the 8 bit low part of an absolute address.
5775 BFD_RELOC_M68HC11_3B
5777 Motorola 68HC11 reloc.
5778 This is the 3 bit of a value.
5780 BFD_RELOC_M68HC11_RL_JUMP
5782 Motorola 68HC11 reloc.
5783 This reloc marks the beginning of a jump/call instruction.
5784 It is used for linker relaxation to correctly identify beginning
5785 of instruction and change some branches to use PC-relative
5788 BFD_RELOC_M68HC11_RL_GROUP
5790 Motorola 68HC11 reloc.
5791 This reloc marks a group of several instructions that gcc generates
5792 and for which the linker relaxation pass can modify and/or remove
5795 BFD_RELOC_M68HC11_LO16
5797 Motorola 68HC11 reloc.
5798 This is the 16-bit lower part of an address. It is used for 'call'
5799 instruction to specify the symbol address without any special
5800 transformation (due to memory bank window).
5802 BFD_RELOC_M68HC11_PAGE
5804 Motorola 68HC11 reloc.
5805 This is a 8-bit reloc that specifies the page number of an address.
5806 It is used by 'call' instruction to specify the page number of
5809 BFD_RELOC_M68HC11_24
5811 Motorola 68HC11 reloc.
5812 This is a 24-bit reloc that represents the address with a 16-bit
5813 value and a 8-bit page number. The symbol address is transformed
5814 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5816 BFD_RELOC_M68HC12_5B
5818 Motorola 68HC12 reloc.
5819 This is the 5 bits of a value.
5821 BFD_RELOC_XGATE_RL_JUMP
5823 Freescale XGATE reloc.
5824 This reloc marks the beginning of a bra/jal instruction.
5826 BFD_RELOC_XGATE_RL_GROUP
5828 Freescale XGATE reloc.
5829 This reloc marks a group of several instructions that gcc generates
5830 and for which the linker relaxation pass can modify and/or remove
5833 BFD_RELOC_XGATE_LO16
5835 Freescale XGATE reloc.
5836 This is the 16-bit lower part of an address. It is used for the '16-bit'
5839 BFD_RELOC_XGATE_GPAGE
5841 Freescale XGATE reloc.
5845 Freescale XGATE reloc.
5847 BFD_RELOC_XGATE_PCREL_9
5849 Freescale XGATE reloc.
5850 This is a 9-bit pc-relative reloc.
5852 BFD_RELOC_XGATE_PCREL_10
5854 Freescale XGATE reloc.
5855 This is a 10-bit pc-relative reloc.
5857 BFD_RELOC_XGATE_IMM8_LO
5859 Freescale XGATE reloc.
5860 This is the 16-bit lower part of an address. It is used for the '16-bit'
5863 BFD_RELOC_XGATE_IMM8_HI
5865 Freescale XGATE reloc.
5866 This is the 16-bit higher part of an address. It is used for the '16-bit'
5869 BFD_RELOC_XGATE_IMM3
5871 Freescale XGATE reloc.
5872 This is a 3-bit pc-relative reloc.
5874 BFD_RELOC_XGATE_IMM4
5876 Freescale XGATE reloc.
5877 This is a 4-bit pc-relative reloc.
5879 BFD_RELOC_XGATE_IMM5
5881 Freescale XGATE reloc.
5882 This is a 5-bit pc-relative reloc.
5884 BFD_RELOC_M68HC12_9B
5886 Motorola 68HC12 reloc.
5887 This is the 9 bits of a value.
5889 BFD_RELOC_M68HC12_16B
5891 Motorola 68HC12 reloc.
5892 This is the 16 bits of a value.
5894 BFD_RELOC_M68HC12_9_PCREL
5896 Motorola 68HC12/XGATE reloc.
5897 This is a PCREL9 branch.
5899 BFD_RELOC_M68HC12_10_PCREL
5901 Motorola 68HC12/XGATE reloc.
5902 This is a PCREL10 branch.
5904 BFD_RELOC_M68HC12_LO8XG
5906 Motorola 68HC12/XGATE reloc.
5907 This is the 8 bit low part of an absolute address and immediately precedes
5908 a matching HI8XG part.
5910 BFD_RELOC_M68HC12_HI8XG
5912 Motorola 68HC12/XGATE reloc.
5913 This is the 8 bit high part of an absolute address and immediately follows
5914 a matching LO8XG part.
5918 BFD_RELOC_16C_NUM08_C
5922 BFD_RELOC_16C_NUM16_C
5926 BFD_RELOC_16C_NUM32_C
5928 BFD_RELOC_16C_DISP04
5930 BFD_RELOC_16C_DISP04_C
5932 BFD_RELOC_16C_DISP08
5934 BFD_RELOC_16C_DISP08_C
5936 BFD_RELOC_16C_DISP16
5938 BFD_RELOC_16C_DISP16_C
5940 BFD_RELOC_16C_DISP24
5942 BFD_RELOC_16C_DISP24_C
5944 BFD_RELOC_16C_DISP24a
5946 BFD_RELOC_16C_DISP24a_C
5950 BFD_RELOC_16C_REG04_C
5952 BFD_RELOC_16C_REG04a
5954 BFD_RELOC_16C_REG04a_C
5958 BFD_RELOC_16C_REG14_C
5962 BFD_RELOC_16C_REG16_C
5966 BFD_RELOC_16C_REG20_C
5970 BFD_RELOC_16C_ABS20_C
5974 BFD_RELOC_16C_ABS24_C
5978 BFD_RELOC_16C_IMM04_C
5982 BFD_RELOC_16C_IMM16_C
5986 BFD_RELOC_16C_IMM20_C
5990 BFD_RELOC_16C_IMM24_C
5994 BFD_RELOC_16C_IMM32_C
5996 NS CR16C Relocations.
6001 BFD_RELOC_CR16_NUM16
6003 BFD_RELOC_CR16_NUM32
6005 BFD_RELOC_CR16_NUM32a
6007 BFD_RELOC_CR16_REGREL0
6009 BFD_RELOC_CR16_REGREL4
6011 BFD_RELOC_CR16_REGREL4a
6013 BFD_RELOC_CR16_REGREL14
6015 BFD_RELOC_CR16_REGREL14a
6017 BFD_RELOC_CR16_REGREL16
6019 BFD_RELOC_CR16_REGREL20
6021 BFD_RELOC_CR16_REGREL20a
6023 BFD_RELOC_CR16_ABS20
6025 BFD_RELOC_CR16_ABS24
6031 BFD_RELOC_CR16_IMM16
6033 BFD_RELOC_CR16_IMM20
6035 BFD_RELOC_CR16_IMM24
6037 BFD_RELOC_CR16_IMM32
6039 BFD_RELOC_CR16_IMM32a
6041 BFD_RELOC_CR16_DISP4
6043 BFD_RELOC_CR16_DISP8
6045 BFD_RELOC_CR16_DISP16
6047 BFD_RELOC_CR16_DISP20
6049 BFD_RELOC_CR16_DISP24
6051 BFD_RELOC_CR16_DISP24a
6053 BFD_RELOC_CR16_SWITCH8
6055 BFD_RELOC_CR16_SWITCH16
6057 BFD_RELOC_CR16_SWITCH32
6059 BFD_RELOC_CR16_GOT_REGREL20
6061 BFD_RELOC_CR16_GOTC_REGREL20
6063 BFD_RELOC_CR16_GLOB_DAT
6065 NS CR16 Relocations.
6072 BFD_RELOC_CRX_REL8_CMP
6080 BFD_RELOC_CRX_REGREL12
6082 BFD_RELOC_CRX_REGREL22
6084 BFD_RELOC_CRX_REGREL28
6086 BFD_RELOC_CRX_REGREL32
6102 BFD_RELOC_CRX_SWITCH8
6104 BFD_RELOC_CRX_SWITCH16
6106 BFD_RELOC_CRX_SWITCH32
6111 BFD_RELOC_CRIS_BDISP8
6113 BFD_RELOC_CRIS_UNSIGNED_5
6115 BFD_RELOC_CRIS_SIGNED_6
6117 BFD_RELOC_CRIS_UNSIGNED_6
6119 BFD_RELOC_CRIS_SIGNED_8
6121 BFD_RELOC_CRIS_UNSIGNED_8
6123 BFD_RELOC_CRIS_SIGNED_16
6125 BFD_RELOC_CRIS_UNSIGNED_16
6127 BFD_RELOC_CRIS_LAPCQ_OFFSET
6129 BFD_RELOC_CRIS_UNSIGNED_4
6131 These relocs are only used within the CRIS assembler. They are not
6132 (at present) written to any object files.
6136 BFD_RELOC_CRIS_GLOB_DAT
6138 BFD_RELOC_CRIS_JUMP_SLOT
6140 BFD_RELOC_CRIS_RELATIVE
6142 Relocs used in ELF shared libraries for CRIS.
6144 BFD_RELOC_CRIS_32_GOT
6146 32-bit offset to symbol-entry within GOT.
6148 BFD_RELOC_CRIS_16_GOT
6150 16-bit offset to symbol-entry within GOT.
6152 BFD_RELOC_CRIS_32_GOTPLT
6154 32-bit offset to symbol-entry within GOT, with PLT handling.
6156 BFD_RELOC_CRIS_16_GOTPLT
6158 16-bit offset to symbol-entry within GOT, with PLT handling.
6160 BFD_RELOC_CRIS_32_GOTREL
6162 32-bit offset to symbol, relative to GOT.
6164 BFD_RELOC_CRIS_32_PLT_GOTREL
6166 32-bit offset to symbol with PLT entry, relative to GOT.
6168 BFD_RELOC_CRIS_32_PLT_PCREL
6170 32-bit offset to symbol with PLT entry, relative to this relocation.
6173 BFD_RELOC_CRIS_32_GOT_GD
6175 BFD_RELOC_CRIS_16_GOT_GD
6177 BFD_RELOC_CRIS_32_GD
6181 BFD_RELOC_CRIS_32_DTPREL
6183 BFD_RELOC_CRIS_16_DTPREL
6185 BFD_RELOC_CRIS_32_GOT_TPREL
6187 BFD_RELOC_CRIS_16_GOT_TPREL
6189 BFD_RELOC_CRIS_32_TPREL
6191 BFD_RELOC_CRIS_16_TPREL
6193 BFD_RELOC_CRIS_DTPMOD
6195 BFD_RELOC_CRIS_32_IE
6197 Relocs used in TLS code for CRIS.
6202 BFD_RELOC_860_GLOB_DAT
6204 BFD_RELOC_860_JUMP_SLOT
6206 BFD_RELOC_860_RELATIVE
6216 BFD_RELOC_860_SPLIT0
6220 BFD_RELOC_860_SPLIT1
6224 BFD_RELOC_860_SPLIT2
6228 BFD_RELOC_860_LOGOT0
6230 BFD_RELOC_860_SPGOT0
6232 BFD_RELOC_860_LOGOT1
6234 BFD_RELOC_860_SPGOT1
6236 BFD_RELOC_860_LOGOTOFF0
6238 BFD_RELOC_860_SPGOTOFF0
6240 BFD_RELOC_860_LOGOTOFF1
6242 BFD_RELOC_860_SPGOTOFF1
6244 BFD_RELOC_860_LOGOTOFF2
6246 BFD_RELOC_860_LOGOTOFF3
6250 BFD_RELOC_860_HIGHADJ
6254 BFD_RELOC_860_HAGOTOFF
6262 BFD_RELOC_860_HIGOTOFF
6264 Intel i860 Relocations.
6267 BFD_RELOC_OR1K_REL_26
6269 BFD_RELOC_OR1K_GOTPC_HI16
6271 BFD_RELOC_OR1K_GOTPC_LO16
6273 BFD_RELOC_OR1K_GOT16
6275 BFD_RELOC_OR1K_PLT26
6277 BFD_RELOC_OR1K_GOTOFF_HI16
6279 BFD_RELOC_OR1K_GOTOFF_LO16
6283 BFD_RELOC_OR1K_GLOB_DAT
6285 BFD_RELOC_OR1K_JMP_SLOT
6287 BFD_RELOC_OR1K_RELATIVE
6289 BFD_RELOC_OR1K_TLS_GD_HI16
6291 BFD_RELOC_OR1K_TLS_GD_LO16
6293 BFD_RELOC_OR1K_TLS_LDM_HI16
6295 BFD_RELOC_OR1K_TLS_LDM_LO16
6297 BFD_RELOC_OR1K_TLS_LDO_HI16
6299 BFD_RELOC_OR1K_TLS_LDO_LO16
6301 BFD_RELOC_OR1K_TLS_IE_HI16
6303 BFD_RELOC_OR1K_TLS_IE_LO16
6305 BFD_RELOC_OR1K_TLS_LE_HI16
6307 BFD_RELOC_OR1K_TLS_LE_LO16
6309 BFD_RELOC_OR1K_TLS_TPOFF
6311 BFD_RELOC_OR1K_TLS_DTPOFF
6313 BFD_RELOC_OR1K_TLS_DTPMOD
6315 OpenRISC 1000 Relocations.
6318 BFD_RELOC_H8_DIR16A8
6320 BFD_RELOC_H8_DIR16R8
6322 BFD_RELOC_H8_DIR24A8
6324 BFD_RELOC_H8_DIR24R8
6326 BFD_RELOC_H8_DIR32A16
6328 BFD_RELOC_H8_DISP32A16
6333 BFD_RELOC_XSTORMY16_REL_12
6335 BFD_RELOC_XSTORMY16_12
6337 BFD_RELOC_XSTORMY16_24
6339 BFD_RELOC_XSTORMY16_FPTR16
6341 Sony Xstormy16 Relocations.
6346 Self-describing complex relocations.
6358 Infineon Relocations.
6361 BFD_RELOC_VAX_GLOB_DAT
6363 BFD_RELOC_VAX_JMP_SLOT
6365 BFD_RELOC_VAX_RELATIVE
6367 Relocations used by VAX ELF.
6372 Morpho MT - 16 bit immediate relocation.
6376 Morpho MT - Hi 16 bits of an address.
6380 Morpho MT - Low 16 bits of an address.
6382 BFD_RELOC_MT_GNU_VTINHERIT
6384 Morpho MT - Used to tell the linker which vtable entries are used.
6386 BFD_RELOC_MT_GNU_VTENTRY
6388 Morpho MT - Used to tell the linker which vtable entries are used.
6390 BFD_RELOC_MT_PCINSN8
6392 Morpho MT - 8 bit immediate relocation.
6395 BFD_RELOC_MSP430_10_PCREL
6397 BFD_RELOC_MSP430_16_PCREL
6401 BFD_RELOC_MSP430_16_PCREL_BYTE
6403 BFD_RELOC_MSP430_16_BYTE
6405 BFD_RELOC_MSP430_2X_PCREL
6407 BFD_RELOC_MSP430_RL_PCREL
6409 BFD_RELOC_MSP430_ABS8
6411 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6413 BFD_RELOC_MSP430X_PCR20_EXT_DST
6415 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6417 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6419 BFD_RELOC_MSP430X_ABS20_EXT_DST
6421 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6423 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6425 BFD_RELOC_MSP430X_ABS20_ADR_DST
6427 BFD_RELOC_MSP430X_PCR16
6429 BFD_RELOC_MSP430X_PCR20_CALL
6431 BFD_RELOC_MSP430X_ABS16
6433 BFD_RELOC_MSP430_ABS_HI16
6435 BFD_RELOC_MSP430_PREL31
6437 BFD_RELOC_MSP430_SYM_DIFF
6439 msp430 specific relocation codes
6446 BFD_RELOC_NIOS2_CALL26
6448 BFD_RELOC_NIOS2_IMM5
6450 BFD_RELOC_NIOS2_CACHE_OPX
6452 BFD_RELOC_NIOS2_IMM6
6454 BFD_RELOC_NIOS2_IMM8
6456 BFD_RELOC_NIOS2_HI16
6458 BFD_RELOC_NIOS2_LO16
6460 BFD_RELOC_NIOS2_HIADJ16
6462 BFD_RELOC_NIOS2_GPREL
6464 BFD_RELOC_NIOS2_UJMP
6466 BFD_RELOC_NIOS2_CJMP
6468 BFD_RELOC_NIOS2_CALLR
6470 BFD_RELOC_NIOS2_ALIGN
6472 BFD_RELOC_NIOS2_GOT16
6474 BFD_RELOC_NIOS2_CALL16
6476 BFD_RELOC_NIOS2_GOTOFF_LO
6478 BFD_RELOC_NIOS2_GOTOFF_HA
6480 BFD_RELOC_NIOS2_PCREL_LO
6482 BFD_RELOC_NIOS2_PCREL_HA
6484 BFD_RELOC_NIOS2_TLS_GD16
6486 BFD_RELOC_NIOS2_TLS_LDM16
6488 BFD_RELOC_NIOS2_TLS_LDO16
6490 BFD_RELOC_NIOS2_TLS_IE16
6492 BFD_RELOC_NIOS2_TLS_LE16
6494 BFD_RELOC_NIOS2_TLS_DTPMOD
6496 BFD_RELOC_NIOS2_TLS_DTPREL
6498 BFD_RELOC_NIOS2_TLS_TPREL
6500 BFD_RELOC_NIOS2_COPY
6502 BFD_RELOC_NIOS2_GLOB_DAT
6504 BFD_RELOC_NIOS2_JUMP_SLOT
6506 BFD_RELOC_NIOS2_RELATIVE
6508 BFD_RELOC_NIOS2_GOTOFF
6510 BFD_RELOC_NIOS2_CALL26_NOAT
6512 BFD_RELOC_NIOS2_GOT_LO
6514 BFD_RELOC_NIOS2_GOT_HA
6516 BFD_RELOC_NIOS2_CALL_LO
6518 BFD_RELOC_NIOS2_CALL_HA
6520 BFD_RELOC_NIOS2_R2_S12
6522 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6524 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6526 BFD_RELOC_NIOS2_R2_T1I7_2
6528 BFD_RELOC_NIOS2_R2_T2I4
6530 BFD_RELOC_NIOS2_R2_T2I4_1
6532 BFD_RELOC_NIOS2_R2_T2I4_2
6534 BFD_RELOC_NIOS2_R2_X1I7_2
6536 BFD_RELOC_NIOS2_R2_X2L5
6538 BFD_RELOC_NIOS2_R2_F1I5_2
6540 BFD_RELOC_NIOS2_R2_L5I4X1
6542 BFD_RELOC_NIOS2_R2_T1X1I6
6544 BFD_RELOC_NIOS2_R2_T1X1I6_2
6546 Relocations used by the Altera Nios II core.
6551 PRU LDI 16-bit unsigned data-memory relocation.
6553 BFD_RELOC_PRU_U16_PMEMIMM
6555 PRU LDI 16-bit unsigned instruction-memory relocation.
6559 PRU relocation for two consecutive LDI load instructions that load a
6560 32 bit value into a register. If the higher bits are all zero, then
6561 the second instruction may be relaxed.
6563 BFD_RELOC_PRU_S10_PCREL
6565 PRU QBBx 10-bit signed PC-relative relocation.
6567 BFD_RELOC_PRU_U8_PCREL
6569 PRU 8-bit unsigned relocation used for the LOOP instruction.
6571 BFD_RELOC_PRU_32_PMEM
6573 BFD_RELOC_PRU_16_PMEM
6575 PRU Program Memory relocations. Used to convert from byte addressing to
6576 32-bit word addressing.
6578 BFD_RELOC_PRU_GNU_DIFF8
6580 BFD_RELOC_PRU_GNU_DIFF16
6582 BFD_RELOC_PRU_GNU_DIFF32
6584 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6586 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6588 PRU relocations to mark the difference of two local symbols.
6589 These are only needed to support linker relaxation and can be ignored
6590 when not relaxing. The field is set to the value of the difference
6591 assuming no relaxation. The relocation encodes the position of the
6592 second symbol so the linker can determine whether to adjust the field
6593 value. The PMEM variants encode the word difference, instead of byte
6594 difference between symbols.
6597 BFD_RELOC_IQ2000_OFFSET_16
6599 BFD_RELOC_IQ2000_OFFSET_21
6601 BFD_RELOC_IQ2000_UHI16
6606 BFD_RELOC_XTENSA_RTLD
6608 Special Xtensa relocation used only by PLT entries in ELF shared
6609 objects to indicate that the runtime linker should set the value
6610 to one of its own internal functions or data structures.
6612 BFD_RELOC_XTENSA_GLOB_DAT
6614 BFD_RELOC_XTENSA_JMP_SLOT
6616 BFD_RELOC_XTENSA_RELATIVE
6618 Xtensa relocations for ELF shared objects.
6620 BFD_RELOC_XTENSA_PLT
6622 Xtensa relocation used in ELF object files for symbols that may require
6623 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6625 BFD_RELOC_XTENSA_DIFF8
6627 BFD_RELOC_XTENSA_DIFF16
6629 BFD_RELOC_XTENSA_DIFF32
6631 Xtensa relocations to mark the difference of two local symbols.
6632 These are only needed to support linker relaxation and can be ignored
6633 when not relaxing. The field is set to the value of the difference
6634 assuming no relaxation. The relocation encodes the position of the
6635 first symbol so the linker can determine whether to adjust the field
6638 BFD_RELOC_XTENSA_SLOT0_OP
6640 BFD_RELOC_XTENSA_SLOT1_OP
6642 BFD_RELOC_XTENSA_SLOT2_OP
6644 BFD_RELOC_XTENSA_SLOT3_OP
6646 BFD_RELOC_XTENSA_SLOT4_OP
6648 BFD_RELOC_XTENSA_SLOT5_OP
6650 BFD_RELOC_XTENSA_SLOT6_OP
6652 BFD_RELOC_XTENSA_SLOT7_OP
6654 BFD_RELOC_XTENSA_SLOT8_OP
6656 BFD_RELOC_XTENSA_SLOT9_OP
6658 BFD_RELOC_XTENSA_SLOT10_OP
6660 BFD_RELOC_XTENSA_SLOT11_OP
6662 BFD_RELOC_XTENSA_SLOT12_OP
6664 BFD_RELOC_XTENSA_SLOT13_OP
6666 BFD_RELOC_XTENSA_SLOT14_OP
6668 Generic Xtensa relocations for instruction operands. Only the slot
6669 number is encoded in the relocation. The relocation applies to the
6670 last PC-relative immediate operand, or if there are no PC-relative
6671 immediates, to the last immediate operand.
6673 BFD_RELOC_XTENSA_SLOT0_ALT
6675 BFD_RELOC_XTENSA_SLOT1_ALT
6677 BFD_RELOC_XTENSA_SLOT2_ALT
6679 BFD_RELOC_XTENSA_SLOT3_ALT
6681 BFD_RELOC_XTENSA_SLOT4_ALT
6683 BFD_RELOC_XTENSA_SLOT5_ALT
6685 BFD_RELOC_XTENSA_SLOT6_ALT
6687 BFD_RELOC_XTENSA_SLOT7_ALT
6689 BFD_RELOC_XTENSA_SLOT8_ALT
6691 BFD_RELOC_XTENSA_SLOT9_ALT
6693 BFD_RELOC_XTENSA_SLOT10_ALT
6695 BFD_RELOC_XTENSA_SLOT11_ALT
6697 BFD_RELOC_XTENSA_SLOT12_ALT
6699 BFD_RELOC_XTENSA_SLOT13_ALT
6701 BFD_RELOC_XTENSA_SLOT14_ALT
6703 Alternate Xtensa relocations. Only the slot is encoded in the
6704 relocation. The meaning of these relocations is opcode-specific.
6706 BFD_RELOC_XTENSA_OP0
6708 BFD_RELOC_XTENSA_OP1
6710 BFD_RELOC_XTENSA_OP2
6712 Xtensa relocations for backward compatibility. These have all been
6713 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6715 BFD_RELOC_XTENSA_ASM_EXPAND
6717 Xtensa relocation to mark that the assembler expanded the
6718 instructions from an original target. The expansion size is
6719 encoded in the reloc size.
6721 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6723 Xtensa relocation to mark that the linker should simplify
6724 assembler-expanded instructions. This is commonly used
6725 internally by the linker after analysis of a
6726 BFD_RELOC_XTENSA_ASM_EXPAND.
6728 BFD_RELOC_XTENSA_TLSDESC_FN
6730 BFD_RELOC_XTENSA_TLSDESC_ARG
6732 BFD_RELOC_XTENSA_TLS_DTPOFF
6734 BFD_RELOC_XTENSA_TLS_TPOFF
6736 BFD_RELOC_XTENSA_TLS_FUNC
6738 BFD_RELOC_XTENSA_TLS_ARG
6740 BFD_RELOC_XTENSA_TLS_CALL
6742 Xtensa TLS relocations.
6747 8 bit signed offset in (ix+d) or (iy+d).
6765 BFD_RELOC_LM32_BRANCH
6767 BFD_RELOC_LM32_16_GOT
6769 BFD_RELOC_LM32_GOTOFF_HI16
6771 BFD_RELOC_LM32_GOTOFF_LO16
6775 BFD_RELOC_LM32_GLOB_DAT
6777 BFD_RELOC_LM32_JMP_SLOT
6779 BFD_RELOC_LM32_RELATIVE
6781 Lattice Mico32 relocations.
6784 BFD_RELOC_MACH_O_SECTDIFF
6786 Difference between two section addreses. Must be followed by a
6787 BFD_RELOC_MACH_O_PAIR.
6789 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6791 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6793 BFD_RELOC_MACH_O_PAIR
6795 Pair of relocation. Contains the first symbol.
6797 BFD_RELOC_MACH_O_SUBTRACTOR32
6799 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6801 BFD_RELOC_MACH_O_SUBTRACTOR64
6803 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6806 BFD_RELOC_MACH_O_X86_64_BRANCH32
6808 BFD_RELOC_MACH_O_X86_64_BRANCH8
6810 PCREL relocations. They are marked as branch to create PLT entry if
6813 BFD_RELOC_MACH_O_X86_64_GOT
6815 Used when referencing a GOT entry.
6817 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6819 Used when loading a GOT entry with movq. It is specially marked so that
6820 the linker could optimize the movq to a leaq if possible.
6822 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6824 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6826 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6828 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6830 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6832 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6836 BFD_RELOC_MACH_O_ARM64_ADDEND
6838 Addend for PAGE or PAGEOFF.
6840 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6842 Relative offset to page of GOT slot.
6844 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6846 Relative offset within page of GOT slot.
6848 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6850 Address of a GOT entry.
6853 BFD_RELOC_MICROBLAZE_32_LO
6855 This is a 32 bit reloc for the microblaze that stores the
6856 low 16 bits of a value
6858 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6860 This is a 32 bit pc-relative reloc for the microblaze that
6861 stores the low 16 bits of a value
6863 BFD_RELOC_MICROBLAZE_32_ROSDA
6865 This is a 32 bit reloc for the microblaze that stores a
6866 value relative to the read-only small data area anchor
6868 BFD_RELOC_MICROBLAZE_32_RWSDA
6870 This is a 32 bit reloc for the microblaze that stores a
6871 value relative to the read-write small data area anchor
6873 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6875 This is a 32 bit reloc for the microblaze to handle
6876 expressions of the form "Symbol Op Symbol"
6878 BFD_RELOC_MICROBLAZE_64_NONE
6880 This is a 64 bit reloc that stores the 32 bit pc relative
6881 value in two words (with an imm instruction). No relocation is
6882 done here - only used for relaxing
6884 BFD_RELOC_MICROBLAZE_64_GOTPC
6886 This is a 64 bit reloc that stores the 32 bit pc relative
6887 value in two words (with an imm instruction). The relocation is
6888 PC-relative GOT offset
6890 BFD_RELOC_MICROBLAZE_64_GOT
6892 This is a 64 bit reloc that stores the 32 bit pc relative
6893 value in two words (with an imm instruction). The relocation is
6896 BFD_RELOC_MICROBLAZE_64_PLT
6898 This is a 64 bit reloc that stores the 32 bit pc relative
6899 value in two words (with an imm instruction). The relocation is
6900 PC-relative offset into PLT
6902 BFD_RELOC_MICROBLAZE_64_GOTOFF
6904 This is a 64 bit reloc that stores the 32 bit GOT relative
6905 value in two words (with an imm instruction). The relocation is
6906 relative offset from _GLOBAL_OFFSET_TABLE_
6908 BFD_RELOC_MICROBLAZE_32_GOTOFF
6910 This is a 32 bit reloc that stores the 32 bit GOT relative
6911 value in a word. The relocation is relative offset from
6912 _GLOBAL_OFFSET_TABLE_
6914 BFD_RELOC_MICROBLAZE_COPY
6916 This is used to tell the dynamic linker to copy the value out of
6917 the dynamic object into the runtime process image.
6919 BFD_RELOC_MICROBLAZE_64_TLS
6923 BFD_RELOC_MICROBLAZE_64_TLSGD
6925 This is a 64 bit reloc that stores the 32 bit GOT relative value
6926 of the GOT TLS GD info entry in two words (with an imm instruction). The
6927 relocation is GOT offset.
6929 BFD_RELOC_MICROBLAZE_64_TLSLD
6931 This is a 64 bit reloc that stores the 32 bit GOT relative value
6932 of the GOT TLS LD info entry in two words (with an imm instruction). The
6933 relocation is GOT offset.
6935 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6937 This is a 32 bit reloc that stores the Module ID to GOT(n).
6939 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6941 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6943 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6945 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6948 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6950 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6951 to two words (uses imm instruction).
6953 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6955 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6956 to two words (uses imm instruction).
6959 BFD_RELOC_AARCH64_RELOC_START
6961 AArch64 pseudo relocation code to mark the start of the AArch64
6962 relocation enumerators. N.B. the order of the enumerators is
6963 important as several tables in the AArch64 bfd backend are indexed
6964 by these enumerators; make sure they are all synced.
6966 BFD_RELOC_AARCH64_NULL
6968 Deprecated AArch64 null relocation code.
6970 BFD_RELOC_AARCH64_NONE
6972 AArch64 null relocation code.
6974 BFD_RELOC_AARCH64_64
6976 BFD_RELOC_AARCH64_32
6978 BFD_RELOC_AARCH64_16
6980 Basic absolute relocations of N bits. These are equivalent to
6981 BFD_RELOC_N and they were added to assist the indexing of the howto
6984 BFD_RELOC_AARCH64_64_PCREL
6986 BFD_RELOC_AARCH64_32_PCREL
6988 BFD_RELOC_AARCH64_16_PCREL
6990 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6991 and they were added to assist the indexing of the howto table.
6993 BFD_RELOC_AARCH64_MOVW_G0
6995 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6996 of an unsigned address/value.
6998 BFD_RELOC_AARCH64_MOVW_G0_NC
7000 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7001 an address/value. No overflow checking.
7003 BFD_RELOC_AARCH64_MOVW_G1
7005 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7006 of an unsigned address/value.
7008 BFD_RELOC_AARCH64_MOVW_G1_NC
7010 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7011 of an address/value. No overflow checking.
7013 BFD_RELOC_AARCH64_MOVW_G2
7015 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7016 of an unsigned address/value.
7018 BFD_RELOC_AARCH64_MOVW_G2_NC
7020 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7021 of an address/value. No overflow checking.
7023 BFD_RELOC_AARCH64_MOVW_G3
7025 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7026 of a signed or unsigned address/value.
7028 BFD_RELOC_AARCH64_MOVW_G0_S
7030 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7031 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7034 BFD_RELOC_AARCH64_MOVW_G1_S
7036 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7037 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7040 BFD_RELOC_AARCH64_MOVW_G2_S
7042 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7043 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7046 BFD_RELOC_AARCH64_LD_LO19_PCREL
7048 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7049 offset. The lowest two bits must be zero and are not stored in the
7050 instruction, giving a 21 bit signed byte offset.
7052 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7054 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7056 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7058 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7059 offset, giving a 4KB aligned page base address.
7061 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7063 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7064 offset, giving a 4KB aligned page base address, but with no overflow
7067 BFD_RELOC_AARCH64_ADD_LO12
7069 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7070 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7072 BFD_RELOC_AARCH64_LDST8_LO12
7074 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7075 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7077 BFD_RELOC_AARCH64_TSTBR14
7079 AArch64 14 bit pc-relative test bit and branch.
7080 The lowest two bits must be zero and are not stored in the instruction,
7081 giving a 16 bit signed byte offset.
7083 BFD_RELOC_AARCH64_BRANCH19
7085 AArch64 19 bit pc-relative conditional branch and compare & branch.
7086 The lowest two bits must be zero and are not stored in the instruction,
7087 giving a 21 bit signed byte offset.
7089 BFD_RELOC_AARCH64_JUMP26
7091 AArch64 26 bit pc-relative unconditional branch.
7092 The lowest two bits must be zero and are not stored in the instruction,
7093 giving a 28 bit signed byte offset.
7095 BFD_RELOC_AARCH64_CALL26
7097 AArch64 26 bit pc-relative unconditional branch and link.
7098 The lowest two bits must be zero and are not stored in the instruction,
7099 giving a 28 bit signed byte offset.
7101 BFD_RELOC_AARCH64_LDST16_LO12
7103 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7104 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7106 BFD_RELOC_AARCH64_LDST32_LO12
7108 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7109 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7111 BFD_RELOC_AARCH64_LDST64_LO12
7113 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7114 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7116 BFD_RELOC_AARCH64_LDST128_LO12
7118 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7119 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7121 BFD_RELOC_AARCH64_GOT_LD_PREL19
7123 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7124 offset of the global offset table entry for a symbol. The lowest two
7125 bits must be zero and are not stored in the instruction, giving a 21
7126 bit signed byte offset. This relocation type requires signed overflow
7129 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7131 Get to the page base of the global offset table entry for a symbol as
7132 part of an ADRP instruction using a 21 bit PC relative value.Used in
7133 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7135 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7137 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7138 the GOT entry for this symbol. Used in conjunction with
7139 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7141 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7143 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7144 the GOT entry for this symbol. Used in conjunction with
7145 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7147 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7149 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7150 for this symbol. Valid in LP64 ABI only.
7152 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7154 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7155 for this symbol. Valid in LP64 ABI only.
7157 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7159 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7160 the GOT entry for this symbol. Valid in LP64 ABI only.
7162 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7164 Scaled 14 bit byte offset to the page base of the global offset table.
7166 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7168 Scaled 15 bit byte offset to the page base of the global offset table.
7170 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7172 Get to the page base of the global offset table entry for a symbols
7173 tls_index structure as part of an adrp instruction using a 21 bit PC
7174 relative value. Used in conjunction with
7175 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7177 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7179 AArch64 TLS General Dynamic
7181 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7183 Unsigned 12 bit byte offset to global offset table entry for a symbols
7184 tls_index structure. Used in conjunction with
7185 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7187 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7189 AArch64 TLS General Dynamic relocation.
7191 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7193 AArch64 TLS General Dynamic relocation.
7195 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7197 AArch64 TLS INITIAL EXEC relocation.
7199 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7201 AArch64 TLS INITIAL EXEC relocation.
7203 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7205 AArch64 TLS INITIAL EXEC relocation.
7207 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7209 AArch64 TLS INITIAL EXEC relocation.
7211 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7213 AArch64 TLS INITIAL EXEC relocation.
7215 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7217 AArch64 TLS INITIAL EXEC relocation.
7219 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7221 bit[23:12] of byte offset to module TLS base address.
7223 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7225 Unsigned 12 bit byte offset to module TLS base address.
7227 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7229 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7231 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7233 Unsigned 12 bit byte offset to global offset table entry for a symbols
7234 tls_index structure. Used in conjunction with
7235 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7237 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7239 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7242 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7244 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7246 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7248 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7251 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7253 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7255 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7257 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7260 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7262 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7264 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7266 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7269 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7271 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7273 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7275 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7278 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7280 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7282 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7284 bit[15:0] of byte offset to module TLS base address.
7286 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7288 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7290 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7292 bit[31:16] of byte offset to module TLS base address.
7294 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7296 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7298 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7300 bit[47:32] of byte offset to module TLS base address.
7302 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7304 AArch64 TLS LOCAL EXEC relocation.
7306 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7308 AArch64 TLS LOCAL EXEC relocation.
7310 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7312 AArch64 TLS LOCAL EXEC relocation.
7314 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7316 AArch64 TLS LOCAL EXEC relocation.
7318 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7320 AArch64 TLS LOCAL EXEC relocation.
7322 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7324 AArch64 TLS LOCAL EXEC relocation.
7326 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7328 AArch64 TLS LOCAL EXEC relocation.
7330 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7332 AArch64 TLS LOCAL EXEC relocation.
7334 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7336 AArch64 TLS DESC relocation.
7338 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7340 AArch64 TLS DESC relocation.
7342 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7344 AArch64 TLS DESC relocation.
7346 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7348 AArch64 TLS DESC relocation.
7350 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7352 AArch64 TLS DESC relocation.
7354 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7356 AArch64 TLS DESC relocation.
7358 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7360 AArch64 TLS DESC relocation.
7362 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7364 AArch64 TLS DESC relocation.
7366 BFD_RELOC_AARCH64_TLSDESC_LDR
7368 AArch64 TLS DESC relocation.
7370 BFD_RELOC_AARCH64_TLSDESC_ADD
7372 AArch64 TLS DESC relocation.
7374 BFD_RELOC_AARCH64_TLSDESC_CALL
7376 AArch64 TLS DESC relocation.
7378 BFD_RELOC_AARCH64_COPY
7380 AArch64 TLS relocation.
7382 BFD_RELOC_AARCH64_GLOB_DAT
7384 AArch64 TLS relocation.
7386 BFD_RELOC_AARCH64_JUMP_SLOT
7388 AArch64 TLS relocation.
7390 BFD_RELOC_AARCH64_RELATIVE
7392 AArch64 TLS relocation.
7394 BFD_RELOC_AARCH64_TLS_DTPMOD
7396 AArch64 TLS relocation.
7398 BFD_RELOC_AARCH64_TLS_DTPREL
7400 AArch64 TLS relocation.
7402 BFD_RELOC_AARCH64_TLS_TPREL
7404 AArch64 TLS relocation.
7406 BFD_RELOC_AARCH64_TLSDESC
7408 AArch64 TLS relocation.
7410 BFD_RELOC_AARCH64_IRELATIVE
7412 AArch64 support for STT_GNU_IFUNC.
7414 BFD_RELOC_AARCH64_RELOC_END
7416 AArch64 pseudo relocation code to mark the end of the AArch64
7417 relocation enumerators that have direct mapping to ELF reloc codes.
7418 There are a few more enumerators after this one; those are mainly
7419 used by the AArch64 assembler for the internal fixup or to select
7420 one of the above enumerators.
7422 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7424 AArch64 pseudo relocation code to be used internally by the AArch64
7425 assembler and not (currently) written to any object files.
7427 BFD_RELOC_AARCH64_LDST_LO12
7429 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7430 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7432 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7434 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7435 used internally by the AArch64 assembler and not (currently) written to
7438 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7440 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7442 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7444 AArch64 pseudo relocation code to be used internally by the AArch64
7445 assembler and not (currently) written to any object files.
7447 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7449 AArch64 pseudo relocation code to be used internally by the AArch64
7450 assembler and not (currently) written to any object files.
7452 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7454 AArch64 pseudo relocation code to be used internally by the AArch64
7455 assembler and not (currently) written to any object files.
7457 BFD_RELOC_TILEPRO_COPY
7459 BFD_RELOC_TILEPRO_GLOB_DAT
7461 BFD_RELOC_TILEPRO_JMP_SLOT
7463 BFD_RELOC_TILEPRO_RELATIVE
7465 BFD_RELOC_TILEPRO_BROFF_X1
7467 BFD_RELOC_TILEPRO_JOFFLONG_X1
7469 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7471 BFD_RELOC_TILEPRO_IMM8_X0
7473 BFD_RELOC_TILEPRO_IMM8_Y0
7475 BFD_RELOC_TILEPRO_IMM8_X1
7477 BFD_RELOC_TILEPRO_IMM8_Y1
7479 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7481 BFD_RELOC_TILEPRO_MT_IMM15_X1
7483 BFD_RELOC_TILEPRO_MF_IMM15_X1
7485 BFD_RELOC_TILEPRO_IMM16_X0
7487 BFD_RELOC_TILEPRO_IMM16_X1
7489 BFD_RELOC_TILEPRO_IMM16_X0_LO
7491 BFD_RELOC_TILEPRO_IMM16_X1_LO
7493 BFD_RELOC_TILEPRO_IMM16_X0_HI
7495 BFD_RELOC_TILEPRO_IMM16_X1_HI
7497 BFD_RELOC_TILEPRO_IMM16_X0_HA
7499 BFD_RELOC_TILEPRO_IMM16_X1_HA
7501 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7503 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7505 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7507 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7509 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7511 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7513 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7515 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7517 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7519 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7521 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7523 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7525 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7527 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7529 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7531 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7533 BFD_RELOC_TILEPRO_MMSTART_X0
7535 BFD_RELOC_TILEPRO_MMEND_X0
7537 BFD_RELOC_TILEPRO_MMSTART_X1
7539 BFD_RELOC_TILEPRO_MMEND_X1
7541 BFD_RELOC_TILEPRO_SHAMT_X0
7543 BFD_RELOC_TILEPRO_SHAMT_X1
7545 BFD_RELOC_TILEPRO_SHAMT_Y0
7547 BFD_RELOC_TILEPRO_SHAMT_Y1
7549 BFD_RELOC_TILEPRO_TLS_GD_CALL
7551 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7553 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7555 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7557 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7559 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7561 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7563 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7565 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7567 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7569 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7571 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7573 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7575 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7577 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7579 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7581 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7583 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7585 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7587 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7589 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7591 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7593 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7595 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7597 BFD_RELOC_TILEPRO_TLS_TPOFF32
7599 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7601 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7603 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7605 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7607 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7609 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7611 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7613 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7615 Tilera TILEPro Relocations.
7617 BFD_RELOC_TILEGX_HW0
7619 BFD_RELOC_TILEGX_HW1
7621 BFD_RELOC_TILEGX_HW2
7623 BFD_RELOC_TILEGX_HW3
7625 BFD_RELOC_TILEGX_HW0_LAST
7627 BFD_RELOC_TILEGX_HW1_LAST
7629 BFD_RELOC_TILEGX_HW2_LAST
7631 BFD_RELOC_TILEGX_COPY
7633 BFD_RELOC_TILEGX_GLOB_DAT
7635 BFD_RELOC_TILEGX_JMP_SLOT
7637 BFD_RELOC_TILEGX_RELATIVE
7639 BFD_RELOC_TILEGX_BROFF_X1
7641 BFD_RELOC_TILEGX_JUMPOFF_X1
7643 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7645 BFD_RELOC_TILEGX_IMM8_X0
7647 BFD_RELOC_TILEGX_IMM8_Y0
7649 BFD_RELOC_TILEGX_IMM8_X1
7651 BFD_RELOC_TILEGX_IMM8_Y1
7653 BFD_RELOC_TILEGX_DEST_IMM8_X1
7655 BFD_RELOC_TILEGX_MT_IMM14_X1
7657 BFD_RELOC_TILEGX_MF_IMM14_X1
7659 BFD_RELOC_TILEGX_MMSTART_X0
7661 BFD_RELOC_TILEGX_MMEND_X0
7663 BFD_RELOC_TILEGX_SHAMT_X0
7665 BFD_RELOC_TILEGX_SHAMT_X1
7667 BFD_RELOC_TILEGX_SHAMT_Y0
7669 BFD_RELOC_TILEGX_SHAMT_Y1
7671 BFD_RELOC_TILEGX_IMM16_X0_HW0
7673 BFD_RELOC_TILEGX_IMM16_X1_HW0
7675 BFD_RELOC_TILEGX_IMM16_X0_HW1
7677 BFD_RELOC_TILEGX_IMM16_X1_HW1
7679 BFD_RELOC_TILEGX_IMM16_X0_HW2
7681 BFD_RELOC_TILEGX_IMM16_X1_HW2
7683 BFD_RELOC_TILEGX_IMM16_X0_HW3
7685 BFD_RELOC_TILEGX_IMM16_X1_HW3
7687 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7689 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7691 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7693 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7695 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7697 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7699 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7701 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7703 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7705 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7707 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7709 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7711 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7713 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7715 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7717 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7719 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7721 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7723 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7725 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7727 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7729 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7731 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7733 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7735 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7737 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7739 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7741 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7743 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7745 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7747 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7749 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7751 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7753 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7755 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7757 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7759 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7761 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7763 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7765 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7767 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7769 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7771 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7773 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7775 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7777 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7779 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7781 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7783 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7785 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7787 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7789 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7791 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7793 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7795 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7797 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7799 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7801 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7803 BFD_RELOC_TILEGX_TLS_DTPMOD64
7805 BFD_RELOC_TILEGX_TLS_DTPOFF64
7807 BFD_RELOC_TILEGX_TLS_TPOFF64
7809 BFD_RELOC_TILEGX_TLS_DTPMOD32
7811 BFD_RELOC_TILEGX_TLS_DTPOFF32
7813 BFD_RELOC_TILEGX_TLS_TPOFF32
7815 BFD_RELOC_TILEGX_TLS_GD_CALL
7817 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7819 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7821 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7823 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7825 BFD_RELOC_TILEGX_TLS_IE_LOAD
7827 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7829 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7831 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7833 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7835 Tilera TILE-Gx Relocations.
7838 BFD_RELOC_EPIPHANY_SIMM8
7840 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7842 BFD_RELOC_EPIPHANY_SIMM24
7844 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7846 BFD_RELOC_EPIPHANY_HIGH
7848 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7850 BFD_RELOC_EPIPHANY_LOW
7852 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7854 BFD_RELOC_EPIPHANY_SIMM11
7856 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7858 BFD_RELOC_EPIPHANY_IMM11
7860 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7862 BFD_RELOC_EPIPHANY_IMM8
7864 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7867 BFD_RELOC_VISIUM_HI16
7869 BFD_RELOC_VISIUM_LO16
7871 BFD_RELOC_VISIUM_IM16
7873 BFD_RELOC_VISIUM_REL16
7875 BFD_RELOC_VISIUM_HI16_PCREL
7877 BFD_RELOC_VISIUM_LO16_PCREL
7879 BFD_RELOC_VISIUM_IM16_PCREL
7884 BFD_RELOC_WASM32_LEB128
7886 BFD_RELOC_WASM32_LEB128_GOT
7888 BFD_RELOC_WASM32_LEB128_GOT_CODE
7890 BFD_RELOC_WASM32_LEB128_PLT
7892 BFD_RELOC_WASM32_PLT_INDEX
7894 BFD_RELOC_WASM32_ABS32_CODE
7896 BFD_RELOC_WASM32_COPY
7898 BFD_RELOC_WASM32_CODE_POINTER
7900 BFD_RELOC_WASM32_INDEX
7902 BFD_RELOC_WASM32_PLT_SIG
7904 WebAssembly relocations.
7910 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7915 bfd_reloc_type_lookup
7916 bfd_reloc_name_lookup
7919 reloc_howto_type *bfd_reloc_type_lookup
7920 (bfd *abfd, bfd_reloc_code_real_type code);
7921 reloc_howto_type *bfd_reloc_name_lookup
7922 (bfd *abfd, const char *reloc_name);
7925 Return a pointer to a howto structure which, when
7926 invoked, will perform the relocation @var{code} on data from the
7932 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7934 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
7938 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
7940 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
7943 static reloc_howto_type bfd_howto_32 =
7944 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
7948 bfd_default_reloc_type_lookup
7951 reloc_howto_type *bfd_default_reloc_type_lookup
7952 (bfd *abfd, bfd_reloc_code_real_type code);
7955 Provides a default relocation lookup routine for any architecture.
7960 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7964 case BFD_RELOC_CTOR:
7965 /* The type of reloc used in a ctor, which will be as wide as the
7966 address - so either a 64, 32, or 16 bitter. */
7967 switch (bfd_arch_bits_per_address (abfd))
7973 return &bfd_howto_32;
7989 bfd_get_reloc_code_name
7992 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7995 Provides a printable name for the supplied relocation code.
7996 Useful mainly for printing error messages.
8000 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
8002 if (code > BFD_RELOC_UNUSED)
8004 return bfd_reloc_code_real_names[code];
8009 bfd_generic_relax_section
8012 bfd_boolean bfd_generic_relax_section
8015 struct bfd_link_info *,
8019 Provides default handling for relaxing for back ends which
8024 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
8025 asection *section ATTRIBUTE_UNUSED,
8026 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
8029 if (bfd_link_relocatable (link_info))
8030 (*link_info->callbacks->einfo)
8031 (_("%P%F: --relax and -r may not be used together\n"));
8039 bfd_generic_gc_sections
8042 bfd_boolean bfd_generic_gc_sections
8043 (bfd *, struct bfd_link_info *);
8046 Provides default handling for relaxing for back ends which
8047 don't do section gc -- i.e., does nothing.
8051 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
8052 struct bfd_link_info *info ATTRIBUTE_UNUSED)
8059 bfd_generic_lookup_section_flags
8062 bfd_boolean bfd_generic_lookup_section_flags
8063 (struct bfd_link_info *, struct flag_info *, asection *);
8066 Provides default handling for section flags lookup
8067 -- i.e., does nothing.
8068 Returns FALSE if the section should be omitted, otherwise TRUE.
8072 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
8073 struct flag_info *flaginfo,
8074 asection *section ATTRIBUTE_UNUSED)
8076 if (flaginfo != NULL)
8078 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported.\n"));
8086 bfd_generic_merge_sections
8089 bfd_boolean bfd_generic_merge_sections
8090 (bfd *, struct bfd_link_info *);
8093 Provides default handling for SEC_MERGE section merging for back ends
8094 which don't have SEC_MERGE support -- i.e., does nothing.
8098 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
8099 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
8106 bfd_generic_get_relocated_section_contents
8109 bfd_byte *bfd_generic_get_relocated_section_contents
8111 struct bfd_link_info *link_info,
8112 struct bfd_link_order *link_order,
8114 bfd_boolean relocatable,
8118 Provides default handling of relocation effort for back ends
8119 which can't be bothered to do it efficiently.
8124 bfd_generic_get_relocated_section_contents (bfd *abfd,
8125 struct bfd_link_info *link_info,
8126 struct bfd_link_order *link_order,
8128 bfd_boolean relocatable,
8131 bfd *input_bfd = link_order->u.indirect.section->owner;
8132 asection *input_section = link_order->u.indirect.section;
8134 arelent **reloc_vector;
8137 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
8141 /* Read in the section. */
8142 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
8148 if (reloc_size == 0)
8151 reloc_vector = (arelent **) bfd_malloc (reloc_size);
8152 if (reloc_vector == NULL)
8155 reloc_count = bfd_canonicalize_reloc (input_bfd,
8159 if (reloc_count < 0)
8162 if (reloc_count > 0)
8166 for (parent = reloc_vector; *parent != NULL; parent++)
8168 char *error_message = NULL;
8170 bfd_reloc_status_type r;
8172 symbol = *(*parent)->sym_ptr_ptr;
8173 /* PR ld/19628: A specially crafted input file
8174 can result in a NULL symbol pointer here. */
8177 link_info->callbacks->einfo
8178 /* xgettext:c-format */
8179 (_("%X%P: %B(%A): error: relocation for offset %V has no value\n"),
8180 abfd, input_section, (* parent)->address);
8184 if (symbol->section && discarded_section (symbol->section))
8187 static reloc_howto_type none_howto
8188 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
8189 "unused", FALSE, 0, 0, FALSE);
8191 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
8192 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
8194 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
8195 (*parent)->addend = 0;
8196 (*parent)->howto = &none_howto;
8200 r = bfd_perform_relocation (input_bfd,
8204 relocatable ? abfd : NULL,
8209 asection *os = input_section->output_section;
8211 /* A partial link, so keep the relocs. */
8212 os->orelocation[os->reloc_count] = *parent;
8216 if (r != bfd_reloc_ok)
8220 case bfd_reloc_undefined:
8221 (*link_info->callbacks->undefined_symbol)
8222 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8223 input_bfd, input_section, (*parent)->address, TRUE);
8225 case bfd_reloc_dangerous:
8226 BFD_ASSERT (error_message != NULL);
8227 (*link_info->callbacks->reloc_dangerous)
8228 (link_info, error_message,
8229 input_bfd, input_section, (*parent)->address);
8231 case bfd_reloc_overflow:
8232 (*link_info->callbacks->reloc_overflow)
8234 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8235 (*parent)->howto->name, (*parent)->addend,
8236 input_bfd, input_section, (*parent)->address);
8238 case bfd_reloc_outofrange:
8240 This error can result when processing some partially
8241 complete binaries. Do not abort, but issue an error
8243 link_info->callbacks->einfo
8244 /* xgettext:c-format */
8245 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
8246 abfd, input_section, * parent);
8249 case bfd_reloc_notsupported:
8251 This error can result when processing a corrupt binary.
8252 Do not abort. Issue an error message instead. */
8253 link_info->callbacks->einfo
8254 /* xgettext:c-format */
8255 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
8256 abfd, input_section, * parent);
8260 /* PR 17512; file: 90c2a92e.
8261 Report unexpected results, without aborting. */
8262 link_info->callbacks->einfo
8263 /* xgettext:c-format */
8264 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
8265 abfd, input_section, * parent, r);
8273 free (reloc_vector);
8277 free (reloc_vector);
8283 _bfd_generic_set_reloc
8286 void _bfd_generic_set_reloc
8290 unsigned int count);
8293 Installs a new set of internal relocations in SECTION.
8297 _bfd_generic_set_reloc (bfd *abfd ATTRIBUTE_UNUSED,
8302 section->orelocation = relptr;
8303 section->reloc_count = count;
8308 _bfd_unrecognized_reloc
8311 bfd_boolean _bfd_unrecognized_reloc
8314 unsigned int r_type);
8317 Reports an unrecognized reloc.
8318 Written as a function in order to reduce code duplication.
8319 Returns FALSE so that it can be called from a return statement.
8323 _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type)
8325 /* xgettext:c-format */
8326 _bfd_error_handler (_("%B: unrecognized relocation (%#x) in section `%A'"),
8327 abfd, r_type, section);
8329 /* PR 21803: Suggest the most likely cause of this error. */
8330 _bfd_error_handler (_("Is this version of the linker - %s - out of date ?"),
8331 BFD_VERSION_STRING);
8333 bfd_set_error (bfd_error_bad_value);