1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2018 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
98 .typedef struct reloc_cache_entry
100 . {* A pointer into the canonical table of pointers. *}
101 . struct bfd_symbol **sym_ptr_ptr;
103 . {* offset in section. *}
104 . bfd_size_type address;
106 . {* addend for relocation value. *}
109 . {* Pointer to how to perform the required relocation. *}
110 . reloc_howto_type *howto;
120 Here is a description of each of the fields within an <<arelent>>:
124 The symbol table pointer points to a pointer to the symbol
125 associated with the relocation request. It is the pointer
126 into the table returned by the back end's
127 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
128 referenced through a pointer to a pointer so that tools like
129 the linker can fix up all the symbols of the same name by
130 modifying only one pointer. The relocation routine looks in
131 the symbol and uses the base of the section the symbol is
132 attached to and the value of the symbol as the initial
133 relocation offset. If the symbol pointer is zero, then the
134 section provided is looked up.
138 The <<address>> field gives the offset in bytes from the base of
139 the section data which owns the relocation record to the first
140 byte of relocatable information. The actual data relocated
141 will be relative to this point; for example, a relocation
142 type which modifies the bottom two bytes of a four byte word
143 would not touch the first byte pointed to in a big endian
148 The <<addend>> is a value provided by the back end to be added (!)
149 to the relocation offset. Its interpretation is dependent upon
150 the howto. For example, on the 68k the code:
155 | return foo[0x12345678];
158 Could be compiled into:
161 | moveb @@#12345678,d0
166 This could create a reloc pointing to <<foo>>, but leave the
167 offset in the data, something like:
169 |RELOCATION RECORDS FOR [.text]:
173 |00000000 4e56 fffc ; linkw fp,#-4
174 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
175 |0000000a 49c0 ; extbl d0
176 |0000000c 4e5e ; unlk fp
179 Using coff and an 88k, some instructions don't have enough
180 space in them to represent the full address range, and
181 pointers have to be loaded in two parts. So you'd get something like:
183 | or.u r13,r0,hi16(_foo+0x12345678)
184 | ld.b r2,r13,lo16(_foo+0x12345678)
187 This should create two relocs, both pointing to <<_foo>>, and with
188 0x12340000 in their addend field. The data would consist of:
190 |RELOCATION RECORDS FOR [.text]:
192 |00000002 HVRT16 _foo+0x12340000
193 |00000006 LVRT16 _foo+0x12340000
195 |00000000 5da05678 ; or.u r13,r0,0x5678
196 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
197 |00000008 f400c001 ; jmp r1
199 The relocation routine digs out the value from the data, adds
200 it to the addend to get the original offset, and then adds the
201 value of <<_foo>>. Note that all 32 bits have to be kept around
202 somewhere, to cope with carry from bit 15 to bit 16.
204 One further example is the sparc and the a.out format. The
205 sparc has a similar problem to the 88k, in that some
206 instructions don't have room for an entire offset, but on the
207 sparc the parts are created in odd sized lumps. The designers of
208 the a.out format chose to not use the data within the section
209 for storing part of the offset; all the offset is kept within
210 the reloc. Anything in the data should be ignored.
213 | sethi %hi(_foo+0x12345678),%g2
214 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
218 Both relocs contain a pointer to <<foo>>, and the offsets
221 |RELOCATION RECORDS FOR [.text]:
223 |00000004 HI22 _foo+0x12345678
224 |00000008 LO10 _foo+0x12345678
226 |00000000 9de3bf90 ; save %sp,-112,%sp
227 |00000004 05000000 ; sethi %hi(_foo+0),%g2
228 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
229 |0000000c 81c7e008 ; ret
230 |00000010 81e80000 ; restore
234 The <<howto>> field can be imagined as a
235 relocation instruction. It is a pointer to a structure which
236 contains information on what to do with all of the other
237 information in the reloc record and data section. A back end
238 would normally have a relocation instruction set and turn
239 relocations into pointers to the correct structure on input -
240 but it would be possible to create each howto field on demand.
246 <<enum complain_overflow>>
248 Indicates what sort of overflow checking should be done when
249 performing a relocation.
253 .enum complain_overflow
255 . {* Do not complain on overflow. *}
256 . complain_overflow_dont,
258 . {* Complain if the value overflows when considered as a signed
259 . number one bit larger than the field. ie. A bitfield of N bits
260 . is allowed to represent -2**n to 2**n-1. *}
261 . complain_overflow_bitfield,
263 . {* Complain if the value overflows when considered as a signed
265 . complain_overflow_signed,
267 . {* Complain if the value overflows when considered as an
268 . unsigned number. *}
269 . complain_overflow_unsigned
278 The <<reloc_howto_type>> is a structure which contains all the
279 information that libbfd needs to know to tie up a back end's data.
282 .struct bfd_symbol; {* Forward declaration. *}
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's
288 . external idea of what a reloc number is stored
289 . in this field. For example, a PC relative word relocation
290 . in a coff environment has the type 023 - because that's
291 . what the outside world calls a R_PCRWORD reloc. *}
294 . {* The value the final relocation is shifted right by. This drops
295 . unwanted data from the relocation. *}
296 . unsigned int rightshift;
298 . {* The size of the item to be relocated. This is *not* a
299 . power-of-two measure. To get the number of bytes operated
300 . on by a type of relocation, use bfd_get_reloc_size. *}
303 . {* The number of bits in the item to be relocated. This is used
304 . when doing overflow checking. *}
305 . unsigned int bitsize;
307 . {* The relocation is relative to the field being relocated. *}
308 . bfd_boolean pc_relative;
310 . {* The bit position of the reloc value in the destination.
311 . The relocated value is left shifted by this amount. *}
312 . unsigned int bitpos;
314 . {* What type of overflow error should be checked for when
316 . enum complain_overflow complain_on_overflow;
318 . {* If this field is non null, then the supplied function is
319 . called rather than the normal function. This allows really
320 . strange relocation methods to be accommodated. *}
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., ELF); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type *howto)
453 How relocs are tied together in an <<asection>>:
455 .typedef struct relent_chain
458 . struct relent_chain *next;
464 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
465 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
472 bfd_reloc_status_type bfd_check_overflow
473 (enum complain_overflow how,
474 unsigned int bitsize,
475 unsigned int rightshift,
476 unsigned int addrsize,
480 Perform overflow checking on @var{relocation} which has
481 @var{bitsize} significant bits and will be shifted right by
482 @var{rightshift} bits, on a machine with addresses containing
483 @var{addrsize} significant bits. The result is either of
484 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
488 bfd_reloc_status_type
489 bfd_check_overflow (enum complain_overflow how,
490 unsigned int bitsize,
491 unsigned int rightshift,
492 unsigned int addrsize,
495 bfd_vma fieldmask, addrmask, signmask, ss, a;
496 bfd_reloc_status_type flag = bfd_reloc_ok;
498 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
499 we'll be permissive: extra bits in the field mask will
500 automatically extend the address mask for purposes of the
502 fieldmask = N_ONES (bitsize);
503 signmask = ~fieldmask;
504 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
505 a = (relocation & addrmask) >> rightshift;
509 case complain_overflow_dont:
512 case complain_overflow_signed:
513 /* If any sign bits are set, all sign bits must be set. That
514 is, A must be a valid negative address after shifting. */
515 signmask = ~ (fieldmask >> 1);
518 case complain_overflow_bitfield:
519 /* Bitfields are sometimes signed, sometimes unsigned. We
520 explicitly allow an address wrap too, which means a bitfield
521 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
522 if the value has some, but not all, bits set outside the
525 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
526 flag = bfd_reloc_overflow;
529 case complain_overflow_unsigned:
530 /* We have an overflow if the address does not fit in the field. */
531 if ((a & signmask) != 0)
532 flag = bfd_reloc_overflow;
544 bfd_reloc_offset_in_range
547 bfd_boolean bfd_reloc_offset_in_range
548 (reloc_howto_type *howto,
551 bfd_size_type offset);
554 Returns TRUE if the reloc described by @var{HOWTO} can be
555 applied at @var{OFFSET} octets in @var{SECTION}.
559 /* HOWTO describes a relocation, at offset OCTET. Return whether the
560 relocation field is within SECTION of ABFD. */
563 bfd_reloc_offset_in_range (reloc_howto_type *howto,
568 bfd_size_type octet_end = bfd_get_section_limit_octets (abfd, section);
569 bfd_size_type reloc_size = bfd_get_reloc_size (howto);
571 /* The reloc field must be contained entirely within the section.
572 Allow zero length fields (marker relocs or NONE relocs where no
573 relocation will be performed) at the end of the section. */
574 return octet <= octet_end && octet + reloc_size <= octet_end;
579 bfd_perform_relocation
582 bfd_reloc_status_type bfd_perform_relocation
584 arelent *reloc_entry,
586 asection *input_section,
588 char **error_message);
591 If @var{output_bfd} is supplied to this function, the
592 generated image will be relocatable; the relocations are
593 copied to the output file after they have been changed to
594 reflect the new state of the world. There are two ways of
595 reflecting the results of partial linkage in an output file:
596 by modifying the output data in place, and by modifying the
597 relocation record. Some native formats (e.g., basic a.out and
598 basic coff) have no way of specifying an addend in the
599 relocation type, so the addend has to go in the output data.
600 This is no big deal since in these formats the output data
601 slot will always be big enough for the addend. Complex reloc
602 types with addends were invented to solve just this problem.
603 The @var{error_message} argument is set to an error message if
604 this return @code{bfd_reloc_dangerous}.
608 bfd_reloc_status_type
609 bfd_perform_relocation (bfd *abfd,
610 arelent *reloc_entry,
612 asection *input_section,
614 char **error_message)
617 bfd_reloc_status_type flag = bfd_reloc_ok;
618 bfd_size_type octets;
619 bfd_vma output_base = 0;
620 reloc_howto_type *howto = reloc_entry->howto;
621 asection *reloc_target_output_section;
624 symbol = *(reloc_entry->sym_ptr_ptr);
626 /* If we are not producing relocatable output, return an error if
627 the symbol is not defined. An undefined weak symbol is
628 considered to have a value of zero (SVR4 ABI, p. 4-27). */
629 if (bfd_is_und_section (symbol->section)
630 && (symbol->flags & BSF_WEAK) == 0
631 && output_bfd == NULL)
632 flag = bfd_reloc_undefined;
634 /* If there is a function supplied to handle this relocation type,
635 call it. It'll return `bfd_reloc_continue' if further processing
637 if (howto && howto->special_function)
639 bfd_reloc_status_type cont;
641 /* Note - we do not call bfd_reloc_offset_in_range here as the
642 reloc_entry->address field might actually be valid for the
643 backend concerned. It is up to the special_function itself
644 to call bfd_reloc_offset_in_range if needed. */
645 cont = howto->special_function (abfd, reloc_entry, symbol, data,
646 input_section, output_bfd,
648 if (cont != bfd_reloc_continue)
652 if (bfd_is_abs_section (symbol->section)
653 && output_bfd != NULL)
655 reloc_entry->address += input_section->output_offset;
659 /* PR 17512: file: 0f67f69d. */
661 return bfd_reloc_undefined;
663 /* Is the address of the relocation really within the section? */
664 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
665 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
666 return bfd_reloc_outofrange;
668 /* Work out which section the relocation is targeted at and the
669 initial relocation command value. */
671 /* Get symbol value. (Common symbols are special.) */
672 if (bfd_is_com_section (symbol->section))
675 relocation = symbol->value;
677 reloc_target_output_section = symbol->section->output_section;
679 /* Convert input-section-relative symbol value to absolute. */
680 if ((output_bfd && ! howto->partial_inplace)
681 || reloc_target_output_section == NULL)
684 output_base = reloc_target_output_section->vma;
686 relocation += output_base + symbol->section->output_offset;
688 /* Add in supplied addend. */
689 relocation += reloc_entry->addend;
691 /* Here the variable relocation holds the final address of the
692 symbol we are relocating against, plus any addend. */
694 if (howto->pc_relative)
696 /* This is a PC relative relocation. We want to set RELOCATION
697 to the distance between the address of the symbol and the
698 location. RELOCATION is already the address of the symbol.
700 We start by subtracting the address of the section containing
703 If pcrel_offset is set, we must further subtract the position
704 of the location within the section. Some targets arrange for
705 the addend to be the negative of the position of the location
706 within the section; for example, i386-aout does this. For
707 i386-aout, pcrel_offset is FALSE. Some other targets do not
708 include the position of the location; for example, ELF.
709 For those targets, pcrel_offset is TRUE.
711 If we are producing relocatable output, then we must ensure
712 that this reloc will be correctly computed when the final
713 relocation is done. If pcrel_offset is FALSE we want to wind
714 up with the negative of the location within the section,
715 which means we must adjust the existing addend by the change
716 in the location within the section. If pcrel_offset is TRUE
717 we do not want to adjust the existing addend at all.
719 FIXME: This seems logical to me, but for the case of
720 producing relocatable output it is not what the code
721 actually does. I don't want to change it, because it seems
722 far too likely that something will break. */
725 input_section->output_section->vma + input_section->output_offset;
727 if (howto->pcrel_offset)
728 relocation -= reloc_entry->address;
731 if (output_bfd != NULL)
733 if (! howto->partial_inplace)
735 /* This is a partial relocation, and we want to apply the relocation
736 to the reloc entry rather than the raw data. Modify the reloc
737 inplace to reflect what we now know. */
738 reloc_entry->addend = relocation;
739 reloc_entry->address += input_section->output_offset;
744 /* This is a partial relocation, but inplace, so modify the
747 If we've relocated with a symbol with a section, change
748 into a ref to the section belonging to the symbol. */
750 reloc_entry->address += input_section->output_offset;
753 if (abfd->xvec->flavour == bfd_target_coff_flavour
754 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
755 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
757 /* For m68k-coff, the addend was being subtracted twice during
758 relocation with -r. Removing the line below this comment
759 fixes that problem; see PR 2953.
761 However, Ian wrote the following, regarding removing the line below,
762 which explains why it is still enabled: --djm
764 If you put a patch like that into BFD you need to check all the COFF
765 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
766 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
767 problem in a different way. There may very well be a reason that the
768 code works as it does.
770 Hmmm. The first obvious point is that bfd_perform_relocation should
771 not have any tests that depend upon the flavour. It's seem like
772 entirely the wrong place for such a thing. The second obvious point
773 is that the current code ignores the reloc addend when producing
774 relocatable output for COFF. That's peculiar. In fact, I really
775 have no idea what the point of the line you want to remove is.
777 A typical COFF reloc subtracts the old value of the symbol and adds in
778 the new value to the location in the object file (if it's a pc
779 relative reloc it adds the difference between the symbol value and the
780 location). When relocating we need to preserve that property.
782 BFD handles this by setting the addend to the negative of the old
783 value of the symbol. Unfortunately it handles common symbols in a
784 non-standard way (it doesn't subtract the old value) but that's a
785 different story (we can't change it without losing backward
786 compatibility with old object files) (coff-i386 does subtract the old
787 value, to be compatible with existing coff-i386 targets, like SCO).
789 So everything works fine when not producing relocatable output. When
790 we are producing relocatable output, logically we should do exactly
791 what we do when not producing relocatable output. Therefore, your
792 patch is correct. In fact, it should probably always just set
793 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
794 add the value into the object file. This won't hurt the COFF code,
795 which doesn't use the addend; I'm not sure what it will do to other
796 formats (the thing to check for would be whether any formats both use
797 the addend and set partial_inplace).
799 When I wanted to make coff-i386 produce relocatable output, I ran
800 into the problem that you are running into: I wanted to remove that
801 line. Rather than risk it, I made the coff-i386 relocs use a special
802 function; it's coff_i386_reloc in coff-i386.c. The function
803 specifically adds the addend field into the object file, knowing that
804 bfd_perform_relocation is not going to. If you remove that line, then
805 coff-i386.c will wind up adding the addend field in twice. It's
806 trivial to fix; it just needs to be done.
808 The problem with removing the line is just that it may break some
809 working code. With BFD it's hard to be sure of anything. The right
810 way to deal with this is simply to build and test at least all the
811 supported COFF targets. It should be straightforward if time and disk
812 space consuming. For each target:
814 2) generate some executable, and link it using -r (I would
815 probably use paranoia.o and link against newlib/libc.a, which
816 for all the supported targets would be available in
817 /usr/cygnus/progressive/H-host/target/lib/libc.a).
818 3) make the change to reloc.c
819 4) rebuild the linker
821 6) if the resulting object files are the same, you have at least
823 7) if they are different you have to figure out which version is
826 relocation -= reloc_entry->addend;
827 reloc_entry->addend = 0;
831 reloc_entry->addend = relocation;
836 /* FIXME: This overflow checking is incomplete, because the value
837 might have overflowed before we get here. For a correct check we
838 need to compute the value in a size larger than bitsize, but we
839 can't reasonably do that for a reloc the same size as a host
841 FIXME: We should also do overflow checking on the result after
842 adding in the value contained in the object file. */
843 if (howto->complain_on_overflow != complain_overflow_dont
844 && flag == bfd_reloc_ok)
845 flag = bfd_check_overflow (howto->complain_on_overflow,
848 bfd_arch_bits_per_address (abfd),
851 /* Either we are relocating all the way, or we don't want to apply
852 the relocation to the reloc entry (probably because there isn't
853 any room in the output format to describe addends to relocs). */
855 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
856 (OSF version 1.3, compiler version 3.11). It miscompiles the
870 x <<= (unsigned long) s.i0;
874 printf ("succeeded (%lx)\n", x);
878 relocation >>= (bfd_vma) howto->rightshift;
880 /* Shift everything up to where it's going to be used. */
881 relocation <<= (bfd_vma) howto->bitpos;
883 /* Wait for the day when all have the mask in them. */
886 i instruction to be left alone
887 o offset within instruction
888 r relocation offset to apply
897 (( i i i i i o o o o o from bfd_get<size>
898 and S S S S S) to get the size offset we want
899 + r r r r r r r r r r) to get the final value to place
900 and D D D D D to chop to right size
901 -----------------------
904 ( i i i i i o o o o o from bfd_get<size>
905 and N N N N N ) get instruction
906 -----------------------
912 -----------------------
913 = R R R R R R R R R R put into bfd_put<size>
917 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
923 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
926 bfd_put_16 (abfd, (bfd_vma) (x >> 8), (bfd_byte *) data + octets);
927 bfd_put_8 (abfd, (x & 0xFF), (unsigned char *) data + 2 + octets);
933 char x = bfd_get_8 (abfd, (char *) data + octets);
935 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
941 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
943 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
948 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
950 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
955 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
956 relocation = -relocation;
958 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
964 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
965 relocation = -relocation;
967 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
978 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
980 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
987 return bfd_reloc_other;
995 bfd_install_relocation
998 bfd_reloc_status_type bfd_install_relocation
1000 arelent *reloc_entry,
1001 void *data, bfd_vma data_start,
1002 asection *input_section,
1003 char **error_message);
1006 This looks remarkably like <<bfd_perform_relocation>>, except it
1007 does not expect that the section contents have been filled in.
1008 I.e., it's suitable for use when creating, rather than applying
1011 For now, this function should be considered reserved for the
1015 bfd_reloc_status_type
1016 bfd_install_relocation (bfd *abfd,
1017 arelent *reloc_entry,
1019 bfd_vma data_start_offset,
1020 asection *input_section,
1021 char **error_message)
1024 bfd_reloc_status_type flag = bfd_reloc_ok;
1025 bfd_size_type octets;
1026 bfd_vma output_base = 0;
1027 reloc_howto_type *howto = reloc_entry->howto;
1028 asection *reloc_target_output_section;
1032 symbol = *(reloc_entry->sym_ptr_ptr);
1034 /* If there is a function supplied to handle this relocation type,
1035 call it. It'll return `bfd_reloc_continue' if further processing
1037 if (howto && howto->special_function)
1039 bfd_reloc_status_type cont;
1041 /* Note - we do not call bfd_reloc_offset_in_range here as the
1042 reloc_entry->address field might actually be valid for the
1043 backend concerned. It is up to the special_function itself
1044 to call bfd_reloc_offset_in_range if needed. */
1045 /* XXX - The special_function calls haven't been fixed up to deal
1046 with creating new relocations and section contents. */
1047 cont = howto->special_function (abfd, reloc_entry, symbol,
1048 /* XXX - Non-portable! */
1049 ((bfd_byte *) data_start
1050 - data_start_offset),
1051 input_section, abfd, error_message);
1052 if (cont != bfd_reloc_continue)
1056 if (bfd_is_abs_section (symbol->section))
1058 reloc_entry->address += input_section->output_offset;
1059 return bfd_reloc_ok;
1062 /* No need to check for howto != NULL if !bfd_is_abs_section as
1063 it will have been checked in `bfd_perform_relocation already'. */
1065 /* Is the address of the relocation really within the section? */
1066 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
1067 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
1068 return bfd_reloc_outofrange;
1070 /* Work out which section the relocation is targeted at and the
1071 initial relocation command value. */
1073 /* Get symbol value. (Common symbols are special.) */
1074 if (bfd_is_com_section (symbol->section))
1077 relocation = symbol->value;
1079 reloc_target_output_section = symbol->section->output_section;
1081 /* Convert input-section-relative symbol value to absolute. */
1082 if (! howto->partial_inplace)
1085 output_base = reloc_target_output_section->vma;
1087 relocation += output_base + symbol->section->output_offset;
1089 /* Add in supplied addend. */
1090 relocation += reloc_entry->addend;
1092 /* Here the variable relocation holds the final address of the
1093 symbol we are relocating against, plus any addend. */
1095 if (howto->pc_relative)
1097 /* This is a PC relative relocation. We want to set RELOCATION
1098 to the distance between the address of the symbol and the
1099 location. RELOCATION is already the address of the symbol.
1101 We start by subtracting the address of the section containing
1104 If pcrel_offset is set, we must further subtract the position
1105 of the location within the section. Some targets arrange for
1106 the addend to be the negative of the position of the location
1107 within the section; for example, i386-aout does this. For
1108 i386-aout, pcrel_offset is FALSE. Some other targets do not
1109 include the position of the location; for example, ELF.
1110 For those targets, pcrel_offset is TRUE.
1112 If we are producing relocatable output, then we must ensure
1113 that this reloc will be correctly computed when the final
1114 relocation is done. If pcrel_offset is FALSE we want to wind
1115 up with the negative of the location within the section,
1116 which means we must adjust the existing addend by the change
1117 in the location within the section. If pcrel_offset is TRUE
1118 we do not want to adjust the existing addend at all.
1120 FIXME: This seems logical to me, but for the case of
1121 producing relocatable output it is not what the code
1122 actually does. I don't want to change it, because it seems
1123 far too likely that something will break. */
1126 input_section->output_section->vma + input_section->output_offset;
1128 if (howto->pcrel_offset && howto->partial_inplace)
1129 relocation -= reloc_entry->address;
1132 if (! howto->partial_inplace)
1134 /* This is a partial relocation, and we want to apply the relocation
1135 to the reloc entry rather than the raw data. Modify the reloc
1136 inplace to reflect what we now know. */
1137 reloc_entry->addend = relocation;
1138 reloc_entry->address += input_section->output_offset;
1143 /* This is a partial relocation, but inplace, so modify the
1146 If we've relocated with a symbol with a section, change
1147 into a ref to the section belonging to the symbol. */
1148 reloc_entry->address += input_section->output_offset;
1151 if (abfd->xvec->flavour == bfd_target_coff_flavour
1152 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1153 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1156 /* For m68k-coff, the addend was being subtracted twice during
1157 relocation with -r. Removing the line below this comment
1158 fixes that problem; see PR 2953.
1160 However, Ian wrote the following, regarding removing the line below,
1161 which explains why it is still enabled: --djm
1163 If you put a patch like that into BFD you need to check all the COFF
1164 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1165 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1166 problem in a different way. There may very well be a reason that the
1167 code works as it does.
1169 Hmmm. The first obvious point is that bfd_install_relocation should
1170 not have any tests that depend upon the flavour. It's seem like
1171 entirely the wrong place for such a thing. The second obvious point
1172 is that the current code ignores the reloc addend when producing
1173 relocatable output for COFF. That's peculiar. In fact, I really
1174 have no idea what the point of the line you want to remove is.
1176 A typical COFF reloc subtracts the old value of the symbol and adds in
1177 the new value to the location in the object file (if it's a pc
1178 relative reloc it adds the difference between the symbol value and the
1179 location). When relocating we need to preserve that property.
1181 BFD handles this by setting the addend to the negative of the old
1182 value of the symbol. Unfortunately it handles common symbols in a
1183 non-standard way (it doesn't subtract the old value) but that's a
1184 different story (we can't change it without losing backward
1185 compatibility with old object files) (coff-i386 does subtract the old
1186 value, to be compatible with existing coff-i386 targets, like SCO).
1188 So everything works fine when not producing relocatable output. When
1189 we are producing relocatable output, logically we should do exactly
1190 what we do when not producing relocatable output. Therefore, your
1191 patch is correct. In fact, it should probably always just set
1192 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1193 add the value into the object file. This won't hurt the COFF code,
1194 which doesn't use the addend; I'm not sure what it will do to other
1195 formats (the thing to check for would be whether any formats both use
1196 the addend and set partial_inplace).
1198 When I wanted to make coff-i386 produce relocatable output, I ran
1199 into the problem that you are running into: I wanted to remove that
1200 line. Rather than risk it, I made the coff-i386 relocs use a special
1201 function; it's coff_i386_reloc in coff-i386.c. The function
1202 specifically adds the addend field into the object file, knowing that
1203 bfd_install_relocation is not going to. If you remove that line, then
1204 coff-i386.c will wind up adding the addend field in twice. It's
1205 trivial to fix; it just needs to be done.
1207 The problem with removing the line is just that it may break some
1208 working code. With BFD it's hard to be sure of anything. The right
1209 way to deal with this is simply to build and test at least all the
1210 supported COFF targets. It should be straightforward if time and disk
1211 space consuming. For each target:
1213 2) generate some executable, and link it using -r (I would
1214 probably use paranoia.o and link against newlib/libc.a, which
1215 for all the supported targets would be available in
1216 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1217 3) make the change to reloc.c
1218 4) rebuild the linker
1220 6) if the resulting object files are the same, you have at least
1222 7) if they are different you have to figure out which version is
1224 relocation -= reloc_entry->addend;
1225 /* FIXME: There should be no target specific code here... */
1226 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1227 reloc_entry->addend = 0;
1231 reloc_entry->addend = relocation;
1235 /* FIXME: This overflow checking is incomplete, because the value
1236 might have overflowed before we get here. For a correct check we
1237 need to compute the value in a size larger than bitsize, but we
1238 can't reasonably do that for a reloc the same size as a host
1240 FIXME: We should also do overflow checking on the result after
1241 adding in the value contained in the object file. */
1242 if (howto->complain_on_overflow != complain_overflow_dont)
1243 flag = bfd_check_overflow (howto->complain_on_overflow,
1246 bfd_arch_bits_per_address (abfd),
1249 /* Either we are relocating all the way, or we don't want to apply
1250 the relocation to the reloc entry (probably because there isn't
1251 any room in the output format to describe addends to relocs). */
1253 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1254 (OSF version 1.3, compiler version 3.11). It miscompiles the
1268 x <<= (unsigned long) s.i0;
1270 printf ("failed\n");
1272 printf ("succeeded (%lx)\n", x);
1276 relocation >>= (bfd_vma) howto->rightshift;
1278 /* Shift everything up to where it's going to be used. */
1279 relocation <<= (bfd_vma) howto->bitpos;
1281 /* Wait for the day when all have the mask in them. */
1284 i instruction to be left alone
1285 o offset within instruction
1286 r relocation offset to apply
1295 (( i i i i i o o o o o from bfd_get<size>
1296 and S S S S S) to get the size offset we want
1297 + r r r r r r r r r r) to get the final value to place
1298 and D D D D D to chop to right size
1299 -----------------------
1302 ( i i i i i o o o o o from bfd_get<size>
1303 and N N N N N ) get instruction
1304 -----------------------
1310 -----------------------
1311 = R R R R R R R R R R put into bfd_put<size>
1315 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1317 data = (bfd_byte *) data_start + (octets - data_start_offset);
1319 switch (howto->size)
1323 char x = bfd_get_8 (abfd, data);
1325 bfd_put_8 (abfd, x, data);
1331 short x = bfd_get_16 (abfd, data);
1333 bfd_put_16 (abfd, (bfd_vma) x, data);
1338 long x = bfd_get_32 (abfd, data);
1340 bfd_put_32 (abfd, (bfd_vma) x, data);
1345 long x = bfd_get_32 (abfd, data);
1346 relocation = -relocation;
1348 bfd_put_32 (abfd, (bfd_vma) x, data);
1358 bfd_vma x = bfd_get_64 (abfd, data);
1360 bfd_put_64 (abfd, x, data);
1364 return bfd_reloc_other;
1370 /* This relocation routine is used by some of the backend linkers.
1371 They do not construct asymbol or arelent structures, so there is no
1372 reason for them to use bfd_perform_relocation. Also,
1373 bfd_perform_relocation is so hacked up it is easier to write a new
1374 function than to try to deal with it.
1376 This routine does a final relocation. Whether it is useful for a
1377 relocatable link depends upon how the object format defines
1380 FIXME: This routine ignores any special_function in the HOWTO,
1381 since the existing special_function values have been written for
1382 bfd_perform_relocation.
1384 HOWTO is the reloc howto information.
1385 INPUT_BFD is the BFD which the reloc applies to.
1386 INPUT_SECTION is the section which the reloc applies to.
1387 CONTENTS is the contents of the section.
1388 ADDRESS is the address of the reloc within INPUT_SECTION.
1389 VALUE is the value of the symbol the reloc refers to.
1390 ADDEND is the addend of the reloc. */
1392 bfd_reloc_status_type
1393 _bfd_final_link_relocate (reloc_howto_type *howto,
1395 asection *input_section,
1402 bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
1404 /* Sanity check the address. */
1405 if (!bfd_reloc_offset_in_range (howto, input_bfd, input_section, octets))
1406 return bfd_reloc_outofrange;
1408 /* This function assumes that we are dealing with a basic relocation
1409 against a symbol. We want to compute the value of the symbol to
1410 relocate to. This is just VALUE, the value of the symbol, plus
1411 ADDEND, any addend associated with the reloc. */
1412 relocation = value + addend;
1414 /* If the relocation is PC relative, we want to set RELOCATION to
1415 the distance between the symbol (currently in RELOCATION) and the
1416 location we are relocating. Some targets (e.g., i386-aout)
1417 arrange for the contents of the section to be the negative of the
1418 offset of the location within the section; for such targets
1419 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1420 the contents of the section as zero; for such targets
1421 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1422 subtract out the offset of the location within the section (which
1423 is just ADDRESS). */
1424 if (howto->pc_relative)
1426 relocation -= (input_section->output_section->vma
1427 + input_section->output_offset);
1428 if (howto->pcrel_offset)
1429 relocation -= address;
1432 return _bfd_relocate_contents (howto, input_bfd, relocation,
1434 + address * bfd_octets_per_byte (input_bfd));
1437 /* Relocate a given location using a given value and howto. */
1439 bfd_reloc_status_type
1440 _bfd_relocate_contents (reloc_howto_type *howto,
1447 bfd_reloc_status_type flag;
1448 unsigned int rightshift = howto->rightshift;
1449 unsigned int bitpos = howto->bitpos;
1451 /* If the size is negative, negate RELOCATION. This isn't very
1453 if (howto->size < 0)
1454 relocation = -relocation;
1456 /* Get the value we are going to relocate. */
1457 size = bfd_get_reloc_size (howto);
1463 return bfd_reloc_ok;
1465 x = bfd_get_8 (input_bfd, location);
1468 x = bfd_get_16 (input_bfd, location);
1471 x = bfd_get_32 (input_bfd, location);
1475 x = bfd_get_64 (input_bfd, location);
1482 /* Check for overflow. FIXME: We may drop bits during the addition
1483 which we don't check for. We must either check at every single
1484 operation, which would be tedious, or we must do the computations
1485 in a type larger than bfd_vma, which would be inefficient. */
1486 flag = bfd_reloc_ok;
1487 if (howto->complain_on_overflow != complain_overflow_dont)
1489 bfd_vma addrmask, fieldmask, signmask, ss;
1492 /* Get the values to be added together. For signed and unsigned
1493 relocations, we assume that all values should be truncated to
1494 the size of an address. For bitfields, all the bits matter.
1495 See also bfd_check_overflow. */
1496 fieldmask = N_ONES (howto->bitsize);
1497 signmask = ~fieldmask;
1498 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1499 | (fieldmask << rightshift));
1500 a = (relocation & addrmask) >> rightshift;
1501 b = (x & howto->src_mask & addrmask) >> bitpos;
1502 addrmask >>= rightshift;
1504 switch (howto->complain_on_overflow)
1506 case complain_overflow_signed:
1507 /* If any sign bits are set, all sign bits must be set.
1508 That is, A must be a valid negative address after
1510 signmask = ~(fieldmask >> 1);
1513 case complain_overflow_bitfield:
1514 /* Much like the signed check, but for a field one bit
1515 wider. We allow a bitfield to represent numbers in the
1516 range -2**n to 2**n-1, where n is the number of bits in the
1517 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1518 can't overflow, which is exactly what we want. */
1520 if (ss != 0 && ss != (addrmask & signmask))
1521 flag = bfd_reloc_overflow;
1523 /* We only need this next bit of code if the sign bit of B
1524 is below the sign bit of A. This would only happen if
1525 SRC_MASK had fewer bits than BITSIZE. Note that if
1526 SRC_MASK has more bits than BITSIZE, we can get into
1527 trouble; we would need to verify that B is in range, as
1528 we do for A above. */
1529 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1532 /* Set all the bits above the sign bit. */
1535 /* Now we can do the addition. */
1538 /* See if the result has the correct sign. Bits above the
1539 sign bit are junk now; ignore them. If the sum is
1540 positive, make sure we did not have all negative inputs;
1541 if the sum is negative, make sure we did not have all
1542 positive inputs. The test below looks only at the sign
1543 bits, and it really just
1544 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1546 We mask with addrmask here to explicitly allow an address
1547 wrap-around. The Linux kernel relies on it, and it is
1548 the only way to write assembler code which can run when
1549 loaded at a location 0x80000000 away from the location at
1550 which it is linked. */
1551 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1552 flag = bfd_reloc_overflow;
1555 case complain_overflow_unsigned:
1556 /* Checking for an unsigned overflow is relatively easy:
1557 trim the addresses and add, and trim the result as well.
1558 Overflow is normally indicated when the result does not
1559 fit in the field. However, we also need to consider the
1560 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1561 input is 0x80000000, and bfd_vma is only 32 bits; then we
1562 will get sum == 0, but there is an overflow, since the
1563 inputs did not fit in the field. Instead of doing a
1564 separate test, we can check for this by or-ing in the
1565 operands when testing for the sum overflowing its final
1567 sum = (a + b) & addrmask;
1568 if ((a | b | sum) & signmask)
1569 flag = bfd_reloc_overflow;
1577 /* Put RELOCATION in the right bits. */
1578 relocation >>= (bfd_vma) rightshift;
1579 relocation <<= (bfd_vma) bitpos;
1581 /* Add RELOCATION to the right bits of X. */
1582 x = ((x & ~howto->dst_mask)
1583 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1585 /* Put the relocated value back in the object file. */
1591 bfd_put_8 (input_bfd, x, location);
1594 bfd_put_16 (input_bfd, x, location);
1597 bfd_put_32 (input_bfd, x, location);
1601 bfd_put_64 (input_bfd, x, location);
1611 /* Clear a given location using a given howto, by applying a fixed relocation
1612 value and discarding any in-place addend. This is used for fixed-up
1613 relocations against discarded symbols, to make ignorable debug or unwind
1614 information more obvious. */
1617 _bfd_clear_contents (reloc_howto_type *howto,
1619 asection *input_section,
1625 /* Get the value we are going to relocate. */
1626 size = bfd_get_reloc_size (howto);
1634 x = bfd_get_8 (input_bfd, location);
1637 x = bfd_get_16 (input_bfd, location);
1640 x = bfd_get_32 (input_bfd, location);
1644 x = bfd_get_64 (input_bfd, location);
1651 /* Zero out the unwanted bits of X. */
1652 x &= ~howto->dst_mask;
1654 /* For a range list, use 1 instead of 0 as placeholder. 0
1655 would terminate the list, hiding any later entries. */
1656 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1657 ".debug_ranges") == 0
1658 && (howto->dst_mask & 1) != 0)
1661 /* Put the relocated value back in the object file. */
1668 bfd_put_8 (input_bfd, x, location);
1671 bfd_put_16 (input_bfd, x, location);
1674 bfd_put_32 (input_bfd, x, location);
1678 bfd_put_64 (input_bfd, x, location);
1689 howto manager, , typedef arelent, Relocations
1694 When an application wants to create a relocation, but doesn't
1695 know what the target machine might call it, it can find out by
1696 using this bit of code.
1705 The insides of a reloc code. The idea is that, eventually, there
1706 will be one enumerator for every type of relocation we ever do.
1707 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1708 return a howto pointer.
1710 This does mean that the application must determine the correct
1711 enumerator value; you can't get a howto pointer from a random set
1732 Basic absolute relocations of N bits.
1747 PC-relative relocations. Sometimes these are relative to the address
1748 of the relocation itself; sometimes they are relative to the start of
1749 the section containing the relocation. It depends on the specific target.
1754 Section relative relocations. Some targets need this for DWARF2.
1757 BFD_RELOC_32_GOT_PCREL
1759 BFD_RELOC_16_GOT_PCREL
1761 BFD_RELOC_8_GOT_PCREL
1767 BFD_RELOC_LO16_GOTOFF
1769 BFD_RELOC_HI16_GOTOFF
1771 BFD_RELOC_HI16_S_GOTOFF
1775 BFD_RELOC_64_PLT_PCREL
1777 BFD_RELOC_32_PLT_PCREL
1779 BFD_RELOC_24_PLT_PCREL
1781 BFD_RELOC_16_PLT_PCREL
1783 BFD_RELOC_8_PLT_PCREL
1791 BFD_RELOC_LO16_PLTOFF
1793 BFD_RELOC_HI16_PLTOFF
1795 BFD_RELOC_HI16_S_PLTOFF
1809 BFD_RELOC_68K_GLOB_DAT
1811 BFD_RELOC_68K_JMP_SLOT
1813 BFD_RELOC_68K_RELATIVE
1815 BFD_RELOC_68K_TLS_GD32
1817 BFD_RELOC_68K_TLS_GD16
1819 BFD_RELOC_68K_TLS_GD8
1821 BFD_RELOC_68K_TLS_LDM32
1823 BFD_RELOC_68K_TLS_LDM16
1825 BFD_RELOC_68K_TLS_LDM8
1827 BFD_RELOC_68K_TLS_LDO32
1829 BFD_RELOC_68K_TLS_LDO16
1831 BFD_RELOC_68K_TLS_LDO8
1833 BFD_RELOC_68K_TLS_IE32
1835 BFD_RELOC_68K_TLS_IE16
1837 BFD_RELOC_68K_TLS_IE8
1839 BFD_RELOC_68K_TLS_LE32
1841 BFD_RELOC_68K_TLS_LE16
1843 BFD_RELOC_68K_TLS_LE8
1845 Relocations used by 68K ELF.
1848 BFD_RELOC_32_BASEREL
1850 BFD_RELOC_16_BASEREL
1852 BFD_RELOC_LO16_BASEREL
1854 BFD_RELOC_HI16_BASEREL
1856 BFD_RELOC_HI16_S_BASEREL
1862 Linkage-table relative.
1867 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1870 BFD_RELOC_32_PCREL_S2
1872 BFD_RELOC_16_PCREL_S2
1874 BFD_RELOC_23_PCREL_S2
1876 These PC-relative relocations are stored as word displacements --
1877 i.e., byte displacements shifted right two bits. The 30-bit word
1878 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1879 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1880 signed 16-bit displacement is used on the MIPS, and the 23-bit
1881 displacement is used on the Alpha.
1888 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1889 the target word. These are used on the SPARC.
1896 For systems that allocate a Global Pointer register, these are
1897 displacements off that register. These relocation types are
1898 handled specially, because the value the register will have is
1899 decided relatively late.
1904 BFD_RELOC_SPARC_WDISP22
1910 BFD_RELOC_SPARC_GOT10
1912 BFD_RELOC_SPARC_GOT13
1914 BFD_RELOC_SPARC_GOT22
1916 BFD_RELOC_SPARC_PC10
1918 BFD_RELOC_SPARC_PC22
1920 BFD_RELOC_SPARC_WPLT30
1922 BFD_RELOC_SPARC_COPY
1924 BFD_RELOC_SPARC_GLOB_DAT
1926 BFD_RELOC_SPARC_JMP_SLOT
1928 BFD_RELOC_SPARC_RELATIVE
1930 BFD_RELOC_SPARC_UA16
1932 BFD_RELOC_SPARC_UA32
1934 BFD_RELOC_SPARC_UA64
1936 BFD_RELOC_SPARC_GOTDATA_HIX22
1938 BFD_RELOC_SPARC_GOTDATA_LOX10
1940 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1942 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1944 BFD_RELOC_SPARC_GOTDATA_OP
1946 BFD_RELOC_SPARC_JMP_IREL
1948 BFD_RELOC_SPARC_IRELATIVE
1950 SPARC ELF relocations. There is probably some overlap with other
1951 relocation types already defined.
1954 BFD_RELOC_SPARC_BASE13
1956 BFD_RELOC_SPARC_BASE22
1958 I think these are specific to SPARC a.out (e.g., Sun 4).
1968 BFD_RELOC_SPARC_OLO10
1970 BFD_RELOC_SPARC_HH22
1972 BFD_RELOC_SPARC_HM10
1974 BFD_RELOC_SPARC_LM22
1976 BFD_RELOC_SPARC_PC_HH22
1978 BFD_RELOC_SPARC_PC_HM10
1980 BFD_RELOC_SPARC_PC_LM22
1982 BFD_RELOC_SPARC_WDISP16
1984 BFD_RELOC_SPARC_WDISP19
1992 BFD_RELOC_SPARC_DISP64
1995 BFD_RELOC_SPARC_PLT32
1997 BFD_RELOC_SPARC_PLT64
1999 BFD_RELOC_SPARC_HIX22
2001 BFD_RELOC_SPARC_LOX10
2009 BFD_RELOC_SPARC_REGISTER
2013 BFD_RELOC_SPARC_SIZE32
2015 BFD_RELOC_SPARC_SIZE64
2017 BFD_RELOC_SPARC_WDISP10
2022 BFD_RELOC_SPARC_REV32
2024 SPARC little endian relocation
2026 BFD_RELOC_SPARC_TLS_GD_HI22
2028 BFD_RELOC_SPARC_TLS_GD_LO10
2030 BFD_RELOC_SPARC_TLS_GD_ADD
2032 BFD_RELOC_SPARC_TLS_GD_CALL
2034 BFD_RELOC_SPARC_TLS_LDM_HI22
2036 BFD_RELOC_SPARC_TLS_LDM_LO10
2038 BFD_RELOC_SPARC_TLS_LDM_ADD
2040 BFD_RELOC_SPARC_TLS_LDM_CALL
2042 BFD_RELOC_SPARC_TLS_LDO_HIX22
2044 BFD_RELOC_SPARC_TLS_LDO_LOX10
2046 BFD_RELOC_SPARC_TLS_LDO_ADD
2048 BFD_RELOC_SPARC_TLS_IE_HI22
2050 BFD_RELOC_SPARC_TLS_IE_LO10
2052 BFD_RELOC_SPARC_TLS_IE_LD
2054 BFD_RELOC_SPARC_TLS_IE_LDX
2056 BFD_RELOC_SPARC_TLS_IE_ADD
2058 BFD_RELOC_SPARC_TLS_LE_HIX22
2060 BFD_RELOC_SPARC_TLS_LE_LOX10
2062 BFD_RELOC_SPARC_TLS_DTPMOD32
2064 BFD_RELOC_SPARC_TLS_DTPMOD64
2066 BFD_RELOC_SPARC_TLS_DTPOFF32
2068 BFD_RELOC_SPARC_TLS_DTPOFF64
2070 BFD_RELOC_SPARC_TLS_TPOFF32
2072 BFD_RELOC_SPARC_TLS_TPOFF64
2074 SPARC TLS relocations
2083 BFD_RELOC_SPU_IMM10W
2087 BFD_RELOC_SPU_IMM16W
2091 BFD_RELOC_SPU_PCREL9a
2093 BFD_RELOC_SPU_PCREL9b
2095 BFD_RELOC_SPU_PCREL16
2105 BFD_RELOC_SPU_ADD_PIC
2110 BFD_RELOC_ALPHA_GPDISP_HI16
2112 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2113 "addend" in some special way.
2114 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2115 writing; when reading, it will be the absolute section symbol. The
2116 addend is the displacement in bytes of the "lda" instruction from
2117 the "ldah" instruction (which is at the address of this reloc).
2119 BFD_RELOC_ALPHA_GPDISP_LO16
2121 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2122 with GPDISP_HI16 relocs. The addend is ignored when writing the
2123 relocations out, and is filled in with the file's GP value on
2124 reading, for convenience.
2127 BFD_RELOC_ALPHA_GPDISP
2129 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2130 relocation except that there is no accompanying GPDISP_LO16
2134 BFD_RELOC_ALPHA_LITERAL
2136 BFD_RELOC_ALPHA_ELF_LITERAL
2138 BFD_RELOC_ALPHA_LITUSE
2140 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2141 the assembler turns it into a LDQ instruction to load the address of
2142 the symbol, and then fills in a register in the real instruction.
2144 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2145 section symbol. The addend is ignored when writing, but is filled
2146 in with the file's GP value on reading, for convenience, as with the
2149 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2150 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2151 but it generates output not based on the position within the .got
2152 section, but relative to the GP value chosen for the file during the
2155 The LITUSE reloc, on the instruction using the loaded address, gives
2156 information to the linker that it might be able to use to optimize
2157 away some literal section references. The symbol is ignored (read
2158 as the absolute section symbol), and the "addend" indicates the type
2159 of instruction using the register:
2160 1 - "memory" fmt insn
2161 2 - byte-manipulation (byte offset reg)
2162 3 - jsr (target of branch)
2165 BFD_RELOC_ALPHA_HINT
2167 The HINT relocation indicates a value that should be filled into the
2168 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2169 prediction logic which may be provided on some processors.
2172 BFD_RELOC_ALPHA_LINKAGE
2174 The LINKAGE relocation outputs a linkage pair in the object file,
2175 which is filled by the linker.
2178 BFD_RELOC_ALPHA_CODEADDR
2180 The CODEADDR relocation outputs a STO_CA in the object file,
2181 which is filled by the linker.
2184 BFD_RELOC_ALPHA_GPREL_HI16
2186 BFD_RELOC_ALPHA_GPREL_LO16
2188 The GPREL_HI/LO relocations together form a 32-bit offset from the
2192 BFD_RELOC_ALPHA_BRSGP
2194 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2195 share a common GP, and the target address is adjusted for
2196 STO_ALPHA_STD_GPLOAD.
2201 The NOP relocation outputs a NOP if the longword displacement
2202 between two procedure entry points is < 2^21.
2207 The BSR relocation outputs a BSR if the longword displacement
2208 between two procedure entry points is < 2^21.
2213 The LDA relocation outputs a LDA if the longword displacement
2214 between two procedure entry points is < 2^16.
2219 The BOH relocation outputs a BSR if the longword displacement
2220 between two procedure entry points is < 2^21, or else a hint.
2223 BFD_RELOC_ALPHA_TLSGD
2225 BFD_RELOC_ALPHA_TLSLDM
2227 BFD_RELOC_ALPHA_DTPMOD64
2229 BFD_RELOC_ALPHA_GOTDTPREL16
2231 BFD_RELOC_ALPHA_DTPREL64
2233 BFD_RELOC_ALPHA_DTPREL_HI16
2235 BFD_RELOC_ALPHA_DTPREL_LO16
2237 BFD_RELOC_ALPHA_DTPREL16
2239 BFD_RELOC_ALPHA_GOTTPREL16
2241 BFD_RELOC_ALPHA_TPREL64
2243 BFD_RELOC_ALPHA_TPREL_HI16
2245 BFD_RELOC_ALPHA_TPREL_LO16
2247 BFD_RELOC_ALPHA_TPREL16
2249 Alpha thread-local storage relocations.
2254 BFD_RELOC_MICROMIPS_JMP
2256 The MIPS jump instruction.
2259 BFD_RELOC_MIPS16_JMP
2261 The MIPS16 jump instruction.
2264 BFD_RELOC_MIPS16_GPREL
2266 MIPS16 GP relative reloc.
2271 High 16 bits of 32-bit value; simple reloc.
2276 High 16 bits of 32-bit value but the low 16 bits will be sign
2277 extended and added to form the final result. If the low 16
2278 bits form a negative number, we need to add one to the high value
2279 to compensate for the borrow when the low bits are added.
2287 BFD_RELOC_HI16_PCREL
2289 High 16 bits of 32-bit pc-relative value
2291 BFD_RELOC_HI16_S_PCREL
2293 High 16 bits of 32-bit pc-relative value, adjusted
2295 BFD_RELOC_LO16_PCREL
2297 Low 16 bits of pc-relative value
2300 BFD_RELOC_MIPS16_GOT16
2302 BFD_RELOC_MIPS16_CALL16
2304 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2305 16-bit immediate fields
2307 BFD_RELOC_MIPS16_HI16
2309 MIPS16 high 16 bits of 32-bit value.
2311 BFD_RELOC_MIPS16_HI16_S
2313 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2314 extended and added to form the final result. If the low 16
2315 bits form a negative number, we need to add one to the high value
2316 to compensate for the borrow when the low bits are added.
2318 BFD_RELOC_MIPS16_LO16
2323 BFD_RELOC_MIPS16_TLS_GD
2325 BFD_RELOC_MIPS16_TLS_LDM
2327 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2329 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2331 BFD_RELOC_MIPS16_TLS_GOTTPREL
2333 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2335 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2337 MIPS16 TLS relocations
2340 BFD_RELOC_MIPS_LITERAL
2342 BFD_RELOC_MICROMIPS_LITERAL
2344 Relocation against a MIPS literal section.
2347 BFD_RELOC_MICROMIPS_7_PCREL_S1
2349 BFD_RELOC_MICROMIPS_10_PCREL_S1
2351 BFD_RELOC_MICROMIPS_16_PCREL_S1
2353 microMIPS PC-relative relocations.
2356 BFD_RELOC_MIPS16_16_PCREL_S1
2358 MIPS16 PC-relative relocation.
2361 BFD_RELOC_MIPS_21_PCREL_S2
2363 BFD_RELOC_MIPS_26_PCREL_S2
2365 BFD_RELOC_MIPS_18_PCREL_S3
2367 BFD_RELOC_MIPS_19_PCREL_S2
2369 MIPS PC-relative relocations.
2372 BFD_RELOC_MICROMIPS_GPREL16
2374 BFD_RELOC_MICROMIPS_HI16
2376 BFD_RELOC_MICROMIPS_HI16_S
2378 BFD_RELOC_MICROMIPS_LO16
2380 microMIPS versions of generic BFD relocs.
2383 BFD_RELOC_MIPS_GOT16
2385 BFD_RELOC_MICROMIPS_GOT16
2387 BFD_RELOC_MIPS_CALL16
2389 BFD_RELOC_MICROMIPS_CALL16
2391 BFD_RELOC_MIPS_GOT_HI16
2393 BFD_RELOC_MICROMIPS_GOT_HI16
2395 BFD_RELOC_MIPS_GOT_LO16
2397 BFD_RELOC_MICROMIPS_GOT_LO16
2399 BFD_RELOC_MIPS_CALL_HI16
2401 BFD_RELOC_MICROMIPS_CALL_HI16
2403 BFD_RELOC_MIPS_CALL_LO16
2405 BFD_RELOC_MICROMIPS_CALL_LO16
2409 BFD_RELOC_MICROMIPS_SUB
2411 BFD_RELOC_MIPS_GOT_PAGE
2413 BFD_RELOC_MICROMIPS_GOT_PAGE
2415 BFD_RELOC_MIPS_GOT_OFST
2417 BFD_RELOC_MICROMIPS_GOT_OFST
2419 BFD_RELOC_MIPS_GOT_DISP
2421 BFD_RELOC_MICROMIPS_GOT_DISP
2423 BFD_RELOC_MIPS_SHIFT5
2425 BFD_RELOC_MIPS_SHIFT6
2427 BFD_RELOC_MIPS_INSERT_A
2429 BFD_RELOC_MIPS_INSERT_B
2431 BFD_RELOC_MIPS_DELETE
2433 BFD_RELOC_MIPS_HIGHEST
2435 BFD_RELOC_MICROMIPS_HIGHEST
2437 BFD_RELOC_MIPS_HIGHER
2439 BFD_RELOC_MICROMIPS_HIGHER
2441 BFD_RELOC_MIPS_SCN_DISP
2443 BFD_RELOC_MICROMIPS_SCN_DISP
2445 BFD_RELOC_MIPS_REL16
2447 BFD_RELOC_MIPS_RELGOT
2451 BFD_RELOC_MICROMIPS_JALR
2453 BFD_RELOC_MIPS_TLS_DTPMOD32
2455 BFD_RELOC_MIPS_TLS_DTPREL32
2457 BFD_RELOC_MIPS_TLS_DTPMOD64
2459 BFD_RELOC_MIPS_TLS_DTPREL64
2461 BFD_RELOC_MIPS_TLS_GD
2463 BFD_RELOC_MICROMIPS_TLS_GD
2465 BFD_RELOC_MIPS_TLS_LDM
2467 BFD_RELOC_MICROMIPS_TLS_LDM
2469 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2471 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2473 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2475 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2477 BFD_RELOC_MIPS_TLS_GOTTPREL
2479 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2481 BFD_RELOC_MIPS_TLS_TPREL32
2483 BFD_RELOC_MIPS_TLS_TPREL64
2485 BFD_RELOC_MIPS_TLS_TPREL_HI16
2487 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2489 BFD_RELOC_MIPS_TLS_TPREL_LO16
2491 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2495 MIPS ELF relocations.
2501 BFD_RELOC_MIPS_JUMP_SLOT
2503 MIPS ELF relocations (VxWorks and PLT extensions).
2507 BFD_RELOC_MOXIE_10_PCREL
2509 Moxie ELF relocations.
2521 BFD_RELOC_FT32_RELAX
2529 BFD_RELOC_FT32_DIFF32
2531 FT32 ELF relocations.
2535 BFD_RELOC_FRV_LABEL16
2537 BFD_RELOC_FRV_LABEL24
2543 BFD_RELOC_FRV_GPREL12
2545 BFD_RELOC_FRV_GPRELU12
2547 BFD_RELOC_FRV_GPREL32
2549 BFD_RELOC_FRV_GPRELHI
2551 BFD_RELOC_FRV_GPRELLO
2559 BFD_RELOC_FRV_FUNCDESC
2561 BFD_RELOC_FRV_FUNCDESC_GOT12
2563 BFD_RELOC_FRV_FUNCDESC_GOTHI
2565 BFD_RELOC_FRV_FUNCDESC_GOTLO
2567 BFD_RELOC_FRV_FUNCDESC_VALUE
2569 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2571 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2573 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2575 BFD_RELOC_FRV_GOTOFF12
2577 BFD_RELOC_FRV_GOTOFFHI
2579 BFD_RELOC_FRV_GOTOFFLO
2581 BFD_RELOC_FRV_GETTLSOFF
2583 BFD_RELOC_FRV_TLSDESC_VALUE
2585 BFD_RELOC_FRV_GOTTLSDESC12
2587 BFD_RELOC_FRV_GOTTLSDESCHI
2589 BFD_RELOC_FRV_GOTTLSDESCLO
2591 BFD_RELOC_FRV_TLSMOFF12
2593 BFD_RELOC_FRV_TLSMOFFHI
2595 BFD_RELOC_FRV_TLSMOFFLO
2597 BFD_RELOC_FRV_GOTTLSOFF12
2599 BFD_RELOC_FRV_GOTTLSOFFHI
2601 BFD_RELOC_FRV_GOTTLSOFFLO
2603 BFD_RELOC_FRV_TLSOFF
2605 BFD_RELOC_FRV_TLSDESC_RELAX
2607 BFD_RELOC_FRV_GETTLSOFF_RELAX
2609 BFD_RELOC_FRV_TLSOFF_RELAX
2611 BFD_RELOC_FRV_TLSMOFF
2613 Fujitsu Frv Relocations.
2617 BFD_RELOC_MN10300_GOTOFF24
2619 This is a 24bit GOT-relative reloc for the mn10300.
2621 BFD_RELOC_MN10300_GOT32
2623 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2626 BFD_RELOC_MN10300_GOT24
2628 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2631 BFD_RELOC_MN10300_GOT16
2633 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2636 BFD_RELOC_MN10300_COPY
2638 Copy symbol at runtime.
2640 BFD_RELOC_MN10300_GLOB_DAT
2644 BFD_RELOC_MN10300_JMP_SLOT
2648 BFD_RELOC_MN10300_RELATIVE
2650 Adjust by program base.
2652 BFD_RELOC_MN10300_SYM_DIFF
2654 Together with another reloc targeted at the same location,
2655 allows for a value that is the difference of two symbols
2656 in the same section.
2658 BFD_RELOC_MN10300_ALIGN
2660 The addend of this reloc is an alignment power that must
2661 be honoured at the offset's location, regardless of linker
2664 BFD_RELOC_MN10300_TLS_GD
2666 BFD_RELOC_MN10300_TLS_LD
2668 BFD_RELOC_MN10300_TLS_LDO
2670 BFD_RELOC_MN10300_TLS_GOTIE
2672 BFD_RELOC_MN10300_TLS_IE
2674 BFD_RELOC_MN10300_TLS_LE
2676 BFD_RELOC_MN10300_TLS_DTPMOD
2678 BFD_RELOC_MN10300_TLS_DTPOFF
2680 BFD_RELOC_MN10300_TLS_TPOFF
2682 Various TLS-related relocations.
2684 BFD_RELOC_MN10300_32_PCREL
2686 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2689 BFD_RELOC_MN10300_16_PCREL
2691 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2702 BFD_RELOC_386_GLOB_DAT
2704 BFD_RELOC_386_JUMP_SLOT
2706 BFD_RELOC_386_RELATIVE
2708 BFD_RELOC_386_GOTOFF
2712 BFD_RELOC_386_TLS_TPOFF
2714 BFD_RELOC_386_TLS_IE
2716 BFD_RELOC_386_TLS_GOTIE
2718 BFD_RELOC_386_TLS_LE
2720 BFD_RELOC_386_TLS_GD
2722 BFD_RELOC_386_TLS_LDM
2724 BFD_RELOC_386_TLS_LDO_32
2726 BFD_RELOC_386_TLS_IE_32
2728 BFD_RELOC_386_TLS_LE_32
2730 BFD_RELOC_386_TLS_DTPMOD32
2732 BFD_RELOC_386_TLS_DTPOFF32
2734 BFD_RELOC_386_TLS_TPOFF32
2736 BFD_RELOC_386_TLS_GOTDESC
2738 BFD_RELOC_386_TLS_DESC_CALL
2740 BFD_RELOC_386_TLS_DESC
2742 BFD_RELOC_386_IRELATIVE
2744 BFD_RELOC_386_GOT32X
2746 i386/elf relocations
2749 BFD_RELOC_X86_64_GOT32
2751 BFD_RELOC_X86_64_PLT32
2753 BFD_RELOC_X86_64_COPY
2755 BFD_RELOC_X86_64_GLOB_DAT
2757 BFD_RELOC_X86_64_JUMP_SLOT
2759 BFD_RELOC_X86_64_RELATIVE
2761 BFD_RELOC_X86_64_GOTPCREL
2763 BFD_RELOC_X86_64_32S
2765 BFD_RELOC_X86_64_DTPMOD64
2767 BFD_RELOC_X86_64_DTPOFF64
2769 BFD_RELOC_X86_64_TPOFF64
2771 BFD_RELOC_X86_64_TLSGD
2773 BFD_RELOC_X86_64_TLSLD
2775 BFD_RELOC_X86_64_DTPOFF32
2777 BFD_RELOC_X86_64_GOTTPOFF
2779 BFD_RELOC_X86_64_TPOFF32
2781 BFD_RELOC_X86_64_GOTOFF64
2783 BFD_RELOC_X86_64_GOTPC32
2785 BFD_RELOC_X86_64_GOT64
2787 BFD_RELOC_X86_64_GOTPCREL64
2789 BFD_RELOC_X86_64_GOTPC64
2791 BFD_RELOC_X86_64_GOTPLT64
2793 BFD_RELOC_X86_64_PLTOFF64
2795 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2797 BFD_RELOC_X86_64_TLSDESC_CALL
2799 BFD_RELOC_X86_64_TLSDESC
2801 BFD_RELOC_X86_64_IRELATIVE
2803 BFD_RELOC_X86_64_PC32_BND
2805 BFD_RELOC_X86_64_PLT32_BND
2807 BFD_RELOC_X86_64_GOTPCRELX
2809 BFD_RELOC_X86_64_REX_GOTPCRELX
2811 x86-64/elf relocations
2814 BFD_RELOC_NS32K_IMM_8
2816 BFD_RELOC_NS32K_IMM_16
2818 BFD_RELOC_NS32K_IMM_32
2820 BFD_RELOC_NS32K_IMM_8_PCREL
2822 BFD_RELOC_NS32K_IMM_16_PCREL
2824 BFD_RELOC_NS32K_IMM_32_PCREL
2826 BFD_RELOC_NS32K_DISP_8
2828 BFD_RELOC_NS32K_DISP_16
2830 BFD_RELOC_NS32K_DISP_32
2832 BFD_RELOC_NS32K_DISP_8_PCREL
2834 BFD_RELOC_NS32K_DISP_16_PCREL
2836 BFD_RELOC_NS32K_DISP_32_PCREL
2841 BFD_RELOC_PDP11_DISP_8_PCREL
2843 BFD_RELOC_PDP11_DISP_6_PCREL
2848 BFD_RELOC_PJ_CODE_HI16
2850 BFD_RELOC_PJ_CODE_LO16
2852 BFD_RELOC_PJ_CODE_DIR16
2854 BFD_RELOC_PJ_CODE_DIR32
2856 BFD_RELOC_PJ_CODE_REL16
2858 BFD_RELOC_PJ_CODE_REL32
2860 Picojava relocs. Not all of these appear in object files.
2871 BFD_RELOC_PPC_B16_BRTAKEN
2873 BFD_RELOC_PPC_B16_BRNTAKEN
2877 BFD_RELOC_PPC_BA16_BRTAKEN
2879 BFD_RELOC_PPC_BA16_BRNTAKEN
2883 BFD_RELOC_PPC_GLOB_DAT
2885 BFD_RELOC_PPC_JMP_SLOT
2887 BFD_RELOC_PPC_RELATIVE
2889 BFD_RELOC_PPC_LOCAL24PC
2891 BFD_RELOC_PPC_EMB_NADDR32
2893 BFD_RELOC_PPC_EMB_NADDR16
2895 BFD_RELOC_PPC_EMB_NADDR16_LO
2897 BFD_RELOC_PPC_EMB_NADDR16_HI
2899 BFD_RELOC_PPC_EMB_NADDR16_HA
2901 BFD_RELOC_PPC_EMB_SDAI16
2903 BFD_RELOC_PPC_EMB_SDA2I16
2905 BFD_RELOC_PPC_EMB_SDA2REL
2907 BFD_RELOC_PPC_EMB_SDA21
2909 BFD_RELOC_PPC_EMB_MRKREF
2911 BFD_RELOC_PPC_EMB_RELSEC16
2913 BFD_RELOC_PPC_EMB_RELST_LO
2915 BFD_RELOC_PPC_EMB_RELST_HI
2917 BFD_RELOC_PPC_EMB_RELST_HA
2919 BFD_RELOC_PPC_EMB_BIT_FLD
2921 BFD_RELOC_PPC_EMB_RELSDA
2923 BFD_RELOC_PPC_VLE_REL8
2925 BFD_RELOC_PPC_VLE_REL15
2927 BFD_RELOC_PPC_VLE_REL24
2929 BFD_RELOC_PPC_VLE_LO16A
2931 BFD_RELOC_PPC_VLE_LO16D
2933 BFD_RELOC_PPC_VLE_HI16A
2935 BFD_RELOC_PPC_VLE_HI16D
2937 BFD_RELOC_PPC_VLE_HA16A
2939 BFD_RELOC_PPC_VLE_HA16D
2941 BFD_RELOC_PPC_VLE_SDA21
2943 BFD_RELOC_PPC_VLE_SDA21_LO
2945 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2947 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2949 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2951 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2953 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2955 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2957 BFD_RELOC_PPC_16DX_HA
2959 BFD_RELOC_PPC_REL16DX_HA
2961 BFD_RELOC_PPC64_HIGHER
2963 BFD_RELOC_PPC64_HIGHER_S
2965 BFD_RELOC_PPC64_HIGHEST
2967 BFD_RELOC_PPC64_HIGHEST_S
2969 BFD_RELOC_PPC64_TOC16_LO
2971 BFD_RELOC_PPC64_TOC16_HI
2973 BFD_RELOC_PPC64_TOC16_HA
2977 BFD_RELOC_PPC64_PLTGOT16
2979 BFD_RELOC_PPC64_PLTGOT16_LO
2981 BFD_RELOC_PPC64_PLTGOT16_HI
2983 BFD_RELOC_PPC64_PLTGOT16_HA
2985 BFD_RELOC_PPC64_ADDR16_DS
2987 BFD_RELOC_PPC64_ADDR16_LO_DS
2989 BFD_RELOC_PPC64_GOT16_DS
2991 BFD_RELOC_PPC64_GOT16_LO_DS
2993 BFD_RELOC_PPC64_PLT16_LO_DS
2995 BFD_RELOC_PPC64_SECTOFF_DS
2997 BFD_RELOC_PPC64_SECTOFF_LO_DS
2999 BFD_RELOC_PPC64_TOC16_DS
3001 BFD_RELOC_PPC64_TOC16_LO_DS
3003 BFD_RELOC_PPC64_PLTGOT16_DS
3005 BFD_RELOC_PPC64_PLTGOT16_LO_DS
3007 BFD_RELOC_PPC64_ADDR16_HIGH
3009 BFD_RELOC_PPC64_ADDR16_HIGHA
3011 BFD_RELOC_PPC64_ADDR64_LOCAL
3013 BFD_RELOC_PPC64_ENTRY
3015 Power(rs6000) and PowerPC relocations.
3024 BFD_RELOC_PPC_DTPMOD
3026 BFD_RELOC_PPC_TPREL16
3028 BFD_RELOC_PPC_TPREL16_LO
3030 BFD_RELOC_PPC_TPREL16_HI
3032 BFD_RELOC_PPC_TPREL16_HA
3036 BFD_RELOC_PPC_DTPREL16
3038 BFD_RELOC_PPC_DTPREL16_LO
3040 BFD_RELOC_PPC_DTPREL16_HI
3042 BFD_RELOC_PPC_DTPREL16_HA
3044 BFD_RELOC_PPC_DTPREL
3046 BFD_RELOC_PPC_GOT_TLSGD16
3048 BFD_RELOC_PPC_GOT_TLSGD16_LO
3050 BFD_RELOC_PPC_GOT_TLSGD16_HI
3052 BFD_RELOC_PPC_GOT_TLSGD16_HA
3054 BFD_RELOC_PPC_GOT_TLSLD16
3056 BFD_RELOC_PPC_GOT_TLSLD16_LO
3058 BFD_RELOC_PPC_GOT_TLSLD16_HI
3060 BFD_RELOC_PPC_GOT_TLSLD16_HA
3062 BFD_RELOC_PPC_GOT_TPREL16
3064 BFD_RELOC_PPC_GOT_TPREL16_LO
3066 BFD_RELOC_PPC_GOT_TPREL16_HI
3068 BFD_RELOC_PPC_GOT_TPREL16_HA
3070 BFD_RELOC_PPC_GOT_DTPREL16
3072 BFD_RELOC_PPC_GOT_DTPREL16_LO
3074 BFD_RELOC_PPC_GOT_DTPREL16_HI
3076 BFD_RELOC_PPC_GOT_DTPREL16_HA
3078 BFD_RELOC_PPC64_TPREL16_DS
3080 BFD_RELOC_PPC64_TPREL16_LO_DS
3082 BFD_RELOC_PPC64_TPREL16_HIGHER
3084 BFD_RELOC_PPC64_TPREL16_HIGHERA
3086 BFD_RELOC_PPC64_TPREL16_HIGHEST
3088 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3090 BFD_RELOC_PPC64_DTPREL16_DS
3092 BFD_RELOC_PPC64_DTPREL16_LO_DS
3094 BFD_RELOC_PPC64_DTPREL16_HIGHER
3096 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3098 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3100 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3102 BFD_RELOC_PPC64_TPREL16_HIGH
3104 BFD_RELOC_PPC64_TPREL16_HIGHA
3106 BFD_RELOC_PPC64_DTPREL16_HIGH
3108 BFD_RELOC_PPC64_DTPREL16_HIGHA
3110 PowerPC and PowerPC64 thread-local storage relocations.
3115 IBM 370/390 relocations
3120 The type of reloc used to build a constructor table - at the moment
3121 probably a 32 bit wide absolute relocation, but the target can choose.
3122 It generally does map to one of the other relocation types.
3125 BFD_RELOC_ARM_PCREL_BRANCH
3127 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3128 not stored in the instruction.
3130 BFD_RELOC_ARM_PCREL_BLX
3132 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3133 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3134 field in the instruction.
3136 BFD_RELOC_THUMB_PCREL_BLX
3138 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3139 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3140 field in the instruction.
3142 BFD_RELOC_ARM_PCREL_CALL
3144 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3146 BFD_RELOC_ARM_PCREL_JUMP
3148 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3151 BFD_RELOC_THUMB_PCREL_BRANCH7
3153 BFD_RELOC_THUMB_PCREL_BRANCH9
3155 BFD_RELOC_THUMB_PCREL_BRANCH12
3157 BFD_RELOC_THUMB_PCREL_BRANCH20
3159 BFD_RELOC_THUMB_PCREL_BRANCH23
3161 BFD_RELOC_THUMB_PCREL_BRANCH25
3163 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3164 The lowest bit must be zero and is not stored in the instruction.
3165 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3166 "nn" one smaller in all cases. Note further that BRANCH23
3167 corresponds to R_ARM_THM_CALL.
3170 BFD_RELOC_ARM_OFFSET_IMM
3172 12-bit immediate offset, used in ARM-format ldr and str instructions.
3175 BFD_RELOC_ARM_THUMB_OFFSET
3177 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3180 BFD_RELOC_ARM_TARGET1
3182 Pc-relative or absolute relocation depending on target. Used for
3183 entries in .init_array sections.
3185 BFD_RELOC_ARM_ROSEGREL32
3187 Read-only segment base relative address.
3189 BFD_RELOC_ARM_SBREL32
3191 Data segment base relative address.
3193 BFD_RELOC_ARM_TARGET2
3195 This reloc is used for references to RTTI data from exception handling
3196 tables. The actual definition depends on the target. It may be a
3197 pc-relative or some form of GOT-indirect relocation.
3199 BFD_RELOC_ARM_PREL31
3201 31-bit PC relative address.
3207 BFD_RELOC_ARM_MOVW_PCREL
3209 BFD_RELOC_ARM_MOVT_PCREL
3211 BFD_RELOC_ARM_THUMB_MOVW
3213 BFD_RELOC_ARM_THUMB_MOVT
3215 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3217 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3219 Low and High halfword relocations for MOVW and MOVT instructions.
3222 BFD_RELOC_ARM_GOTFUNCDESC
3224 BFD_RELOC_ARM_GOTOFFFUNCDESC
3226 BFD_RELOC_ARM_FUNCDESC
3228 BFD_RELOC_ARM_FUNCDESC_VALUE
3230 BFD_RELOC_ARM_TLS_GD32_FDPIC
3232 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3234 BFD_RELOC_ARM_TLS_IE32_FDPIC
3236 ARM FDPIC specific relocations.
3239 BFD_RELOC_ARM_JUMP_SLOT
3241 BFD_RELOC_ARM_GLOB_DAT
3247 BFD_RELOC_ARM_RELATIVE
3249 BFD_RELOC_ARM_GOTOFF
3253 BFD_RELOC_ARM_GOT_PREL
3255 Relocations for setting up GOTs and PLTs for shared libraries.
3258 BFD_RELOC_ARM_TLS_GD32
3260 BFD_RELOC_ARM_TLS_LDO32
3262 BFD_RELOC_ARM_TLS_LDM32
3264 BFD_RELOC_ARM_TLS_DTPOFF32
3266 BFD_RELOC_ARM_TLS_DTPMOD32
3268 BFD_RELOC_ARM_TLS_TPOFF32
3270 BFD_RELOC_ARM_TLS_IE32
3272 BFD_RELOC_ARM_TLS_LE32
3274 BFD_RELOC_ARM_TLS_GOTDESC
3276 BFD_RELOC_ARM_TLS_CALL
3278 BFD_RELOC_ARM_THM_TLS_CALL
3280 BFD_RELOC_ARM_TLS_DESCSEQ
3282 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3284 BFD_RELOC_ARM_TLS_DESC
3286 ARM thread-local storage relocations.
3289 BFD_RELOC_ARM_ALU_PC_G0_NC
3291 BFD_RELOC_ARM_ALU_PC_G0
3293 BFD_RELOC_ARM_ALU_PC_G1_NC
3295 BFD_RELOC_ARM_ALU_PC_G1
3297 BFD_RELOC_ARM_ALU_PC_G2
3299 BFD_RELOC_ARM_LDR_PC_G0
3301 BFD_RELOC_ARM_LDR_PC_G1
3303 BFD_RELOC_ARM_LDR_PC_G2
3305 BFD_RELOC_ARM_LDRS_PC_G0
3307 BFD_RELOC_ARM_LDRS_PC_G1
3309 BFD_RELOC_ARM_LDRS_PC_G2
3311 BFD_RELOC_ARM_LDC_PC_G0
3313 BFD_RELOC_ARM_LDC_PC_G1
3315 BFD_RELOC_ARM_LDC_PC_G2
3317 BFD_RELOC_ARM_ALU_SB_G0_NC
3319 BFD_RELOC_ARM_ALU_SB_G0
3321 BFD_RELOC_ARM_ALU_SB_G1_NC
3323 BFD_RELOC_ARM_ALU_SB_G1
3325 BFD_RELOC_ARM_ALU_SB_G2
3327 BFD_RELOC_ARM_LDR_SB_G0
3329 BFD_RELOC_ARM_LDR_SB_G1
3331 BFD_RELOC_ARM_LDR_SB_G2
3333 BFD_RELOC_ARM_LDRS_SB_G0
3335 BFD_RELOC_ARM_LDRS_SB_G1
3337 BFD_RELOC_ARM_LDRS_SB_G2
3339 BFD_RELOC_ARM_LDC_SB_G0
3341 BFD_RELOC_ARM_LDC_SB_G1
3343 BFD_RELOC_ARM_LDC_SB_G2
3345 ARM group relocations.
3350 Annotation of BX instructions.
3353 BFD_RELOC_ARM_IRELATIVE
3355 ARM support for STT_GNU_IFUNC.
3358 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3360 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3362 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3364 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3366 Thumb1 relocations to support execute-only code.
3369 BFD_RELOC_ARM_IMMEDIATE
3371 BFD_RELOC_ARM_ADRL_IMMEDIATE
3373 BFD_RELOC_ARM_T32_IMMEDIATE
3375 BFD_RELOC_ARM_T32_ADD_IMM
3377 BFD_RELOC_ARM_T32_IMM12
3379 BFD_RELOC_ARM_T32_ADD_PC12
3381 BFD_RELOC_ARM_SHIFT_IMM
3391 BFD_RELOC_ARM_CP_OFF_IMM
3393 BFD_RELOC_ARM_CP_OFF_IMM_S2
3395 BFD_RELOC_ARM_T32_CP_OFF_IMM
3397 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3399 BFD_RELOC_ARM_ADR_IMM
3401 BFD_RELOC_ARM_LDR_IMM
3403 BFD_RELOC_ARM_LITERAL
3405 BFD_RELOC_ARM_IN_POOL
3407 BFD_RELOC_ARM_OFFSET_IMM8
3409 BFD_RELOC_ARM_T32_OFFSET_U8
3411 BFD_RELOC_ARM_T32_OFFSET_IMM
3413 BFD_RELOC_ARM_HWLITERAL
3415 BFD_RELOC_ARM_THUMB_ADD
3417 BFD_RELOC_ARM_THUMB_IMM
3419 BFD_RELOC_ARM_THUMB_SHIFT
3421 These relocs are only used within the ARM assembler. They are not
3422 (at present) written to any object files.
3425 BFD_RELOC_SH_PCDISP8BY2
3427 BFD_RELOC_SH_PCDISP12BY2
3435 BFD_RELOC_SH_DISP12BY2
3437 BFD_RELOC_SH_DISP12BY4
3439 BFD_RELOC_SH_DISP12BY8
3443 BFD_RELOC_SH_DISP20BY8
3447 BFD_RELOC_SH_IMM4BY2
3449 BFD_RELOC_SH_IMM4BY4
3453 BFD_RELOC_SH_IMM8BY2
3455 BFD_RELOC_SH_IMM8BY4
3457 BFD_RELOC_SH_PCRELIMM8BY2
3459 BFD_RELOC_SH_PCRELIMM8BY4
3461 BFD_RELOC_SH_SWITCH16
3463 BFD_RELOC_SH_SWITCH32
3477 BFD_RELOC_SH_LOOP_START
3479 BFD_RELOC_SH_LOOP_END
3483 BFD_RELOC_SH_GLOB_DAT
3485 BFD_RELOC_SH_JMP_SLOT
3487 BFD_RELOC_SH_RELATIVE
3491 BFD_RELOC_SH_GOT_LOW16
3493 BFD_RELOC_SH_GOT_MEDLOW16
3495 BFD_RELOC_SH_GOT_MEDHI16
3497 BFD_RELOC_SH_GOT_HI16
3499 BFD_RELOC_SH_GOTPLT_LOW16
3501 BFD_RELOC_SH_GOTPLT_MEDLOW16
3503 BFD_RELOC_SH_GOTPLT_MEDHI16
3505 BFD_RELOC_SH_GOTPLT_HI16
3507 BFD_RELOC_SH_PLT_LOW16
3509 BFD_RELOC_SH_PLT_MEDLOW16
3511 BFD_RELOC_SH_PLT_MEDHI16
3513 BFD_RELOC_SH_PLT_HI16
3515 BFD_RELOC_SH_GOTOFF_LOW16
3517 BFD_RELOC_SH_GOTOFF_MEDLOW16
3519 BFD_RELOC_SH_GOTOFF_MEDHI16
3521 BFD_RELOC_SH_GOTOFF_HI16
3523 BFD_RELOC_SH_GOTPC_LOW16
3525 BFD_RELOC_SH_GOTPC_MEDLOW16
3527 BFD_RELOC_SH_GOTPC_MEDHI16
3529 BFD_RELOC_SH_GOTPC_HI16
3533 BFD_RELOC_SH_GLOB_DAT64
3535 BFD_RELOC_SH_JMP_SLOT64
3537 BFD_RELOC_SH_RELATIVE64
3539 BFD_RELOC_SH_GOT10BY4
3541 BFD_RELOC_SH_GOT10BY8
3543 BFD_RELOC_SH_GOTPLT10BY4
3545 BFD_RELOC_SH_GOTPLT10BY8
3547 BFD_RELOC_SH_GOTPLT32
3549 BFD_RELOC_SH_SHMEDIA_CODE
3555 BFD_RELOC_SH_IMMS6BY32
3561 BFD_RELOC_SH_IMMS10BY2
3563 BFD_RELOC_SH_IMMS10BY4
3565 BFD_RELOC_SH_IMMS10BY8
3571 BFD_RELOC_SH_IMM_LOW16
3573 BFD_RELOC_SH_IMM_LOW16_PCREL
3575 BFD_RELOC_SH_IMM_MEDLOW16
3577 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3579 BFD_RELOC_SH_IMM_MEDHI16
3581 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3583 BFD_RELOC_SH_IMM_HI16
3585 BFD_RELOC_SH_IMM_HI16_PCREL
3589 BFD_RELOC_SH_TLS_GD_32
3591 BFD_RELOC_SH_TLS_LD_32
3593 BFD_RELOC_SH_TLS_LDO_32
3595 BFD_RELOC_SH_TLS_IE_32
3597 BFD_RELOC_SH_TLS_LE_32
3599 BFD_RELOC_SH_TLS_DTPMOD32
3601 BFD_RELOC_SH_TLS_DTPOFF32
3603 BFD_RELOC_SH_TLS_TPOFF32
3607 BFD_RELOC_SH_GOTOFF20
3609 BFD_RELOC_SH_GOTFUNCDESC
3611 BFD_RELOC_SH_GOTFUNCDESC20
3613 BFD_RELOC_SH_GOTOFFFUNCDESC
3615 BFD_RELOC_SH_GOTOFFFUNCDESC20
3617 BFD_RELOC_SH_FUNCDESC
3619 Renesas / SuperH SH relocs. Not all of these appear in object files.
3642 BFD_RELOC_ARC_SECTOFF
3644 BFD_RELOC_ARC_S21H_PCREL
3646 BFD_RELOC_ARC_S21W_PCREL
3648 BFD_RELOC_ARC_S25H_PCREL
3650 BFD_RELOC_ARC_S25W_PCREL
3654 BFD_RELOC_ARC_SDA_LDST
3656 BFD_RELOC_ARC_SDA_LDST1
3658 BFD_RELOC_ARC_SDA_LDST2
3660 BFD_RELOC_ARC_SDA16_LD
3662 BFD_RELOC_ARC_SDA16_LD1
3664 BFD_RELOC_ARC_SDA16_LD2
3666 BFD_RELOC_ARC_S13_PCREL
3672 BFD_RELOC_ARC_32_ME_S
3674 BFD_RELOC_ARC_N32_ME
3676 BFD_RELOC_ARC_SECTOFF_ME
3678 BFD_RELOC_ARC_SDA32_ME
3682 BFD_RELOC_AC_SECTOFF_U8
3684 BFD_RELOC_AC_SECTOFF_U8_1
3686 BFD_RELOC_AC_SECTOFF_U8_2
3688 BFD_RELOC_AC_SECTOFF_S9
3690 BFD_RELOC_AC_SECTOFF_S9_1
3692 BFD_RELOC_AC_SECTOFF_S9_2
3694 BFD_RELOC_ARC_SECTOFF_ME_1
3696 BFD_RELOC_ARC_SECTOFF_ME_2
3698 BFD_RELOC_ARC_SECTOFF_1
3700 BFD_RELOC_ARC_SECTOFF_2
3702 BFD_RELOC_ARC_SDA_12
3704 BFD_RELOC_ARC_SDA16_ST2
3706 BFD_RELOC_ARC_32_PCREL
3712 BFD_RELOC_ARC_GOTPC32
3718 BFD_RELOC_ARC_GLOB_DAT
3720 BFD_RELOC_ARC_JMP_SLOT
3722 BFD_RELOC_ARC_RELATIVE
3724 BFD_RELOC_ARC_GOTOFF
3728 BFD_RELOC_ARC_S21W_PCREL_PLT
3730 BFD_RELOC_ARC_S25H_PCREL_PLT
3732 BFD_RELOC_ARC_TLS_DTPMOD
3734 BFD_RELOC_ARC_TLS_TPOFF
3736 BFD_RELOC_ARC_TLS_GD_GOT
3738 BFD_RELOC_ARC_TLS_GD_LD
3740 BFD_RELOC_ARC_TLS_GD_CALL
3742 BFD_RELOC_ARC_TLS_IE_GOT
3744 BFD_RELOC_ARC_TLS_DTPOFF
3746 BFD_RELOC_ARC_TLS_DTPOFF_S9
3748 BFD_RELOC_ARC_TLS_LE_S9
3750 BFD_RELOC_ARC_TLS_LE_32
3752 BFD_RELOC_ARC_S25W_PCREL_PLT
3754 BFD_RELOC_ARC_S21H_PCREL_PLT
3756 BFD_RELOC_ARC_NPS_CMEM16
3758 BFD_RELOC_ARC_JLI_SECTOFF
3763 BFD_RELOC_BFIN_16_IMM
3765 ADI Blackfin 16 bit immediate absolute reloc.
3767 BFD_RELOC_BFIN_16_HIGH
3769 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3771 BFD_RELOC_BFIN_4_PCREL
3773 ADI Blackfin 'a' part of LSETUP.
3775 BFD_RELOC_BFIN_5_PCREL
3779 BFD_RELOC_BFIN_16_LOW
3781 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3783 BFD_RELOC_BFIN_10_PCREL
3787 BFD_RELOC_BFIN_11_PCREL
3789 ADI Blackfin 'b' part of LSETUP.
3791 BFD_RELOC_BFIN_12_PCREL_JUMP
3795 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3797 ADI Blackfin Short jump, pcrel.
3799 BFD_RELOC_BFIN_24_PCREL_CALL_X
3801 ADI Blackfin Call.x not implemented.
3803 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3805 ADI Blackfin Long Jump pcrel.
3807 BFD_RELOC_BFIN_GOT17M4
3809 BFD_RELOC_BFIN_GOTHI
3811 BFD_RELOC_BFIN_GOTLO
3813 BFD_RELOC_BFIN_FUNCDESC
3815 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3817 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3819 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3821 BFD_RELOC_BFIN_FUNCDESC_VALUE
3823 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3825 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3827 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3829 BFD_RELOC_BFIN_GOTOFF17M4
3831 BFD_RELOC_BFIN_GOTOFFHI
3833 BFD_RELOC_BFIN_GOTOFFLO
3835 ADI Blackfin FD-PIC relocations.
3839 ADI Blackfin GOT relocation.
3841 BFD_RELOC_BFIN_PLTPC
3843 ADI Blackfin PLTPC relocation.
3845 BFD_ARELOC_BFIN_PUSH
3847 ADI Blackfin arithmetic relocation.
3849 BFD_ARELOC_BFIN_CONST
3851 ADI Blackfin arithmetic relocation.
3855 ADI Blackfin arithmetic relocation.
3859 ADI Blackfin arithmetic relocation.
3861 BFD_ARELOC_BFIN_MULT
3863 ADI Blackfin arithmetic relocation.
3867 ADI Blackfin arithmetic relocation.
3871 ADI Blackfin arithmetic relocation.
3873 BFD_ARELOC_BFIN_LSHIFT
3875 ADI Blackfin arithmetic relocation.
3877 BFD_ARELOC_BFIN_RSHIFT
3879 ADI Blackfin arithmetic relocation.
3883 ADI Blackfin arithmetic relocation.
3887 ADI Blackfin arithmetic relocation.
3891 ADI Blackfin arithmetic relocation.
3893 BFD_ARELOC_BFIN_LAND
3895 ADI Blackfin arithmetic relocation.
3899 ADI Blackfin arithmetic relocation.
3903 ADI Blackfin arithmetic relocation.
3907 ADI Blackfin arithmetic relocation.
3909 BFD_ARELOC_BFIN_COMP
3911 ADI Blackfin arithmetic relocation.
3913 BFD_ARELOC_BFIN_PAGE
3915 ADI Blackfin arithmetic relocation.
3917 BFD_ARELOC_BFIN_HWPAGE
3919 ADI Blackfin arithmetic relocation.
3921 BFD_ARELOC_BFIN_ADDR
3923 ADI Blackfin arithmetic relocation.
3926 BFD_RELOC_D10V_10_PCREL_R
3928 Mitsubishi D10V relocs.
3929 This is a 10-bit reloc with the right 2 bits
3932 BFD_RELOC_D10V_10_PCREL_L
3934 Mitsubishi D10V relocs.
3935 This is a 10-bit reloc with the right 2 bits
3936 assumed to be 0. This is the same as the previous reloc
3937 except it is in the left container, i.e.,
3938 shifted left 15 bits.
3942 This is an 18-bit reloc with the right 2 bits
3945 BFD_RELOC_D10V_18_PCREL
3947 This is an 18-bit reloc with the right 2 bits
3953 Mitsubishi D30V relocs.
3954 This is a 6-bit absolute reloc.
3956 BFD_RELOC_D30V_9_PCREL
3958 This is a 6-bit pc-relative reloc with
3959 the right 3 bits assumed to be 0.
3961 BFD_RELOC_D30V_9_PCREL_R
3963 This is a 6-bit pc-relative reloc with
3964 the right 3 bits assumed to be 0. Same
3965 as the previous reloc but on the right side
3970 This is a 12-bit absolute reloc with the
3971 right 3 bitsassumed to be 0.
3973 BFD_RELOC_D30V_15_PCREL
3975 This is a 12-bit pc-relative reloc with
3976 the right 3 bits assumed to be 0.
3978 BFD_RELOC_D30V_15_PCREL_R
3980 This is a 12-bit pc-relative reloc with
3981 the right 3 bits assumed to be 0. Same
3982 as the previous reloc but on the right side
3987 This is an 18-bit absolute reloc with
3988 the right 3 bits assumed to be 0.
3990 BFD_RELOC_D30V_21_PCREL
3992 This is an 18-bit pc-relative reloc with
3993 the right 3 bits assumed to be 0.
3995 BFD_RELOC_D30V_21_PCREL_R
3997 This is an 18-bit pc-relative reloc with
3998 the right 3 bits assumed to be 0. Same
3999 as the previous reloc but on the right side
4004 This is a 32-bit absolute reloc.
4006 BFD_RELOC_D30V_32_PCREL
4008 This is a 32-bit pc-relative reloc.
4011 BFD_RELOC_DLX_HI16_S
4026 BFD_RELOC_M32C_RL_JUMP
4028 BFD_RELOC_M32C_RL_1ADDR
4030 BFD_RELOC_M32C_RL_2ADDR
4032 Renesas M16C/M32C Relocations.
4037 Renesas M32R (formerly Mitsubishi M32R) relocs.
4038 This is a 24 bit absolute address.
4040 BFD_RELOC_M32R_10_PCREL
4042 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4044 BFD_RELOC_M32R_18_PCREL
4046 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4048 BFD_RELOC_M32R_26_PCREL
4050 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4052 BFD_RELOC_M32R_HI16_ULO
4054 This is a 16-bit reloc containing the high 16 bits of an address
4055 used when the lower 16 bits are treated as unsigned.
4057 BFD_RELOC_M32R_HI16_SLO
4059 This is a 16-bit reloc containing the high 16 bits of an address
4060 used when the lower 16 bits are treated as signed.
4064 This is a 16-bit reloc containing the lower 16 bits of an address.
4066 BFD_RELOC_M32R_SDA16
4068 This is a 16-bit reloc containing the small data area offset for use in
4069 add3, load, and store instructions.
4071 BFD_RELOC_M32R_GOT24
4073 BFD_RELOC_M32R_26_PLTREL
4077 BFD_RELOC_M32R_GLOB_DAT
4079 BFD_RELOC_M32R_JMP_SLOT
4081 BFD_RELOC_M32R_RELATIVE
4083 BFD_RELOC_M32R_GOTOFF
4085 BFD_RELOC_M32R_GOTOFF_HI_ULO
4087 BFD_RELOC_M32R_GOTOFF_HI_SLO
4089 BFD_RELOC_M32R_GOTOFF_LO
4091 BFD_RELOC_M32R_GOTPC24
4093 BFD_RELOC_M32R_GOT16_HI_ULO
4095 BFD_RELOC_M32R_GOT16_HI_SLO
4097 BFD_RELOC_M32R_GOT16_LO
4099 BFD_RELOC_M32R_GOTPC_HI_ULO
4101 BFD_RELOC_M32R_GOTPC_HI_SLO
4103 BFD_RELOC_M32R_GOTPC_LO
4112 This is a 20 bit absolute address.
4114 BFD_RELOC_NDS32_9_PCREL
4116 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4118 BFD_RELOC_NDS32_WORD_9_PCREL
4120 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4122 BFD_RELOC_NDS32_15_PCREL
4124 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4126 BFD_RELOC_NDS32_17_PCREL
4128 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4130 BFD_RELOC_NDS32_25_PCREL
4132 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4134 BFD_RELOC_NDS32_HI20
4136 This is a 20-bit reloc containing the high 20 bits of an address
4137 used with the lower 12 bits
4139 BFD_RELOC_NDS32_LO12S3
4141 This is a 12-bit reloc containing the lower 12 bits of an address
4142 then shift right by 3. This is used with ldi,sdi...
4144 BFD_RELOC_NDS32_LO12S2
4146 This is a 12-bit reloc containing the lower 12 bits of an address
4147 then shift left by 2. This is used with lwi,swi...
4149 BFD_RELOC_NDS32_LO12S1
4151 This is a 12-bit reloc containing the lower 12 bits of an address
4152 then shift left by 1. This is used with lhi,shi...
4154 BFD_RELOC_NDS32_LO12S0
4156 This is a 12-bit reloc containing the lower 12 bits of an address
4157 then shift left by 0. This is used with lbisbi...
4159 BFD_RELOC_NDS32_LO12S0_ORI
4161 This is a 12-bit reloc containing the lower 12 bits of an address
4162 then shift left by 0. This is only used with branch relaxations
4164 BFD_RELOC_NDS32_SDA15S3
4166 This is a 15-bit reloc containing the small data area 18-bit signed offset
4167 and shift left by 3 for use in ldi, sdi...
4169 BFD_RELOC_NDS32_SDA15S2
4171 This is a 15-bit reloc containing the small data area 17-bit signed offset
4172 and shift left by 2 for use in lwi, swi...
4174 BFD_RELOC_NDS32_SDA15S1
4176 This is a 15-bit reloc containing the small data area 16-bit signed offset
4177 and shift left by 1 for use in lhi, shi...
4179 BFD_RELOC_NDS32_SDA15S0
4181 This is a 15-bit reloc containing the small data area 15-bit signed offset
4182 and shift left by 0 for use in lbi, sbi...
4184 BFD_RELOC_NDS32_SDA16S3
4186 This is a 16-bit reloc containing the small data area 16-bit signed offset
4189 BFD_RELOC_NDS32_SDA17S2
4191 This is a 17-bit reloc containing the small data area 17-bit signed offset
4192 and shift left by 2 for use in lwi.gp, swi.gp...
4194 BFD_RELOC_NDS32_SDA18S1
4196 This is a 18-bit reloc containing the small data area 18-bit signed offset
4197 and shift left by 1 for use in lhi.gp, shi.gp...
4199 BFD_RELOC_NDS32_SDA19S0
4201 This is a 19-bit reloc containing the small data area 19-bit signed offset
4202 and shift left by 0 for use in lbi.gp, sbi.gp...
4204 BFD_RELOC_NDS32_GOT20
4206 BFD_RELOC_NDS32_9_PLTREL
4208 BFD_RELOC_NDS32_25_PLTREL
4210 BFD_RELOC_NDS32_COPY
4212 BFD_RELOC_NDS32_GLOB_DAT
4214 BFD_RELOC_NDS32_JMP_SLOT
4216 BFD_RELOC_NDS32_RELATIVE
4218 BFD_RELOC_NDS32_GOTOFF
4220 BFD_RELOC_NDS32_GOTOFF_HI20
4222 BFD_RELOC_NDS32_GOTOFF_LO12
4224 BFD_RELOC_NDS32_GOTPC20
4226 BFD_RELOC_NDS32_GOT_HI20
4228 BFD_RELOC_NDS32_GOT_LO12
4230 BFD_RELOC_NDS32_GOTPC_HI20
4232 BFD_RELOC_NDS32_GOTPC_LO12
4236 BFD_RELOC_NDS32_INSN16
4238 BFD_RELOC_NDS32_LABEL
4240 BFD_RELOC_NDS32_LONGCALL1
4242 BFD_RELOC_NDS32_LONGCALL2
4244 BFD_RELOC_NDS32_LONGCALL3
4246 BFD_RELOC_NDS32_LONGJUMP1
4248 BFD_RELOC_NDS32_LONGJUMP2
4250 BFD_RELOC_NDS32_LONGJUMP3
4252 BFD_RELOC_NDS32_LOADSTORE
4254 BFD_RELOC_NDS32_9_FIXED
4256 BFD_RELOC_NDS32_15_FIXED
4258 BFD_RELOC_NDS32_17_FIXED
4260 BFD_RELOC_NDS32_25_FIXED
4262 BFD_RELOC_NDS32_LONGCALL4
4264 BFD_RELOC_NDS32_LONGCALL5
4266 BFD_RELOC_NDS32_LONGCALL6
4268 BFD_RELOC_NDS32_LONGJUMP4
4270 BFD_RELOC_NDS32_LONGJUMP5
4272 BFD_RELOC_NDS32_LONGJUMP6
4274 BFD_RELOC_NDS32_LONGJUMP7
4278 BFD_RELOC_NDS32_PLTREL_HI20
4280 BFD_RELOC_NDS32_PLTREL_LO12
4282 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4284 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4288 BFD_RELOC_NDS32_SDA12S2_DP
4290 BFD_RELOC_NDS32_SDA12S2_SP
4292 BFD_RELOC_NDS32_LO12S2_DP
4294 BFD_RELOC_NDS32_LO12S2_SP
4298 BFD_RELOC_NDS32_DWARF2_OP1
4300 BFD_RELOC_NDS32_DWARF2_OP2
4302 BFD_RELOC_NDS32_DWARF2_LEB
4304 for dwarf2 debug_line.
4306 BFD_RELOC_NDS32_UPDATE_TA
4308 for eliminate 16-bit instructions
4310 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4312 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4314 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4316 BFD_RELOC_NDS32_GOT_LO15
4318 BFD_RELOC_NDS32_GOT_LO19
4320 BFD_RELOC_NDS32_GOTOFF_LO15
4322 BFD_RELOC_NDS32_GOTOFF_LO19
4324 BFD_RELOC_NDS32_GOT15S2
4326 BFD_RELOC_NDS32_GOT17S2
4328 for PIC object relaxation
4333 This is a 5 bit absolute address.
4335 BFD_RELOC_NDS32_10_UPCREL
4337 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4339 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4341 If fp were omitted, fp can used as another gp.
4343 BFD_RELOC_NDS32_RELAX_ENTRY
4345 BFD_RELOC_NDS32_GOT_SUFF
4347 BFD_RELOC_NDS32_GOTOFF_SUFF
4349 BFD_RELOC_NDS32_PLT_GOT_SUFF
4351 BFD_RELOC_NDS32_MULCALL_SUFF
4355 BFD_RELOC_NDS32_PTR_COUNT
4357 BFD_RELOC_NDS32_PTR_RESOLVED
4359 BFD_RELOC_NDS32_PLTBLOCK
4361 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4363 BFD_RELOC_NDS32_RELAX_REGION_END
4365 BFD_RELOC_NDS32_MINUEND
4367 BFD_RELOC_NDS32_SUBTRAHEND
4369 BFD_RELOC_NDS32_DIFF8
4371 BFD_RELOC_NDS32_DIFF16
4373 BFD_RELOC_NDS32_DIFF32
4375 BFD_RELOC_NDS32_DIFF_ULEB128
4377 BFD_RELOC_NDS32_EMPTY
4379 relaxation relative relocation types
4381 BFD_RELOC_NDS32_25_ABS
4383 This is a 25 bit absolute address.
4385 BFD_RELOC_NDS32_DATA
4387 BFD_RELOC_NDS32_TRAN
4389 BFD_RELOC_NDS32_17IFC_PCREL
4391 BFD_RELOC_NDS32_10IFCU_PCREL
4393 For ex9 and ifc using.
4395 BFD_RELOC_NDS32_TPOFF
4397 BFD_RELOC_NDS32_TLS_LE_HI20
4399 BFD_RELOC_NDS32_TLS_LE_LO12
4401 BFD_RELOC_NDS32_TLS_LE_ADD
4403 BFD_RELOC_NDS32_TLS_LE_LS
4405 BFD_RELOC_NDS32_GOTTPOFF
4407 BFD_RELOC_NDS32_TLS_IE_HI20
4409 BFD_RELOC_NDS32_TLS_IE_LO12S2
4411 BFD_RELOC_NDS32_TLS_TPOFF
4413 BFD_RELOC_NDS32_TLS_LE_20
4415 BFD_RELOC_NDS32_TLS_LE_15S0
4417 BFD_RELOC_NDS32_TLS_LE_15S1
4419 BFD_RELOC_NDS32_TLS_LE_15S2
4425 BFD_RELOC_V850_9_PCREL
4427 This is a 9-bit reloc
4429 BFD_RELOC_V850_22_PCREL
4431 This is a 22-bit reloc
4434 BFD_RELOC_V850_SDA_16_16_OFFSET
4436 This is a 16 bit offset from the short data area pointer.
4438 BFD_RELOC_V850_SDA_15_16_OFFSET
4440 This is a 16 bit offset (of which only 15 bits are used) from the
4441 short data area pointer.
4443 BFD_RELOC_V850_ZDA_16_16_OFFSET
4445 This is a 16 bit offset from the zero data area pointer.
4447 BFD_RELOC_V850_ZDA_15_16_OFFSET
4449 This is a 16 bit offset (of which only 15 bits are used) from the
4450 zero data area pointer.
4452 BFD_RELOC_V850_TDA_6_8_OFFSET
4454 This is an 8 bit offset (of which only 6 bits are used) from the
4455 tiny data area pointer.
4457 BFD_RELOC_V850_TDA_7_8_OFFSET
4459 This is an 8bit offset (of which only 7 bits are used) from the tiny
4462 BFD_RELOC_V850_TDA_7_7_OFFSET
4464 This is a 7 bit offset from the tiny data area pointer.
4466 BFD_RELOC_V850_TDA_16_16_OFFSET
4468 This is a 16 bit offset from the tiny data area pointer.
4471 BFD_RELOC_V850_TDA_4_5_OFFSET
4473 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4476 BFD_RELOC_V850_TDA_4_4_OFFSET
4478 This is a 4 bit offset from the tiny data area pointer.
4480 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4482 This is a 16 bit offset from the short data area pointer, with the
4483 bits placed non-contiguously in the instruction.
4485 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4487 This is a 16 bit offset from the zero data area pointer, with the
4488 bits placed non-contiguously in the instruction.
4490 BFD_RELOC_V850_CALLT_6_7_OFFSET
4492 This is a 6 bit offset from the call table base pointer.
4494 BFD_RELOC_V850_CALLT_16_16_OFFSET
4496 This is a 16 bit offset from the call table base pointer.
4498 BFD_RELOC_V850_LONGCALL
4500 Used for relaxing indirect function calls.
4502 BFD_RELOC_V850_LONGJUMP
4504 Used for relaxing indirect jumps.
4506 BFD_RELOC_V850_ALIGN
4508 Used to maintain alignment whilst relaxing.
4510 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4512 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4515 BFD_RELOC_V850_16_PCREL
4517 This is a 16-bit reloc.
4519 BFD_RELOC_V850_17_PCREL
4521 This is a 17-bit reloc.
4525 This is a 23-bit reloc.
4527 BFD_RELOC_V850_32_PCREL
4529 This is a 32-bit reloc.
4531 BFD_RELOC_V850_32_ABS
4533 This is a 32-bit reloc.
4535 BFD_RELOC_V850_16_SPLIT_OFFSET
4537 This is a 16-bit reloc.
4539 BFD_RELOC_V850_16_S1
4541 This is a 16-bit reloc.
4543 BFD_RELOC_V850_LO16_S1
4545 Low 16 bits. 16 bit shifted by 1.
4547 BFD_RELOC_V850_CALLT_15_16_OFFSET
4549 This is a 16 bit offset from the call table base pointer.
4551 BFD_RELOC_V850_32_GOTPCREL
4555 BFD_RELOC_V850_16_GOT
4559 BFD_RELOC_V850_32_GOT
4563 BFD_RELOC_V850_22_PLT_PCREL
4567 BFD_RELOC_V850_32_PLT_PCREL
4575 BFD_RELOC_V850_GLOB_DAT
4579 BFD_RELOC_V850_JMP_SLOT
4583 BFD_RELOC_V850_RELATIVE
4587 BFD_RELOC_V850_16_GOTOFF
4591 BFD_RELOC_V850_32_GOTOFF
4606 This is a 8bit DP reloc for the tms320c30, where the most
4607 significant 8 bits of a 24 bit word are placed into the least
4608 significant 8 bits of the opcode.
4611 BFD_RELOC_TIC54X_PARTLS7
4613 This is a 7bit reloc for the tms320c54x, where the least
4614 significant 7 bits of a 16 bit word are placed into the least
4615 significant 7 bits of the opcode.
4618 BFD_RELOC_TIC54X_PARTMS9
4620 This is a 9bit DP reloc for the tms320c54x, where the most
4621 significant 9 bits of a 16 bit word are placed into the least
4622 significant 9 bits of the opcode.
4627 This is an extended address 23-bit reloc for the tms320c54x.
4630 BFD_RELOC_TIC54X_16_OF_23
4632 This is a 16-bit reloc for the tms320c54x, where the least
4633 significant 16 bits of a 23-bit extended address are placed into
4637 BFD_RELOC_TIC54X_MS7_OF_23
4639 This is a reloc for the tms320c54x, where the most
4640 significant 7 bits of a 23-bit extended address are placed into
4644 BFD_RELOC_C6000_PCR_S21
4646 BFD_RELOC_C6000_PCR_S12
4648 BFD_RELOC_C6000_PCR_S10
4650 BFD_RELOC_C6000_PCR_S7
4652 BFD_RELOC_C6000_ABS_S16
4654 BFD_RELOC_C6000_ABS_L16
4656 BFD_RELOC_C6000_ABS_H16
4658 BFD_RELOC_C6000_SBR_U15_B
4660 BFD_RELOC_C6000_SBR_U15_H
4662 BFD_RELOC_C6000_SBR_U15_W
4664 BFD_RELOC_C6000_SBR_S16
4666 BFD_RELOC_C6000_SBR_L16_B
4668 BFD_RELOC_C6000_SBR_L16_H
4670 BFD_RELOC_C6000_SBR_L16_W
4672 BFD_RELOC_C6000_SBR_H16_B
4674 BFD_RELOC_C6000_SBR_H16_H
4676 BFD_RELOC_C6000_SBR_H16_W
4678 BFD_RELOC_C6000_SBR_GOT_U15_W
4680 BFD_RELOC_C6000_SBR_GOT_L16_W
4682 BFD_RELOC_C6000_SBR_GOT_H16_W
4684 BFD_RELOC_C6000_DSBT_INDEX
4686 BFD_RELOC_C6000_PREL31
4688 BFD_RELOC_C6000_COPY
4690 BFD_RELOC_C6000_JUMP_SLOT
4692 BFD_RELOC_C6000_EHTYPE
4694 BFD_RELOC_C6000_PCR_H16
4696 BFD_RELOC_C6000_PCR_L16
4698 BFD_RELOC_C6000_ALIGN
4700 BFD_RELOC_C6000_FPHEAD
4702 BFD_RELOC_C6000_NOCMP
4704 TMS320C6000 relocations.
4709 This is a 48 bit reloc for the FR30 that stores 32 bits.
4713 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4716 BFD_RELOC_FR30_6_IN_4
4718 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4721 BFD_RELOC_FR30_8_IN_8
4723 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4726 BFD_RELOC_FR30_9_IN_8
4728 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4731 BFD_RELOC_FR30_10_IN_8
4733 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4736 BFD_RELOC_FR30_9_PCREL
4738 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4739 short offset into 8 bits.
4741 BFD_RELOC_FR30_12_PCREL
4743 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4744 short offset into 11 bits.
4747 BFD_RELOC_MCORE_PCREL_IMM8BY4
4749 BFD_RELOC_MCORE_PCREL_IMM11BY2
4751 BFD_RELOC_MCORE_PCREL_IMM4BY2
4753 BFD_RELOC_MCORE_PCREL_32
4755 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4759 Motorola Mcore relocations.
4768 BFD_RELOC_MEP_PCREL8A2
4770 BFD_RELOC_MEP_PCREL12A2
4772 BFD_RELOC_MEP_PCREL17A2
4774 BFD_RELOC_MEP_PCREL24A2
4776 BFD_RELOC_MEP_PCABS24A2
4788 BFD_RELOC_MEP_TPREL7
4790 BFD_RELOC_MEP_TPREL7A2
4792 BFD_RELOC_MEP_TPREL7A4
4794 BFD_RELOC_MEP_UIMM24
4796 BFD_RELOC_MEP_ADDR24A4
4798 BFD_RELOC_MEP_GNU_VTINHERIT
4800 BFD_RELOC_MEP_GNU_VTENTRY
4802 Toshiba Media Processor Relocations.
4806 BFD_RELOC_METAG_HIADDR16
4808 BFD_RELOC_METAG_LOADDR16
4810 BFD_RELOC_METAG_RELBRANCH
4812 BFD_RELOC_METAG_GETSETOFF
4814 BFD_RELOC_METAG_HIOG
4816 BFD_RELOC_METAG_LOOG
4818 BFD_RELOC_METAG_REL8
4820 BFD_RELOC_METAG_REL16
4822 BFD_RELOC_METAG_HI16_GOTOFF
4824 BFD_RELOC_METAG_LO16_GOTOFF
4826 BFD_RELOC_METAG_GETSET_GOTOFF
4828 BFD_RELOC_METAG_GETSET_GOT
4830 BFD_RELOC_METAG_HI16_GOTPC
4832 BFD_RELOC_METAG_LO16_GOTPC
4834 BFD_RELOC_METAG_HI16_PLT
4836 BFD_RELOC_METAG_LO16_PLT
4838 BFD_RELOC_METAG_RELBRANCH_PLT
4840 BFD_RELOC_METAG_GOTOFF
4844 BFD_RELOC_METAG_COPY
4846 BFD_RELOC_METAG_JMP_SLOT
4848 BFD_RELOC_METAG_RELATIVE
4850 BFD_RELOC_METAG_GLOB_DAT
4852 BFD_RELOC_METAG_TLS_GD
4854 BFD_RELOC_METAG_TLS_LDM
4856 BFD_RELOC_METAG_TLS_LDO_HI16
4858 BFD_RELOC_METAG_TLS_LDO_LO16
4860 BFD_RELOC_METAG_TLS_LDO
4862 BFD_RELOC_METAG_TLS_IE
4864 BFD_RELOC_METAG_TLS_IENONPIC
4866 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4868 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4870 BFD_RELOC_METAG_TLS_TPOFF
4872 BFD_RELOC_METAG_TLS_DTPMOD
4874 BFD_RELOC_METAG_TLS_DTPOFF
4876 BFD_RELOC_METAG_TLS_LE
4878 BFD_RELOC_METAG_TLS_LE_HI16
4880 BFD_RELOC_METAG_TLS_LE_LO16
4882 Imagination Technologies Meta relocations.
4887 BFD_RELOC_MMIX_GETA_1
4889 BFD_RELOC_MMIX_GETA_2
4891 BFD_RELOC_MMIX_GETA_3
4893 These are relocations for the GETA instruction.
4895 BFD_RELOC_MMIX_CBRANCH
4897 BFD_RELOC_MMIX_CBRANCH_J
4899 BFD_RELOC_MMIX_CBRANCH_1
4901 BFD_RELOC_MMIX_CBRANCH_2
4903 BFD_RELOC_MMIX_CBRANCH_3
4905 These are relocations for a conditional branch instruction.
4907 BFD_RELOC_MMIX_PUSHJ
4909 BFD_RELOC_MMIX_PUSHJ_1
4911 BFD_RELOC_MMIX_PUSHJ_2
4913 BFD_RELOC_MMIX_PUSHJ_3
4915 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4917 These are relocations for the PUSHJ instruction.
4921 BFD_RELOC_MMIX_JMP_1
4923 BFD_RELOC_MMIX_JMP_2
4925 BFD_RELOC_MMIX_JMP_3
4927 These are relocations for the JMP instruction.
4929 BFD_RELOC_MMIX_ADDR19
4931 This is a relocation for a relative address as in a GETA instruction or
4934 BFD_RELOC_MMIX_ADDR27
4936 This is a relocation for a relative address as in a JMP instruction.
4938 BFD_RELOC_MMIX_REG_OR_BYTE
4940 This is a relocation for an instruction field that may be a general
4941 register or a value 0..255.
4945 This is a relocation for an instruction field that may be a general
4948 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4950 This is a relocation for two instruction fields holding a register and
4951 an offset, the equivalent of the relocation.
4953 BFD_RELOC_MMIX_LOCAL
4955 This relocation is an assertion that the expression is not allocated as
4956 a global register. It does not modify contents.
4959 BFD_RELOC_AVR_7_PCREL
4961 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4962 short offset into 7 bits.
4964 BFD_RELOC_AVR_13_PCREL
4966 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4967 short offset into 12 bits.
4971 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4972 program memory address) into 16 bits.
4974 BFD_RELOC_AVR_LO8_LDI
4976 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4977 data memory address) into 8 bit immediate value of LDI insn.
4979 BFD_RELOC_AVR_HI8_LDI
4981 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4982 of data memory address) into 8 bit immediate value of LDI insn.
4984 BFD_RELOC_AVR_HH8_LDI
4986 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4987 of program memory address) into 8 bit immediate value of LDI insn.
4989 BFD_RELOC_AVR_MS8_LDI
4991 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4992 of 32 bit value) into 8 bit immediate value of LDI insn.
4994 BFD_RELOC_AVR_LO8_LDI_NEG
4996 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4997 (usually data memory address) into 8 bit immediate value of SUBI insn.
4999 BFD_RELOC_AVR_HI8_LDI_NEG
5001 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5002 (high 8 bit of data memory address) into 8 bit immediate value of
5005 BFD_RELOC_AVR_HH8_LDI_NEG
5007 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5008 (most high 8 bit of program memory address) into 8 bit immediate value
5009 of LDI or SUBI insn.
5011 BFD_RELOC_AVR_MS8_LDI_NEG
5013 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
5014 of 32 bit value) into 8 bit immediate value of LDI insn.
5016 BFD_RELOC_AVR_LO8_LDI_PM
5018 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5019 command address) into 8 bit immediate value of LDI insn.
5021 BFD_RELOC_AVR_LO8_LDI_GS
5023 This is a 16 bit reloc for the AVR that stores 8 bit value
5024 (command address) into 8 bit immediate value of LDI insn. If the address
5025 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5028 BFD_RELOC_AVR_HI8_LDI_PM
5030 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5031 of command address) into 8 bit immediate value of LDI insn.
5033 BFD_RELOC_AVR_HI8_LDI_GS
5035 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5036 of command address) into 8 bit immediate value of LDI insn. If the address
5037 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5040 BFD_RELOC_AVR_HH8_LDI_PM
5042 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5043 of command address) into 8 bit immediate value of LDI insn.
5045 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5047 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5048 (usually command address) into 8 bit immediate value of SUBI insn.
5050 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5052 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5053 (high 8 bit of 16 bit command address) into 8 bit immediate value
5056 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5058 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5059 (high 6 bit of 22 bit command address) into 8 bit immediate
5064 This is a 32 bit reloc for the AVR that stores 23 bit value
5069 This is a 16 bit reloc for the AVR that stores all needed bits
5070 for absolute addressing with ldi with overflow check to linktime
5074 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5077 BFD_RELOC_AVR_6_ADIW
5079 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5084 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5085 in .byte lo8(symbol)
5089 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5090 in .byte hi8(symbol)
5094 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5095 in .byte hlo8(symbol)
5099 BFD_RELOC_AVR_DIFF16
5101 BFD_RELOC_AVR_DIFF32
5103 AVR relocations to mark the difference of two local symbols.
5104 These are only needed to support linker relaxation and can be ignored
5105 when not relaxing. The field is set to the value of the difference
5106 assuming no relaxation. The relocation encodes the position of the
5107 second symbol so the linker can determine whether to adjust the field
5110 BFD_RELOC_AVR_LDS_STS_16
5112 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5113 lds and sts instructions supported only tiny core.
5117 This is a 6 bit reloc for the AVR that stores an I/O register
5118 number for the IN and OUT instructions
5122 This is a 5 bit reloc for the AVR that stores an I/O register
5123 number for the SBIC, SBIS, SBI and CBI instructions
5126 BFD_RELOC_RISCV_HI20
5128 BFD_RELOC_RISCV_PCREL_HI20
5130 BFD_RELOC_RISCV_PCREL_LO12_I
5132 BFD_RELOC_RISCV_PCREL_LO12_S
5134 BFD_RELOC_RISCV_LO12_I
5136 BFD_RELOC_RISCV_LO12_S
5138 BFD_RELOC_RISCV_GPREL12_I
5140 BFD_RELOC_RISCV_GPREL12_S
5142 BFD_RELOC_RISCV_TPREL_HI20
5144 BFD_RELOC_RISCV_TPREL_LO12_I
5146 BFD_RELOC_RISCV_TPREL_LO12_S
5148 BFD_RELOC_RISCV_TPREL_ADD
5150 BFD_RELOC_RISCV_CALL
5152 BFD_RELOC_RISCV_CALL_PLT
5154 BFD_RELOC_RISCV_ADD8
5156 BFD_RELOC_RISCV_ADD16
5158 BFD_RELOC_RISCV_ADD32
5160 BFD_RELOC_RISCV_ADD64
5162 BFD_RELOC_RISCV_SUB8
5164 BFD_RELOC_RISCV_SUB16
5166 BFD_RELOC_RISCV_SUB32
5168 BFD_RELOC_RISCV_SUB64
5170 BFD_RELOC_RISCV_GOT_HI20
5172 BFD_RELOC_RISCV_TLS_GOT_HI20
5174 BFD_RELOC_RISCV_TLS_GD_HI20
5178 BFD_RELOC_RISCV_TLS_DTPMOD32
5180 BFD_RELOC_RISCV_TLS_DTPREL32
5182 BFD_RELOC_RISCV_TLS_DTPMOD64
5184 BFD_RELOC_RISCV_TLS_DTPREL64
5186 BFD_RELOC_RISCV_TLS_TPREL32
5188 BFD_RELOC_RISCV_TLS_TPREL64
5190 BFD_RELOC_RISCV_ALIGN
5192 BFD_RELOC_RISCV_RVC_BRANCH
5194 BFD_RELOC_RISCV_RVC_JUMP
5196 BFD_RELOC_RISCV_RVC_LUI
5198 BFD_RELOC_RISCV_GPREL_I
5200 BFD_RELOC_RISCV_GPREL_S
5202 BFD_RELOC_RISCV_TPREL_I
5204 BFD_RELOC_RISCV_TPREL_S
5206 BFD_RELOC_RISCV_RELAX
5210 BFD_RELOC_RISCV_SUB6
5212 BFD_RELOC_RISCV_SET6
5214 BFD_RELOC_RISCV_SET8
5216 BFD_RELOC_RISCV_SET16
5218 BFD_RELOC_RISCV_SET32
5220 BFD_RELOC_RISCV_32_PCREL
5227 BFD_RELOC_RL78_NEG16
5229 BFD_RELOC_RL78_NEG24
5231 BFD_RELOC_RL78_NEG32
5233 BFD_RELOC_RL78_16_OP
5235 BFD_RELOC_RL78_24_OP
5237 BFD_RELOC_RL78_32_OP
5245 BFD_RELOC_RL78_DIR3U_PCREL
5249 BFD_RELOC_RL78_GPRELB
5251 BFD_RELOC_RL78_GPRELW
5253 BFD_RELOC_RL78_GPRELL
5257 BFD_RELOC_RL78_OP_SUBTRACT
5259 BFD_RELOC_RL78_OP_NEG
5261 BFD_RELOC_RL78_OP_AND
5263 BFD_RELOC_RL78_OP_SHRA
5267 BFD_RELOC_RL78_ABS16
5269 BFD_RELOC_RL78_ABS16_REV
5271 BFD_RELOC_RL78_ABS32
5273 BFD_RELOC_RL78_ABS32_REV
5275 BFD_RELOC_RL78_ABS16U
5277 BFD_RELOC_RL78_ABS16UW
5279 BFD_RELOC_RL78_ABS16UL
5281 BFD_RELOC_RL78_RELAX
5291 BFD_RELOC_RL78_SADDR
5293 Renesas RL78 Relocations.
5316 BFD_RELOC_RX_DIR3U_PCREL
5328 BFD_RELOC_RX_OP_SUBTRACT
5336 BFD_RELOC_RX_ABS16_REV
5340 BFD_RELOC_RX_ABS32_REV
5344 BFD_RELOC_RX_ABS16UW
5346 BFD_RELOC_RX_ABS16UL
5350 Renesas RX Relocations.
5363 32 bit PC relative PLT address.
5367 Copy symbol at runtime.
5369 BFD_RELOC_390_GLOB_DAT
5373 BFD_RELOC_390_JMP_SLOT
5377 BFD_RELOC_390_RELATIVE
5379 Adjust by program base.
5383 32 bit PC relative offset to GOT.
5389 BFD_RELOC_390_PC12DBL
5391 PC relative 12 bit shifted by 1.
5393 BFD_RELOC_390_PLT12DBL
5395 12 bit PC rel. PLT shifted by 1.
5397 BFD_RELOC_390_PC16DBL
5399 PC relative 16 bit shifted by 1.
5401 BFD_RELOC_390_PLT16DBL
5403 16 bit PC rel. PLT shifted by 1.
5405 BFD_RELOC_390_PC24DBL
5407 PC relative 24 bit shifted by 1.
5409 BFD_RELOC_390_PLT24DBL
5411 24 bit PC rel. PLT shifted by 1.
5413 BFD_RELOC_390_PC32DBL
5415 PC relative 32 bit shifted by 1.
5417 BFD_RELOC_390_PLT32DBL
5419 32 bit PC rel. PLT shifted by 1.
5421 BFD_RELOC_390_GOTPCDBL
5423 32 bit PC rel. GOT shifted by 1.
5431 64 bit PC relative PLT address.
5433 BFD_RELOC_390_GOTENT
5435 32 bit rel. offset to GOT entry.
5437 BFD_RELOC_390_GOTOFF64
5439 64 bit offset to GOT.
5441 BFD_RELOC_390_GOTPLT12
5443 12-bit offset to symbol-entry within GOT, with PLT handling.
5445 BFD_RELOC_390_GOTPLT16
5447 16-bit offset to symbol-entry within GOT, with PLT handling.
5449 BFD_RELOC_390_GOTPLT32
5451 32-bit offset to symbol-entry within GOT, with PLT handling.
5453 BFD_RELOC_390_GOTPLT64
5455 64-bit offset to symbol-entry within GOT, with PLT handling.
5457 BFD_RELOC_390_GOTPLTENT
5459 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5461 BFD_RELOC_390_PLTOFF16
5463 16-bit rel. offset from the GOT to a PLT entry.
5465 BFD_RELOC_390_PLTOFF32
5467 32-bit rel. offset from the GOT to a PLT entry.
5469 BFD_RELOC_390_PLTOFF64
5471 64-bit rel. offset from the GOT to a PLT entry.
5474 BFD_RELOC_390_TLS_LOAD
5476 BFD_RELOC_390_TLS_GDCALL
5478 BFD_RELOC_390_TLS_LDCALL
5480 BFD_RELOC_390_TLS_GD32
5482 BFD_RELOC_390_TLS_GD64
5484 BFD_RELOC_390_TLS_GOTIE12
5486 BFD_RELOC_390_TLS_GOTIE32
5488 BFD_RELOC_390_TLS_GOTIE64
5490 BFD_RELOC_390_TLS_LDM32
5492 BFD_RELOC_390_TLS_LDM64
5494 BFD_RELOC_390_TLS_IE32
5496 BFD_RELOC_390_TLS_IE64
5498 BFD_RELOC_390_TLS_IEENT
5500 BFD_RELOC_390_TLS_LE32
5502 BFD_RELOC_390_TLS_LE64
5504 BFD_RELOC_390_TLS_LDO32
5506 BFD_RELOC_390_TLS_LDO64
5508 BFD_RELOC_390_TLS_DTPMOD
5510 BFD_RELOC_390_TLS_DTPOFF
5512 BFD_RELOC_390_TLS_TPOFF
5514 s390 tls relocations.
5521 BFD_RELOC_390_GOTPLT20
5523 BFD_RELOC_390_TLS_GOTIE20
5525 Long displacement extension.
5528 BFD_RELOC_390_IRELATIVE
5530 STT_GNU_IFUNC relocation.
5533 BFD_RELOC_SCORE_GPREL15
5536 Low 16 bit for load/store
5538 BFD_RELOC_SCORE_DUMMY2
5542 This is a 24-bit reloc with the right 1 bit assumed to be 0
5544 BFD_RELOC_SCORE_BRANCH
5546 This is a 19-bit reloc with the right 1 bit assumed to be 0
5548 BFD_RELOC_SCORE_IMM30
5550 This is a 32-bit reloc for 48-bit instructions.
5552 BFD_RELOC_SCORE_IMM32
5554 This is a 32-bit reloc for 48-bit instructions.
5556 BFD_RELOC_SCORE16_JMP
5558 This is a 11-bit reloc with the right 1 bit assumed to be 0
5560 BFD_RELOC_SCORE16_BRANCH
5562 This is a 8-bit reloc with the right 1 bit assumed to be 0
5564 BFD_RELOC_SCORE_BCMP
5566 This is a 9-bit reloc with the right 1 bit assumed to be 0
5568 BFD_RELOC_SCORE_GOT15
5570 BFD_RELOC_SCORE_GOT_LO16
5572 BFD_RELOC_SCORE_CALL15
5574 BFD_RELOC_SCORE_DUMMY_HI16
5576 Undocumented Score relocs
5581 Scenix IP2K - 9-bit register number / data address
5585 Scenix IP2K - 4-bit register/data bank number
5587 BFD_RELOC_IP2K_ADDR16CJP
5589 Scenix IP2K - low 13 bits of instruction word address
5591 BFD_RELOC_IP2K_PAGE3
5593 Scenix IP2K - high 3 bits of instruction word address
5595 BFD_RELOC_IP2K_LO8DATA
5597 BFD_RELOC_IP2K_HI8DATA
5599 BFD_RELOC_IP2K_EX8DATA
5601 Scenix IP2K - ext/low/high 8 bits of data address
5603 BFD_RELOC_IP2K_LO8INSN
5605 BFD_RELOC_IP2K_HI8INSN
5607 Scenix IP2K - low/high 8 bits of instruction word address
5609 BFD_RELOC_IP2K_PC_SKIP
5611 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5615 Scenix IP2K - 16 bit word address in text section.
5617 BFD_RELOC_IP2K_FR_OFFSET
5619 Scenix IP2K - 7-bit sp or dp offset
5621 BFD_RELOC_VPE4KMATH_DATA
5623 BFD_RELOC_VPE4KMATH_INSN
5625 Scenix VPE4K coprocessor - data/insn-space addressing
5628 BFD_RELOC_VTABLE_INHERIT
5630 BFD_RELOC_VTABLE_ENTRY
5632 These two relocations are used by the linker to determine which of
5633 the entries in a C++ virtual function table are actually used. When
5634 the --gc-sections option is given, the linker will zero out the entries
5635 that are not used, so that the code for those functions need not be
5636 included in the output.
5638 VTABLE_INHERIT is a zero-space relocation used to describe to the
5639 linker the inheritance tree of a C++ virtual function table. The
5640 relocation's symbol should be the parent class' vtable, and the
5641 relocation should be located at the child vtable.
5643 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5644 virtual function table entry. The reloc's symbol should refer to the
5645 table of the class mentioned in the code. Off of that base, an offset
5646 describes the entry that is being used. For Rela hosts, this offset
5647 is stored in the reloc's addend. For Rel hosts, we are forced to put
5648 this offset in the reloc's section offset.
5651 BFD_RELOC_IA64_IMM14
5653 BFD_RELOC_IA64_IMM22
5655 BFD_RELOC_IA64_IMM64
5657 BFD_RELOC_IA64_DIR32MSB
5659 BFD_RELOC_IA64_DIR32LSB
5661 BFD_RELOC_IA64_DIR64MSB
5663 BFD_RELOC_IA64_DIR64LSB
5665 BFD_RELOC_IA64_GPREL22
5667 BFD_RELOC_IA64_GPREL64I
5669 BFD_RELOC_IA64_GPREL32MSB
5671 BFD_RELOC_IA64_GPREL32LSB
5673 BFD_RELOC_IA64_GPREL64MSB
5675 BFD_RELOC_IA64_GPREL64LSB
5677 BFD_RELOC_IA64_LTOFF22
5679 BFD_RELOC_IA64_LTOFF64I
5681 BFD_RELOC_IA64_PLTOFF22
5683 BFD_RELOC_IA64_PLTOFF64I
5685 BFD_RELOC_IA64_PLTOFF64MSB
5687 BFD_RELOC_IA64_PLTOFF64LSB
5689 BFD_RELOC_IA64_FPTR64I
5691 BFD_RELOC_IA64_FPTR32MSB
5693 BFD_RELOC_IA64_FPTR32LSB
5695 BFD_RELOC_IA64_FPTR64MSB
5697 BFD_RELOC_IA64_FPTR64LSB
5699 BFD_RELOC_IA64_PCREL21B
5701 BFD_RELOC_IA64_PCREL21BI
5703 BFD_RELOC_IA64_PCREL21M
5705 BFD_RELOC_IA64_PCREL21F
5707 BFD_RELOC_IA64_PCREL22
5709 BFD_RELOC_IA64_PCREL60B
5711 BFD_RELOC_IA64_PCREL64I
5713 BFD_RELOC_IA64_PCREL32MSB
5715 BFD_RELOC_IA64_PCREL32LSB
5717 BFD_RELOC_IA64_PCREL64MSB
5719 BFD_RELOC_IA64_PCREL64LSB
5721 BFD_RELOC_IA64_LTOFF_FPTR22
5723 BFD_RELOC_IA64_LTOFF_FPTR64I
5725 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5727 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5729 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5731 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5733 BFD_RELOC_IA64_SEGREL32MSB
5735 BFD_RELOC_IA64_SEGREL32LSB
5737 BFD_RELOC_IA64_SEGREL64MSB
5739 BFD_RELOC_IA64_SEGREL64LSB
5741 BFD_RELOC_IA64_SECREL32MSB
5743 BFD_RELOC_IA64_SECREL32LSB
5745 BFD_RELOC_IA64_SECREL64MSB
5747 BFD_RELOC_IA64_SECREL64LSB
5749 BFD_RELOC_IA64_REL32MSB
5751 BFD_RELOC_IA64_REL32LSB
5753 BFD_RELOC_IA64_REL64MSB
5755 BFD_RELOC_IA64_REL64LSB
5757 BFD_RELOC_IA64_LTV32MSB
5759 BFD_RELOC_IA64_LTV32LSB
5761 BFD_RELOC_IA64_LTV64MSB
5763 BFD_RELOC_IA64_LTV64LSB
5765 BFD_RELOC_IA64_IPLTMSB
5767 BFD_RELOC_IA64_IPLTLSB
5771 BFD_RELOC_IA64_LTOFF22X
5773 BFD_RELOC_IA64_LDXMOV
5775 BFD_RELOC_IA64_TPREL14
5777 BFD_RELOC_IA64_TPREL22
5779 BFD_RELOC_IA64_TPREL64I
5781 BFD_RELOC_IA64_TPREL64MSB
5783 BFD_RELOC_IA64_TPREL64LSB
5785 BFD_RELOC_IA64_LTOFF_TPREL22
5787 BFD_RELOC_IA64_DTPMOD64MSB
5789 BFD_RELOC_IA64_DTPMOD64LSB
5791 BFD_RELOC_IA64_LTOFF_DTPMOD22
5793 BFD_RELOC_IA64_DTPREL14
5795 BFD_RELOC_IA64_DTPREL22
5797 BFD_RELOC_IA64_DTPREL64I
5799 BFD_RELOC_IA64_DTPREL32MSB
5801 BFD_RELOC_IA64_DTPREL32LSB
5803 BFD_RELOC_IA64_DTPREL64MSB
5805 BFD_RELOC_IA64_DTPREL64LSB
5807 BFD_RELOC_IA64_LTOFF_DTPREL22
5809 Intel IA64 Relocations.
5812 BFD_RELOC_M68HC11_HI8
5814 Motorola 68HC11 reloc.
5815 This is the 8 bit high part of an absolute address.
5817 BFD_RELOC_M68HC11_LO8
5819 Motorola 68HC11 reloc.
5820 This is the 8 bit low part of an absolute address.
5822 BFD_RELOC_M68HC11_3B
5824 Motorola 68HC11 reloc.
5825 This is the 3 bit of a value.
5827 BFD_RELOC_M68HC11_RL_JUMP
5829 Motorola 68HC11 reloc.
5830 This reloc marks the beginning of a jump/call instruction.
5831 It is used for linker relaxation to correctly identify beginning
5832 of instruction and change some branches to use PC-relative
5835 BFD_RELOC_M68HC11_RL_GROUP
5837 Motorola 68HC11 reloc.
5838 This reloc marks a group of several instructions that gcc generates
5839 and for which the linker relaxation pass can modify and/or remove
5842 BFD_RELOC_M68HC11_LO16
5844 Motorola 68HC11 reloc.
5845 This is the 16-bit lower part of an address. It is used for 'call'
5846 instruction to specify the symbol address without any special
5847 transformation (due to memory bank window).
5849 BFD_RELOC_M68HC11_PAGE
5851 Motorola 68HC11 reloc.
5852 This is a 8-bit reloc that specifies the page number of an address.
5853 It is used by 'call' instruction to specify the page number of
5856 BFD_RELOC_M68HC11_24
5858 Motorola 68HC11 reloc.
5859 This is a 24-bit reloc that represents the address with a 16-bit
5860 value and a 8-bit page number. The symbol address is transformed
5861 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5863 BFD_RELOC_M68HC12_5B
5865 Motorola 68HC12 reloc.
5866 This is the 5 bits of a value.
5868 BFD_RELOC_XGATE_RL_JUMP
5870 Freescale XGATE reloc.
5871 This reloc marks the beginning of a bra/jal instruction.
5873 BFD_RELOC_XGATE_RL_GROUP
5875 Freescale XGATE reloc.
5876 This reloc marks a group of several instructions that gcc generates
5877 and for which the linker relaxation pass can modify and/or remove
5880 BFD_RELOC_XGATE_LO16
5882 Freescale XGATE reloc.
5883 This is the 16-bit lower part of an address. It is used for the '16-bit'
5886 BFD_RELOC_XGATE_GPAGE
5888 Freescale XGATE reloc.
5892 Freescale XGATE reloc.
5894 BFD_RELOC_XGATE_PCREL_9
5896 Freescale XGATE reloc.
5897 This is a 9-bit pc-relative reloc.
5899 BFD_RELOC_XGATE_PCREL_10
5901 Freescale XGATE reloc.
5902 This is a 10-bit pc-relative reloc.
5904 BFD_RELOC_XGATE_IMM8_LO
5906 Freescale XGATE reloc.
5907 This is the 16-bit lower part of an address. It is used for the '16-bit'
5910 BFD_RELOC_XGATE_IMM8_HI
5912 Freescale XGATE reloc.
5913 This is the 16-bit higher part of an address. It is used for the '16-bit'
5916 BFD_RELOC_XGATE_IMM3
5918 Freescale XGATE reloc.
5919 This is a 3-bit pc-relative reloc.
5921 BFD_RELOC_XGATE_IMM4
5923 Freescale XGATE reloc.
5924 This is a 4-bit pc-relative reloc.
5926 BFD_RELOC_XGATE_IMM5
5928 Freescale XGATE reloc.
5929 This is a 5-bit pc-relative reloc.
5931 BFD_RELOC_M68HC12_9B
5933 Motorola 68HC12 reloc.
5934 This is the 9 bits of a value.
5936 BFD_RELOC_M68HC12_16B
5938 Motorola 68HC12 reloc.
5939 This is the 16 bits of a value.
5941 BFD_RELOC_M68HC12_9_PCREL
5943 Motorola 68HC12/XGATE reloc.
5944 This is a PCREL9 branch.
5946 BFD_RELOC_M68HC12_10_PCREL
5948 Motorola 68HC12/XGATE reloc.
5949 This is a PCREL10 branch.
5951 BFD_RELOC_M68HC12_LO8XG
5953 Motorola 68HC12/XGATE reloc.
5954 This is the 8 bit low part of an absolute address and immediately precedes
5955 a matching HI8XG part.
5957 BFD_RELOC_M68HC12_HI8XG
5959 Motorola 68HC12/XGATE reloc.
5960 This is the 8 bit high part of an absolute address and immediately follows
5961 a matching LO8XG part.
5963 BFD_RELOC_S12Z_15_PCREL
5965 Freescale S12Z reloc.
5966 This is a 15 bit relative address. If the most significant bits are all zero
5967 then it may be truncated to 8 bits.
5971 BFD_RELOC_16C_NUM08_C
5975 BFD_RELOC_16C_NUM16_C
5979 BFD_RELOC_16C_NUM32_C
5981 BFD_RELOC_16C_DISP04
5983 BFD_RELOC_16C_DISP04_C
5985 BFD_RELOC_16C_DISP08
5987 BFD_RELOC_16C_DISP08_C
5989 BFD_RELOC_16C_DISP16
5991 BFD_RELOC_16C_DISP16_C
5993 BFD_RELOC_16C_DISP24
5995 BFD_RELOC_16C_DISP24_C
5997 BFD_RELOC_16C_DISP24a
5999 BFD_RELOC_16C_DISP24a_C
6003 BFD_RELOC_16C_REG04_C
6005 BFD_RELOC_16C_REG04a
6007 BFD_RELOC_16C_REG04a_C
6011 BFD_RELOC_16C_REG14_C
6015 BFD_RELOC_16C_REG16_C
6019 BFD_RELOC_16C_REG20_C
6023 BFD_RELOC_16C_ABS20_C
6027 BFD_RELOC_16C_ABS24_C
6031 BFD_RELOC_16C_IMM04_C
6035 BFD_RELOC_16C_IMM16_C
6039 BFD_RELOC_16C_IMM20_C
6043 BFD_RELOC_16C_IMM24_C
6047 BFD_RELOC_16C_IMM32_C
6049 NS CR16C Relocations.
6054 BFD_RELOC_CR16_NUM16
6056 BFD_RELOC_CR16_NUM32
6058 BFD_RELOC_CR16_NUM32a
6060 BFD_RELOC_CR16_REGREL0
6062 BFD_RELOC_CR16_REGREL4
6064 BFD_RELOC_CR16_REGREL4a
6066 BFD_RELOC_CR16_REGREL14
6068 BFD_RELOC_CR16_REGREL14a
6070 BFD_RELOC_CR16_REGREL16
6072 BFD_RELOC_CR16_REGREL20
6074 BFD_RELOC_CR16_REGREL20a
6076 BFD_RELOC_CR16_ABS20
6078 BFD_RELOC_CR16_ABS24
6084 BFD_RELOC_CR16_IMM16
6086 BFD_RELOC_CR16_IMM20
6088 BFD_RELOC_CR16_IMM24
6090 BFD_RELOC_CR16_IMM32
6092 BFD_RELOC_CR16_IMM32a
6094 BFD_RELOC_CR16_DISP4
6096 BFD_RELOC_CR16_DISP8
6098 BFD_RELOC_CR16_DISP16
6100 BFD_RELOC_CR16_DISP20
6102 BFD_RELOC_CR16_DISP24
6104 BFD_RELOC_CR16_DISP24a
6106 BFD_RELOC_CR16_SWITCH8
6108 BFD_RELOC_CR16_SWITCH16
6110 BFD_RELOC_CR16_SWITCH32
6112 BFD_RELOC_CR16_GOT_REGREL20
6114 BFD_RELOC_CR16_GOTC_REGREL20
6116 BFD_RELOC_CR16_GLOB_DAT
6118 NS CR16 Relocations.
6125 BFD_RELOC_CRX_REL8_CMP
6133 BFD_RELOC_CRX_REGREL12
6135 BFD_RELOC_CRX_REGREL22
6137 BFD_RELOC_CRX_REGREL28
6139 BFD_RELOC_CRX_REGREL32
6155 BFD_RELOC_CRX_SWITCH8
6157 BFD_RELOC_CRX_SWITCH16
6159 BFD_RELOC_CRX_SWITCH32
6164 BFD_RELOC_CRIS_BDISP8
6166 BFD_RELOC_CRIS_UNSIGNED_5
6168 BFD_RELOC_CRIS_SIGNED_6
6170 BFD_RELOC_CRIS_UNSIGNED_6
6172 BFD_RELOC_CRIS_SIGNED_8
6174 BFD_RELOC_CRIS_UNSIGNED_8
6176 BFD_RELOC_CRIS_SIGNED_16
6178 BFD_RELOC_CRIS_UNSIGNED_16
6180 BFD_RELOC_CRIS_LAPCQ_OFFSET
6182 BFD_RELOC_CRIS_UNSIGNED_4
6184 These relocs are only used within the CRIS assembler. They are not
6185 (at present) written to any object files.
6189 BFD_RELOC_CRIS_GLOB_DAT
6191 BFD_RELOC_CRIS_JUMP_SLOT
6193 BFD_RELOC_CRIS_RELATIVE
6195 Relocs used in ELF shared libraries for CRIS.
6197 BFD_RELOC_CRIS_32_GOT
6199 32-bit offset to symbol-entry within GOT.
6201 BFD_RELOC_CRIS_16_GOT
6203 16-bit offset to symbol-entry within GOT.
6205 BFD_RELOC_CRIS_32_GOTPLT
6207 32-bit offset to symbol-entry within GOT, with PLT handling.
6209 BFD_RELOC_CRIS_16_GOTPLT
6211 16-bit offset to symbol-entry within GOT, with PLT handling.
6213 BFD_RELOC_CRIS_32_GOTREL
6215 32-bit offset to symbol, relative to GOT.
6217 BFD_RELOC_CRIS_32_PLT_GOTREL
6219 32-bit offset to symbol with PLT entry, relative to GOT.
6221 BFD_RELOC_CRIS_32_PLT_PCREL
6223 32-bit offset to symbol with PLT entry, relative to this relocation.
6226 BFD_RELOC_CRIS_32_GOT_GD
6228 BFD_RELOC_CRIS_16_GOT_GD
6230 BFD_RELOC_CRIS_32_GD
6234 BFD_RELOC_CRIS_32_DTPREL
6236 BFD_RELOC_CRIS_16_DTPREL
6238 BFD_RELOC_CRIS_32_GOT_TPREL
6240 BFD_RELOC_CRIS_16_GOT_TPREL
6242 BFD_RELOC_CRIS_32_TPREL
6244 BFD_RELOC_CRIS_16_TPREL
6246 BFD_RELOC_CRIS_DTPMOD
6248 BFD_RELOC_CRIS_32_IE
6250 Relocs used in TLS code for CRIS.
6253 BFD_RELOC_OR1K_REL_26
6255 BFD_RELOC_OR1K_GOTPC_HI16
6257 BFD_RELOC_OR1K_GOTPC_LO16
6259 BFD_RELOC_OR1K_GOT16
6261 BFD_RELOC_OR1K_PLT26
6263 BFD_RELOC_OR1K_GOTOFF_HI16
6265 BFD_RELOC_OR1K_GOTOFF_LO16
6269 BFD_RELOC_OR1K_GLOB_DAT
6271 BFD_RELOC_OR1K_JMP_SLOT
6273 BFD_RELOC_OR1K_RELATIVE
6275 BFD_RELOC_OR1K_TLS_GD_HI16
6277 BFD_RELOC_OR1K_TLS_GD_LO16
6279 BFD_RELOC_OR1K_TLS_LDM_HI16
6281 BFD_RELOC_OR1K_TLS_LDM_LO16
6283 BFD_RELOC_OR1K_TLS_LDO_HI16
6285 BFD_RELOC_OR1K_TLS_LDO_LO16
6287 BFD_RELOC_OR1K_TLS_IE_HI16
6289 BFD_RELOC_OR1K_TLS_IE_LO16
6291 BFD_RELOC_OR1K_TLS_LE_HI16
6293 BFD_RELOC_OR1K_TLS_LE_LO16
6295 BFD_RELOC_OR1K_TLS_TPOFF
6297 BFD_RELOC_OR1K_TLS_DTPOFF
6299 BFD_RELOC_OR1K_TLS_DTPMOD
6301 OpenRISC 1000 Relocations.
6304 BFD_RELOC_H8_DIR16A8
6306 BFD_RELOC_H8_DIR16R8
6308 BFD_RELOC_H8_DIR24A8
6310 BFD_RELOC_H8_DIR24R8
6312 BFD_RELOC_H8_DIR32A16
6314 BFD_RELOC_H8_DISP32A16
6319 BFD_RELOC_XSTORMY16_REL_12
6321 BFD_RELOC_XSTORMY16_12
6323 BFD_RELOC_XSTORMY16_24
6325 BFD_RELOC_XSTORMY16_FPTR16
6327 Sony Xstormy16 Relocations.
6332 Self-describing complex relocations.
6344 Infineon Relocations.
6347 BFD_RELOC_VAX_GLOB_DAT
6349 BFD_RELOC_VAX_JMP_SLOT
6351 BFD_RELOC_VAX_RELATIVE
6353 Relocations used by VAX ELF.
6358 Morpho MT - 16 bit immediate relocation.
6362 Morpho MT - Hi 16 bits of an address.
6366 Morpho MT - Low 16 bits of an address.
6368 BFD_RELOC_MT_GNU_VTINHERIT
6370 Morpho MT - Used to tell the linker which vtable entries are used.
6372 BFD_RELOC_MT_GNU_VTENTRY
6374 Morpho MT - Used to tell the linker which vtable entries are used.
6376 BFD_RELOC_MT_PCINSN8
6378 Morpho MT - 8 bit immediate relocation.
6381 BFD_RELOC_MSP430_10_PCREL
6383 BFD_RELOC_MSP430_16_PCREL
6387 BFD_RELOC_MSP430_16_PCREL_BYTE
6389 BFD_RELOC_MSP430_16_BYTE
6391 BFD_RELOC_MSP430_2X_PCREL
6393 BFD_RELOC_MSP430_RL_PCREL
6395 BFD_RELOC_MSP430_ABS8
6397 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6399 BFD_RELOC_MSP430X_PCR20_EXT_DST
6401 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6403 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6405 BFD_RELOC_MSP430X_ABS20_EXT_DST
6407 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6409 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6411 BFD_RELOC_MSP430X_ABS20_ADR_DST
6413 BFD_RELOC_MSP430X_PCR16
6415 BFD_RELOC_MSP430X_PCR20_CALL
6417 BFD_RELOC_MSP430X_ABS16
6419 BFD_RELOC_MSP430_ABS_HI16
6421 BFD_RELOC_MSP430_PREL31
6423 BFD_RELOC_MSP430_SYM_DIFF
6425 msp430 specific relocation codes
6432 BFD_RELOC_NIOS2_CALL26
6434 BFD_RELOC_NIOS2_IMM5
6436 BFD_RELOC_NIOS2_CACHE_OPX
6438 BFD_RELOC_NIOS2_IMM6
6440 BFD_RELOC_NIOS2_IMM8
6442 BFD_RELOC_NIOS2_HI16
6444 BFD_RELOC_NIOS2_LO16
6446 BFD_RELOC_NIOS2_HIADJ16
6448 BFD_RELOC_NIOS2_GPREL
6450 BFD_RELOC_NIOS2_UJMP
6452 BFD_RELOC_NIOS2_CJMP
6454 BFD_RELOC_NIOS2_CALLR
6456 BFD_RELOC_NIOS2_ALIGN
6458 BFD_RELOC_NIOS2_GOT16
6460 BFD_RELOC_NIOS2_CALL16
6462 BFD_RELOC_NIOS2_GOTOFF_LO
6464 BFD_RELOC_NIOS2_GOTOFF_HA
6466 BFD_RELOC_NIOS2_PCREL_LO
6468 BFD_RELOC_NIOS2_PCREL_HA
6470 BFD_RELOC_NIOS2_TLS_GD16
6472 BFD_RELOC_NIOS2_TLS_LDM16
6474 BFD_RELOC_NIOS2_TLS_LDO16
6476 BFD_RELOC_NIOS2_TLS_IE16
6478 BFD_RELOC_NIOS2_TLS_LE16
6480 BFD_RELOC_NIOS2_TLS_DTPMOD
6482 BFD_RELOC_NIOS2_TLS_DTPREL
6484 BFD_RELOC_NIOS2_TLS_TPREL
6486 BFD_RELOC_NIOS2_COPY
6488 BFD_RELOC_NIOS2_GLOB_DAT
6490 BFD_RELOC_NIOS2_JUMP_SLOT
6492 BFD_RELOC_NIOS2_RELATIVE
6494 BFD_RELOC_NIOS2_GOTOFF
6496 BFD_RELOC_NIOS2_CALL26_NOAT
6498 BFD_RELOC_NIOS2_GOT_LO
6500 BFD_RELOC_NIOS2_GOT_HA
6502 BFD_RELOC_NIOS2_CALL_LO
6504 BFD_RELOC_NIOS2_CALL_HA
6506 BFD_RELOC_NIOS2_R2_S12
6508 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6510 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6512 BFD_RELOC_NIOS2_R2_T1I7_2
6514 BFD_RELOC_NIOS2_R2_T2I4
6516 BFD_RELOC_NIOS2_R2_T2I4_1
6518 BFD_RELOC_NIOS2_R2_T2I4_2
6520 BFD_RELOC_NIOS2_R2_X1I7_2
6522 BFD_RELOC_NIOS2_R2_X2L5
6524 BFD_RELOC_NIOS2_R2_F1I5_2
6526 BFD_RELOC_NIOS2_R2_L5I4X1
6528 BFD_RELOC_NIOS2_R2_T1X1I6
6530 BFD_RELOC_NIOS2_R2_T1X1I6_2
6532 Relocations used by the Altera Nios II core.
6537 PRU LDI 16-bit unsigned data-memory relocation.
6539 BFD_RELOC_PRU_U16_PMEMIMM
6541 PRU LDI 16-bit unsigned instruction-memory relocation.
6545 PRU relocation for two consecutive LDI load instructions that load a
6546 32 bit value into a register. If the higher bits are all zero, then
6547 the second instruction may be relaxed.
6549 BFD_RELOC_PRU_S10_PCREL
6551 PRU QBBx 10-bit signed PC-relative relocation.
6553 BFD_RELOC_PRU_U8_PCREL
6555 PRU 8-bit unsigned relocation used for the LOOP instruction.
6557 BFD_RELOC_PRU_32_PMEM
6559 BFD_RELOC_PRU_16_PMEM
6561 PRU Program Memory relocations. Used to convert from byte addressing to
6562 32-bit word addressing.
6564 BFD_RELOC_PRU_GNU_DIFF8
6566 BFD_RELOC_PRU_GNU_DIFF16
6568 BFD_RELOC_PRU_GNU_DIFF32
6570 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6572 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6574 PRU relocations to mark the difference of two local symbols.
6575 These are only needed to support linker relaxation and can be ignored
6576 when not relaxing. The field is set to the value of the difference
6577 assuming no relaxation. The relocation encodes the position of the
6578 second symbol so the linker can determine whether to adjust the field
6579 value. The PMEM variants encode the word difference, instead of byte
6580 difference between symbols.
6583 BFD_RELOC_IQ2000_OFFSET_16
6585 BFD_RELOC_IQ2000_OFFSET_21
6587 BFD_RELOC_IQ2000_UHI16
6592 BFD_RELOC_XTENSA_RTLD
6594 Special Xtensa relocation used only by PLT entries in ELF shared
6595 objects to indicate that the runtime linker should set the value
6596 to one of its own internal functions or data structures.
6598 BFD_RELOC_XTENSA_GLOB_DAT
6600 BFD_RELOC_XTENSA_JMP_SLOT
6602 BFD_RELOC_XTENSA_RELATIVE
6604 Xtensa relocations for ELF shared objects.
6606 BFD_RELOC_XTENSA_PLT
6608 Xtensa relocation used in ELF object files for symbols that may require
6609 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6611 BFD_RELOC_XTENSA_DIFF8
6613 BFD_RELOC_XTENSA_DIFF16
6615 BFD_RELOC_XTENSA_DIFF32
6617 Xtensa relocations to mark the difference of two local symbols.
6618 These are only needed to support linker relaxation and can be ignored
6619 when not relaxing. The field is set to the value of the difference
6620 assuming no relaxation. The relocation encodes the position of the
6621 first symbol so the linker can determine whether to adjust the field
6624 BFD_RELOC_XTENSA_SLOT0_OP
6626 BFD_RELOC_XTENSA_SLOT1_OP
6628 BFD_RELOC_XTENSA_SLOT2_OP
6630 BFD_RELOC_XTENSA_SLOT3_OP
6632 BFD_RELOC_XTENSA_SLOT4_OP
6634 BFD_RELOC_XTENSA_SLOT5_OP
6636 BFD_RELOC_XTENSA_SLOT6_OP
6638 BFD_RELOC_XTENSA_SLOT7_OP
6640 BFD_RELOC_XTENSA_SLOT8_OP
6642 BFD_RELOC_XTENSA_SLOT9_OP
6644 BFD_RELOC_XTENSA_SLOT10_OP
6646 BFD_RELOC_XTENSA_SLOT11_OP
6648 BFD_RELOC_XTENSA_SLOT12_OP
6650 BFD_RELOC_XTENSA_SLOT13_OP
6652 BFD_RELOC_XTENSA_SLOT14_OP
6654 Generic Xtensa relocations for instruction operands. Only the slot
6655 number is encoded in the relocation. The relocation applies to the
6656 last PC-relative immediate operand, or if there are no PC-relative
6657 immediates, to the last immediate operand.
6659 BFD_RELOC_XTENSA_SLOT0_ALT
6661 BFD_RELOC_XTENSA_SLOT1_ALT
6663 BFD_RELOC_XTENSA_SLOT2_ALT
6665 BFD_RELOC_XTENSA_SLOT3_ALT
6667 BFD_RELOC_XTENSA_SLOT4_ALT
6669 BFD_RELOC_XTENSA_SLOT5_ALT
6671 BFD_RELOC_XTENSA_SLOT6_ALT
6673 BFD_RELOC_XTENSA_SLOT7_ALT
6675 BFD_RELOC_XTENSA_SLOT8_ALT
6677 BFD_RELOC_XTENSA_SLOT9_ALT
6679 BFD_RELOC_XTENSA_SLOT10_ALT
6681 BFD_RELOC_XTENSA_SLOT11_ALT
6683 BFD_RELOC_XTENSA_SLOT12_ALT
6685 BFD_RELOC_XTENSA_SLOT13_ALT
6687 BFD_RELOC_XTENSA_SLOT14_ALT
6689 Alternate Xtensa relocations. Only the slot is encoded in the
6690 relocation. The meaning of these relocations is opcode-specific.
6692 BFD_RELOC_XTENSA_OP0
6694 BFD_RELOC_XTENSA_OP1
6696 BFD_RELOC_XTENSA_OP2
6698 Xtensa relocations for backward compatibility. These have all been
6699 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6701 BFD_RELOC_XTENSA_ASM_EXPAND
6703 Xtensa relocation to mark that the assembler expanded the
6704 instructions from an original target. The expansion size is
6705 encoded in the reloc size.
6707 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6709 Xtensa relocation to mark that the linker should simplify
6710 assembler-expanded instructions. This is commonly used
6711 internally by the linker after analysis of a
6712 BFD_RELOC_XTENSA_ASM_EXPAND.
6714 BFD_RELOC_XTENSA_TLSDESC_FN
6716 BFD_RELOC_XTENSA_TLSDESC_ARG
6718 BFD_RELOC_XTENSA_TLS_DTPOFF
6720 BFD_RELOC_XTENSA_TLS_TPOFF
6722 BFD_RELOC_XTENSA_TLS_FUNC
6724 BFD_RELOC_XTENSA_TLS_ARG
6726 BFD_RELOC_XTENSA_TLS_CALL
6728 Xtensa TLS relocations.
6733 8 bit signed offset in (ix+d) or (iy+d).
6751 BFD_RELOC_LM32_BRANCH
6753 BFD_RELOC_LM32_16_GOT
6755 BFD_RELOC_LM32_GOTOFF_HI16
6757 BFD_RELOC_LM32_GOTOFF_LO16
6761 BFD_RELOC_LM32_GLOB_DAT
6763 BFD_RELOC_LM32_JMP_SLOT
6765 BFD_RELOC_LM32_RELATIVE
6767 Lattice Mico32 relocations.
6770 BFD_RELOC_MACH_O_SECTDIFF
6772 Difference between two section addreses. Must be followed by a
6773 BFD_RELOC_MACH_O_PAIR.
6775 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6777 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6779 BFD_RELOC_MACH_O_PAIR
6781 Pair of relocation. Contains the first symbol.
6783 BFD_RELOC_MACH_O_SUBTRACTOR32
6785 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6787 BFD_RELOC_MACH_O_SUBTRACTOR64
6789 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6792 BFD_RELOC_MACH_O_X86_64_BRANCH32
6794 BFD_RELOC_MACH_O_X86_64_BRANCH8
6796 PCREL relocations. They are marked as branch to create PLT entry if
6799 BFD_RELOC_MACH_O_X86_64_GOT
6801 Used when referencing a GOT entry.
6803 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6805 Used when loading a GOT entry with movq. It is specially marked so that
6806 the linker could optimize the movq to a leaq if possible.
6808 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6810 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6812 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6814 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6816 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6818 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6822 BFD_RELOC_MACH_O_ARM64_ADDEND
6824 Addend for PAGE or PAGEOFF.
6826 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6828 Relative offset to page of GOT slot.
6830 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6832 Relative offset within page of GOT slot.
6834 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6836 Address of a GOT entry.
6839 BFD_RELOC_MICROBLAZE_32_LO
6841 This is a 32 bit reloc for the microblaze that stores the
6842 low 16 bits of a value
6844 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6846 This is a 32 bit pc-relative reloc for the microblaze that
6847 stores the low 16 bits of a value
6849 BFD_RELOC_MICROBLAZE_32_ROSDA
6851 This is a 32 bit reloc for the microblaze that stores a
6852 value relative to the read-only small data area anchor
6854 BFD_RELOC_MICROBLAZE_32_RWSDA
6856 This is a 32 bit reloc for the microblaze that stores a
6857 value relative to the read-write small data area anchor
6859 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6861 This is a 32 bit reloc for the microblaze to handle
6862 expressions of the form "Symbol Op Symbol"
6864 BFD_RELOC_MICROBLAZE_64_NONE
6866 This is a 64 bit reloc that stores the 32 bit pc relative
6867 value in two words (with an imm instruction). No relocation is
6868 done here - only used for relaxing
6870 BFD_RELOC_MICROBLAZE_64_GOTPC
6872 This is a 64 bit reloc that stores the 32 bit pc relative
6873 value in two words (with an imm instruction). The relocation is
6874 PC-relative GOT offset
6876 BFD_RELOC_MICROBLAZE_64_GOT
6878 This is a 64 bit reloc that stores the 32 bit pc relative
6879 value in two words (with an imm instruction). The relocation is
6882 BFD_RELOC_MICROBLAZE_64_PLT
6884 This is a 64 bit reloc that stores the 32 bit pc relative
6885 value in two words (with an imm instruction). The relocation is
6886 PC-relative offset into PLT
6888 BFD_RELOC_MICROBLAZE_64_GOTOFF
6890 This is a 64 bit reloc that stores the 32 bit GOT relative
6891 value in two words (with an imm instruction). The relocation is
6892 relative offset from _GLOBAL_OFFSET_TABLE_
6894 BFD_RELOC_MICROBLAZE_32_GOTOFF
6896 This is a 32 bit reloc that stores the 32 bit GOT relative
6897 value in a word. The relocation is relative offset from
6898 _GLOBAL_OFFSET_TABLE_
6900 BFD_RELOC_MICROBLAZE_COPY
6902 This is used to tell the dynamic linker to copy the value out of
6903 the dynamic object into the runtime process image.
6905 BFD_RELOC_MICROBLAZE_64_TLS
6909 BFD_RELOC_MICROBLAZE_64_TLSGD
6911 This is a 64 bit reloc that stores the 32 bit GOT relative value
6912 of the GOT TLS GD info entry in two words (with an imm instruction). The
6913 relocation is GOT offset.
6915 BFD_RELOC_MICROBLAZE_64_TLSLD
6917 This is a 64 bit reloc that stores the 32 bit GOT relative value
6918 of the GOT TLS LD info entry in two words (with an imm instruction). The
6919 relocation is GOT offset.
6921 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6923 This is a 32 bit reloc that stores the Module ID to GOT(n).
6925 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6927 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6929 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6931 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6934 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6936 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6937 to two words (uses imm instruction).
6939 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6941 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6942 to two words (uses imm instruction).
6944 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6946 This is a 64 bit reloc that stores the 32 bit pc relative
6947 value in two words (with an imm instruction). The relocation is
6948 PC-relative offset from start of TEXT.
6950 BFD_RELOC_MICROBLAZE_64_TEXTREL
6952 This is a 64 bit reloc that stores the 32 bit offset
6953 value in two words (with an imm instruction). The relocation is
6954 relative offset from start of TEXT.
6957 BFD_RELOC_AARCH64_RELOC_START
6959 AArch64 pseudo relocation code to mark the start of the AArch64
6960 relocation enumerators. N.B. the order of the enumerators is
6961 important as several tables in the AArch64 bfd backend are indexed
6962 by these enumerators; make sure they are all synced.
6964 BFD_RELOC_AARCH64_NULL
6966 Deprecated AArch64 null relocation code.
6968 BFD_RELOC_AARCH64_NONE
6970 AArch64 null relocation code.
6972 BFD_RELOC_AARCH64_64
6974 BFD_RELOC_AARCH64_32
6976 BFD_RELOC_AARCH64_16
6978 Basic absolute relocations of N bits. These are equivalent to
6979 BFD_RELOC_N and they were added to assist the indexing of the howto
6982 BFD_RELOC_AARCH64_64_PCREL
6984 BFD_RELOC_AARCH64_32_PCREL
6986 BFD_RELOC_AARCH64_16_PCREL
6988 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6989 and they were added to assist the indexing of the howto table.
6991 BFD_RELOC_AARCH64_MOVW_G0
6993 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6994 of an unsigned address/value.
6996 BFD_RELOC_AARCH64_MOVW_G0_NC
6998 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6999 an address/value. No overflow checking.
7001 BFD_RELOC_AARCH64_MOVW_G1
7003 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7004 of an unsigned address/value.
7006 BFD_RELOC_AARCH64_MOVW_G1_NC
7008 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7009 of an address/value. No overflow checking.
7011 BFD_RELOC_AARCH64_MOVW_G2
7013 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7014 of an unsigned address/value.
7016 BFD_RELOC_AARCH64_MOVW_G2_NC
7018 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7019 of an address/value. No overflow checking.
7021 BFD_RELOC_AARCH64_MOVW_G3
7023 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7024 of a signed or unsigned address/value.
7026 BFD_RELOC_AARCH64_MOVW_G0_S
7028 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7029 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7032 BFD_RELOC_AARCH64_MOVW_G1_S
7034 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7035 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7038 BFD_RELOC_AARCH64_MOVW_G2_S
7040 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7041 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7044 BFD_RELOC_AARCH64_MOVW_PREL_G0
7046 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7047 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7050 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7052 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7053 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7056 BFD_RELOC_AARCH64_MOVW_PREL_G1
7058 AArch64 MOVK instruction with most significant bits 16 to 31
7061 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7063 AArch64 MOVK instruction with most significant bits 16 to 31
7066 BFD_RELOC_AARCH64_MOVW_PREL_G2
7068 AArch64 MOVK instruction with most significant bits 32 to 47
7071 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7073 AArch64 MOVK instruction with most significant bits 32 to 47
7076 BFD_RELOC_AARCH64_MOVW_PREL_G3
7078 AArch64 MOVK instruction with most significant bits 47 to 63
7081 BFD_RELOC_AARCH64_LD_LO19_PCREL
7083 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7084 offset. The lowest two bits must be zero and are not stored in the
7085 instruction, giving a 21 bit signed byte offset.
7087 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7089 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7091 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7093 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7094 offset, giving a 4KB aligned page base address.
7096 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7098 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7099 offset, giving a 4KB aligned page base address, but with no overflow
7102 BFD_RELOC_AARCH64_ADD_LO12
7104 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7105 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7107 BFD_RELOC_AARCH64_LDST8_LO12
7109 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7110 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7112 BFD_RELOC_AARCH64_TSTBR14
7114 AArch64 14 bit pc-relative test bit and branch.
7115 The lowest two bits must be zero and are not stored in the instruction,
7116 giving a 16 bit signed byte offset.
7118 BFD_RELOC_AARCH64_BRANCH19
7120 AArch64 19 bit pc-relative conditional branch and compare & branch.
7121 The lowest two bits must be zero and are not stored in the instruction,
7122 giving a 21 bit signed byte offset.
7124 BFD_RELOC_AARCH64_JUMP26
7126 AArch64 26 bit pc-relative unconditional branch.
7127 The lowest two bits must be zero and are not stored in the instruction,
7128 giving a 28 bit signed byte offset.
7130 BFD_RELOC_AARCH64_CALL26
7132 AArch64 26 bit pc-relative unconditional branch and link.
7133 The lowest two bits must be zero and are not stored in the instruction,
7134 giving a 28 bit signed byte offset.
7136 BFD_RELOC_AARCH64_LDST16_LO12
7138 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7139 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7141 BFD_RELOC_AARCH64_LDST32_LO12
7143 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7144 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7146 BFD_RELOC_AARCH64_LDST64_LO12
7148 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7149 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7151 BFD_RELOC_AARCH64_LDST128_LO12
7153 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7154 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7156 BFD_RELOC_AARCH64_GOT_LD_PREL19
7158 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7159 offset of the global offset table entry for a symbol. The lowest two
7160 bits must be zero and are not stored in the instruction, giving a 21
7161 bit signed byte offset. This relocation type requires signed overflow
7164 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7166 Get to the page base of the global offset table entry for a symbol as
7167 part of an ADRP instruction using a 21 bit PC relative value.Used in
7168 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7170 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7172 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7173 the GOT entry for this symbol. Used in conjunction with
7174 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7176 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7178 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7179 the GOT entry for this symbol. Used in conjunction with
7180 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7182 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7184 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7185 for this symbol. Valid in LP64 ABI only.
7187 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7189 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7190 for this symbol. Valid in LP64 ABI only.
7192 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7194 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7195 the GOT entry for this symbol. Valid in LP64 ABI only.
7197 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7199 Scaled 14 bit byte offset to the page base of the global offset table.
7201 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7203 Scaled 15 bit byte offset to the page base of the global offset table.
7205 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7207 Get to the page base of the global offset table entry for a symbols
7208 tls_index structure as part of an adrp instruction using a 21 bit PC
7209 relative value. Used in conjunction with
7210 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7212 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7214 AArch64 TLS General Dynamic
7216 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7218 Unsigned 12 bit byte offset to global offset table entry for a symbols
7219 tls_index structure. Used in conjunction with
7220 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7222 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7224 AArch64 TLS General Dynamic relocation.
7226 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7228 AArch64 TLS General Dynamic relocation.
7230 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7232 AArch64 TLS INITIAL EXEC relocation.
7234 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7236 AArch64 TLS INITIAL EXEC relocation.
7238 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7240 AArch64 TLS INITIAL EXEC relocation.
7242 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7244 AArch64 TLS INITIAL EXEC relocation.
7246 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7248 AArch64 TLS INITIAL EXEC relocation.
7250 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7252 AArch64 TLS INITIAL EXEC relocation.
7254 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7256 bit[23:12] of byte offset to module TLS base address.
7258 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7260 Unsigned 12 bit byte offset to module TLS base address.
7262 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7264 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7266 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7268 Unsigned 12 bit byte offset to global offset table entry for a symbols
7269 tls_index structure. Used in conjunction with
7270 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7272 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7274 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7277 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7279 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7281 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7283 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7286 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7288 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7290 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7292 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7295 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7297 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7299 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7301 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7304 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7306 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7308 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7310 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7313 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7315 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7317 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7319 bit[15:0] of byte offset to module TLS base address.
7321 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7323 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7325 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7327 bit[31:16] of byte offset to module TLS base address.
7329 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7331 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7333 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7335 bit[47:32] of byte offset to module TLS base address.
7337 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7339 AArch64 TLS LOCAL EXEC relocation.
7341 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7343 AArch64 TLS LOCAL EXEC relocation.
7345 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7347 AArch64 TLS LOCAL EXEC relocation.
7349 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7351 AArch64 TLS LOCAL EXEC relocation.
7353 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7355 AArch64 TLS LOCAL EXEC relocation.
7357 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7359 AArch64 TLS LOCAL EXEC relocation.
7361 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7363 AArch64 TLS LOCAL EXEC relocation.
7365 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7367 AArch64 TLS LOCAL EXEC relocation.
7369 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7371 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7374 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7376 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7378 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7380 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7383 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7385 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7387 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7389 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7392 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7394 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7396 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7398 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7401 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7403 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7405 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7407 AArch64 TLS DESC relocation.
7409 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7411 AArch64 TLS DESC relocation.
7413 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7415 AArch64 TLS DESC relocation.
7417 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7419 AArch64 TLS DESC relocation.
7421 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7423 AArch64 TLS DESC relocation.
7425 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7427 AArch64 TLS DESC relocation.
7429 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7431 AArch64 TLS DESC relocation.
7433 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7435 AArch64 TLS DESC relocation.
7437 BFD_RELOC_AARCH64_TLSDESC_LDR
7439 AArch64 TLS DESC relocation.
7441 BFD_RELOC_AARCH64_TLSDESC_ADD
7443 AArch64 TLS DESC relocation.
7445 BFD_RELOC_AARCH64_TLSDESC_CALL
7447 AArch64 TLS DESC relocation.
7449 BFD_RELOC_AARCH64_COPY
7451 AArch64 TLS relocation.
7453 BFD_RELOC_AARCH64_GLOB_DAT
7455 AArch64 TLS relocation.
7457 BFD_RELOC_AARCH64_JUMP_SLOT
7459 AArch64 TLS relocation.
7461 BFD_RELOC_AARCH64_RELATIVE
7463 AArch64 TLS relocation.
7465 BFD_RELOC_AARCH64_TLS_DTPMOD
7467 AArch64 TLS relocation.
7469 BFD_RELOC_AARCH64_TLS_DTPREL
7471 AArch64 TLS relocation.
7473 BFD_RELOC_AARCH64_TLS_TPREL
7475 AArch64 TLS relocation.
7477 BFD_RELOC_AARCH64_TLSDESC
7479 AArch64 TLS relocation.
7481 BFD_RELOC_AARCH64_IRELATIVE
7483 AArch64 support for STT_GNU_IFUNC.
7485 BFD_RELOC_AARCH64_RELOC_END
7487 AArch64 pseudo relocation code to mark the end of the AArch64
7488 relocation enumerators that have direct mapping to ELF reloc codes.
7489 There are a few more enumerators after this one; those are mainly
7490 used by the AArch64 assembler for the internal fixup or to select
7491 one of the above enumerators.
7493 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7495 AArch64 pseudo relocation code to be used internally by the AArch64
7496 assembler and not (currently) written to any object files.
7498 BFD_RELOC_AARCH64_LDST_LO12
7500 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7501 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7503 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7505 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7506 used internally by the AArch64 assembler and not (currently) written to
7509 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7511 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7513 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7515 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7516 used internally by the AArch64 assembler and not (currently) written to
7519 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7521 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7523 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7525 AArch64 pseudo relocation code to be used internally by the AArch64
7526 assembler and not (currently) written to any object files.
7528 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7530 AArch64 pseudo relocation code to be used internally by the AArch64
7531 assembler and not (currently) written to any object files.
7533 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7535 AArch64 pseudo relocation code to be used internally by the AArch64
7536 assembler and not (currently) written to any object files.
7538 BFD_RELOC_TILEPRO_COPY
7540 BFD_RELOC_TILEPRO_GLOB_DAT
7542 BFD_RELOC_TILEPRO_JMP_SLOT
7544 BFD_RELOC_TILEPRO_RELATIVE
7546 BFD_RELOC_TILEPRO_BROFF_X1
7548 BFD_RELOC_TILEPRO_JOFFLONG_X1
7550 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7552 BFD_RELOC_TILEPRO_IMM8_X0
7554 BFD_RELOC_TILEPRO_IMM8_Y0
7556 BFD_RELOC_TILEPRO_IMM8_X1
7558 BFD_RELOC_TILEPRO_IMM8_Y1
7560 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7562 BFD_RELOC_TILEPRO_MT_IMM15_X1
7564 BFD_RELOC_TILEPRO_MF_IMM15_X1
7566 BFD_RELOC_TILEPRO_IMM16_X0
7568 BFD_RELOC_TILEPRO_IMM16_X1
7570 BFD_RELOC_TILEPRO_IMM16_X0_LO
7572 BFD_RELOC_TILEPRO_IMM16_X1_LO
7574 BFD_RELOC_TILEPRO_IMM16_X0_HI
7576 BFD_RELOC_TILEPRO_IMM16_X1_HI
7578 BFD_RELOC_TILEPRO_IMM16_X0_HA
7580 BFD_RELOC_TILEPRO_IMM16_X1_HA
7582 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7584 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7586 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7588 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7590 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7592 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7594 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7596 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7598 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7600 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7602 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7604 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7606 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7608 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7610 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7612 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7614 BFD_RELOC_TILEPRO_MMSTART_X0
7616 BFD_RELOC_TILEPRO_MMEND_X0
7618 BFD_RELOC_TILEPRO_MMSTART_X1
7620 BFD_RELOC_TILEPRO_MMEND_X1
7622 BFD_RELOC_TILEPRO_SHAMT_X0
7624 BFD_RELOC_TILEPRO_SHAMT_X1
7626 BFD_RELOC_TILEPRO_SHAMT_Y0
7628 BFD_RELOC_TILEPRO_SHAMT_Y1
7630 BFD_RELOC_TILEPRO_TLS_GD_CALL
7632 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7634 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7636 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7638 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7640 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7642 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7644 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7646 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7648 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7650 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7652 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7654 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7656 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7658 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7660 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7662 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7664 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7666 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7668 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7670 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7672 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7674 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7676 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7678 BFD_RELOC_TILEPRO_TLS_TPOFF32
7680 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7682 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7684 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7686 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7688 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7690 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7692 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7694 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7696 Tilera TILEPro Relocations.
7698 BFD_RELOC_TILEGX_HW0
7700 BFD_RELOC_TILEGX_HW1
7702 BFD_RELOC_TILEGX_HW2
7704 BFD_RELOC_TILEGX_HW3
7706 BFD_RELOC_TILEGX_HW0_LAST
7708 BFD_RELOC_TILEGX_HW1_LAST
7710 BFD_RELOC_TILEGX_HW2_LAST
7712 BFD_RELOC_TILEGX_COPY
7714 BFD_RELOC_TILEGX_GLOB_DAT
7716 BFD_RELOC_TILEGX_JMP_SLOT
7718 BFD_RELOC_TILEGX_RELATIVE
7720 BFD_RELOC_TILEGX_BROFF_X1
7722 BFD_RELOC_TILEGX_JUMPOFF_X1
7724 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7726 BFD_RELOC_TILEGX_IMM8_X0
7728 BFD_RELOC_TILEGX_IMM8_Y0
7730 BFD_RELOC_TILEGX_IMM8_X1
7732 BFD_RELOC_TILEGX_IMM8_Y1
7734 BFD_RELOC_TILEGX_DEST_IMM8_X1
7736 BFD_RELOC_TILEGX_MT_IMM14_X1
7738 BFD_RELOC_TILEGX_MF_IMM14_X1
7740 BFD_RELOC_TILEGX_MMSTART_X0
7742 BFD_RELOC_TILEGX_MMEND_X0
7744 BFD_RELOC_TILEGX_SHAMT_X0
7746 BFD_RELOC_TILEGX_SHAMT_X1
7748 BFD_RELOC_TILEGX_SHAMT_Y0
7750 BFD_RELOC_TILEGX_SHAMT_Y1
7752 BFD_RELOC_TILEGX_IMM16_X0_HW0
7754 BFD_RELOC_TILEGX_IMM16_X1_HW0
7756 BFD_RELOC_TILEGX_IMM16_X0_HW1
7758 BFD_RELOC_TILEGX_IMM16_X1_HW1
7760 BFD_RELOC_TILEGX_IMM16_X0_HW2
7762 BFD_RELOC_TILEGX_IMM16_X1_HW2
7764 BFD_RELOC_TILEGX_IMM16_X0_HW3
7766 BFD_RELOC_TILEGX_IMM16_X1_HW3
7768 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7770 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7772 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7774 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7776 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7778 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7780 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7782 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7784 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7786 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7788 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7790 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7792 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7794 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7796 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7798 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7800 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7802 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7804 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7806 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7808 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7810 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7812 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7814 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7816 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7818 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7820 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7822 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7824 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7826 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7828 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7830 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7832 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7834 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7836 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7838 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7840 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7842 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7844 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7846 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7848 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7850 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7852 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7854 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7856 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7858 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7860 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7862 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7864 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7866 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7868 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7870 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7872 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7874 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7876 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7878 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7880 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7882 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7884 BFD_RELOC_TILEGX_TLS_DTPMOD64
7886 BFD_RELOC_TILEGX_TLS_DTPOFF64
7888 BFD_RELOC_TILEGX_TLS_TPOFF64
7890 BFD_RELOC_TILEGX_TLS_DTPMOD32
7892 BFD_RELOC_TILEGX_TLS_DTPOFF32
7894 BFD_RELOC_TILEGX_TLS_TPOFF32
7896 BFD_RELOC_TILEGX_TLS_GD_CALL
7898 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7900 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7902 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7904 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7906 BFD_RELOC_TILEGX_TLS_IE_LOAD
7908 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7910 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7912 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7914 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7916 Tilera TILE-Gx Relocations.
7919 BFD_RELOC_EPIPHANY_SIMM8
7921 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7923 BFD_RELOC_EPIPHANY_SIMM24
7925 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7927 BFD_RELOC_EPIPHANY_HIGH
7929 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7931 BFD_RELOC_EPIPHANY_LOW
7933 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7935 BFD_RELOC_EPIPHANY_SIMM11
7937 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7939 BFD_RELOC_EPIPHANY_IMM11
7941 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7943 BFD_RELOC_EPIPHANY_IMM8
7945 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7948 BFD_RELOC_VISIUM_HI16
7950 BFD_RELOC_VISIUM_LO16
7952 BFD_RELOC_VISIUM_IM16
7954 BFD_RELOC_VISIUM_REL16
7956 BFD_RELOC_VISIUM_HI16_PCREL
7958 BFD_RELOC_VISIUM_LO16_PCREL
7960 BFD_RELOC_VISIUM_IM16_PCREL
7965 BFD_RELOC_WASM32_LEB128
7967 BFD_RELOC_WASM32_LEB128_GOT
7969 BFD_RELOC_WASM32_LEB128_GOT_CODE
7971 BFD_RELOC_WASM32_LEB128_PLT
7973 BFD_RELOC_WASM32_PLT_INDEX
7975 BFD_RELOC_WASM32_ABS32_CODE
7977 BFD_RELOC_WASM32_COPY
7979 BFD_RELOC_WASM32_CODE_POINTER
7981 BFD_RELOC_WASM32_INDEX
7983 BFD_RELOC_WASM32_PLT_SIG
7985 WebAssembly relocations.
7991 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7996 bfd_reloc_type_lookup
7997 bfd_reloc_name_lookup
8000 reloc_howto_type *bfd_reloc_type_lookup
8001 (bfd *abfd, bfd_reloc_code_real_type code);
8002 reloc_howto_type *bfd_reloc_name_lookup
8003 (bfd *abfd, const char *reloc_name);
8006 Return a pointer to a howto structure which, when
8007 invoked, will perform the relocation @var{code} on data from the
8013 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8015 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
8019 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
8021 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
8024 static reloc_howto_type bfd_howto_32 =
8025 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
8029 bfd_default_reloc_type_lookup
8032 reloc_howto_type *bfd_default_reloc_type_lookup
8033 (bfd *abfd, bfd_reloc_code_real_type code);
8036 Provides a default relocation lookup routine for any architecture.
8041 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8045 case BFD_RELOC_CTOR:
8046 /* The type of reloc used in a ctor, which will be as wide as the
8047 address - so either a 64, 32, or 16 bitter. */
8048 switch (bfd_arch_bits_per_address (abfd))
8054 return &bfd_howto_32;
8070 bfd_get_reloc_code_name
8073 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8076 Provides a printable name for the supplied relocation code.
8077 Useful mainly for printing error messages.
8081 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
8083 if (code > BFD_RELOC_UNUSED)
8085 return bfd_reloc_code_real_names[code];
8090 bfd_generic_relax_section
8093 bfd_boolean bfd_generic_relax_section
8096 struct bfd_link_info *,
8100 Provides default handling for relaxing for back ends which
8105 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
8106 asection *section ATTRIBUTE_UNUSED,
8107 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
8110 if (bfd_link_relocatable (link_info))
8111 (*link_info->callbacks->einfo)
8112 (_("%P%F: --relax and -r may not be used together\n"));
8120 bfd_generic_gc_sections
8123 bfd_boolean bfd_generic_gc_sections
8124 (bfd *, struct bfd_link_info *);
8127 Provides default handling for relaxing for back ends which
8128 don't do section gc -- i.e., does nothing.
8132 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
8133 struct bfd_link_info *info ATTRIBUTE_UNUSED)
8140 bfd_generic_lookup_section_flags
8143 bfd_boolean bfd_generic_lookup_section_flags
8144 (struct bfd_link_info *, struct flag_info *, asection *);
8147 Provides default handling for section flags lookup
8148 -- i.e., does nothing.
8149 Returns FALSE if the section should be omitted, otherwise TRUE.
8153 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
8154 struct flag_info *flaginfo,
8155 asection *section ATTRIBUTE_UNUSED)
8157 if (flaginfo != NULL)
8159 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8167 bfd_generic_merge_sections
8170 bfd_boolean bfd_generic_merge_sections
8171 (bfd *, struct bfd_link_info *);
8174 Provides default handling for SEC_MERGE section merging for back ends
8175 which don't have SEC_MERGE support -- i.e., does nothing.
8179 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
8180 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
8187 bfd_generic_get_relocated_section_contents
8190 bfd_byte *bfd_generic_get_relocated_section_contents
8192 struct bfd_link_info *link_info,
8193 struct bfd_link_order *link_order,
8195 bfd_boolean relocatable,
8199 Provides default handling of relocation effort for back ends
8200 which can't be bothered to do it efficiently.
8205 bfd_generic_get_relocated_section_contents (bfd *abfd,
8206 struct bfd_link_info *link_info,
8207 struct bfd_link_order *link_order,
8209 bfd_boolean relocatable,
8212 bfd *input_bfd = link_order->u.indirect.section->owner;
8213 asection *input_section = link_order->u.indirect.section;
8215 arelent **reloc_vector;
8218 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
8222 /* Read in the section. */
8223 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
8229 if (reloc_size == 0)
8232 reloc_vector = (arelent **) bfd_malloc (reloc_size);
8233 if (reloc_vector == NULL)
8236 reloc_count = bfd_canonicalize_reloc (input_bfd,
8240 if (reloc_count < 0)
8243 if (reloc_count > 0)
8247 for (parent = reloc_vector; *parent != NULL; parent++)
8249 char *error_message = NULL;
8251 bfd_reloc_status_type r;
8253 symbol = *(*parent)->sym_ptr_ptr;
8254 /* PR ld/19628: A specially crafted input file
8255 can result in a NULL symbol pointer here. */
8258 link_info->callbacks->einfo
8259 /* xgettext:c-format */
8260 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8261 abfd, input_section, (* parent)->address);
8265 if (symbol->section && discarded_section (symbol->section))
8268 static reloc_howto_type none_howto
8269 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
8270 "unused", FALSE, 0, 0, FALSE);
8272 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
8273 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
8275 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
8276 (*parent)->addend = 0;
8277 (*parent)->howto = &none_howto;
8281 r = bfd_perform_relocation (input_bfd,
8285 relocatable ? abfd : NULL,
8290 asection *os = input_section->output_section;
8292 /* A partial link, so keep the relocs. */
8293 os->orelocation[os->reloc_count] = *parent;
8297 if (r != bfd_reloc_ok)
8301 case bfd_reloc_undefined:
8302 (*link_info->callbacks->undefined_symbol)
8303 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8304 input_bfd, input_section, (*parent)->address, TRUE);
8306 case bfd_reloc_dangerous:
8307 BFD_ASSERT (error_message != NULL);
8308 (*link_info->callbacks->reloc_dangerous)
8309 (link_info, error_message,
8310 input_bfd, input_section, (*parent)->address);
8312 case bfd_reloc_overflow:
8313 (*link_info->callbacks->reloc_overflow)
8315 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8316 (*parent)->howto->name, (*parent)->addend,
8317 input_bfd, input_section, (*parent)->address);
8319 case bfd_reloc_outofrange:
8321 This error can result when processing some partially
8322 complete binaries. Do not abort, but issue an error
8324 link_info->callbacks->einfo
8325 /* xgettext:c-format */
8326 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8327 abfd, input_section, * parent);
8330 case bfd_reloc_notsupported:
8332 This error can result when processing a corrupt binary.
8333 Do not abort. Issue an error message instead. */
8334 link_info->callbacks->einfo
8335 /* xgettext:c-format */
8336 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8337 abfd, input_section, * parent);
8341 /* PR 17512; file: 90c2a92e.
8342 Report unexpected results, without aborting. */
8343 link_info->callbacks->einfo
8344 /* xgettext:c-format */
8345 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8346 abfd, input_section, * parent, r);
8354 free (reloc_vector);
8358 free (reloc_vector);
8364 _bfd_generic_set_reloc
8367 void _bfd_generic_set_reloc
8371 unsigned int count);
8374 Installs a new set of internal relocations in SECTION.
8378 _bfd_generic_set_reloc (bfd *abfd ATTRIBUTE_UNUSED,
8383 section->orelocation = relptr;
8384 section->reloc_count = count;
8389 _bfd_unrecognized_reloc
8392 bfd_boolean _bfd_unrecognized_reloc
8395 unsigned int r_type);
8398 Reports an unrecognized reloc.
8399 Written as a function in order to reduce code duplication.
8400 Returns FALSE so that it can be called from a return statement.
8404 _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type)
8406 /* xgettext:c-format */
8407 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8408 abfd, r_type, section);
8410 /* PR 21803: Suggest the most likely cause of this error. */
8411 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8412 BFD_VERSION_STRING);
8414 bfd_set_error (bfd_error_bad_value);
8419 _bfd_norelocs_bfd_reloc_type_lookup
8421 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED)
8423 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8427 _bfd_norelocs_bfd_reloc_name_lookup (bfd *abfd,
8428 const char *reloc_name ATTRIBUTE_UNUSED)
8430 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8434 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd *abfd,
8435 arelent **relp ATTRIBUTE_UNUSED,
8436 asymbol **symp ATTRIBUTE_UNUSED)
8438 return _bfd_long_bfd_n1_error (abfd);