1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type *howto)
451 How relocs are tied together in an <<asection>>:
453 .typedef struct relent_chain
456 . struct relent_chain *next;
462 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
463 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
470 bfd_reloc_status_type bfd_check_overflow
471 (enum complain_overflow how,
472 unsigned int bitsize,
473 unsigned int rightshift,
474 unsigned int addrsize,
478 Perform overflow checking on @var{relocation} which has
479 @var{bitsize} significant bits and will be shifted right by
480 @var{rightshift} bits, on a machine with addresses containing
481 @var{addrsize} significant bits. The result is either of
482 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
486 bfd_reloc_status_type
487 bfd_check_overflow (enum complain_overflow how,
488 unsigned int bitsize,
489 unsigned int rightshift,
490 unsigned int addrsize,
493 bfd_vma fieldmask, addrmask, signmask, ss, a;
494 bfd_reloc_status_type flag = bfd_reloc_ok;
496 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
497 we'll be permissive: extra bits in the field mask will
498 automatically extend the address mask for purposes of the
500 fieldmask = N_ONES (bitsize);
501 signmask = ~fieldmask;
502 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
503 a = (relocation & addrmask) >> rightshift;
507 case complain_overflow_dont:
510 case complain_overflow_signed:
511 /* If any sign bits are set, all sign bits must be set. That
512 is, A must be a valid negative address after shifting. */
513 signmask = ~ (fieldmask >> 1);
516 case complain_overflow_bitfield:
517 /* Bitfields are sometimes signed, sometimes unsigned. We
518 explicitly allow an address wrap too, which means a bitfield
519 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
520 if the value has some, but not all, bits set outside the
523 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
524 flag = bfd_reloc_overflow;
527 case complain_overflow_unsigned:
528 /* We have an overflow if the address does not fit in the field. */
529 if ((a & signmask) != 0)
530 flag = bfd_reloc_overflow;
542 bfd_perform_relocation
545 bfd_reloc_status_type bfd_perform_relocation
547 arelent *reloc_entry,
549 asection *input_section,
551 char **error_message);
554 If @var{output_bfd} is supplied to this function, the
555 generated image will be relocatable; the relocations are
556 copied to the output file after they have been changed to
557 reflect the new state of the world. There are two ways of
558 reflecting the results of partial linkage in an output file:
559 by modifying the output data in place, and by modifying the
560 relocation record. Some native formats (e.g., basic a.out and
561 basic coff) have no way of specifying an addend in the
562 relocation type, so the addend has to go in the output data.
563 This is no big deal since in these formats the output data
564 slot will always be big enough for the addend. Complex reloc
565 types with addends were invented to solve just this problem.
566 The @var{error_message} argument is set to an error message if
567 this return @code{bfd_reloc_dangerous}.
571 bfd_reloc_status_type
572 bfd_perform_relocation (bfd *abfd,
573 arelent *reloc_entry,
575 asection *input_section,
577 char **error_message)
580 bfd_reloc_status_type flag = bfd_reloc_ok;
581 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
582 bfd_vma output_base = 0;
583 reloc_howto_type *howto = reloc_entry->howto;
584 asection *reloc_target_output_section;
587 symbol = *(reloc_entry->sym_ptr_ptr);
588 if (bfd_is_abs_section (symbol->section)
589 && output_bfd != NULL)
591 reloc_entry->address += input_section->output_offset;
595 /* If we are not producing relocatable output, return an error if
596 the symbol is not defined. An undefined weak symbol is
597 considered to have a value of zero (SVR4 ABI, p. 4-27). */
598 if (bfd_is_und_section (symbol->section)
599 && (symbol->flags & BSF_WEAK) == 0
600 && output_bfd == NULL)
601 flag = bfd_reloc_undefined;
603 /* If there is a function supplied to handle this relocation type,
604 call it. It'll return `bfd_reloc_continue' if further processing
606 if (howto->special_function)
608 bfd_reloc_status_type cont;
609 cont = howto->special_function (abfd, reloc_entry, symbol, data,
610 input_section, output_bfd,
612 if (cont != bfd_reloc_continue)
616 /* Is the address of the relocation really within the section? */
617 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
618 return bfd_reloc_outofrange;
620 /* Work out which section the relocation is targeted at and the
621 initial relocation command value. */
623 /* Get symbol value. (Common symbols are special.) */
624 if (bfd_is_com_section (symbol->section))
627 relocation = symbol->value;
629 reloc_target_output_section = symbol->section->output_section;
631 /* Convert input-section-relative symbol value to absolute. */
632 if ((output_bfd && ! howto->partial_inplace)
633 || reloc_target_output_section == NULL)
636 output_base = reloc_target_output_section->vma;
638 relocation += output_base + symbol->section->output_offset;
640 /* Add in supplied addend. */
641 relocation += reloc_entry->addend;
643 /* Here the variable relocation holds the final address of the
644 symbol we are relocating against, plus any addend. */
646 if (howto->pc_relative)
648 /* This is a PC relative relocation. We want to set RELOCATION
649 to the distance between the address of the symbol and the
650 location. RELOCATION is already the address of the symbol.
652 We start by subtracting the address of the section containing
655 If pcrel_offset is set, we must further subtract the position
656 of the location within the section. Some targets arrange for
657 the addend to be the negative of the position of the location
658 within the section; for example, i386-aout does this. For
659 i386-aout, pcrel_offset is FALSE. Some other targets do not
660 include the position of the location; for example, m88kbcs,
661 or ELF. For those targets, pcrel_offset is TRUE.
663 If we are producing relocatable output, then we must ensure
664 that this reloc will be correctly computed when the final
665 relocation is done. If pcrel_offset is FALSE we want to wind
666 up with the negative of the location within the section,
667 which means we must adjust the existing addend by the change
668 in the location within the section. If pcrel_offset is TRUE
669 we do not want to adjust the existing addend at all.
671 FIXME: This seems logical to me, but for the case of
672 producing relocatable output it is not what the code
673 actually does. I don't want to change it, because it seems
674 far too likely that something will break. */
677 input_section->output_section->vma + input_section->output_offset;
679 if (howto->pcrel_offset)
680 relocation -= reloc_entry->address;
683 if (output_bfd != NULL)
685 if (! howto->partial_inplace)
687 /* This is a partial relocation, and we want to apply the relocation
688 to the reloc entry rather than the raw data. Modify the reloc
689 inplace to reflect what we now know. */
690 reloc_entry->addend = relocation;
691 reloc_entry->address += input_section->output_offset;
696 /* This is a partial relocation, but inplace, so modify the
699 If we've relocated with a symbol with a section, change
700 into a ref to the section belonging to the symbol. */
702 reloc_entry->address += input_section->output_offset;
705 if (abfd->xvec->flavour == bfd_target_coff_flavour
706 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
707 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
709 /* For m68k-coff, the addend was being subtracted twice during
710 relocation with -r. Removing the line below this comment
711 fixes that problem; see PR 2953.
713 However, Ian wrote the following, regarding removing the line below,
714 which explains why it is still enabled: --djm
716 If you put a patch like that into BFD you need to check all the COFF
717 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
718 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
719 problem in a different way. There may very well be a reason that the
720 code works as it does.
722 Hmmm. The first obvious point is that bfd_perform_relocation should
723 not have any tests that depend upon the flavour. It's seem like
724 entirely the wrong place for such a thing. The second obvious point
725 is that the current code ignores the reloc addend when producing
726 relocatable output for COFF. That's peculiar. In fact, I really
727 have no idea what the point of the line you want to remove is.
729 A typical COFF reloc subtracts the old value of the symbol and adds in
730 the new value to the location in the object file (if it's a pc
731 relative reloc it adds the difference between the symbol value and the
732 location). When relocating we need to preserve that property.
734 BFD handles this by setting the addend to the negative of the old
735 value of the symbol. Unfortunately it handles common symbols in a
736 non-standard way (it doesn't subtract the old value) but that's a
737 different story (we can't change it without losing backward
738 compatibility with old object files) (coff-i386 does subtract the old
739 value, to be compatible with existing coff-i386 targets, like SCO).
741 So everything works fine when not producing relocatable output. When
742 we are producing relocatable output, logically we should do exactly
743 what we do when not producing relocatable output. Therefore, your
744 patch is correct. In fact, it should probably always just set
745 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
746 add the value into the object file. This won't hurt the COFF code,
747 which doesn't use the addend; I'm not sure what it will do to other
748 formats (the thing to check for would be whether any formats both use
749 the addend and set partial_inplace).
751 When I wanted to make coff-i386 produce relocatable output, I ran
752 into the problem that you are running into: I wanted to remove that
753 line. Rather than risk it, I made the coff-i386 relocs use a special
754 function; it's coff_i386_reloc in coff-i386.c. The function
755 specifically adds the addend field into the object file, knowing that
756 bfd_perform_relocation is not going to. If you remove that line, then
757 coff-i386.c will wind up adding the addend field in twice. It's
758 trivial to fix; it just needs to be done.
760 The problem with removing the line is just that it may break some
761 working code. With BFD it's hard to be sure of anything. The right
762 way to deal with this is simply to build and test at least all the
763 supported COFF targets. It should be straightforward if time and disk
764 space consuming. For each target:
766 2) generate some executable, and link it using -r (I would
767 probably use paranoia.o and link against newlib/libc.a, which
768 for all the supported targets would be available in
769 /usr/cygnus/progressive/H-host/target/lib/libc.a).
770 3) make the change to reloc.c
771 4) rebuild the linker
773 6) if the resulting object files are the same, you have at least
775 7) if they are different you have to figure out which version is
778 relocation -= reloc_entry->addend;
779 reloc_entry->addend = 0;
783 reloc_entry->addend = relocation;
788 /* FIXME: This overflow checking is incomplete, because the value
789 might have overflowed before we get here. For a correct check we
790 need to compute the value in a size larger than bitsize, but we
791 can't reasonably do that for a reloc the same size as a host
793 FIXME: We should also do overflow checking on the result after
794 adding in the value contained in the object file. */
795 if (howto->complain_on_overflow != complain_overflow_dont
796 && flag == bfd_reloc_ok)
797 flag = bfd_check_overflow (howto->complain_on_overflow,
800 bfd_arch_bits_per_address (abfd),
803 /* Either we are relocating all the way, or we don't want to apply
804 the relocation to the reloc entry (probably because there isn't
805 any room in the output format to describe addends to relocs). */
807 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
808 (OSF version 1.3, compiler version 3.11). It miscompiles the
822 x <<= (unsigned long) s.i0;
826 printf ("succeeded (%lx)\n", x);
830 relocation >>= (bfd_vma) howto->rightshift;
832 /* Shift everything up to where it's going to be used. */
833 relocation <<= (bfd_vma) howto->bitpos;
835 /* Wait for the day when all have the mask in them. */
838 i instruction to be left alone
839 o offset within instruction
840 r relocation offset to apply
849 (( i i i i i o o o o o from bfd_get<size>
850 and S S S S S) to get the size offset we want
851 + r r r r r r r r r r) to get the final value to place
852 and D D D D D to chop to right size
853 -----------------------
856 ( i i i i i o o o o o from bfd_get<size>
857 and N N N N N ) get instruction
858 -----------------------
864 -----------------------
865 = R R R R R R R R R R put into bfd_put<size>
869 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
875 char x = bfd_get_8 (abfd, (char *) data + octets);
877 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
883 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
885 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
890 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
892 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
897 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
898 relocation = -relocation;
900 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
906 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
907 relocation = -relocation;
909 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
920 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
922 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
929 return bfd_reloc_other;
937 bfd_install_relocation
940 bfd_reloc_status_type bfd_install_relocation
942 arelent *reloc_entry,
943 void *data, bfd_vma data_start,
944 asection *input_section,
945 char **error_message);
948 This looks remarkably like <<bfd_perform_relocation>>, except it
949 does not expect that the section contents have been filled in.
950 I.e., it's suitable for use when creating, rather than applying
953 For now, this function should be considered reserved for the
957 bfd_reloc_status_type
958 bfd_install_relocation (bfd *abfd,
959 arelent *reloc_entry,
961 bfd_vma data_start_offset,
962 asection *input_section,
963 char **error_message)
966 bfd_reloc_status_type flag = bfd_reloc_ok;
967 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
968 bfd_vma output_base = 0;
969 reloc_howto_type *howto = reloc_entry->howto;
970 asection *reloc_target_output_section;
974 symbol = *(reloc_entry->sym_ptr_ptr);
975 if (bfd_is_abs_section (symbol->section))
977 reloc_entry->address += input_section->output_offset;
981 /* If there is a function supplied to handle this relocation type,
982 call it. It'll return `bfd_reloc_continue' if further processing
984 if (howto->special_function)
986 bfd_reloc_status_type cont;
988 /* XXX - The special_function calls haven't been fixed up to deal
989 with creating new relocations and section contents. */
990 cont = howto->special_function (abfd, reloc_entry, symbol,
991 /* XXX - Non-portable! */
992 ((bfd_byte *) data_start
993 - data_start_offset),
994 input_section, abfd, error_message);
995 if (cont != bfd_reloc_continue)
999 /* Is the address of the relocation really within the section? */
1000 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
1001 return bfd_reloc_outofrange;
1003 /* Work out which section the relocation is targeted at and the
1004 initial relocation command value. */
1006 /* Get symbol value. (Common symbols are special.) */
1007 if (bfd_is_com_section (symbol->section))
1010 relocation = symbol->value;
1012 reloc_target_output_section = symbol->section->output_section;
1014 /* Convert input-section-relative symbol value to absolute. */
1015 if (! howto->partial_inplace)
1018 output_base = reloc_target_output_section->vma;
1020 relocation += output_base + symbol->section->output_offset;
1022 /* Add in supplied addend. */
1023 relocation += reloc_entry->addend;
1025 /* Here the variable relocation holds the final address of the
1026 symbol we are relocating against, plus any addend. */
1028 if (howto->pc_relative)
1030 /* This is a PC relative relocation. We want to set RELOCATION
1031 to the distance between the address of the symbol and the
1032 location. RELOCATION is already the address of the symbol.
1034 We start by subtracting the address of the section containing
1037 If pcrel_offset is set, we must further subtract the position
1038 of the location within the section. Some targets arrange for
1039 the addend to be the negative of the position of the location
1040 within the section; for example, i386-aout does this. For
1041 i386-aout, pcrel_offset is FALSE. Some other targets do not
1042 include the position of the location; for example, m88kbcs,
1043 or ELF. For those targets, pcrel_offset is TRUE.
1045 If we are producing relocatable output, then we must ensure
1046 that this reloc will be correctly computed when the final
1047 relocation is done. If pcrel_offset is FALSE we want to wind
1048 up with the negative of the location within the section,
1049 which means we must adjust the existing addend by the change
1050 in the location within the section. If pcrel_offset is TRUE
1051 we do not want to adjust the existing addend at all.
1053 FIXME: This seems logical to me, but for the case of
1054 producing relocatable output it is not what the code
1055 actually does. I don't want to change it, because it seems
1056 far too likely that something will break. */
1059 input_section->output_section->vma + input_section->output_offset;
1061 if (howto->pcrel_offset && howto->partial_inplace)
1062 relocation -= reloc_entry->address;
1065 if (! howto->partial_inplace)
1067 /* This is a partial relocation, and we want to apply the relocation
1068 to the reloc entry rather than the raw data. Modify the reloc
1069 inplace to reflect what we now know. */
1070 reloc_entry->addend = relocation;
1071 reloc_entry->address += input_section->output_offset;
1076 /* This is a partial relocation, but inplace, so modify the
1079 If we've relocated with a symbol with a section, change
1080 into a ref to the section belonging to the symbol. */
1081 reloc_entry->address += input_section->output_offset;
1084 if (abfd->xvec->flavour == bfd_target_coff_flavour
1085 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1086 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1089 /* For m68k-coff, the addend was being subtracted twice during
1090 relocation with -r. Removing the line below this comment
1091 fixes that problem; see PR 2953.
1093 However, Ian wrote the following, regarding removing the line below,
1094 which explains why it is still enabled: --djm
1096 If you put a patch like that into BFD you need to check all the COFF
1097 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1098 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1099 problem in a different way. There may very well be a reason that the
1100 code works as it does.
1102 Hmmm. The first obvious point is that bfd_install_relocation should
1103 not have any tests that depend upon the flavour. It's seem like
1104 entirely the wrong place for such a thing. The second obvious point
1105 is that the current code ignores the reloc addend when producing
1106 relocatable output for COFF. That's peculiar. In fact, I really
1107 have no idea what the point of the line you want to remove is.
1109 A typical COFF reloc subtracts the old value of the symbol and adds in
1110 the new value to the location in the object file (if it's a pc
1111 relative reloc it adds the difference between the symbol value and the
1112 location). When relocating we need to preserve that property.
1114 BFD handles this by setting the addend to the negative of the old
1115 value of the symbol. Unfortunately it handles common symbols in a
1116 non-standard way (it doesn't subtract the old value) but that's a
1117 different story (we can't change it without losing backward
1118 compatibility with old object files) (coff-i386 does subtract the old
1119 value, to be compatible with existing coff-i386 targets, like SCO).
1121 So everything works fine when not producing relocatable output. When
1122 we are producing relocatable output, logically we should do exactly
1123 what we do when not producing relocatable output. Therefore, your
1124 patch is correct. In fact, it should probably always just set
1125 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1126 add the value into the object file. This won't hurt the COFF code,
1127 which doesn't use the addend; I'm not sure what it will do to other
1128 formats (the thing to check for would be whether any formats both use
1129 the addend and set partial_inplace).
1131 When I wanted to make coff-i386 produce relocatable output, I ran
1132 into the problem that you are running into: I wanted to remove that
1133 line. Rather than risk it, I made the coff-i386 relocs use a special
1134 function; it's coff_i386_reloc in coff-i386.c. The function
1135 specifically adds the addend field into the object file, knowing that
1136 bfd_install_relocation is not going to. If you remove that line, then
1137 coff-i386.c will wind up adding the addend field in twice. It's
1138 trivial to fix; it just needs to be done.
1140 The problem with removing the line is just that it may break some
1141 working code. With BFD it's hard to be sure of anything. The right
1142 way to deal with this is simply to build and test at least all the
1143 supported COFF targets. It should be straightforward if time and disk
1144 space consuming. For each target:
1146 2) generate some executable, and link it using -r (I would
1147 probably use paranoia.o and link against newlib/libc.a, which
1148 for all the supported targets would be available in
1149 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1150 3) make the change to reloc.c
1151 4) rebuild the linker
1153 6) if the resulting object files are the same, you have at least
1155 7) if they are different you have to figure out which version is
1157 relocation -= reloc_entry->addend;
1158 /* FIXME: There should be no target specific code here... */
1159 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1160 reloc_entry->addend = 0;
1164 reloc_entry->addend = relocation;
1168 /* FIXME: This overflow checking is incomplete, because the value
1169 might have overflowed before we get here. For a correct check we
1170 need to compute the value in a size larger than bitsize, but we
1171 can't reasonably do that for a reloc the same size as a host
1173 FIXME: We should also do overflow checking on the result after
1174 adding in the value contained in the object file. */
1175 if (howto->complain_on_overflow != complain_overflow_dont)
1176 flag = bfd_check_overflow (howto->complain_on_overflow,
1179 bfd_arch_bits_per_address (abfd),
1182 /* Either we are relocating all the way, or we don't want to apply
1183 the relocation to the reloc entry (probably because there isn't
1184 any room in the output format to describe addends to relocs). */
1186 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1187 (OSF version 1.3, compiler version 3.11). It miscompiles the
1201 x <<= (unsigned long) s.i0;
1203 printf ("failed\n");
1205 printf ("succeeded (%lx)\n", x);
1209 relocation >>= (bfd_vma) howto->rightshift;
1211 /* Shift everything up to where it's going to be used. */
1212 relocation <<= (bfd_vma) howto->bitpos;
1214 /* Wait for the day when all have the mask in them. */
1217 i instruction to be left alone
1218 o offset within instruction
1219 r relocation offset to apply
1228 (( i i i i i o o o o o from bfd_get<size>
1229 and S S S S S) to get the size offset we want
1230 + r r r r r r r r r r) to get the final value to place
1231 and D D D D D to chop to right size
1232 -----------------------
1235 ( i i i i i o o o o o from bfd_get<size>
1236 and N N N N N ) get instruction
1237 -----------------------
1243 -----------------------
1244 = R R R R R R R R R R put into bfd_put<size>
1248 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1250 data = (bfd_byte *) data_start + (octets - data_start_offset);
1252 switch (howto->size)
1256 char x = bfd_get_8 (abfd, data);
1258 bfd_put_8 (abfd, x, data);
1264 short x = bfd_get_16 (abfd, data);
1266 bfd_put_16 (abfd, (bfd_vma) x, data);
1271 long x = bfd_get_32 (abfd, data);
1273 bfd_put_32 (abfd, (bfd_vma) x, data);
1278 long x = bfd_get_32 (abfd, data);
1279 relocation = -relocation;
1281 bfd_put_32 (abfd, (bfd_vma) x, data);
1291 bfd_vma x = bfd_get_64 (abfd, data);
1293 bfd_put_64 (abfd, x, data);
1297 return bfd_reloc_other;
1303 /* This relocation routine is used by some of the backend linkers.
1304 They do not construct asymbol or arelent structures, so there is no
1305 reason for them to use bfd_perform_relocation. Also,
1306 bfd_perform_relocation is so hacked up it is easier to write a new
1307 function than to try to deal with it.
1309 This routine does a final relocation. Whether it is useful for a
1310 relocatable link depends upon how the object format defines
1313 FIXME: This routine ignores any special_function in the HOWTO,
1314 since the existing special_function values have been written for
1315 bfd_perform_relocation.
1317 HOWTO is the reloc howto information.
1318 INPUT_BFD is the BFD which the reloc applies to.
1319 INPUT_SECTION is the section which the reloc applies to.
1320 CONTENTS is the contents of the section.
1321 ADDRESS is the address of the reloc within INPUT_SECTION.
1322 VALUE is the value of the symbol the reloc refers to.
1323 ADDEND is the addend of the reloc. */
1325 bfd_reloc_status_type
1326 _bfd_final_link_relocate (reloc_howto_type *howto,
1328 asection *input_section,
1336 /* Sanity check the address. */
1337 if (address > bfd_get_section_limit (input_bfd, input_section))
1338 return bfd_reloc_outofrange;
1340 /* This function assumes that we are dealing with a basic relocation
1341 against a symbol. We want to compute the value of the symbol to
1342 relocate to. This is just VALUE, the value of the symbol, plus
1343 ADDEND, any addend associated with the reloc. */
1344 relocation = value + addend;
1346 /* If the relocation is PC relative, we want to set RELOCATION to
1347 the distance between the symbol (currently in RELOCATION) and the
1348 location we are relocating. Some targets (e.g., i386-aout)
1349 arrange for the contents of the section to be the negative of the
1350 offset of the location within the section; for such targets
1351 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1352 simply leave the contents of the section as zero; for such
1353 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1354 need to subtract out the offset of the location within the
1355 section (which is just ADDRESS). */
1356 if (howto->pc_relative)
1358 relocation -= (input_section->output_section->vma
1359 + input_section->output_offset);
1360 if (howto->pcrel_offset)
1361 relocation -= address;
1364 return _bfd_relocate_contents (howto, input_bfd, relocation,
1365 contents + address);
1368 /* Relocate a given location using a given value and howto. */
1370 bfd_reloc_status_type
1371 _bfd_relocate_contents (reloc_howto_type *howto,
1378 bfd_reloc_status_type flag;
1379 unsigned int rightshift = howto->rightshift;
1380 unsigned int bitpos = howto->bitpos;
1382 /* If the size is negative, negate RELOCATION. This isn't very
1384 if (howto->size < 0)
1385 relocation = -relocation;
1387 /* Get the value we are going to relocate. */
1388 size = bfd_get_reloc_size (howto);
1395 x = bfd_get_8 (input_bfd, location);
1398 x = bfd_get_16 (input_bfd, location);
1401 x = bfd_get_32 (input_bfd, location);
1405 x = bfd_get_64 (input_bfd, location);
1412 /* Check for overflow. FIXME: We may drop bits during the addition
1413 which we don't check for. We must either check at every single
1414 operation, which would be tedious, or we must do the computations
1415 in a type larger than bfd_vma, which would be inefficient. */
1416 flag = bfd_reloc_ok;
1417 if (howto->complain_on_overflow != complain_overflow_dont)
1419 bfd_vma addrmask, fieldmask, signmask, ss;
1422 /* Get the values to be added together. For signed and unsigned
1423 relocations, we assume that all values should be truncated to
1424 the size of an address. For bitfields, all the bits matter.
1425 See also bfd_check_overflow. */
1426 fieldmask = N_ONES (howto->bitsize);
1427 signmask = ~fieldmask;
1428 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1429 | (fieldmask << rightshift));
1430 a = (relocation & addrmask) >> rightshift;
1431 b = (x & howto->src_mask & addrmask) >> bitpos;
1432 addrmask >>= rightshift;
1434 switch (howto->complain_on_overflow)
1436 case complain_overflow_signed:
1437 /* If any sign bits are set, all sign bits must be set.
1438 That is, A must be a valid negative address after
1440 signmask = ~(fieldmask >> 1);
1443 case complain_overflow_bitfield:
1444 /* Much like the signed check, but for a field one bit
1445 wider. We allow a bitfield to represent numbers in the
1446 range -2**n to 2**n-1, where n is the number of bits in the
1447 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1448 can't overflow, which is exactly what we want. */
1450 if (ss != 0 && ss != (addrmask & signmask))
1451 flag = bfd_reloc_overflow;
1453 /* We only need this next bit of code if the sign bit of B
1454 is below the sign bit of A. This would only happen if
1455 SRC_MASK had fewer bits than BITSIZE. Note that if
1456 SRC_MASK has more bits than BITSIZE, we can get into
1457 trouble; we would need to verify that B is in range, as
1458 we do for A above. */
1459 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1462 /* Set all the bits above the sign bit. */
1465 /* Now we can do the addition. */
1468 /* See if the result has the correct sign. Bits above the
1469 sign bit are junk now; ignore them. If the sum is
1470 positive, make sure we did not have all negative inputs;
1471 if the sum is negative, make sure we did not have all
1472 positive inputs. The test below looks only at the sign
1473 bits, and it really just
1474 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1476 We mask with addrmask here to explicitly allow an address
1477 wrap-around. The Linux kernel relies on it, and it is
1478 the only way to write assembler code which can run when
1479 loaded at a location 0x80000000 away from the location at
1480 which it is linked. */
1481 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1482 flag = bfd_reloc_overflow;
1485 case complain_overflow_unsigned:
1486 /* Checking for an unsigned overflow is relatively easy:
1487 trim the addresses and add, and trim the result as well.
1488 Overflow is normally indicated when the result does not
1489 fit in the field. However, we also need to consider the
1490 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1491 input is 0x80000000, and bfd_vma is only 32 bits; then we
1492 will get sum == 0, but there is an overflow, since the
1493 inputs did not fit in the field. Instead of doing a
1494 separate test, we can check for this by or-ing in the
1495 operands when testing for the sum overflowing its final
1497 sum = (a + b) & addrmask;
1498 if ((a | b | sum) & signmask)
1499 flag = bfd_reloc_overflow;
1507 /* Put RELOCATION in the right bits. */
1508 relocation >>= (bfd_vma) rightshift;
1509 relocation <<= (bfd_vma) bitpos;
1511 /* Add RELOCATION to the right bits of X. */
1512 x = ((x & ~howto->dst_mask)
1513 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1515 /* Put the relocated value back in the object file. */
1521 bfd_put_8 (input_bfd, x, location);
1524 bfd_put_16 (input_bfd, x, location);
1527 bfd_put_32 (input_bfd, x, location);
1531 bfd_put_64 (input_bfd, x, location);
1541 /* Clear a given location using a given howto, by applying a fixed relocation
1542 value and discarding any in-place addend. This is used for fixed-up
1543 relocations against discarded symbols, to make ignorable debug or unwind
1544 information more obvious. */
1547 _bfd_clear_contents (reloc_howto_type *howto,
1549 asection *input_section,
1555 /* Get the value we are going to relocate. */
1556 size = bfd_get_reloc_size (howto);
1563 x = bfd_get_8 (input_bfd, location);
1566 x = bfd_get_16 (input_bfd, location);
1569 x = bfd_get_32 (input_bfd, location);
1573 x = bfd_get_64 (input_bfd, location);
1580 /* Zero out the unwanted bits of X. */
1581 x &= ~howto->dst_mask;
1583 /* For a range list, use 1 instead of 0 as placeholder. 0
1584 would terminate the list, hiding any later entries. */
1585 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1586 ".debug_ranges") == 0
1587 && (howto->dst_mask & 1) != 0)
1590 /* Put the relocated value back in the object file. */
1597 bfd_put_8 (input_bfd, x, location);
1600 bfd_put_16 (input_bfd, x, location);
1603 bfd_put_32 (input_bfd, x, location);
1607 bfd_put_64 (input_bfd, x, location);
1618 howto manager, , typedef arelent, Relocations
1623 When an application wants to create a relocation, but doesn't
1624 know what the target machine might call it, it can find out by
1625 using this bit of code.
1634 The insides of a reloc code. The idea is that, eventually, there
1635 will be one enumerator for every type of relocation we ever do.
1636 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1637 return a howto pointer.
1639 This does mean that the application must determine the correct
1640 enumerator value; you can't get a howto pointer from a random set
1661 Basic absolute relocations of N bits.
1676 PC-relative relocations. Sometimes these are relative to the address
1677 of the relocation itself; sometimes they are relative to the start of
1678 the section containing the relocation. It depends on the specific target.
1680 The 24-bit relocation is used in some Intel 960 configurations.
1685 Section relative relocations. Some targets need this for DWARF2.
1688 BFD_RELOC_32_GOT_PCREL
1690 BFD_RELOC_16_GOT_PCREL
1692 BFD_RELOC_8_GOT_PCREL
1698 BFD_RELOC_LO16_GOTOFF
1700 BFD_RELOC_HI16_GOTOFF
1702 BFD_RELOC_HI16_S_GOTOFF
1706 BFD_RELOC_64_PLT_PCREL
1708 BFD_RELOC_32_PLT_PCREL
1710 BFD_RELOC_24_PLT_PCREL
1712 BFD_RELOC_16_PLT_PCREL
1714 BFD_RELOC_8_PLT_PCREL
1722 BFD_RELOC_LO16_PLTOFF
1724 BFD_RELOC_HI16_PLTOFF
1726 BFD_RELOC_HI16_S_PLTOFF
1740 BFD_RELOC_68K_GLOB_DAT
1742 BFD_RELOC_68K_JMP_SLOT
1744 BFD_RELOC_68K_RELATIVE
1746 BFD_RELOC_68K_TLS_GD32
1748 BFD_RELOC_68K_TLS_GD16
1750 BFD_RELOC_68K_TLS_GD8
1752 BFD_RELOC_68K_TLS_LDM32
1754 BFD_RELOC_68K_TLS_LDM16
1756 BFD_RELOC_68K_TLS_LDM8
1758 BFD_RELOC_68K_TLS_LDO32
1760 BFD_RELOC_68K_TLS_LDO16
1762 BFD_RELOC_68K_TLS_LDO8
1764 BFD_RELOC_68K_TLS_IE32
1766 BFD_RELOC_68K_TLS_IE16
1768 BFD_RELOC_68K_TLS_IE8
1770 BFD_RELOC_68K_TLS_LE32
1772 BFD_RELOC_68K_TLS_LE16
1774 BFD_RELOC_68K_TLS_LE8
1776 Relocations used by 68K ELF.
1779 BFD_RELOC_32_BASEREL
1781 BFD_RELOC_16_BASEREL
1783 BFD_RELOC_LO16_BASEREL
1785 BFD_RELOC_HI16_BASEREL
1787 BFD_RELOC_HI16_S_BASEREL
1793 Linkage-table relative.
1798 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1801 BFD_RELOC_32_PCREL_S2
1803 BFD_RELOC_16_PCREL_S2
1805 BFD_RELOC_23_PCREL_S2
1807 These PC-relative relocations are stored as word displacements --
1808 i.e., byte displacements shifted right two bits. The 30-bit word
1809 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1810 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1811 signed 16-bit displacement is used on the MIPS, and the 23-bit
1812 displacement is used on the Alpha.
1819 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1820 the target word. These are used on the SPARC.
1827 For systems that allocate a Global Pointer register, these are
1828 displacements off that register. These relocation types are
1829 handled specially, because the value the register will have is
1830 decided relatively late.
1833 BFD_RELOC_I960_CALLJ
1835 Reloc types used for i960/b.out.
1840 BFD_RELOC_SPARC_WDISP22
1846 BFD_RELOC_SPARC_GOT10
1848 BFD_RELOC_SPARC_GOT13
1850 BFD_RELOC_SPARC_GOT22
1852 BFD_RELOC_SPARC_PC10
1854 BFD_RELOC_SPARC_PC22
1856 BFD_RELOC_SPARC_WPLT30
1858 BFD_RELOC_SPARC_COPY
1860 BFD_RELOC_SPARC_GLOB_DAT
1862 BFD_RELOC_SPARC_JMP_SLOT
1864 BFD_RELOC_SPARC_RELATIVE
1866 BFD_RELOC_SPARC_UA16
1868 BFD_RELOC_SPARC_UA32
1870 BFD_RELOC_SPARC_UA64
1872 BFD_RELOC_SPARC_GOTDATA_HIX22
1874 BFD_RELOC_SPARC_GOTDATA_LOX10
1876 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1878 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1880 BFD_RELOC_SPARC_GOTDATA_OP
1882 BFD_RELOC_SPARC_JMP_IREL
1884 BFD_RELOC_SPARC_IRELATIVE
1886 SPARC ELF relocations. There is probably some overlap with other
1887 relocation types already defined.
1890 BFD_RELOC_SPARC_BASE13
1892 BFD_RELOC_SPARC_BASE22
1894 I think these are specific to SPARC a.out (e.g., Sun 4).
1904 BFD_RELOC_SPARC_OLO10
1906 BFD_RELOC_SPARC_HH22
1908 BFD_RELOC_SPARC_HM10
1910 BFD_RELOC_SPARC_LM22
1912 BFD_RELOC_SPARC_PC_HH22
1914 BFD_RELOC_SPARC_PC_HM10
1916 BFD_RELOC_SPARC_PC_LM22
1918 BFD_RELOC_SPARC_WDISP16
1920 BFD_RELOC_SPARC_WDISP19
1928 BFD_RELOC_SPARC_DISP64
1931 BFD_RELOC_SPARC_PLT32
1933 BFD_RELOC_SPARC_PLT64
1935 BFD_RELOC_SPARC_HIX22
1937 BFD_RELOC_SPARC_LOX10
1945 BFD_RELOC_SPARC_REGISTER
1949 BFD_RELOC_SPARC_SIZE32
1951 BFD_RELOC_SPARC_SIZE64
1953 BFD_RELOC_SPARC_WDISP10
1958 BFD_RELOC_SPARC_REV32
1960 SPARC little endian relocation
1962 BFD_RELOC_SPARC_TLS_GD_HI22
1964 BFD_RELOC_SPARC_TLS_GD_LO10
1966 BFD_RELOC_SPARC_TLS_GD_ADD
1968 BFD_RELOC_SPARC_TLS_GD_CALL
1970 BFD_RELOC_SPARC_TLS_LDM_HI22
1972 BFD_RELOC_SPARC_TLS_LDM_LO10
1974 BFD_RELOC_SPARC_TLS_LDM_ADD
1976 BFD_RELOC_SPARC_TLS_LDM_CALL
1978 BFD_RELOC_SPARC_TLS_LDO_HIX22
1980 BFD_RELOC_SPARC_TLS_LDO_LOX10
1982 BFD_RELOC_SPARC_TLS_LDO_ADD
1984 BFD_RELOC_SPARC_TLS_IE_HI22
1986 BFD_RELOC_SPARC_TLS_IE_LO10
1988 BFD_RELOC_SPARC_TLS_IE_LD
1990 BFD_RELOC_SPARC_TLS_IE_LDX
1992 BFD_RELOC_SPARC_TLS_IE_ADD
1994 BFD_RELOC_SPARC_TLS_LE_HIX22
1996 BFD_RELOC_SPARC_TLS_LE_LOX10
1998 BFD_RELOC_SPARC_TLS_DTPMOD32
2000 BFD_RELOC_SPARC_TLS_DTPMOD64
2002 BFD_RELOC_SPARC_TLS_DTPOFF32
2004 BFD_RELOC_SPARC_TLS_DTPOFF64
2006 BFD_RELOC_SPARC_TLS_TPOFF32
2008 BFD_RELOC_SPARC_TLS_TPOFF64
2010 SPARC TLS relocations
2019 BFD_RELOC_SPU_IMM10W
2023 BFD_RELOC_SPU_IMM16W
2027 BFD_RELOC_SPU_PCREL9a
2029 BFD_RELOC_SPU_PCREL9b
2031 BFD_RELOC_SPU_PCREL16
2041 BFD_RELOC_SPU_ADD_PIC
2046 BFD_RELOC_ALPHA_GPDISP_HI16
2048 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2049 "addend" in some special way.
2050 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2051 writing; when reading, it will be the absolute section symbol. The
2052 addend is the displacement in bytes of the "lda" instruction from
2053 the "ldah" instruction (which is at the address of this reloc).
2055 BFD_RELOC_ALPHA_GPDISP_LO16
2057 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2058 with GPDISP_HI16 relocs. The addend is ignored when writing the
2059 relocations out, and is filled in with the file's GP value on
2060 reading, for convenience.
2063 BFD_RELOC_ALPHA_GPDISP
2065 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2066 relocation except that there is no accompanying GPDISP_LO16
2070 BFD_RELOC_ALPHA_LITERAL
2072 BFD_RELOC_ALPHA_ELF_LITERAL
2074 BFD_RELOC_ALPHA_LITUSE
2076 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2077 the assembler turns it into a LDQ instruction to load the address of
2078 the symbol, and then fills in a register in the real instruction.
2080 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2081 section symbol. The addend is ignored when writing, but is filled
2082 in with the file's GP value on reading, for convenience, as with the
2085 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2086 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2087 but it generates output not based on the position within the .got
2088 section, but relative to the GP value chosen for the file during the
2091 The LITUSE reloc, on the instruction using the loaded address, gives
2092 information to the linker that it might be able to use to optimize
2093 away some literal section references. The symbol is ignored (read
2094 as the absolute section symbol), and the "addend" indicates the type
2095 of instruction using the register:
2096 1 - "memory" fmt insn
2097 2 - byte-manipulation (byte offset reg)
2098 3 - jsr (target of branch)
2101 BFD_RELOC_ALPHA_HINT
2103 The HINT relocation indicates a value that should be filled into the
2104 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2105 prediction logic which may be provided on some processors.
2108 BFD_RELOC_ALPHA_LINKAGE
2110 The LINKAGE relocation outputs a linkage pair in the object file,
2111 which is filled by the linker.
2114 BFD_RELOC_ALPHA_CODEADDR
2116 The CODEADDR relocation outputs a STO_CA in the object file,
2117 which is filled by the linker.
2120 BFD_RELOC_ALPHA_GPREL_HI16
2122 BFD_RELOC_ALPHA_GPREL_LO16
2124 The GPREL_HI/LO relocations together form a 32-bit offset from the
2128 BFD_RELOC_ALPHA_BRSGP
2130 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2131 share a common GP, and the target address is adjusted for
2132 STO_ALPHA_STD_GPLOAD.
2137 The NOP relocation outputs a NOP if the longword displacement
2138 between two procedure entry points is < 2^21.
2143 The BSR relocation outputs a BSR if the longword displacement
2144 between two procedure entry points is < 2^21.
2149 The LDA relocation outputs a LDA if the longword displacement
2150 between two procedure entry points is < 2^16.
2155 The BOH relocation outputs a BSR if the longword displacement
2156 between two procedure entry points is < 2^21, or else a hint.
2159 BFD_RELOC_ALPHA_TLSGD
2161 BFD_RELOC_ALPHA_TLSLDM
2163 BFD_RELOC_ALPHA_DTPMOD64
2165 BFD_RELOC_ALPHA_GOTDTPREL16
2167 BFD_RELOC_ALPHA_DTPREL64
2169 BFD_RELOC_ALPHA_DTPREL_HI16
2171 BFD_RELOC_ALPHA_DTPREL_LO16
2173 BFD_RELOC_ALPHA_DTPREL16
2175 BFD_RELOC_ALPHA_GOTTPREL16
2177 BFD_RELOC_ALPHA_TPREL64
2179 BFD_RELOC_ALPHA_TPREL_HI16
2181 BFD_RELOC_ALPHA_TPREL_LO16
2183 BFD_RELOC_ALPHA_TPREL16
2185 Alpha thread-local storage relocations.
2190 BFD_RELOC_MICROMIPS_JMP
2192 The MIPS jump instruction.
2195 BFD_RELOC_MIPS16_JMP
2197 The MIPS16 jump instruction.
2200 BFD_RELOC_MIPS16_GPREL
2202 MIPS16 GP relative reloc.
2207 High 16 bits of 32-bit value; simple reloc.
2212 High 16 bits of 32-bit value but the low 16 bits will be sign
2213 extended and added to form the final result. If the low 16
2214 bits form a negative number, we need to add one to the high value
2215 to compensate for the borrow when the low bits are added.
2223 BFD_RELOC_HI16_PCREL
2225 High 16 bits of 32-bit pc-relative value
2227 BFD_RELOC_HI16_S_PCREL
2229 High 16 bits of 32-bit pc-relative value, adjusted
2231 BFD_RELOC_LO16_PCREL
2233 Low 16 bits of pc-relative value
2236 BFD_RELOC_MIPS16_GOT16
2238 BFD_RELOC_MIPS16_CALL16
2240 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2241 16-bit immediate fields
2243 BFD_RELOC_MIPS16_HI16
2245 MIPS16 high 16 bits of 32-bit value.
2247 BFD_RELOC_MIPS16_HI16_S
2249 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2250 extended and added to form the final result. If the low 16
2251 bits form a negative number, we need to add one to the high value
2252 to compensate for the borrow when the low bits are added.
2254 BFD_RELOC_MIPS16_LO16
2259 BFD_RELOC_MIPS16_TLS_GD
2261 BFD_RELOC_MIPS16_TLS_LDM
2263 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2265 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2267 BFD_RELOC_MIPS16_TLS_GOTTPREL
2269 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2271 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2273 MIPS16 TLS relocations
2276 BFD_RELOC_MIPS_LITERAL
2278 BFD_RELOC_MICROMIPS_LITERAL
2280 Relocation against a MIPS literal section.
2283 BFD_RELOC_MICROMIPS_7_PCREL_S1
2285 BFD_RELOC_MICROMIPS_10_PCREL_S1
2287 BFD_RELOC_MICROMIPS_16_PCREL_S1
2289 microMIPS PC-relative relocations.
2292 BFD_RELOC_MIPS_21_PCREL_S2
2294 BFD_RELOC_MIPS_26_PCREL_S2
2296 BFD_RELOC_MIPS_18_PCREL_S3
2298 BFD_RELOC_MIPS_19_PCREL_S2
2300 MIPS PC-relative relocations.
2303 BFD_RELOC_MICROMIPS_GPREL16
2305 BFD_RELOC_MICROMIPS_HI16
2307 BFD_RELOC_MICROMIPS_HI16_S
2309 BFD_RELOC_MICROMIPS_LO16
2311 microMIPS versions of generic BFD relocs.
2314 BFD_RELOC_MIPS_GOT16
2316 BFD_RELOC_MICROMIPS_GOT16
2318 BFD_RELOC_MIPS_CALL16
2320 BFD_RELOC_MICROMIPS_CALL16
2322 BFD_RELOC_MIPS_GOT_HI16
2324 BFD_RELOC_MICROMIPS_GOT_HI16
2326 BFD_RELOC_MIPS_GOT_LO16
2328 BFD_RELOC_MICROMIPS_GOT_LO16
2330 BFD_RELOC_MIPS_CALL_HI16
2332 BFD_RELOC_MICROMIPS_CALL_HI16
2334 BFD_RELOC_MIPS_CALL_LO16
2336 BFD_RELOC_MICROMIPS_CALL_LO16
2340 BFD_RELOC_MICROMIPS_SUB
2342 BFD_RELOC_MIPS_GOT_PAGE
2344 BFD_RELOC_MICROMIPS_GOT_PAGE
2346 BFD_RELOC_MIPS_GOT_OFST
2348 BFD_RELOC_MICROMIPS_GOT_OFST
2350 BFD_RELOC_MIPS_GOT_DISP
2352 BFD_RELOC_MICROMIPS_GOT_DISP
2354 BFD_RELOC_MIPS_SHIFT5
2356 BFD_RELOC_MIPS_SHIFT6
2358 BFD_RELOC_MIPS_INSERT_A
2360 BFD_RELOC_MIPS_INSERT_B
2362 BFD_RELOC_MIPS_DELETE
2364 BFD_RELOC_MIPS_HIGHEST
2366 BFD_RELOC_MICROMIPS_HIGHEST
2368 BFD_RELOC_MIPS_HIGHER
2370 BFD_RELOC_MICROMIPS_HIGHER
2372 BFD_RELOC_MIPS_SCN_DISP
2374 BFD_RELOC_MICROMIPS_SCN_DISP
2376 BFD_RELOC_MIPS_REL16
2378 BFD_RELOC_MIPS_RELGOT
2382 BFD_RELOC_MICROMIPS_JALR
2384 BFD_RELOC_MIPS_TLS_DTPMOD32
2386 BFD_RELOC_MIPS_TLS_DTPREL32
2388 BFD_RELOC_MIPS_TLS_DTPMOD64
2390 BFD_RELOC_MIPS_TLS_DTPREL64
2392 BFD_RELOC_MIPS_TLS_GD
2394 BFD_RELOC_MICROMIPS_TLS_GD
2396 BFD_RELOC_MIPS_TLS_LDM
2398 BFD_RELOC_MICROMIPS_TLS_LDM
2400 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2402 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2404 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2406 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2408 BFD_RELOC_MIPS_TLS_GOTTPREL
2410 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2412 BFD_RELOC_MIPS_TLS_TPREL32
2414 BFD_RELOC_MIPS_TLS_TPREL64
2416 BFD_RELOC_MIPS_TLS_TPREL_HI16
2418 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2420 BFD_RELOC_MIPS_TLS_TPREL_LO16
2422 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2426 MIPS ELF relocations.
2432 BFD_RELOC_MIPS_JUMP_SLOT
2434 MIPS ELF relocations (VxWorks and PLT extensions).
2438 BFD_RELOC_MOXIE_10_PCREL
2440 Moxie ELF relocations.
2444 BFD_RELOC_FRV_LABEL16
2446 BFD_RELOC_FRV_LABEL24
2452 BFD_RELOC_FRV_GPREL12
2454 BFD_RELOC_FRV_GPRELU12
2456 BFD_RELOC_FRV_GPREL32
2458 BFD_RELOC_FRV_GPRELHI
2460 BFD_RELOC_FRV_GPRELLO
2468 BFD_RELOC_FRV_FUNCDESC
2470 BFD_RELOC_FRV_FUNCDESC_GOT12
2472 BFD_RELOC_FRV_FUNCDESC_GOTHI
2474 BFD_RELOC_FRV_FUNCDESC_GOTLO
2476 BFD_RELOC_FRV_FUNCDESC_VALUE
2478 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2480 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2482 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2484 BFD_RELOC_FRV_GOTOFF12
2486 BFD_RELOC_FRV_GOTOFFHI
2488 BFD_RELOC_FRV_GOTOFFLO
2490 BFD_RELOC_FRV_GETTLSOFF
2492 BFD_RELOC_FRV_TLSDESC_VALUE
2494 BFD_RELOC_FRV_GOTTLSDESC12
2496 BFD_RELOC_FRV_GOTTLSDESCHI
2498 BFD_RELOC_FRV_GOTTLSDESCLO
2500 BFD_RELOC_FRV_TLSMOFF12
2502 BFD_RELOC_FRV_TLSMOFFHI
2504 BFD_RELOC_FRV_TLSMOFFLO
2506 BFD_RELOC_FRV_GOTTLSOFF12
2508 BFD_RELOC_FRV_GOTTLSOFFHI
2510 BFD_RELOC_FRV_GOTTLSOFFLO
2512 BFD_RELOC_FRV_TLSOFF
2514 BFD_RELOC_FRV_TLSDESC_RELAX
2516 BFD_RELOC_FRV_GETTLSOFF_RELAX
2518 BFD_RELOC_FRV_TLSOFF_RELAX
2520 BFD_RELOC_FRV_TLSMOFF
2522 Fujitsu Frv Relocations.
2526 BFD_RELOC_MN10300_GOTOFF24
2528 This is a 24bit GOT-relative reloc for the mn10300.
2530 BFD_RELOC_MN10300_GOT32
2532 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2535 BFD_RELOC_MN10300_GOT24
2537 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2540 BFD_RELOC_MN10300_GOT16
2542 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2545 BFD_RELOC_MN10300_COPY
2547 Copy symbol at runtime.
2549 BFD_RELOC_MN10300_GLOB_DAT
2553 BFD_RELOC_MN10300_JMP_SLOT
2557 BFD_RELOC_MN10300_RELATIVE
2559 Adjust by program base.
2561 BFD_RELOC_MN10300_SYM_DIFF
2563 Together with another reloc targeted at the same location,
2564 allows for a value that is the difference of two symbols
2565 in the same section.
2567 BFD_RELOC_MN10300_ALIGN
2569 The addend of this reloc is an alignment power that must
2570 be honoured at the offset's location, regardless of linker
2573 BFD_RELOC_MN10300_TLS_GD
2575 BFD_RELOC_MN10300_TLS_LD
2577 BFD_RELOC_MN10300_TLS_LDO
2579 BFD_RELOC_MN10300_TLS_GOTIE
2581 BFD_RELOC_MN10300_TLS_IE
2583 BFD_RELOC_MN10300_TLS_LE
2585 BFD_RELOC_MN10300_TLS_DTPMOD
2587 BFD_RELOC_MN10300_TLS_DTPOFF
2589 BFD_RELOC_MN10300_TLS_TPOFF
2591 Various TLS-related relocations.
2593 BFD_RELOC_MN10300_32_PCREL
2595 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2598 BFD_RELOC_MN10300_16_PCREL
2600 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2611 BFD_RELOC_386_GLOB_DAT
2613 BFD_RELOC_386_JUMP_SLOT
2615 BFD_RELOC_386_RELATIVE
2617 BFD_RELOC_386_GOTOFF
2621 BFD_RELOC_386_TLS_TPOFF
2623 BFD_RELOC_386_TLS_IE
2625 BFD_RELOC_386_TLS_GOTIE
2627 BFD_RELOC_386_TLS_LE
2629 BFD_RELOC_386_TLS_GD
2631 BFD_RELOC_386_TLS_LDM
2633 BFD_RELOC_386_TLS_LDO_32
2635 BFD_RELOC_386_TLS_IE_32
2637 BFD_RELOC_386_TLS_LE_32
2639 BFD_RELOC_386_TLS_DTPMOD32
2641 BFD_RELOC_386_TLS_DTPOFF32
2643 BFD_RELOC_386_TLS_TPOFF32
2645 BFD_RELOC_386_TLS_GOTDESC
2647 BFD_RELOC_386_TLS_DESC_CALL
2649 BFD_RELOC_386_TLS_DESC
2651 BFD_RELOC_386_IRELATIVE
2653 i386/elf relocations
2656 BFD_RELOC_X86_64_GOT32
2658 BFD_RELOC_X86_64_PLT32
2660 BFD_RELOC_X86_64_COPY
2662 BFD_RELOC_X86_64_GLOB_DAT
2664 BFD_RELOC_X86_64_JUMP_SLOT
2666 BFD_RELOC_X86_64_RELATIVE
2668 BFD_RELOC_X86_64_GOTPCREL
2670 BFD_RELOC_X86_64_32S
2672 BFD_RELOC_X86_64_DTPMOD64
2674 BFD_RELOC_X86_64_DTPOFF64
2676 BFD_RELOC_X86_64_TPOFF64
2678 BFD_RELOC_X86_64_TLSGD
2680 BFD_RELOC_X86_64_TLSLD
2682 BFD_RELOC_X86_64_DTPOFF32
2684 BFD_RELOC_X86_64_GOTTPOFF
2686 BFD_RELOC_X86_64_TPOFF32
2688 BFD_RELOC_X86_64_GOTOFF64
2690 BFD_RELOC_X86_64_GOTPC32
2692 BFD_RELOC_X86_64_GOT64
2694 BFD_RELOC_X86_64_GOTPCREL64
2696 BFD_RELOC_X86_64_GOTPC64
2698 BFD_RELOC_X86_64_GOTPLT64
2700 BFD_RELOC_X86_64_PLTOFF64
2702 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2704 BFD_RELOC_X86_64_TLSDESC_CALL
2706 BFD_RELOC_X86_64_TLSDESC
2708 BFD_RELOC_X86_64_IRELATIVE
2710 BFD_RELOC_X86_64_PC32_BND
2712 BFD_RELOC_X86_64_PLT32_BND
2714 x86-64/elf relocations
2717 BFD_RELOC_NS32K_IMM_8
2719 BFD_RELOC_NS32K_IMM_16
2721 BFD_RELOC_NS32K_IMM_32
2723 BFD_RELOC_NS32K_IMM_8_PCREL
2725 BFD_RELOC_NS32K_IMM_16_PCREL
2727 BFD_RELOC_NS32K_IMM_32_PCREL
2729 BFD_RELOC_NS32K_DISP_8
2731 BFD_RELOC_NS32K_DISP_16
2733 BFD_RELOC_NS32K_DISP_32
2735 BFD_RELOC_NS32K_DISP_8_PCREL
2737 BFD_RELOC_NS32K_DISP_16_PCREL
2739 BFD_RELOC_NS32K_DISP_32_PCREL
2744 BFD_RELOC_PDP11_DISP_8_PCREL
2746 BFD_RELOC_PDP11_DISP_6_PCREL
2751 BFD_RELOC_PJ_CODE_HI16
2753 BFD_RELOC_PJ_CODE_LO16
2755 BFD_RELOC_PJ_CODE_DIR16
2757 BFD_RELOC_PJ_CODE_DIR32
2759 BFD_RELOC_PJ_CODE_REL16
2761 BFD_RELOC_PJ_CODE_REL32
2763 Picojava relocs. Not all of these appear in object files.
2774 BFD_RELOC_PPC_B16_BRTAKEN
2776 BFD_RELOC_PPC_B16_BRNTAKEN
2780 BFD_RELOC_PPC_BA16_BRTAKEN
2782 BFD_RELOC_PPC_BA16_BRNTAKEN
2786 BFD_RELOC_PPC_GLOB_DAT
2788 BFD_RELOC_PPC_JMP_SLOT
2790 BFD_RELOC_PPC_RELATIVE
2792 BFD_RELOC_PPC_LOCAL24PC
2794 BFD_RELOC_PPC_EMB_NADDR32
2796 BFD_RELOC_PPC_EMB_NADDR16
2798 BFD_RELOC_PPC_EMB_NADDR16_LO
2800 BFD_RELOC_PPC_EMB_NADDR16_HI
2802 BFD_RELOC_PPC_EMB_NADDR16_HA
2804 BFD_RELOC_PPC_EMB_SDAI16
2806 BFD_RELOC_PPC_EMB_SDA2I16
2808 BFD_RELOC_PPC_EMB_SDA2REL
2810 BFD_RELOC_PPC_EMB_SDA21
2812 BFD_RELOC_PPC_EMB_MRKREF
2814 BFD_RELOC_PPC_EMB_RELSEC16
2816 BFD_RELOC_PPC_EMB_RELST_LO
2818 BFD_RELOC_PPC_EMB_RELST_HI
2820 BFD_RELOC_PPC_EMB_RELST_HA
2822 BFD_RELOC_PPC_EMB_BIT_FLD
2824 BFD_RELOC_PPC_EMB_RELSDA
2826 BFD_RELOC_PPC_VLE_REL8
2828 BFD_RELOC_PPC_VLE_REL15
2830 BFD_RELOC_PPC_VLE_REL24
2832 BFD_RELOC_PPC_VLE_LO16A
2834 BFD_RELOC_PPC_VLE_LO16D
2836 BFD_RELOC_PPC_VLE_HI16A
2838 BFD_RELOC_PPC_VLE_HI16D
2840 BFD_RELOC_PPC_VLE_HA16A
2842 BFD_RELOC_PPC_VLE_HA16D
2844 BFD_RELOC_PPC_VLE_SDA21
2846 BFD_RELOC_PPC_VLE_SDA21_LO
2848 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2850 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2852 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2854 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2856 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2858 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2860 BFD_RELOC_PPC64_HIGHER
2862 BFD_RELOC_PPC64_HIGHER_S
2864 BFD_RELOC_PPC64_HIGHEST
2866 BFD_RELOC_PPC64_HIGHEST_S
2868 BFD_RELOC_PPC64_TOC16_LO
2870 BFD_RELOC_PPC64_TOC16_HI
2872 BFD_RELOC_PPC64_TOC16_HA
2876 BFD_RELOC_PPC64_PLTGOT16
2878 BFD_RELOC_PPC64_PLTGOT16_LO
2880 BFD_RELOC_PPC64_PLTGOT16_HI
2882 BFD_RELOC_PPC64_PLTGOT16_HA
2884 BFD_RELOC_PPC64_ADDR16_DS
2886 BFD_RELOC_PPC64_ADDR16_LO_DS
2888 BFD_RELOC_PPC64_GOT16_DS
2890 BFD_RELOC_PPC64_GOT16_LO_DS
2892 BFD_RELOC_PPC64_PLT16_LO_DS
2894 BFD_RELOC_PPC64_SECTOFF_DS
2896 BFD_RELOC_PPC64_SECTOFF_LO_DS
2898 BFD_RELOC_PPC64_TOC16_DS
2900 BFD_RELOC_PPC64_TOC16_LO_DS
2902 BFD_RELOC_PPC64_PLTGOT16_DS
2904 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2906 BFD_RELOC_PPC64_ADDR16_HIGH
2908 BFD_RELOC_PPC64_ADDR16_HIGHA
2910 BFD_RELOC_PPC64_ADDR64_LOCAL
2912 Power(rs6000) and PowerPC relocations.
2921 BFD_RELOC_PPC_DTPMOD
2923 BFD_RELOC_PPC_TPREL16
2925 BFD_RELOC_PPC_TPREL16_LO
2927 BFD_RELOC_PPC_TPREL16_HI
2929 BFD_RELOC_PPC_TPREL16_HA
2933 BFD_RELOC_PPC_DTPREL16
2935 BFD_RELOC_PPC_DTPREL16_LO
2937 BFD_RELOC_PPC_DTPREL16_HI
2939 BFD_RELOC_PPC_DTPREL16_HA
2941 BFD_RELOC_PPC_DTPREL
2943 BFD_RELOC_PPC_GOT_TLSGD16
2945 BFD_RELOC_PPC_GOT_TLSGD16_LO
2947 BFD_RELOC_PPC_GOT_TLSGD16_HI
2949 BFD_RELOC_PPC_GOT_TLSGD16_HA
2951 BFD_RELOC_PPC_GOT_TLSLD16
2953 BFD_RELOC_PPC_GOT_TLSLD16_LO
2955 BFD_RELOC_PPC_GOT_TLSLD16_HI
2957 BFD_RELOC_PPC_GOT_TLSLD16_HA
2959 BFD_RELOC_PPC_GOT_TPREL16
2961 BFD_RELOC_PPC_GOT_TPREL16_LO
2963 BFD_RELOC_PPC_GOT_TPREL16_HI
2965 BFD_RELOC_PPC_GOT_TPREL16_HA
2967 BFD_RELOC_PPC_GOT_DTPREL16
2969 BFD_RELOC_PPC_GOT_DTPREL16_LO
2971 BFD_RELOC_PPC_GOT_DTPREL16_HI
2973 BFD_RELOC_PPC_GOT_DTPREL16_HA
2975 BFD_RELOC_PPC64_TPREL16_DS
2977 BFD_RELOC_PPC64_TPREL16_LO_DS
2979 BFD_RELOC_PPC64_TPREL16_HIGHER
2981 BFD_RELOC_PPC64_TPREL16_HIGHERA
2983 BFD_RELOC_PPC64_TPREL16_HIGHEST
2985 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2987 BFD_RELOC_PPC64_DTPREL16_DS
2989 BFD_RELOC_PPC64_DTPREL16_LO_DS
2991 BFD_RELOC_PPC64_DTPREL16_HIGHER
2993 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2995 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2997 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2999 BFD_RELOC_PPC64_TPREL16_HIGH
3001 BFD_RELOC_PPC64_TPREL16_HIGHA
3003 BFD_RELOC_PPC64_DTPREL16_HIGH
3005 BFD_RELOC_PPC64_DTPREL16_HIGHA
3007 PowerPC and PowerPC64 thread-local storage relocations.
3012 IBM 370/390 relocations
3017 The type of reloc used to build a constructor table - at the moment
3018 probably a 32 bit wide absolute relocation, but the target can choose.
3019 It generally does map to one of the other relocation types.
3022 BFD_RELOC_ARM_PCREL_BRANCH
3024 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3025 not stored in the instruction.
3027 BFD_RELOC_ARM_PCREL_BLX
3029 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3030 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3031 field in the instruction.
3033 BFD_RELOC_THUMB_PCREL_BLX
3035 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3036 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3037 field in the instruction.
3039 BFD_RELOC_ARM_PCREL_CALL
3041 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3043 BFD_RELOC_ARM_PCREL_JUMP
3045 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3048 BFD_RELOC_THUMB_PCREL_BRANCH7
3050 BFD_RELOC_THUMB_PCREL_BRANCH9
3052 BFD_RELOC_THUMB_PCREL_BRANCH12
3054 BFD_RELOC_THUMB_PCREL_BRANCH20
3056 BFD_RELOC_THUMB_PCREL_BRANCH23
3058 BFD_RELOC_THUMB_PCREL_BRANCH25
3060 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3061 The lowest bit must be zero and is not stored in the instruction.
3062 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3063 "nn" one smaller in all cases. Note further that BRANCH23
3064 corresponds to R_ARM_THM_CALL.
3067 BFD_RELOC_ARM_OFFSET_IMM
3069 12-bit immediate offset, used in ARM-format ldr and str instructions.
3072 BFD_RELOC_ARM_THUMB_OFFSET
3074 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3077 BFD_RELOC_ARM_TARGET1
3079 Pc-relative or absolute relocation depending on target. Used for
3080 entries in .init_array sections.
3082 BFD_RELOC_ARM_ROSEGREL32
3084 Read-only segment base relative address.
3086 BFD_RELOC_ARM_SBREL32
3088 Data segment base relative address.
3090 BFD_RELOC_ARM_TARGET2
3092 This reloc is used for references to RTTI data from exception handling
3093 tables. The actual definition depends on the target. It may be a
3094 pc-relative or some form of GOT-indirect relocation.
3096 BFD_RELOC_ARM_PREL31
3098 31-bit PC relative address.
3104 BFD_RELOC_ARM_MOVW_PCREL
3106 BFD_RELOC_ARM_MOVT_PCREL
3108 BFD_RELOC_ARM_THUMB_MOVW
3110 BFD_RELOC_ARM_THUMB_MOVT
3112 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3114 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3116 Low and High halfword relocations for MOVW and MOVT instructions.
3119 BFD_RELOC_ARM_JUMP_SLOT
3121 BFD_RELOC_ARM_GLOB_DAT
3127 BFD_RELOC_ARM_RELATIVE
3129 BFD_RELOC_ARM_GOTOFF
3133 BFD_RELOC_ARM_GOT_PREL
3135 Relocations for setting up GOTs and PLTs for shared libraries.
3138 BFD_RELOC_ARM_TLS_GD32
3140 BFD_RELOC_ARM_TLS_LDO32
3142 BFD_RELOC_ARM_TLS_LDM32
3144 BFD_RELOC_ARM_TLS_DTPOFF32
3146 BFD_RELOC_ARM_TLS_DTPMOD32
3148 BFD_RELOC_ARM_TLS_TPOFF32
3150 BFD_RELOC_ARM_TLS_IE32
3152 BFD_RELOC_ARM_TLS_LE32
3154 BFD_RELOC_ARM_TLS_GOTDESC
3156 BFD_RELOC_ARM_TLS_CALL
3158 BFD_RELOC_ARM_THM_TLS_CALL
3160 BFD_RELOC_ARM_TLS_DESCSEQ
3162 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3164 BFD_RELOC_ARM_TLS_DESC
3166 ARM thread-local storage relocations.
3169 BFD_RELOC_ARM_ALU_PC_G0_NC
3171 BFD_RELOC_ARM_ALU_PC_G0
3173 BFD_RELOC_ARM_ALU_PC_G1_NC
3175 BFD_RELOC_ARM_ALU_PC_G1
3177 BFD_RELOC_ARM_ALU_PC_G2
3179 BFD_RELOC_ARM_LDR_PC_G0
3181 BFD_RELOC_ARM_LDR_PC_G1
3183 BFD_RELOC_ARM_LDR_PC_G2
3185 BFD_RELOC_ARM_LDRS_PC_G0
3187 BFD_RELOC_ARM_LDRS_PC_G1
3189 BFD_RELOC_ARM_LDRS_PC_G2
3191 BFD_RELOC_ARM_LDC_PC_G0
3193 BFD_RELOC_ARM_LDC_PC_G1
3195 BFD_RELOC_ARM_LDC_PC_G2
3197 BFD_RELOC_ARM_ALU_SB_G0_NC
3199 BFD_RELOC_ARM_ALU_SB_G0
3201 BFD_RELOC_ARM_ALU_SB_G1_NC
3203 BFD_RELOC_ARM_ALU_SB_G1
3205 BFD_RELOC_ARM_ALU_SB_G2
3207 BFD_RELOC_ARM_LDR_SB_G0
3209 BFD_RELOC_ARM_LDR_SB_G1
3211 BFD_RELOC_ARM_LDR_SB_G2
3213 BFD_RELOC_ARM_LDRS_SB_G0
3215 BFD_RELOC_ARM_LDRS_SB_G1
3217 BFD_RELOC_ARM_LDRS_SB_G2
3219 BFD_RELOC_ARM_LDC_SB_G0
3221 BFD_RELOC_ARM_LDC_SB_G1
3223 BFD_RELOC_ARM_LDC_SB_G2
3225 ARM group relocations.
3230 Annotation of BX instructions.
3233 BFD_RELOC_ARM_IRELATIVE
3235 ARM support for STT_GNU_IFUNC.
3238 BFD_RELOC_ARM_IMMEDIATE
3240 BFD_RELOC_ARM_ADRL_IMMEDIATE
3242 BFD_RELOC_ARM_T32_IMMEDIATE
3244 BFD_RELOC_ARM_T32_ADD_IMM
3246 BFD_RELOC_ARM_T32_IMM12
3248 BFD_RELOC_ARM_T32_ADD_PC12
3250 BFD_RELOC_ARM_SHIFT_IMM
3260 BFD_RELOC_ARM_CP_OFF_IMM
3262 BFD_RELOC_ARM_CP_OFF_IMM_S2
3264 BFD_RELOC_ARM_T32_CP_OFF_IMM
3266 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3268 BFD_RELOC_ARM_ADR_IMM
3270 BFD_RELOC_ARM_LDR_IMM
3272 BFD_RELOC_ARM_LITERAL
3274 BFD_RELOC_ARM_IN_POOL
3276 BFD_RELOC_ARM_OFFSET_IMM8
3278 BFD_RELOC_ARM_T32_OFFSET_U8
3280 BFD_RELOC_ARM_T32_OFFSET_IMM
3282 BFD_RELOC_ARM_HWLITERAL
3284 BFD_RELOC_ARM_THUMB_ADD
3286 BFD_RELOC_ARM_THUMB_IMM
3288 BFD_RELOC_ARM_THUMB_SHIFT
3290 These relocs are only used within the ARM assembler. They are not
3291 (at present) written to any object files.
3294 BFD_RELOC_SH_PCDISP8BY2
3296 BFD_RELOC_SH_PCDISP12BY2
3304 BFD_RELOC_SH_DISP12BY2
3306 BFD_RELOC_SH_DISP12BY4
3308 BFD_RELOC_SH_DISP12BY8
3312 BFD_RELOC_SH_DISP20BY8
3316 BFD_RELOC_SH_IMM4BY2
3318 BFD_RELOC_SH_IMM4BY4
3322 BFD_RELOC_SH_IMM8BY2
3324 BFD_RELOC_SH_IMM8BY4
3326 BFD_RELOC_SH_PCRELIMM8BY2
3328 BFD_RELOC_SH_PCRELIMM8BY4
3330 BFD_RELOC_SH_SWITCH16
3332 BFD_RELOC_SH_SWITCH32
3346 BFD_RELOC_SH_LOOP_START
3348 BFD_RELOC_SH_LOOP_END
3352 BFD_RELOC_SH_GLOB_DAT
3354 BFD_RELOC_SH_JMP_SLOT
3356 BFD_RELOC_SH_RELATIVE
3360 BFD_RELOC_SH_GOT_LOW16
3362 BFD_RELOC_SH_GOT_MEDLOW16
3364 BFD_RELOC_SH_GOT_MEDHI16
3366 BFD_RELOC_SH_GOT_HI16
3368 BFD_RELOC_SH_GOTPLT_LOW16
3370 BFD_RELOC_SH_GOTPLT_MEDLOW16
3372 BFD_RELOC_SH_GOTPLT_MEDHI16
3374 BFD_RELOC_SH_GOTPLT_HI16
3376 BFD_RELOC_SH_PLT_LOW16
3378 BFD_RELOC_SH_PLT_MEDLOW16
3380 BFD_RELOC_SH_PLT_MEDHI16
3382 BFD_RELOC_SH_PLT_HI16
3384 BFD_RELOC_SH_GOTOFF_LOW16
3386 BFD_RELOC_SH_GOTOFF_MEDLOW16
3388 BFD_RELOC_SH_GOTOFF_MEDHI16
3390 BFD_RELOC_SH_GOTOFF_HI16
3392 BFD_RELOC_SH_GOTPC_LOW16
3394 BFD_RELOC_SH_GOTPC_MEDLOW16
3396 BFD_RELOC_SH_GOTPC_MEDHI16
3398 BFD_RELOC_SH_GOTPC_HI16
3402 BFD_RELOC_SH_GLOB_DAT64
3404 BFD_RELOC_SH_JMP_SLOT64
3406 BFD_RELOC_SH_RELATIVE64
3408 BFD_RELOC_SH_GOT10BY4
3410 BFD_RELOC_SH_GOT10BY8
3412 BFD_RELOC_SH_GOTPLT10BY4
3414 BFD_RELOC_SH_GOTPLT10BY8
3416 BFD_RELOC_SH_GOTPLT32
3418 BFD_RELOC_SH_SHMEDIA_CODE
3424 BFD_RELOC_SH_IMMS6BY32
3430 BFD_RELOC_SH_IMMS10BY2
3432 BFD_RELOC_SH_IMMS10BY4
3434 BFD_RELOC_SH_IMMS10BY8
3440 BFD_RELOC_SH_IMM_LOW16
3442 BFD_RELOC_SH_IMM_LOW16_PCREL
3444 BFD_RELOC_SH_IMM_MEDLOW16
3446 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3448 BFD_RELOC_SH_IMM_MEDHI16
3450 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3452 BFD_RELOC_SH_IMM_HI16
3454 BFD_RELOC_SH_IMM_HI16_PCREL
3458 BFD_RELOC_SH_TLS_GD_32
3460 BFD_RELOC_SH_TLS_LD_32
3462 BFD_RELOC_SH_TLS_LDO_32
3464 BFD_RELOC_SH_TLS_IE_32
3466 BFD_RELOC_SH_TLS_LE_32
3468 BFD_RELOC_SH_TLS_DTPMOD32
3470 BFD_RELOC_SH_TLS_DTPOFF32
3472 BFD_RELOC_SH_TLS_TPOFF32
3476 BFD_RELOC_SH_GOTOFF20
3478 BFD_RELOC_SH_GOTFUNCDESC
3480 BFD_RELOC_SH_GOTFUNCDESC20
3482 BFD_RELOC_SH_GOTOFFFUNCDESC
3484 BFD_RELOC_SH_GOTOFFFUNCDESC20
3486 BFD_RELOC_SH_FUNCDESC
3488 Renesas / SuperH SH relocs. Not all of these appear in object files.
3491 BFD_RELOC_ARC_B22_PCREL
3494 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
3495 not stored in the instruction. The high 20 bits are installed in bits 26
3496 through 7 of the instruction.
3500 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
3501 stored in the instruction. The high 24 bits are installed in bits 23
3505 BFD_RELOC_BFIN_16_IMM
3507 ADI Blackfin 16 bit immediate absolute reloc.
3509 BFD_RELOC_BFIN_16_HIGH
3511 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3513 BFD_RELOC_BFIN_4_PCREL
3515 ADI Blackfin 'a' part of LSETUP.
3517 BFD_RELOC_BFIN_5_PCREL
3521 BFD_RELOC_BFIN_16_LOW
3523 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3525 BFD_RELOC_BFIN_10_PCREL
3529 BFD_RELOC_BFIN_11_PCREL
3531 ADI Blackfin 'b' part of LSETUP.
3533 BFD_RELOC_BFIN_12_PCREL_JUMP
3537 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3539 ADI Blackfin Short jump, pcrel.
3541 BFD_RELOC_BFIN_24_PCREL_CALL_X
3543 ADI Blackfin Call.x not implemented.
3545 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3547 ADI Blackfin Long Jump pcrel.
3549 BFD_RELOC_BFIN_GOT17M4
3551 BFD_RELOC_BFIN_GOTHI
3553 BFD_RELOC_BFIN_GOTLO
3555 BFD_RELOC_BFIN_FUNCDESC
3557 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3559 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3561 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3563 BFD_RELOC_BFIN_FUNCDESC_VALUE
3565 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3567 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3569 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3571 BFD_RELOC_BFIN_GOTOFF17M4
3573 BFD_RELOC_BFIN_GOTOFFHI
3575 BFD_RELOC_BFIN_GOTOFFLO
3577 ADI Blackfin FD-PIC relocations.
3581 ADI Blackfin GOT relocation.
3583 BFD_RELOC_BFIN_PLTPC
3585 ADI Blackfin PLTPC relocation.
3587 BFD_ARELOC_BFIN_PUSH
3589 ADI Blackfin arithmetic relocation.
3591 BFD_ARELOC_BFIN_CONST
3593 ADI Blackfin arithmetic relocation.
3597 ADI Blackfin arithmetic relocation.
3601 ADI Blackfin arithmetic relocation.
3603 BFD_ARELOC_BFIN_MULT
3605 ADI Blackfin arithmetic relocation.
3609 ADI Blackfin arithmetic relocation.
3613 ADI Blackfin arithmetic relocation.
3615 BFD_ARELOC_BFIN_LSHIFT
3617 ADI Blackfin arithmetic relocation.
3619 BFD_ARELOC_BFIN_RSHIFT
3621 ADI Blackfin arithmetic relocation.
3625 ADI Blackfin arithmetic relocation.
3629 ADI Blackfin arithmetic relocation.
3633 ADI Blackfin arithmetic relocation.
3635 BFD_ARELOC_BFIN_LAND
3637 ADI Blackfin arithmetic relocation.
3641 ADI Blackfin arithmetic relocation.
3645 ADI Blackfin arithmetic relocation.
3649 ADI Blackfin arithmetic relocation.
3651 BFD_ARELOC_BFIN_COMP
3653 ADI Blackfin arithmetic relocation.
3655 BFD_ARELOC_BFIN_PAGE
3657 ADI Blackfin arithmetic relocation.
3659 BFD_ARELOC_BFIN_HWPAGE
3661 ADI Blackfin arithmetic relocation.
3663 BFD_ARELOC_BFIN_ADDR
3665 ADI Blackfin arithmetic relocation.
3668 BFD_RELOC_D10V_10_PCREL_R
3670 Mitsubishi D10V relocs.
3671 This is a 10-bit reloc with the right 2 bits
3674 BFD_RELOC_D10V_10_PCREL_L
3676 Mitsubishi D10V relocs.
3677 This is a 10-bit reloc with the right 2 bits
3678 assumed to be 0. This is the same as the previous reloc
3679 except it is in the left container, i.e.,
3680 shifted left 15 bits.
3684 This is an 18-bit reloc with the right 2 bits
3687 BFD_RELOC_D10V_18_PCREL
3689 This is an 18-bit reloc with the right 2 bits
3695 Mitsubishi D30V relocs.
3696 This is a 6-bit absolute reloc.
3698 BFD_RELOC_D30V_9_PCREL
3700 This is a 6-bit pc-relative reloc with
3701 the right 3 bits assumed to be 0.
3703 BFD_RELOC_D30V_9_PCREL_R
3705 This is a 6-bit pc-relative reloc with
3706 the right 3 bits assumed to be 0. Same
3707 as the previous reloc but on the right side
3712 This is a 12-bit absolute reloc with the
3713 right 3 bitsassumed to be 0.
3715 BFD_RELOC_D30V_15_PCREL
3717 This is a 12-bit pc-relative reloc with
3718 the right 3 bits assumed to be 0.
3720 BFD_RELOC_D30V_15_PCREL_R
3722 This is a 12-bit pc-relative reloc with
3723 the right 3 bits assumed to be 0. Same
3724 as the previous reloc but on the right side
3729 This is an 18-bit absolute reloc with
3730 the right 3 bits assumed to be 0.
3732 BFD_RELOC_D30V_21_PCREL
3734 This is an 18-bit pc-relative reloc with
3735 the right 3 bits assumed to be 0.
3737 BFD_RELOC_D30V_21_PCREL_R
3739 This is an 18-bit pc-relative reloc with
3740 the right 3 bits assumed to be 0. Same
3741 as the previous reloc but on the right side
3746 This is a 32-bit absolute reloc.
3748 BFD_RELOC_D30V_32_PCREL
3750 This is a 32-bit pc-relative reloc.
3753 BFD_RELOC_DLX_HI16_S
3768 BFD_RELOC_M32C_RL_JUMP
3770 BFD_RELOC_M32C_RL_1ADDR
3772 BFD_RELOC_M32C_RL_2ADDR
3774 Renesas M16C/M32C Relocations.
3779 Renesas M32R (formerly Mitsubishi M32R) relocs.
3780 This is a 24 bit absolute address.
3782 BFD_RELOC_M32R_10_PCREL
3784 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3786 BFD_RELOC_M32R_18_PCREL
3788 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3790 BFD_RELOC_M32R_26_PCREL
3792 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3794 BFD_RELOC_M32R_HI16_ULO
3796 This is a 16-bit reloc containing the high 16 bits of an address
3797 used when the lower 16 bits are treated as unsigned.
3799 BFD_RELOC_M32R_HI16_SLO
3801 This is a 16-bit reloc containing the high 16 bits of an address
3802 used when the lower 16 bits are treated as signed.
3806 This is a 16-bit reloc containing the lower 16 bits of an address.
3808 BFD_RELOC_M32R_SDA16
3810 This is a 16-bit reloc containing the small data area offset for use in
3811 add3, load, and store instructions.
3813 BFD_RELOC_M32R_GOT24
3815 BFD_RELOC_M32R_26_PLTREL
3819 BFD_RELOC_M32R_GLOB_DAT
3821 BFD_RELOC_M32R_JMP_SLOT
3823 BFD_RELOC_M32R_RELATIVE
3825 BFD_RELOC_M32R_GOTOFF
3827 BFD_RELOC_M32R_GOTOFF_HI_ULO
3829 BFD_RELOC_M32R_GOTOFF_HI_SLO
3831 BFD_RELOC_M32R_GOTOFF_LO
3833 BFD_RELOC_M32R_GOTPC24
3835 BFD_RELOC_M32R_GOT16_HI_ULO
3837 BFD_RELOC_M32R_GOT16_HI_SLO
3839 BFD_RELOC_M32R_GOT16_LO
3841 BFD_RELOC_M32R_GOTPC_HI_ULO
3843 BFD_RELOC_M32R_GOTPC_HI_SLO
3845 BFD_RELOC_M32R_GOTPC_LO
3854 This is a 20 bit absolute address.
3856 BFD_RELOC_NDS32_9_PCREL
3858 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3860 BFD_RELOC_NDS32_WORD_9_PCREL
3862 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3864 BFD_RELOC_NDS32_15_PCREL
3866 This is an 15-bit reloc with the right 1 bit assumed to be 0.
3868 BFD_RELOC_NDS32_17_PCREL
3870 This is an 17-bit reloc with the right 1 bit assumed to be 0.
3872 BFD_RELOC_NDS32_25_PCREL
3874 This is a 25-bit reloc with the right 1 bit assumed to be 0.
3876 BFD_RELOC_NDS32_HI20
3878 This is a 20-bit reloc containing the high 20 bits of an address
3879 used with the lower 12 bits
3881 BFD_RELOC_NDS32_LO12S3
3883 This is a 12-bit reloc containing the lower 12 bits of an address
3884 then shift right by 3. This is used with ldi,sdi...
3886 BFD_RELOC_NDS32_LO12S2
3888 This is a 12-bit reloc containing the lower 12 bits of an address
3889 then shift left by 2. This is used with lwi,swi...
3891 BFD_RELOC_NDS32_LO12S1
3893 This is a 12-bit reloc containing the lower 12 bits of an address
3894 then shift left by 1. This is used with lhi,shi...
3896 BFD_RELOC_NDS32_LO12S0
3898 This is a 12-bit reloc containing the lower 12 bits of an address
3899 then shift left by 0. This is used with lbisbi...
3901 BFD_RELOC_NDS32_LO12S0_ORI
3903 This is a 12-bit reloc containing the lower 12 bits of an address
3904 then shift left by 0. This is only used with branch relaxations
3906 BFD_RELOC_NDS32_SDA15S3
3908 This is a 15-bit reloc containing the small data area 18-bit signed offset
3909 and shift left by 3 for use in ldi, sdi...
3911 BFD_RELOC_NDS32_SDA15S2
3913 This is a 15-bit reloc containing the small data area 17-bit signed offset
3914 and shift left by 2 for use in lwi, swi...
3916 BFD_RELOC_NDS32_SDA15S1
3918 This is a 15-bit reloc containing the small data area 16-bit signed offset
3919 and shift left by 1 for use in lhi, shi...
3921 BFD_RELOC_NDS32_SDA15S0
3923 This is a 15-bit reloc containing the small data area 15-bit signed offset
3924 and shift left by 0 for use in lbi, sbi...
3926 BFD_RELOC_NDS32_SDA16S3
3928 This is a 16-bit reloc containing the small data area 16-bit signed offset
3931 BFD_RELOC_NDS32_SDA17S2
3933 This is a 17-bit reloc containing the small data area 17-bit signed offset
3934 and shift left by 2 for use in lwi.gp, swi.gp...
3936 BFD_RELOC_NDS32_SDA18S1
3938 This is a 18-bit reloc containing the small data area 18-bit signed offset
3939 and shift left by 1 for use in lhi.gp, shi.gp...
3941 BFD_RELOC_NDS32_SDA19S0
3943 This is a 19-bit reloc containing the small data area 19-bit signed offset
3944 and shift left by 0 for use in lbi.gp, sbi.gp...
3946 BFD_RELOC_NDS32_GOT20
3948 BFD_RELOC_NDS32_9_PLTREL
3950 BFD_RELOC_NDS32_25_PLTREL
3952 BFD_RELOC_NDS32_COPY
3954 BFD_RELOC_NDS32_GLOB_DAT
3956 BFD_RELOC_NDS32_JMP_SLOT
3958 BFD_RELOC_NDS32_RELATIVE
3960 BFD_RELOC_NDS32_GOTOFF
3962 BFD_RELOC_NDS32_GOTOFF_HI20
3964 BFD_RELOC_NDS32_GOTOFF_LO12
3966 BFD_RELOC_NDS32_GOTPC20
3968 BFD_RELOC_NDS32_GOT_HI20
3970 BFD_RELOC_NDS32_GOT_LO12
3972 BFD_RELOC_NDS32_GOTPC_HI20
3974 BFD_RELOC_NDS32_GOTPC_LO12
3978 BFD_RELOC_NDS32_INSN16
3980 BFD_RELOC_NDS32_LABEL
3982 BFD_RELOC_NDS32_LONGCALL1
3984 BFD_RELOC_NDS32_LONGCALL2
3986 BFD_RELOC_NDS32_LONGCALL3
3988 BFD_RELOC_NDS32_LONGJUMP1
3990 BFD_RELOC_NDS32_LONGJUMP2
3992 BFD_RELOC_NDS32_LONGJUMP3
3994 BFD_RELOC_NDS32_LOADSTORE
3996 BFD_RELOC_NDS32_9_FIXED
3998 BFD_RELOC_NDS32_15_FIXED
4000 BFD_RELOC_NDS32_17_FIXED
4002 BFD_RELOC_NDS32_25_FIXED
4006 BFD_RELOC_NDS32_PLTREL_HI20
4008 BFD_RELOC_NDS32_PLTREL_LO12
4010 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4012 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4016 BFD_RELOC_NDS32_SDA12S2_DP
4018 BFD_RELOC_NDS32_SDA12S2_SP
4020 BFD_RELOC_NDS32_LO12S2_DP
4022 BFD_RELOC_NDS32_LO12S2_SP
4026 BFD_RELOC_NDS32_DWARF2_OP1
4028 BFD_RELOC_NDS32_DWARF2_OP2
4030 BFD_RELOC_NDS32_DWARF2_LEB
4032 for dwarf2 debug_line.
4034 BFD_RELOC_NDS32_UPDATE_TA
4036 for eliminate 16-bit instructions
4038 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4040 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4042 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4044 BFD_RELOC_NDS32_GOT_LO15
4046 BFD_RELOC_NDS32_GOT_LO19
4048 BFD_RELOC_NDS32_GOTOFF_LO15
4050 BFD_RELOC_NDS32_GOTOFF_LO19
4052 BFD_RELOC_NDS32_GOT15S2
4054 BFD_RELOC_NDS32_GOT17S2
4056 for PIC object relaxation
4061 This is a 5 bit absolute address.
4063 BFD_RELOC_NDS32_10_UPCREL
4065 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4067 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4069 If fp were omitted, fp can used as another gp.
4071 BFD_RELOC_NDS32_RELAX_ENTRY
4073 BFD_RELOC_NDS32_GOT_SUFF
4075 BFD_RELOC_NDS32_GOTOFF_SUFF
4077 BFD_RELOC_NDS32_PLT_GOT_SUFF
4079 BFD_RELOC_NDS32_MULCALL_SUFF
4083 BFD_RELOC_NDS32_PTR_COUNT
4085 BFD_RELOC_NDS32_PTR_RESOLVED
4087 BFD_RELOC_NDS32_PLTBLOCK
4089 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4091 BFD_RELOC_NDS32_RELAX_REGION_END
4093 BFD_RELOC_NDS32_MINUEND
4095 BFD_RELOC_NDS32_SUBTRAHEND
4097 BFD_RELOC_NDS32_DIFF8
4099 BFD_RELOC_NDS32_DIFF16
4101 BFD_RELOC_NDS32_DIFF32
4103 BFD_RELOC_NDS32_DIFF_ULEB128
4105 BFD_RELOC_NDS32_25_ABS
4107 BFD_RELOC_NDS32_DATA
4109 BFD_RELOC_NDS32_TRAN
4111 BFD_RELOC_NDS32_17IFC_PCREL
4113 BFD_RELOC_NDS32_10IFCU_PCREL
4115 relaxation relative relocation types
4119 BFD_RELOC_V850_9_PCREL
4121 This is a 9-bit reloc
4123 BFD_RELOC_V850_22_PCREL
4125 This is a 22-bit reloc
4128 BFD_RELOC_V850_SDA_16_16_OFFSET
4130 This is a 16 bit offset from the short data area pointer.
4132 BFD_RELOC_V850_SDA_15_16_OFFSET
4134 This is a 16 bit offset (of which only 15 bits are used) from the
4135 short data area pointer.
4137 BFD_RELOC_V850_ZDA_16_16_OFFSET
4139 This is a 16 bit offset from the zero data area pointer.
4141 BFD_RELOC_V850_ZDA_15_16_OFFSET
4143 This is a 16 bit offset (of which only 15 bits are used) from the
4144 zero data area pointer.
4146 BFD_RELOC_V850_TDA_6_8_OFFSET
4148 This is an 8 bit offset (of which only 6 bits are used) from the
4149 tiny data area pointer.
4151 BFD_RELOC_V850_TDA_7_8_OFFSET
4153 This is an 8bit offset (of which only 7 bits are used) from the tiny
4156 BFD_RELOC_V850_TDA_7_7_OFFSET
4158 This is a 7 bit offset from the tiny data area pointer.
4160 BFD_RELOC_V850_TDA_16_16_OFFSET
4162 This is a 16 bit offset from the tiny data area pointer.
4165 BFD_RELOC_V850_TDA_4_5_OFFSET
4167 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4170 BFD_RELOC_V850_TDA_4_4_OFFSET
4172 This is a 4 bit offset from the tiny data area pointer.
4174 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4176 This is a 16 bit offset from the short data area pointer, with the
4177 bits placed non-contiguously in the instruction.
4179 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4181 This is a 16 bit offset from the zero data area pointer, with the
4182 bits placed non-contiguously in the instruction.
4184 BFD_RELOC_V850_CALLT_6_7_OFFSET
4186 This is a 6 bit offset from the call table base pointer.
4188 BFD_RELOC_V850_CALLT_16_16_OFFSET
4190 This is a 16 bit offset from the call table base pointer.
4192 BFD_RELOC_V850_LONGCALL
4194 Used for relaxing indirect function calls.
4196 BFD_RELOC_V850_LONGJUMP
4198 Used for relaxing indirect jumps.
4200 BFD_RELOC_V850_ALIGN
4202 Used to maintain alignment whilst relaxing.
4204 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4206 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4209 BFD_RELOC_V850_16_PCREL
4211 This is a 16-bit reloc.
4213 BFD_RELOC_V850_17_PCREL
4215 This is a 17-bit reloc.
4219 This is a 23-bit reloc.
4221 BFD_RELOC_V850_32_PCREL
4223 This is a 32-bit reloc.
4225 BFD_RELOC_V850_32_ABS
4227 This is a 32-bit reloc.
4229 BFD_RELOC_V850_16_SPLIT_OFFSET
4231 This is a 16-bit reloc.
4233 BFD_RELOC_V850_16_S1
4235 This is a 16-bit reloc.
4237 BFD_RELOC_V850_LO16_S1
4239 Low 16 bits. 16 bit shifted by 1.
4241 BFD_RELOC_V850_CALLT_15_16_OFFSET
4243 This is a 16 bit offset from the call table base pointer.
4245 BFD_RELOC_V850_32_GOTPCREL
4249 BFD_RELOC_V850_16_GOT
4253 BFD_RELOC_V850_32_GOT
4257 BFD_RELOC_V850_22_PLT_PCREL
4261 BFD_RELOC_V850_32_PLT_PCREL
4269 BFD_RELOC_V850_GLOB_DAT
4273 BFD_RELOC_V850_JMP_SLOT
4277 BFD_RELOC_V850_RELATIVE
4281 BFD_RELOC_V850_16_GOTOFF
4285 BFD_RELOC_V850_32_GOTOFF
4300 This is a 8bit DP reloc for the tms320c30, where the most
4301 significant 8 bits of a 24 bit word are placed into the least
4302 significant 8 bits of the opcode.
4305 BFD_RELOC_TIC54X_PARTLS7
4307 This is a 7bit reloc for the tms320c54x, where the least
4308 significant 7 bits of a 16 bit word are placed into the least
4309 significant 7 bits of the opcode.
4312 BFD_RELOC_TIC54X_PARTMS9
4314 This is a 9bit DP reloc for the tms320c54x, where the most
4315 significant 9 bits of a 16 bit word are placed into the least
4316 significant 9 bits of the opcode.
4321 This is an extended address 23-bit reloc for the tms320c54x.
4324 BFD_RELOC_TIC54X_16_OF_23
4326 This is a 16-bit reloc for the tms320c54x, where the least
4327 significant 16 bits of a 23-bit extended address are placed into
4331 BFD_RELOC_TIC54X_MS7_OF_23
4333 This is a reloc for the tms320c54x, where the most
4334 significant 7 bits of a 23-bit extended address are placed into
4338 BFD_RELOC_C6000_PCR_S21
4340 BFD_RELOC_C6000_PCR_S12
4342 BFD_RELOC_C6000_PCR_S10
4344 BFD_RELOC_C6000_PCR_S7
4346 BFD_RELOC_C6000_ABS_S16
4348 BFD_RELOC_C6000_ABS_L16
4350 BFD_RELOC_C6000_ABS_H16
4352 BFD_RELOC_C6000_SBR_U15_B
4354 BFD_RELOC_C6000_SBR_U15_H
4356 BFD_RELOC_C6000_SBR_U15_W
4358 BFD_RELOC_C6000_SBR_S16
4360 BFD_RELOC_C6000_SBR_L16_B
4362 BFD_RELOC_C6000_SBR_L16_H
4364 BFD_RELOC_C6000_SBR_L16_W
4366 BFD_RELOC_C6000_SBR_H16_B
4368 BFD_RELOC_C6000_SBR_H16_H
4370 BFD_RELOC_C6000_SBR_H16_W
4372 BFD_RELOC_C6000_SBR_GOT_U15_W
4374 BFD_RELOC_C6000_SBR_GOT_L16_W
4376 BFD_RELOC_C6000_SBR_GOT_H16_W
4378 BFD_RELOC_C6000_DSBT_INDEX
4380 BFD_RELOC_C6000_PREL31
4382 BFD_RELOC_C6000_COPY
4384 BFD_RELOC_C6000_JUMP_SLOT
4386 BFD_RELOC_C6000_EHTYPE
4388 BFD_RELOC_C6000_PCR_H16
4390 BFD_RELOC_C6000_PCR_L16
4392 BFD_RELOC_C6000_ALIGN
4394 BFD_RELOC_C6000_FPHEAD
4396 BFD_RELOC_C6000_NOCMP
4398 TMS320C6000 relocations.
4403 This is a 48 bit reloc for the FR30 that stores 32 bits.
4407 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4410 BFD_RELOC_FR30_6_IN_4
4412 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4415 BFD_RELOC_FR30_8_IN_8
4417 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4420 BFD_RELOC_FR30_9_IN_8
4422 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4425 BFD_RELOC_FR30_10_IN_8
4427 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4430 BFD_RELOC_FR30_9_PCREL
4432 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4433 short offset into 8 bits.
4435 BFD_RELOC_FR30_12_PCREL
4437 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4438 short offset into 11 bits.
4441 BFD_RELOC_MCORE_PCREL_IMM8BY4
4443 BFD_RELOC_MCORE_PCREL_IMM11BY2
4445 BFD_RELOC_MCORE_PCREL_IMM4BY2
4447 BFD_RELOC_MCORE_PCREL_32
4449 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4453 Motorola Mcore relocations.
4462 BFD_RELOC_MEP_PCREL8A2
4464 BFD_RELOC_MEP_PCREL12A2
4466 BFD_RELOC_MEP_PCREL17A2
4468 BFD_RELOC_MEP_PCREL24A2
4470 BFD_RELOC_MEP_PCABS24A2
4482 BFD_RELOC_MEP_TPREL7
4484 BFD_RELOC_MEP_TPREL7A2
4486 BFD_RELOC_MEP_TPREL7A4
4488 BFD_RELOC_MEP_UIMM24
4490 BFD_RELOC_MEP_ADDR24A4
4492 BFD_RELOC_MEP_GNU_VTINHERIT
4494 BFD_RELOC_MEP_GNU_VTENTRY
4496 Toshiba Media Processor Relocations.
4500 BFD_RELOC_METAG_HIADDR16
4502 BFD_RELOC_METAG_LOADDR16
4504 BFD_RELOC_METAG_RELBRANCH
4506 BFD_RELOC_METAG_GETSETOFF
4508 BFD_RELOC_METAG_HIOG
4510 BFD_RELOC_METAG_LOOG
4512 BFD_RELOC_METAG_REL8
4514 BFD_RELOC_METAG_REL16
4516 BFD_RELOC_METAG_HI16_GOTOFF
4518 BFD_RELOC_METAG_LO16_GOTOFF
4520 BFD_RELOC_METAG_GETSET_GOTOFF
4522 BFD_RELOC_METAG_GETSET_GOT
4524 BFD_RELOC_METAG_HI16_GOTPC
4526 BFD_RELOC_METAG_LO16_GOTPC
4528 BFD_RELOC_METAG_HI16_PLT
4530 BFD_RELOC_METAG_LO16_PLT
4532 BFD_RELOC_METAG_RELBRANCH_PLT
4534 BFD_RELOC_METAG_GOTOFF
4538 BFD_RELOC_METAG_COPY
4540 BFD_RELOC_METAG_JMP_SLOT
4542 BFD_RELOC_METAG_RELATIVE
4544 BFD_RELOC_METAG_GLOB_DAT
4546 BFD_RELOC_METAG_TLS_GD
4548 BFD_RELOC_METAG_TLS_LDM
4550 BFD_RELOC_METAG_TLS_LDO_HI16
4552 BFD_RELOC_METAG_TLS_LDO_LO16
4554 BFD_RELOC_METAG_TLS_LDO
4556 BFD_RELOC_METAG_TLS_IE
4558 BFD_RELOC_METAG_TLS_IENONPIC
4560 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4562 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4564 BFD_RELOC_METAG_TLS_TPOFF
4566 BFD_RELOC_METAG_TLS_DTPMOD
4568 BFD_RELOC_METAG_TLS_DTPOFF
4570 BFD_RELOC_METAG_TLS_LE
4572 BFD_RELOC_METAG_TLS_LE_HI16
4574 BFD_RELOC_METAG_TLS_LE_LO16
4576 Imagination Technologies Meta relocations.
4581 BFD_RELOC_MMIX_GETA_1
4583 BFD_RELOC_MMIX_GETA_2
4585 BFD_RELOC_MMIX_GETA_3
4587 These are relocations for the GETA instruction.
4589 BFD_RELOC_MMIX_CBRANCH
4591 BFD_RELOC_MMIX_CBRANCH_J
4593 BFD_RELOC_MMIX_CBRANCH_1
4595 BFD_RELOC_MMIX_CBRANCH_2
4597 BFD_RELOC_MMIX_CBRANCH_3
4599 These are relocations for a conditional branch instruction.
4601 BFD_RELOC_MMIX_PUSHJ
4603 BFD_RELOC_MMIX_PUSHJ_1
4605 BFD_RELOC_MMIX_PUSHJ_2
4607 BFD_RELOC_MMIX_PUSHJ_3
4609 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4611 These are relocations for the PUSHJ instruction.
4615 BFD_RELOC_MMIX_JMP_1
4617 BFD_RELOC_MMIX_JMP_2
4619 BFD_RELOC_MMIX_JMP_3
4621 These are relocations for the JMP instruction.
4623 BFD_RELOC_MMIX_ADDR19
4625 This is a relocation for a relative address as in a GETA instruction or
4628 BFD_RELOC_MMIX_ADDR27
4630 This is a relocation for a relative address as in a JMP instruction.
4632 BFD_RELOC_MMIX_REG_OR_BYTE
4634 This is a relocation for an instruction field that may be a general
4635 register or a value 0..255.
4639 This is a relocation for an instruction field that may be a general
4642 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4644 This is a relocation for two instruction fields holding a register and
4645 an offset, the equivalent of the relocation.
4647 BFD_RELOC_MMIX_LOCAL
4649 This relocation is an assertion that the expression is not allocated as
4650 a global register. It does not modify contents.
4653 BFD_RELOC_AVR_7_PCREL
4655 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4656 short offset into 7 bits.
4658 BFD_RELOC_AVR_13_PCREL
4660 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4661 short offset into 12 bits.
4665 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4666 program memory address) into 16 bits.
4668 BFD_RELOC_AVR_LO8_LDI
4670 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4671 data memory address) into 8 bit immediate value of LDI insn.
4673 BFD_RELOC_AVR_HI8_LDI
4675 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4676 of data memory address) into 8 bit immediate value of LDI insn.
4678 BFD_RELOC_AVR_HH8_LDI
4680 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4681 of program memory address) into 8 bit immediate value of LDI insn.
4683 BFD_RELOC_AVR_MS8_LDI
4685 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4686 of 32 bit value) into 8 bit immediate value of LDI insn.
4688 BFD_RELOC_AVR_LO8_LDI_NEG
4690 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4691 (usually data memory address) into 8 bit immediate value of SUBI insn.
4693 BFD_RELOC_AVR_HI8_LDI_NEG
4695 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4696 (high 8 bit of data memory address) into 8 bit immediate value of
4699 BFD_RELOC_AVR_HH8_LDI_NEG
4701 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4702 (most high 8 bit of program memory address) into 8 bit immediate value
4703 of LDI or SUBI insn.
4705 BFD_RELOC_AVR_MS8_LDI_NEG
4707 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4708 of 32 bit value) into 8 bit immediate value of LDI insn.
4710 BFD_RELOC_AVR_LO8_LDI_PM
4712 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4713 command address) into 8 bit immediate value of LDI insn.
4715 BFD_RELOC_AVR_LO8_LDI_GS
4717 This is a 16 bit reloc for the AVR that stores 8 bit value
4718 (command address) into 8 bit immediate value of LDI insn. If the address
4719 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4722 BFD_RELOC_AVR_HI8_LDI_PM
4724 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4725 of command address) into 8 bit immediate value of LDI insn.
4727 BFD_RELOC_AVR_HI8_LDI_GS
4729 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4730 of command address) into 8 bit immediate value of LDI insn. If the address
4731 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4734 BFD_RELOC_AVR_HH8_LDI_PM
4736 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4737 of command address) into 8 bit immediate value of LDI insn.
4739 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4741 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4742 (usually command address) into 8 bit immediate value of SUBI insn.
4744 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4746 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4747 (high 8 bit of 16 bit command address) into 8 bit immediate value
4750 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4752 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4753 (high 6 bit of 22 bit command address) into 8 bit immediate
4758 This is a 32 bit reloc for the AVR that stores 23 bit value
4763 This is a 16 bit reloc for the AVR that stores all needed bits
4764 for absolute addressing with ldi with overflow check to linktime
4768 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4771 BFD_RELOC_AVR_6_ADIW
4773 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4778 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4779 in .byte lo8(symbol)
4783 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4784 in .byte hi8(symbol)
4788 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4789 in .byte hlo8(symbol)
4793 BFD_RELOC_AVR_DIFF16
4795 BFD_RELOC_AVR_DIFF32
4797 AVR relocations to mark the difference of two local symbols.
4798 These are only needed to support linker relaxation and can be ignored
4799 when not relaxing. The field is set to the value of the difference
4800 assuming no relaxation. The relocation encodes the position of the
4801 second symbol so the linker can determine whether to adjust the field
4804 BFD_RELOC_AVR_LDS_STS_16
4806 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
4807 lds and sts instructions supported only tiny core.
4811 This is a 6 bit reloc for the AVR that stores an I/O register
4812 number for the IN and OUT instructions
4816 This is a 5 bit reloc for the AVR that stores an I/O register
4817 number for the SBIC, SBIS, SBI and CBI instructions
4821 BFD_RELOC_RL78_NEG16
4823 BFD_RELOC_RL78_NEG24
4825 BFD_RELOC_RL78_NEG32
4827 BFD_RELOC_RL78_16_OP
4829 BFD_RELOC_RL78_24_OP
4831 BFD_RELOC_RL78_32_OP
4839 BFD_RELOC_RL78_DIR3U_PCREL
4843 BFD_RELOC_RL78_GPRELB
4845 BFD_RELOC_RL78_GPRELW
4847 BFD_RELOC_RL78_GPRELL
4851 BFD_RELOC_RL78_OP_SUBTRACT
4853 BFD_RELOC_RL78_OP_NEG
4855 BFD_RELOC_RL78_OP_AND
4857 BFD_RELOC_RL78_OP_SHRA
4861 BFD_RELOC_RL78_ABS16
4863 BFD_RELOC_RL78_ABS16_REV
4865 BFD_RELOC_RL78_ABS32
4867 BFD_RELOC_RL78_ABS32_REV
4869 BFD_RELOC_RL78_ABS16U
4871 BFD_RELOC_RL78_ABS16UW
4873 BFD_RELOC_RL78_ABS16UL
4875 BFD_RELOC_RL78_RELAX
4885 Renesas RL78 Relocations.
4908 BFD_RELOC_RX_DIR3U_PCREL
4920 BFD_RELOC_RX_OP_SUBTRACT
4928 BFD_RELOC_RX_ABS16_REV
4932 BFD_RELOC_RX_ABS32_REV
4936 BFD_RELOC_RX_ABS16UW
4938 BFD_RELOC_RX_ABS16UL
4942 Renesas RX Relocations.
4955 32 bit PC relative PLT address.
4959 Copy symbol at runtime.
4961 BFD_RELOC_390_GLOB_DAT
4965 BFD_RELOC_390_JMP_SLOT
4969 BFD_RELOC_390_RELATIVE
4971 Adjust by program base.
4975 32 bit PC relative offset to GOT.
4981 BFD_RELOC_390_PC12DBL
4983 PC relative 12 bit shifted by 1.
4985 BFD_RELOC_390_PLT12DBL
4987 12 bit PC rel. PLT shifted by 1.
4989 BFD_RELOC_390_PC16DBL
4991 PC relative 16 bit shifted by 1.
4993 BFD_RELOC_390_PLT16DBL
4995 16 bit PC rel. PLT shifted by 1.
4997 BFD_RELOC_390_PC24DBL
4999 PC relative 24 bit shifted by 1.
5001 BFD_RELOC_390_PLT24DBL
5003 24 bit PC rel. PLT shifted by 1.
5005 BFD_RELOC_390_PC32DBL
5007 PC relative 32 bit shifted by 1.
5009 BFD_RELOC_390_PLT32DBL
5011 32 bit PC rel. PLT shifted by 1.
5013 BFD_RELOC_390_GOTPCDBL
5015 32 bit PC rel. GOT shifted by 1.
5023 64 bit PC relative PLT address.
5025 BFD_RELOC_390_GOTENT
5027 32 bit rel. offset to GOT entry.
5029 BFD_RELOC_390_GOTOFF64
5031 64 bit offset to GOT.
5033 BFD_RELOC_390_GOTPLT12
5035 12-bit offset to symbol-entry within GOT, with PLT handling.
5037 BFD_RELOC_390_GOTPLT16
5039 16-bit offset to symbol-entry within GOT, with PLT handling.
5041 BFD_RELOC_390_GOTPLT32
5043 32-bit offset to symbol-entry within GOT, with PLT handling.
5045 BFD_RELOC_390_GOTPLT64
5047 64-bit offset to symbol-entry within GOT, with PLT handling.
5049 BFD_RELOC_390_GOTPLTENT
5051 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5053 BFD_RELOC_390_PLTOFF16
5055 16-bit rel. offset from the GOT to a PLT entry.
5057 BFD_RELOC_390_PLTOFF32
5059 32-bit rel. offset from the GOT to a PLT entry.
5061 BFD_RELOC_390_PLTOFF64
5063 64-bit rel. offset from the GOT to a PLT entry.
5066 BFD_RELOC_390_TLS_LOAD
5068 BFD_RELOC_390_TLS_GDCALL
5070 BFD_RELOC_390_TLS_LDCALL
5072 BFD_RELOC_390_TLS_GD32
5074 BFD_RELOC_390_TLS_GD64
5076 BFD_RELOC_390_TLS_GOTIE12
5078 BFD_RELOC_390_TLS_GOTIE32
5080 BFD_RELOC_390_TLS_GOTIE64
5082 BFD_RELOC_390_TLS_LDM32
5084 BFD_RELOC_390_TLS_LDM64
5086 BFD_RELOC_390_TLS_IE32
5088 BFD_RELOC_390_TLS_IE64
5090 BFD_RELOC_390_TLS_IEENT
5092 BFD_RELOC_390_TLS_LE32
5094 BFD_RELOC_390_TLS_LE64
5096 BFD_RELOC_390_TLS_LDO32
5098 BFD_RELOC_390_TLS_LDO64
5100 BFD_RELOC_390_TLS_DTPMOD
5102 BFD_RELOC_390_TLS_DTPOFF
5104 BFD_RELOC_390_TLS_TPOFF
5106 s390 tls relocations.
5113 BFD_RELOC_390_GOTPLT20
5115 BFD_RELOC_390_TLS_GOTIE20
5117 Long displacement extension.
5120 BFD_RELOC_390_IRELATIVE
5122 STT_GNU_IFUNC relocation.
5125 BFD_RELOC_SCORE_GPREL15
5128 Low 16 bit for load/store
5130 BFD_RELOC_SCORE_DUMMY2
5134 This is a 24-bit reloc with the right 1 bit assumed to be 0
5136 BFD_RELOC_SCORE_BRANCH
5138 This is a 19-bit reloc with the right 1 bit assumed to be 0
5140 BFD_RELOC_SCORE_IMM30
5142 This is a 32-bit reloc for 48-bit instructions.
5144 BFD_RELOC_SCORE_IMM32
5146 This is a 32-bit reloc for 48-bit instructions.
5148 BFD_RELOC_SCORE16_JMP
5150 This is a 11-bit reloc with the right 1 bit assumed to be 0
5152 BFD_RELOC_SCORE16_BRANCH
5154 This is a 8-bit reloc with the right 1 bit assumed to be 0
5156 BFD_RELOC_SCORE_BCMP
5158 This is a 9-bit reloc with the right 1 bit assumed to be 0
5160 BFD_RELOC_SCORE_GOT15
5162 BFD_RELOC_SCORE_GOT_LO16
5164 BFD_RELOC_SCORE_CALL15
5166 BFD_RELOC_SCORE_DUMMY_HI16
5168 Undocumented Score relocs
5173 Scenix IP2K - 9-bit register number / data address
5177 Scenix IP2K - 4-bit register/data bank number
5179 BFD_RELOC_IP2K_ADDR16CJP
5181 Scenix IP2K - low 13 bits of instruction word address
5183 BFD_RELOC_IP2K_PAGE3
5185 Scenix IP2K - high 3 bits of instruction word address
5187 BFD_RELOC_IP2K_LO8DATA
5189 BFD_RELOC_IP2K_HI8DATA
5191 BFD_RELOC_IP2K_EX8DATA
5193 Scenix IP2K - ext/low/high 8 bits of data address
5195 BFD_RELOC_IP2K_LO8INSN
5197 BFD_RELOC_IP2K_HI8INSN
5199 Scenix IP2K - low/high 8 bits of instruction word address
5201 BFD_RELOC_IP2K_PC_SKIP
5203 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5207 Scenix IP2K - 16 bit word address in text section.
5209 BFD_RELOC_IP2K_FR_OFFSET
5211 Scenix IP2K - 7-bit sp or dp offset
5213 BFD_RELOC_VPE4KMATH_DATA
5215 BFD_RELOC_VPE4KMATH_INSN
5217 Scenix VPE4K coprocessor - data/insn-space addressing
5220 BFD_RELOC_VTABLE_INHERIT
5222 BFD_RELOC_VTABLE_ENTRY
5224 These two relocations are used by the linker to determine which of
5225 the entries in a C++ virtual function table are actually used. When
5226 the --gc-sections option is given, the linker will zero out the entries
5227 that are not used, so that the code for those functions need not be
5228 included in the output.
5230 VTABLE_INHERIT is a zero-space relocation used to describe to the
5231 linker the inheritance tree of a C++ virtual function table. The
5232 relocation's symbol should be the parent class' vtable, and the
5233 relocation should be located at the child vtable.
5235 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5236 virtual function table entry. The reloc's symbol should refer to the
5237 table of the class mentioned in the code. Off of that base, an offset
5238 describes the entry that is being used. For Rela hosts, this offset
5239 is stored in the reloc's addend. For Rel hosts, we are forced to put
5240 this offset in the reloc's section offset.
5243 BFD_RELOC_IA64_IMM14
5245 BFD_RELOC_IA64_IMM22
5247 BFD_RELOC_IA64_IMM64
5249 BFD_RELOC_IA64_DIR32MSB
5251 BFD_RELOC_IA64_DIR32LSB
5253 BFD_RELOC_IA64_DIR64MSB
5255 BFD_RELOC_IA64_DIR64LSB
5257 BFD_RELOC_IA64_GPREL22
5259 BFD_RELOC_IA64_GPREL64I
5261 BFD_RELOC_IA64_GPREL32MSB
5263 BFD_RELOC_IA64_GPREL32LSB
5265 BFD_RELOC_IA64_GPREL64MSB
5267 BFD_RELOC_IA64_GPREL64LSB
5269 BFD_RELOC_IA64_LTOFF22
5271 BFD_RELOC_IA64_LTOFF64I
5273 BFD_RELOC_IA64_PLTOFF22
5275 BFD_RELOC_IA64_PLTOFF64I
5277 BFD_RELOC_IA64_PLTOFF64MSB
5279 BFD_RELOC_IA64_PLTOFF64LSB
5281 BFD_RELOC_IA64_FPTR64I
5283 BFD_RELOC_IA64_FPTR32MSB
5285 BFD_RELOC_IA64_FPTR32LSB
5287 BFD_RELOC_IA64_FPTR64MSB
5289 BFD_RELOC_IA64_FPTR64LSB
5291 BFD_RELOC_IA64_PCREL21B
5293 BFD_RELOC_IA64_PCREL21BI
5295 BFD_RELOC_IA64_PCREL21M
5297 BFD_RELOC_IA64_PCREL21F
5299 BFD_RELOC_IA64_PCREL22
5301 BFD_RELOC_IA64_PCREL60B
5303 BFD_RELOC_IA64_PCREL64I
5305 BFD_RELOC_IA64_PCREL32MSB
5307 BFD_RELOC_IA64_PCREL32LSB
5309 BFD_RELOC_IA64_PCREL64MSB
5311 BFD_RELOC_IA64_PCREL64LSB
5313 BFD_RELOC_IA64_LTOFF_FPTR22
5315 BFD_RELOC_IA64_LTOFF_FPTR64I
5317 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5319 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5321 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5323 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5325 BFD_RELOC_IA64_SEGREL32MSB
5327 BFD_RELOC_IA64_SEGREL32LSB
5329 BFD_RELOC_IA64_SEGREL64MSB
5331 BFD_RELOC_IA64_SEGREL64LSB
5333 BFD_RELOC_IA64_SECREL32MSB
5335 BFD_RELOC_IA64_SECREL32LSB
5337 BFD_RELOC_IA64_SECREL64MSB
5339 BFD_RELOC_IA64_SECREL64LSB
5341 BFD_RELOC_IA64_REL32MSB
5343 BFD_RELOC_IA64_REL32LSB
5345 BFD_RELOC_IA64_REL64MSB
5347 BFD_RELOC_IA64_REL64LSB
5349 BFD_RELOC_IA64_LTV32MSB
5351 BFD_RELOC_IA64_LTV32LSB
5353 BFD_RELOC_IA64_LTV64MSB
5355 BFD_RELOC_IA64_LTV64LSB
5357 BFD_RELOC_IA64_IPLTMSB
5359 BFD_RELOC_IA64_IPLTLSB
5363 BFD_RELOC_IA64_LTOFF22X
5365 BFD_RELOC_IA64_LDXMOV
5367 BFD_RELOC_IA64_TPREL14
5369 BFD_RELOC_IA64_TPREL22
5371 BFD_RELOC_IA64_TPREL64I
5373 BFD_RELOC_IA64_TPREL64MSB
5375 BFD_RELOC_IA64_TPREL64LSB
5377 BFD_RELOC_IA64_LTOFF_TPREL22
5379 BFD_RELOC_IA64_DTPMOD64MSB
5381 BFD_RELOC_IA64_DTPMOD64LSB
5383 BFD_RELOC_IA64_LTOFF_DTPMOD22
5385 BFD_RELOC_IA64_DTPREL14
5387 BFD_RELOC_IA64_DTPREL22
5389 BFD_RELOC_IA64_DTPREL64I
5391 BFD_RELOC_IA64_DTPREL32MSB
5393 BFD_RELOC_IA64_DTPREL32LSB
5395 BFD_RELOC_IA64_DTPREL64MSB
5397 BFD_RELOC_IA64_DTPREL64LSB
5399 BFD_RELOC_IA64_LTOFF_DTPREL22
5401 Intel IA64 Relocations.
5404 BFD_RELOC_M68HC11_HI8
5406 Motorola 68HC11 reloc.
5407 This is the 8 bit high part of an absolute address.
5409 BFD_RELOC_M68HC11_LO8
5411 Motorola 68HC11 reloc.
5412 This is the 8 bit low part of an absolute address.
5414 BFD_RELOC_M68HC11_3B
5416 Motorola 68HC11 reloc.
5417 This is the 3 bit of a value.
5419 BFD_RELOC_M68HC11_RL_JUMP
5421 Motorola 68HC11 reloc.
5422 This reloc marks the beginning of a jump/call instruction.
5423 It is used for linker relaxation to correctly identify beginning
5424 of instruction and change some branches to use PC-relative
5427 BFD_RELOC_M68HC11_RL_GROUP
5429 Motorola 68HC11 reloc.
5430 This reloc marks a group of several instructions that gcc generates
5431 and for which the linker relaxation pass can modify and/or remove
5434 BFD_RELOC_M68HC11_LO16
5436 Motorola 68HC11 reloc.
5437 This is the 16-bit lower part of an address. It is used for 'call'
5438 instruction to specify the symbol address without any special
5439 transformation (due to memory bank window).
5441 BFD_RELOC_M68HC11_PAGE
5443 Motorola 68HC11 reloc.
5444 This is a 8-bit reloc that specifies the page number of an address.
5445 It is used by 'call' instruction to specify the page number of
5448 BFD_RELOC_M68HC11_24
5450 Motorola 68HC11 reloc.
5451 This is a 24-bit reloc that represents the address with a 16-bit
5452 value and a 8-bit page number. The symbol address is transformed
5453 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5455 BFD_RELOC_M68HC12_5B
5457 Motorola 68HC12 reloc.
5458 This is the 5 bits of a value.
5460 BFD_RELOC_XGATE_RL_JUMP
5462 Freescale XGATE reloc.
5463 This reloc marks the beginning of a bra/jal instruction.
5465 BFD_RELOC_XGATE_RL_GROUP
5467 Freescale XGATE reloc.
5468 This reloc marks a group of several instructions that gcc generates
5469 and for which the linker relaxation pass can modify and/or remove
5472 BFD_RELOC_XGATE_LO16
5474 Freescale XGATE reloc.
5475 This is the 16-bit lower part of an address. It is used for the '16-bit'
5478 BFD_RELOC_XGATE_GPAGE
5480 Freescale XGATE reloc.
5484 Freescale XGATE reloc.
5486 BFD_RELOC_XGATE_PCREL_9
5488 Freescale XGATE reloc.
5489 This is a 9-bit pc-relative reloc.
5491 BFD_RELOC_XGATE_PCREL_10
5493 Freescale XGATE reloc.
5494 This is a 10-bit pc-relative reloc.
5496 BFD_RELOC_XGATE_IMM8_LO
5498 Freescale XGATE reloc.
5499 This is the 16-bit lower part of an address. It is used for the '16-bit'
5502 BFD_RELOC_XGATE_IMM8_HI
5504 Freescale XGATE reloc.
5505 This is the 16-bit higher part of an address. It is used for the '16-bit'
5508 BFD_RELOC_XGATE_IMM3
5510 Freescale XGATE reloc.
5511 This is a 3-bit pc-relative reloc.
5513 BFD_RELOC_XGATE_IMM4
5515 Freescale XGATE reloc.
5516 This is a 4-bit pc-relative reloc.
5518 BFD_RELOC_XGATE_IMM5
5520 Freescale XGATE reloc.
5521 This is a 5-bit pc-relative reloc.
5523 BFD_RELOC_M68HC12_9B
5525 Motorola 68HC12 reloc.
5526 This is the 9 bits of a value.
5528 BFD_RELOC_M68HC12_16B
5530 Motorola 68HC12 reloc.
5531 This is the 16 bits of a value.
5533 BFD_RELOC_M68HC12_9_PCREL
5535 Motorola 68HC12/XGATE reloc.
5536 This is a PCREL9 branch.
5538 BFD_RELOC_M68HC12_10_PCREL
5540 Motorola 68HC12/XGATE reloc.
5541 This is a PCREL10 branch.
5543 BFD_RELOC_M68HC12_LO8XG
5545 Motorola 68HC12/XGATE reloc.
5546 This is the 8 bit low part of an absolute address and immediately precedes
5547 a matching HI8XG part.
5549 BFD_RELOC_M68HC12_HI8XG
5551 Motorola 68HC12/XGATE reloc.
5552 This is the 8 bit high part of an absolute address and immediately follows
5553 a matching LO8XG part.
5557 BFD_RELOC_16C_NUM08_C
5561 BFD_RELOC_16C_NUM16_C
5565 BFD_RELOC_16C_NUM32_C
5567 BFD_RELOC_16C_DISP04
5569 BFD_RELOC_16C_DISP04_C
5571 BFD_RELOC_16C_DISP08
5573 BFD_RELOC_16C_DISP08_C
5575 BFD_RELOC_16C_DISP16
5577 BFD_RELOC_16C_DISP16_C
5579 BFD_RELOC_16C_DISP24
5581 BFD_RELOC_16C_DISP24_C
5583 BFD_RELOC_16C_DISP24a
5585 BFD_RELOC_16C_DISP24a_C
5589 BFD_RELOC_16C_REG04_C
5591 BFD_RELOC_16C_REG04a
5593 BFD_RELOC_16C_REG04a_C
5597 BFD_RELOC_16C_REG14_C
5601 BFD_RELOC_16C_REG16_C
5605 BFD_RELOC_16C_REG20_C
5609 BFD_RELOC_16C_ABS20_C
5613 BFD_RELOC_16C_ABS24_C
5617 BFD_RELOC_16C_IMM04_C
5621 BFD_RELOC_16C_IMM16_C
5625 BFD_RELOC_16C_IMM20_C
5629 BFD_RELOC_16C_IMM24_C
5633 BFD_RELOC_16C_IMM32_C
5635 NS CR16C Relocations.
5640 BFD_RELOC_CR16_NUM16
5642 BFD_RELOC_CR16_NUM32
5644 BFD_RELOC_CR16_NUM32a
5646 BFD_RELOC_CR16_REGREL0
5648 BFD_RELOC_CR16_REGREL4
5650 BFD_RELOC_CR16_REGREL4a
5652 BFD_RELOC_CR16_REGREL14
5654 BFD_RELOC_CR16_REGREL14a
5656 BFD_RELOC_CR16_REGREL16
5658 BFD_RELOC_CR16_REGREL20
5660 BFD_RELOC_CR16_REGREL20a
5662 BFD_RELOC_CR16_ABS20
5664 BFD_RELOC_CR16_ABS24
5670 BFD_RELOC_CR16_IMM16
5672 BFD_RELOC_CR16_IMM20
5674 BFD_RELOC_CR16_IMM24
5676 BFD_RELOC_CR16_IMM32
5678 BFD_RELOC_CR16_IMM32a
5680 BFD_RELOC_CR16_DISP4
5682 BFD_RELOC_CR16_DISP8
5684 BFD_RELOC_CR16_DISP16
5686 BFD_RELOC_CR16_DISP20
5688 BFD_RELOC_CR16_DISP24
5690 BFD_RELOC_CR16_DISP24a
5692 BFD_RELOC_CR16_SWITCH8
5694 BFD_RELOC_CR16_SWITCH16
5696 BFD_RELOC_CR16_SWITCH32
5698 BFD_RELOC_CR16_GOT_REGREL20
5700 BFD_RELOC_CR16_GOTC_REGREL20
5702 BFD_RELOC_CR16_GLOB_DAT
5704 NS CR16 Relocations.
5711 BFD_RELOC_CRX_REL8_CMP
5719 BFD_RELOC_CRX_REGREL12
5721 BFD_RELOC_CRX_REGREL22
5723 BFD_RELOC_CRX_REGREL28
5725 BFD_RELOC_CRX_REGREL32
5741 BFD_RELOC_CRX_SWITCH8
5743 BFD_RELOC_CRX_SWITCH16
5745 BFD_RELOC_CRX_SWITCH32
5750 BFD_RELOC_CRIS_BDISP8
5752 BFD_RELOC_CRIS_UNSIGNED_5
5754 BFD_RELOC_CRIS_SIGNED_6
5756 BFD_RELOC_CRIS_UNSIGNED_6
5758 BFD_RELOC_CRIS_SIGNED_8
5760 BFD_RELOC_CRIS_UNSIGNED_8
5762 BFD_RELOC_CRIS_SIGNED_16
5764 BFD_RELOC_CRIS_UNSIGNED_16
5766 BFD_RELOC_CRIS_LAPCQ_OFFSET
5768 BFD_RELOC_CRIS_UNSIGNED_4
5770 These relocs are only used within the CRIS assembler. They are not
5771 (at present) written to any object files.
5775 BFD_RELOC_CRIS_GLOB_DAT
5777 BFD_RELOC_CRIS_JUMP_SLOT
5779 BFD_RELOC_CRIS_RELATIVE
5781 Relocs used in ELF shared libraries for CRIS.
5783 BFD_RELOC_CRIS_32_GOT
5785 32-bit offset to symbol-entry within GOT.
5787 BFD_RELOC_CRIS_16_GOT
5789 16-bit offset to symbol-entry within GOT.
5791 BFD_RELOC_CRIS_32_GOTPLT
5793 32-bit offset to symbol-entry within GOT, with PLT handling.
5795 BFD_RELOC_CRIS_16_GOTPLT
5797 16-bit offset to symbol-entry within GOT, with PLT handling.
5799 BFD_RELOC_CRIS_32_GOTREL
5801 32-bit offset to symbol, relative to GOT.
5803 BFD_RELOC_CRIS_32_PLT_GOTREL
5805 32-bit offset to symbol with PLT entry, relative to GOT.
5807 BFD_RELOC_CRIS_32_PLT_PCREL
5809 32-bit offset to symbol with PLT entry, relative to this relocation.
5812 BFD_RELOC_CRIS_32_GOT_GD
5814 BFD_RELOC_CRIS_16_GOT_GD
5816 BFD_RELOC_CRIS_32_GD
5820 BFD_RELOC_CRIS_32_DTPREL
5822 BFD_RELOC_CRIS_16_DTPREL
5824 BFD_RELOC_CRIS_32_GOT_TPREL
5826 BFD_RELOC_CRIS_16_GOT_TPREL
5828 BFD_RELOC_CRIS_32_TPREL
5830 BFD_RELOC_CRIS_16_TPREL
5832 BFD_RELOC_CRIS_DTPMOD
5834 BFD_RELOC_CRIS_32_IE
5836 Relocs used in TLS code for CRIS.
5841 BFD_RELOC_860_GLOB_DAT
5843 BFD_RELOC_860_JUMP_SLOT
5845 BFD_RELOC_860_RELATIVE
5855 BFD_RELOC_860_SPLIT0
5859 BFD_RELOC_860_SPLIT1
5863 BFD_RELOC_860_SPLIT2
5867 BFD_RELOC_860_LOGOT0
5869 BFD_RELOC_860_SPGOT0
5871 BFD_RELOC_860_LOGOT1
5873 BFD_RELOC_860_SPGOT1
5875 BFD_RELOC_860_LOGOTOFF0
5877 BFD_RELOC_860_SPGOTOFF0
5879 BFD_RELOC_860_LOGOTOFF1
5881 BFD_RELOC_860_SPGOTOFF1
5883 BFD_RELOC_860_LOGOTOFF2
5885 BFD_RELOC_860_LOGOTOFF3
5889 BFD_RELOC_860_HIGHADJ
5893 BFD_RELOC_860_HAGOTOFF
5901 BFD_RELOC_860_HIGOTOFF
5903 Intel i860 Relocations.
5906 BFD_RELOC_OR1K_REL_26
5908 BFD_RELOC_OR1K_GOTPC_HI16
5910 BFD_RELOC_OR1K_GOTPC_LO16
5912 BFD_RELOC_OR1K_GOT16
5914 BFD_RELOC_OR1K_PLT26
5916 BFD_RELOC_OR1K_GOTOFF_HI16
5918 BFD_RELOC_OR1K_GOTOFF_LO16
5922 BFD_RELOC_OR1K_GLOB_DAT
5924 BFD_RELOC_OR1K_JMP_SLOT
5926 BFD_RELOC_OR1K_RELATIVE
5928 BFD_RELOC_OR1K_TLS_GD_HI16
5930 BFD_RELOC_OR1K_TLS_GD_LO16
5932 BFD_RELOC_OR1K_TLS_LDM_HI16
5934 BFD_RELOC_OR1K_TLS_LDM_LO16
5936 BFD_RELOC_OR1K_TLS_LDO_HI16
5938 BFD_RELOC_OR1K_TLS_LDO_LO16
5940 BFD_RELOC_OR1K_TLS_IE_HI16
5942 BFD_RELOC_OR1K_TLS_IE_LO16
5944 BFD_RELOC_OR1K_TLS_LE_HI16
5946 BFD_RELOC_OR1K_TLS_LE_LO16
5948 BFD_RELOC_OR1K_TLS_TPOFF
5950 BFD_RELOC_OR1K_TLS_DTPOFF
5952 BFD_RELOC_OR1K_TLS_DTPMOD
5954 OpenRISC 1000 Relocations.
5957 BFD_RELOC_H8_DIR16A8
5959 BFD_RELOC_H8_DIR16R8
5961 BFD_RELOC_H8_DIR24A8
5963 BFD_RELOC_H8_DIR24R8
5965 BFD_RELOC_H8_DIR32A16
5967 BFD_RELOC_H8_DISP32A16
5972 BFD_RELOC_XSTORMY16_REL_12
5974 BFD_RELOC_XSTORMY16_12
5976 BFD_RELOC_XSTORMY16_24
5978 BFD_RELOC_XSTORMY16_FPTR16
5980 Sony Xstormy16 Relocations.
5985 Self-describing complex relocations.
5997 Infineon Relocations.
6000 BFD_RELOC_VAX_GLOB_DAT
6002 BFD_RELOC_VAX_JMP_SLOT
6004 BFD_RELOC_VAX_RELATIVE
6006 Relocations used by VAX ELF.
6011 Morpho MT - 16 bit immediate relocation.
6015 Morpho MT - Hi 16 bits of an address.
6019 Morpho MT - Low 16 bits of an address.
6021 BFD_RELOC_MT_GNU_VTINHERIT
6023 Morpho MT - Used to tell the linker which vtable entries are used.
6025 BFD_RELOC_MT_GNU_VTENTRY
6027 Morpho MT - Used to tell the linker which vtable entries are used.
6029 BFD_RELOC_MT_PCINSN8
6031 Morpho MT - 8 bit immediate relocation.
6034 BFD_RELOC_MSP430_10_PCREL
6036 BFD_RELOC_MSP430_16_PCREL
6040 BFD_RELOC_MSP430_16_PCREL_BYTE
6042 BFD_RELOC_MSP430_16_BYTE
6044 BFD_RELOC_MSP430_2X_PCREL
6046 BFD_RELOC_MSP430_RL_PCREL
6048 BFD_RELOC_MSP430_ABS8
6050 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6052 BFD_RELOC_MSP430X_PCR20_EXT_DST
6054 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6056 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6058 BFD_RELOC_MSP430X_ABS20_EXT_DST
6060 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6062 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6064 BFD_RELOC_MSP430X_ABS20_ADR_DST
6066 BFD_RELOC_MSP430X_PCR16
6068 BFD_RELOC_MSP430X_PCR20_CALL
6070 BFD_RELOC_MSP430X_ABS16
6072 BFD_RELOC_MSP430_ABS_HI16
6074 BFD_RELOC_MSP430_PREL31
6076 BFD_RELOC_MSP430_SYM_DIFF
6078 msp430 specific relocation codes
6085 BFD_RELOC_NIOS2_CALL26
6087 BFD_RELOC_NIOS2_IMM5
6089 BFD_RELOC_NIOS2_CACHE_OPX
6091 BFD_RELOC_NIOS2_IMM6
6093 BFD_RELOC_NIOS2_IMM8
6095 BFD_RELOC_NIOS2_HI16
6097 BFD_RELOC_NIOS2_LO16
6099 BFD_RELOC_NIOS2_HIADJ16
6101 BFD_RELOC_NIOS2_GPREL
6103 BFD_RELOC_NIOS2_UJMP
6105 BFD_RELOC_NIOS2_CJMP
6107 BFD_RELOC_NIOS2_CALLR
6109 BFD_RELOC_NIOS2_ALIGN
6111 BFD_RELOC_NIOS2_GOT16
6113 BFD_RELOC_NIOS2_CALL16
6115 BFD_RELOC_NIOS2_GOTOFF_LO
6117 BFD_RELOC_NIOS2_GOTOFF_HA
6119 BFD_RELOC_NIOS2_PCREL_LO
6121 BFD_RELOC_NIOS2_PCREL_HA
6123 BFD_RELOC_NIOS2_TLS_GD16
6125 BFD_RELOC_NIOS2_TLS_LDM16
6127 BFD_RELOC_NIOS2_TLS_LDO16
6129 BFD_RELOC_NIOS2_TLS_IE16
6131 BFD_RELOC_NIOS2_TLS_LE16
6133 BFD_RELOC_NIOS2_TLS_DTPMOD
6135 BFD_RELOC_NIOS2_TLS_DTPREL
6137 BFD_RELOC_NIOS2_TLS_TPREL
6139 BFD_RELOC_NIOS2_COPY
6141 BFD_RELOC_NIOS2_GLOB_DAT
6143 BFD_RELOC_NIOS2_JUMP_SLOT
6145 BFD_RELOC_NIOS2_RELATIVE
6147 BFD_RELOC_NIOS2_GOTOFF
6149 BFD_RELOC_NIOS2_CALL26_NOAT
6151 BFD_RELOC_NIOS2_GOT_LO
6153 BFD_RELOC_NIOS2_GOT_HA
6155 BFD_RELOC_NIOS2_CALL_LO
6157 BFD_RELOC_NIOS2_CALL_HA
6159 Relocations used by the Altera Nios II core.
6162 BFD_RELOC_IQ2000_OFFSET_16
6164 BFD_RELOC_IQ2000_OFFSET_21
6166 BFD_RELOC_IQ2000_UHI16
6171 BFD_RELOC_XTENSA_RTLD
6173 Special Xtensa relocation used only by PLT entries in ELF shared
6174 objects to indicate that the runtime linker should set the value
6175 to one of its own internal functions or data structures.
6177 BFD_RELOC_XTENSA_GLOB_DAT
6179 BFD_RELOC_XTENSA_JMP_SLOT
6181 BFD_RELOC_XTENSA_RELATIVE
6183 Xtensa relocations for ELF shared objects.
6185 BFD_RELOC_XTENSA_PLT
6187 Xtensa relocation used in ELF object files for symbols that may require
6188 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6190 BFD_RELOC_XTENSA_DIFF8
6192 BFD_RELOC_XTENSA_DIFF16
6194 BFD_RELOC_XTENSA_DIFF32
6196 Xtensa relocations to mark the difference of two local symbols.
6197 These are only needed to support linker relaxation and can be ignored
6198 when not relaxing. The field is set to the value of the difference
6199 assuming no relaxation. The relocation encodes the position of the
6200 first symbol so the linker can determine whether to adjust the field
6203 BFD_RELOC_XTENSA_SLOT0_OP
6205 BFD_RELOC_XTENSA_SLOT1_OP
6207 BFD_RELOC_XTENSA_SLOT2_OP
6209 BFD_RELOC_XTENSA_SLOT3_OP
6211 BFD_RELOC_XTENSA_SLOT4_OP
6213 BFD_RELOC_XTENSA_SLOT5_OP
6215 BFD_RELOC_XTENSA_SLOT6_OP
6217 BFD_RELOC_XTENSA_SLOT7_OP
6219 BFD_RELOC_XTENSA_SLOT8_OP
6221 BFD_RELOC_XTENSA_SLOT9_OP
6223 BFD_RELOC_XTENSA_SLOT10_OP
6225 BFD_RELOC_XTENSA_SLOT11_OP
6227 BFD_RELOC_XTENSA_SLOT12_OP
6229 BFD_RELOC_XTENSA_SLOT13_OP
6231 BFD_RELOC_XTENSA_SLOT14_OP
6233 Generic Xtensa relocations for instruction operands. Only the slot
6234 number is encoded in the relocation. The relocation applies to the
6235 last PC-relative immediate operand, or if there are no PC-relative
6236 immediates, to the last immediate operand.
6238 BFD_RELOC_XTENSA_SLOT0_ALT
6240 BFD_RELOC_XTENSA_SLOT1_ALT
6242 BFD_RELOC_XTENSA_SLOT2_ALT
6244 BFD_RELOC_XTENSA_SLOT3_ALT
6246 BFD_RELOC_XTENSA_SLOT4_ALT
6248 BFD_RELOC_XTENSA_SLOT5_ALT
6250 BFD_RELOC_XTENSA_SLOT6_ALT
6252 BFD_RELOC_XTENSA_SLOT7_ALT
6254 BFD_RELOC_XTENSA_SLOT8_ALT
6256 BFD_RELOC_XTENSA_SLOT9_ALT
6258 BFD_RELOC_XTENSA_SLOT10_ALT
6260 BFD_RELOC_XTENSA_SLOT11_ALT
6262 BFD_RELOC_XTENSA_SLOT12_ALT
6264 BFD_RELOC_XTENSA_SLOT13_ALT
6266 BFD_RELOC_XTENSA_SLOT14_ALT
6268 Alternate Xtensa relocations. Only the slot is encoded in the
6269 relocation. The meaning of these relocations is opcode-specific.
6271 BFD_RELOC_XTENSA_OP0
6273 BFD_RELOC_XTENSA_OP1
6275 BFD_RELOC_XTENSA_OP2
6277 Xtensa relocations for backward compatibility. These have all been
6278 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6280 BFD_RELOC_XTENSA_ASM_EXPAND
6282 Xtensa relocation to mark that the assembler expanded the
6283 instructions from an original target. The expansion size is
6284 encoded in the reloc size.
6286 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6288 Xtensa relocation to mark that the linker should simplify
6289 assembler-expanded instructions. This is commonly used
6290 internally by the linker after analysis of a
6291 BFD_RELOC_XTENSA_ASM_EXPAND.
6293 BFD_RELOC_XTENSA_TLSDESC_FN
6295 BFD_RELOC_XTENSA_TLSDESC_ARG
6297 BFD_RELOC_XTENSA_TLS_DTPOFF
6299 BFD_RELOC_XTENSA_TLS_TPOFF
6301 BFD_RELOC_XTENSA_TLS_FUNC
6303 BFD_RELOC_XTENSA_TLS_ARG
6305 BFD_RELOC_XTENSA_TLS_CALL
6307 Xtensa TLS relocations.
6312 8 bit signed offset in (ix+d) or (iy+d).
6330 BFD_RELOC_LM32_BRANCH
6332 BFD_RELOC_LM32_16_GOT
6334 BFD_RELOC_LM32_GOTOFF_HI16
6336 BFD_RELOC_LM32_GOTOFF_LO16
6340 BFD_RELOC_LM32_GLOB_DAT
6342 BFD_RELOC_LM32_JMP_SLOT
6344 BFD_RELOC_LM32_RELATIVE
6346 Lattice Mico32 relocations.
6349 BFD_RELOC_MACH_O_SECTDIFF
6351 Difference between two section addreses. Must be followed by a
6352 BFD_RELOC_MACH_O_PAIR.
6354 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6356 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6358 BFD_RELOC_MACH_O_PAIR
6360 Pair of relocation. Contains the first symbol.
6363 BFD_RELOC_MACH_O_X86_64_BRANCH32
6365 BFD_RELOC_MACH_O_X86_64_BRANCH8
6367 PCREL relocations. They are marked as branch to create PLT entry if
6370 BFD_RELOC_MACH_O_X86_64_GOT
6372 Used when referencing a GOT entry.
6374 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6376 Used when loading a GOT entry with movq. It is specially marked so that
6377 the linker could optimize the movq to a leaq if possible.
6379 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
6381 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6383 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
6385 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6387 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6389 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6391 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6393 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6395 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6397 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6400 BFD_RELOC_MICROBLAZE_32_LO
6402 This is a 32 bit reloc for the microblaze that stores the
6403 low 16 bits of a value
6405 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6407 This is a 32 bit pc-relative reloc for the microblaze that
6408 stores the low 16 bits of a value
6410 BFD_RELOC_MICROBLAZE_32_ROSDA
6412 This is a 32 bit reloc for the microblaze that stores a
6413 value relative to the read-only small data area anchor
6415 BFD_RELOC_MICROBLAZE_32_RWSDA
6417 This is a 32 bit reloc for the microblaze that stores a
6418 value relative to the read-write small data area anchor
6420 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6422 This is a 32 bit reloc for the microblaze to handle
6423 expressions of the form "Symbol Op Symbol"
6425 BFD_RELOC_MICROBLAZE_64_NONE
6427 This is a 64 bit reloc that stores the 32 bit pc relative
6428 value in two words (with an imm instruction). No relocation is
6429 done here - only used for relaxing
6431 BFD_RELOC_MICROBLAZE_64_GOTPC
6433 This is a 64 bit reloc that stores the 32 bit pc relative
6434 value in two words (with an imm instruction). The relocation is
6435 PC-relative GOT offset
6437 BFD_RELOC_MICROBLAZE_64_GOT
6439 This is a 64 bit reloc that stores the 32 bit pc relative
6440 value in two words (with an imm instruction). The relocation is
6443 BFD_RELOC_MICROBLAZE_64_PLT
6445 This is a 64 bit reloc that stores the 32 bit pc relative
6446 value in two words (with an imm instruction). The relocation is
6447 PC-relative offset into PLT
6449 BFD_RELOC_MICROBLAZE_64_GOTOFF
6451 This is a 64 bit reloc that stores the 32 bit GOT relative
6452 value in two words (with an imm instruction). The relocation is
6453 relative offset from _GLOBAL_OFFSET_TABLE_
6455 BFD_RELOC_MICROBLAZE_32_GOTOFF
6457 This is a 32 bit reloc that stores the 32 bit GOT relative
6458 value in a word. The relocation is relative offset from
6459 _GLOBAL_OFFSET_TABLE_
6461 BFD_RELOC_MICROBLAZE_COPY
6463 This is used to tell the dynamic linker to copy the value out of
6464 the dynamic object into the runtime process image.
6466 BFD_RELOC_MICROBLAZE_64_TLS
6470 BFD_RELOC_MICROBLAZE_64_TLSGD
6472 This is a 64 bit reloc that stores the 32 bit GOT relative value
6473 of the GOT TLS GD info entry in two words (with an imm instruction). The
6474 relocation is GOT offset.
6476 BFD_RELOC_MICROBLAZE_64_TLSLD
6478 This is a 64 bit reloc that stores the 32 bit GOT relative value
6479 of the GOT TLS LD info entry in two words (with an imm instruction). The
6480 relocation is GOT offset.
6482 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6484 This is a 32 bit reloc that stores the Module ID to GOT(n).
6486 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6488 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6490 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6492 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6495 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6497 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6498 to two words (uses imm instruction).
6500 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6502 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6503 to two words (uses imm instruction).
6506 BFD_RELOC_AARCH64_RELOC_START
6508 AArch64 pseudo relocation code to mark the start of the AArch64
6509 relocation enumerators. N.B. the order of the enumerators is
6510 important as several tables in the AArch64 bfd backend are indexed
6511 by these enumerators; make sure they are all synced.
6513 BFD_RELOC_AARCH64_NONE
6515 AArch64 null relocation code.
6517 BFD_RELOC_AARCH64_64
6519 BFD_RELOC_AARCH64_32
6521 BFD_RELOC_AARCH64_16
6523 Basic absolute relocations of N bits. These are equivalent to
6524 BFD_RELOC_N and they were added to assist the indexing of the howto
6527 BFD_RELOC_AARCH64_64_PCREL
6529 BFD_RELOC_AARCH64_32_PCREL
6531 BFD_RELOC_AARCH64_16_PCREL
6533 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6534 and they were added to assist the indexing of the howto table.
6536 BFD_RELOC_AARCH64_MOVW_G0
6538 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6539 of an unsigned address/value.
6541 BFD_RELOC_AARCH64_MOVW_G0_NC
6543 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6544 an address/value. No overflow checking.
6546 BFD_RELOC_AARCH64_MOVW_G1
6548 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6549 of an unsigned address/value.
6551 BFD_RELOC_AARCH64_MOVW_G1_NC
6553 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6554 of an address/value. No overflow checking.
6556 BFD_RELOC_AARCH64_MOVW_G2
6558 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6559 of an unsigned address/value.
6561 BFD_RELOC_AARCH64_MOVW_G2_NC
6563 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6564 of an address/value. No overflow checking.
6566 BFD_RELOC_AARCH64_MOVW_G3
6568 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6569 of a signed or unsigned address/value.
6571 BFD_RELOC_AARCH64_MOVW_G0_S
6573 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6574 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6577 BFD_RELOC_AARCH64_MOVW_G1_S
6579 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6580 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6583 BFD_RELOC_AARCH64_MOVW_G2_S
6585 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6586 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6589 BFD_RELOC_AARCH64_LD_LO19_PCREL
6591 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6592 offset. The lowest two bits must be zero and are not stored in the
6593 instruction, giving a 21 bit signed byte offset.
6595 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6597 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6599 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6601 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6602 offset, giving a 4KB aligned page base address.
6604 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6606 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6607 offset, giving a 4KB aligned page base address, but with no overflow
6610 BFD_RELOC_AARCH64_ADD_LO12
6612 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6613 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6615 BFD_RELOC_AARCH64_LDST8_LO12
6617 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6618 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6620 BFD_RELOC_AARCH64_TSTBR14
6622 AArch64 14 bit pc-relative test bit and branch.
6623 The lowest two bits must be zero and are not stored in the instruction,
6624 giving a 16 bit signed byte offset.
6626 BFD_RELOC_AARCH64_BRANCH19
6628 AArch64 19 bit pc-relative conditional branch and compare & branch.
6629 The lowest two bits must be zero and are not stored in the instruction,
6630 giving a 21 bit signed byte offset.
6632 BFD_RELOC_AARCH64_JUMP26
6634 AArch64 26 bit pc-relative unconditional branch.
6635 The lowest two bits must be zero and are not stored in the instruction,
6636 giving a 28 bit signed byte offset.
6638 BFD_RELOC_AARCH64_CALL26
6640 AArch64 26 bit pc-relative unconditional branch and link.
6641 The lowest two bits must be zero and are not stored in the instruction,
6642 giving a 28 bit signed byte offset.
6644 BFD_RELOC_AARCH64_LDST16_LO12
6646 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6647 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6649 BFD_RELOC_AARCH64_LDST32_LO12
6651 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6652 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6654 BFD_RELOC_AARCH64_LDST64_LO12
6656 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6657 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6659 BFD_RELOC_AARCH64_LDST128_LO12
6661 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6662 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6664 BFD_RELOC_AARCH64_GOT_LD_PREL19
6666 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6667 offset of the global offset table entry for a symbol. The lowest two
6668 bits must be zero and are not stored in the instruction, giving a 21
6669 bit signed byte offset. This relocation type requires signed overflow
6672 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6674 Get to the page base of the global offset table entry for a symbol as
6675 part of an ADRP instruction using a 21 bit PC relative value.Used in
6676 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6678 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6680 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6681 the GOT entry for this symbol. Used in conjunction with
6682 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
6684 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6686 Unsigned 12 bit byte offset for 32 bit load/store from the page of
6687 the GOT entry for this symbol. Used in conjunction with
6688 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
6690 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6692 Get to the page base of the global offset table entry for a symbols
6693 tls_index structure as part of an adrp instruction using a 21 bit PC
6694 relative value. Used in conjunction with
6695 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6697 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6699 Unsigned 12 bit byte offset to global offset table entry for a symbols
6700 tls_index structure. Used in conjunction with
6701 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
6703 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
6705 AArch64 TLS INITIAL EXEC relocation.
6707 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
6709 AArch64 TLS INITIAL EXEC relocation.
6711 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
6713 AArch64 TLS INITIAL EXEC relocation.
6715 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
6717 AArch64 TLS INITIAL EXEC relocation.
6719 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6721 AArch64 TLS INITIAL EXEC relocation.
6723 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
6725 AArch64 TLS INITIAL EXEC relocation.
6727 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
6729 AArch64 TLS LOCAL EXEC relocation.
6731 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
6733 AArch64 TLS LOCAL EXEC relocation.
6735 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
6737 AArch64 TLS LOCAL EXEC relocation.
6739 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
6741 AArch64 TLS LOCAL EXEC relocation.
6743 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
6745 AArch64 TLS LOCAL EXEC relocation.
6747 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
6749 AArch64 TLS LOCAL EXEC relocation.
6751 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
6753 AArch64 TLS LOCAL EXEC relocation.
6755 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
6757 AArch64 TLS LOCAL EXEC relocation.
6759 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
6761 AArch64 TLS DESC relocation.
6763 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
6765 AArch64 TLS DESC relocation.
6767 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
6769 AArch64 TLS DESC relocation.
6771 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
6773 AArch64 TLS DESC relocation.
6775 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6777 AArch64 TLS DESC relocation.
6779 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
6781 AArch64 TLS DESC relocation.
6783 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
6785 AArch64 TLS DESC relocation.
6787 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
6789 AArch64 TLS DESC relocation.
6791 BFD_RELOC_AARCH64_TLSDESC_LDR
6793 AArch64 TLS DESC relocation.
6795 BFD_RELOC_AARCH64_TLSDESC_ADD
6797 AArch64 TLS DESC relocation.
6799 BFD_RELOC_AARCH64_TLSDESC_CALL
6801 AArch64 TLS DESC relocation.
6803 BFD_RELOC_AARCH64_COPY
6805 AArch64 TLS relocation.
6807 BFD_RELOC_AARCH64_GLOB_DAT
6809 AArch64 TLS relocation.
6811 BFD_RELOC_AARCH64_JUMP_SLOT
6813 AArch64 TLS relocation.
6815 BFD_RELOC_AARCH64_RELATIVE
6817 AArch64 TLS relocation.
6819 BFD_RELOC_AARCH64_TLS_DTPMOD
6821 AArch64 TLS relocation.
6823 BFD_RELOC_AARCH64_TLS_DTPREL
6825 AArch64 TLS relocation.
6827 BFD_RELOC_AARCH64_TLS_TPREL
6829 AArch64 TLS relocation.
6831 BFD_RELOC_AARCH64_TLSDESC
6833 AArch64 TLS relocation.
6835 BFD_RELOC_AARCH64_IRELATIVE
6837 AArch64 support for STT_GNU_IFUNC.
6839 BFD_RELOC_AARCH64_RELOC_END
6841 AArch64 pseudo relocation code to mark the end of the AArch64
6842 relocation enumerators that have direct mapping to ELF reloc codes.
6843 There are a few more enumerators after this one; those are mainly
6844 used by the AArch64 assembler for the internal fixup or to select
6845 one of the above enumerators.
6847 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
6849 AArch64 pseudo relocation code to be used internally by the AArch64
6850 assembler and not (currently) written to any object files.
6852 BFD_RELOC_AARCH64_LDST_LO12
6854 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
6855 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6857 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
6859 AArch64 pseudo relocation code to be used internally by the AArch64
6860 assembler and not (currently) written to any object files.
6862 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
6864 AArch64 pseudo relocation code to be used internally by the AArch64
6865 assembler and not (currently) written to any object files.
6867 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
6869 AArch64 pseudo relocation code to be used internally by the AArch64
6870 assembler and not (currently) written to any object files.
6873 BFD_RELOC_TILEPRO_COPY
6875 BFD_RELOC_TILEPRO_GLOB_DAT
6877 BFD_RELOC_TILEPRO_JMP_SLOT
6879 BFD_RELOC_TILEPRO_RELATIVE
6881 BFD_RELOC_TILEPRO_BROFF_X1
6883 BFD_RELOC_TILEPRO_JOFFLONG_X1
6885 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
6887 BFD_RELOC_TILEPRO_IMM8_X0
6889 BFD_RELOC_TILEPRO_IMM8_Y0
6891 BFD_RELOC_TILEPRO_IMM8_X1
6893 BFD_RELOC_TILEPRO_IMM8_Y1
6895 BFD_RELOC_TILEPRO_DEST_IMM8_X1
6897 BFD_RELOC_TILEPRO_MT_IMM15_X1
6899 BFD_RELOC_TILEPRO_MF_IMM15_X1
6901 BFD_RELOC_TILEPRO_IMM16_X0
6903 BFD_RELOC_TILEPRO_IMM16_X1
6905 BFD_RELOC_TILEPRO_IMM16_X0_LO
6907 BFD_RELOC_TILEPRO_IMM16_X1_LO
6909 BFD_RELOC_TILEPRO_IMM16_X0_HI
6911 BFD_RELOC_TILEPRO_IMM16_X1_HI
6913 BFD_RELOC_TILEPRO_IMM16_X0_HA
6915 BFD_RELOC_TILEPRO_IMM16_X1_HA
6917 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
6919 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
6921 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
6923 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
6925 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
6927 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
6929 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
6931 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
6933 BFD_RELOC_TILEPRO_IMM16_X0_GOT
6935 BFD_RELOC_TILEPRO_IMM16_X1_GOT
6937 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
6939 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
6941 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
6943 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
6945 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
6947 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
6949 BFD_RELOC_TILEPRO_MMSTART_X0
6951 BFD_RELOC_TILEPRO_MMEND_X0
6953 BFD_RELOC_TILEPRO_MMSTART_X1
6955 BFD_RELOC_TILEPRO_MMEND_X1
6957 BFD_RELOC_TILEPRO_SHAMT_X0
6959 BFD_RELOC_TILEPRO_SHAMT_X1
6961 BFD_RELOC_TILEPRO_SHAMT_Y0
6963 BFD_RELOC_TILEPRO_SHAMT_Y1
6965 BFD_RELOC_TILEPRO_TLS_GD_CALL
6967 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
6969 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
6971 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
6973 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
6975 BFD_RELOC_TILEPRO_TLS_IE_LOAD
6977 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
6979 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
6981 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
6983 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
6985 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
6987 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
6989 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
6991 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
6993 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
6995 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
6997 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
6999 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7001 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7003 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7005 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7007 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7009 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7011 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7013 BFD_RELOC_TILEPRO_TLS_TPOFF32
7015 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7017 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7019 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7021 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7023 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7025 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7027 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7029 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7031 Tilera TILEPro Relocations.
7033 BFD_RELOC_TILEGX_HW0
7035 BFD_RELOC_TILEGX_HW1
7037 BFD_RELOC_TILEGX_HW2
7039 BFD_RELOC_TILEGX_HW3
7041 BFD_RELOC_TILEGX_HW0_LAST
7043 BFD_RELOC_TILEGX_HW1_LAST
7045 BFD_RELOC_TILEGX_HW2_LAST
7047 BFD_RELOC_TILEGX_COPY
7049 BFD_RELOC_TILEGX_GLOB_DAT
7051 BFD_RELOC_TILEGX_JMP_SLOT
7053 BFD_RELOC_TILEGX_RELATIVE
7055 BFD_RELOC_TILEGX_BROFF_X1
7057 BFD_RELOC_TILEGX_JUMPOFF_X1
7059 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7061 BFD_RELOC_TILEGX_IMM8_X0
7063 BFD_RELOC_TILEGX_IMM8_Y0
7065 BFD_RELOC_TILEGX_IMM8_X1
7067 BFD_RELOC_TILEGX_IMM8_Y1
7069 BFD_RELOC_TILEGX_DEST_IMM8_X1
7071 BFD_RELOC_TILEGX_MT_IMM14_X1
7073 BFD_RELOC_TILEGX_MF_IMM14_X1
7075 BFD_RELOC_TILEGX_MMSTART_X0
7077 BFD_RELOC_TILEGX_MMEND_X0
7079 BFD_RELOC_TILEGX_SHAMT_X0
7081 BFD_RELOC_TILEGX_SHAMT_X1
7083 BFD_RELOC_TILEGX_SHAMT_Y0
7085 BFD_RELOC_TILEGX_SHAMT_Y1
7087 BFD_RELOC_TILEGX_IMM16_X0_HW0
7089 BFD_RELOC_TILEGX_IMM16_X1_HW0
7091 BFD_RELOC_TILEGX_IMM16_X0_HW1
7093 BFD_RELOC_TILEGX_IMM16_X1_HW1
7095 BFD_RELOC_TILEGX_IMM16_X0_HW2
7097 BFD_RELOC_TILEGX_IMM16_X1_HW2
7099 BFD_RELOC_TILEGX_IMM16_X0_HW3
7101 BFD_RELOC_TILEGX_IMM16_X1_HW3
7103 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7105 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7107 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7109 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7111 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7113 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7115 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7117 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7119 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7121 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7123 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7125 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7127 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7129 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7131 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7133 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7135 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7137 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7139 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7141 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7143 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7145 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7147 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7149 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7151 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7153 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7155 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7157 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7159 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7161 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7163 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7165 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7167 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7169 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7171 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7173 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7175 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7177 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7179 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7181 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7183 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7185 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7187 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7189 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7191 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7193 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7195 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7197 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7199 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7201 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7203 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7205 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7207 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7209 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7211 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7213 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7215 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7217 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7219 BFD_RELOC_TILEGX_TLS_DTPMOD64
7221 BFD_RELOC_TILEGX_TLS_DTPOFF64
7223 BFD_RELOC_TILEGX_TLS_TPOFF64
7225 BFD_RELOC_TILEGX_TLS_DTPMOD32
7227 BFD_RELOC_TILEGX_TLS_DTPOFF32
7229 BFD_RELOC_TILEGX_TLS_TPOFF32
7231 BFD_RELOC_TILEGX_TLS_GD_CALL
7233 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7235 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7237 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7239 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7241 BFD_RELOC_TILEGX_TLS_IE_LOAD
7243 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7245 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7247 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7249 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7251 Tilera TILE-Gx Relocations.
7253 BFD_RELOC_EPIPHANY_SIMM8
7255 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7257 BFD_RELOC_EPIPHANY_SIMM24
7259 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7261 BFD_RELOC_EPIPHANY_HIGH
7263 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7265 BFD_RELOC_EPIPHANY_LOW
7267 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7269 BFD_RELOC_EPIPHANY_SIMM11
7271 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7273 BFD_RELOC_EPIPHANY_IMM11
7275 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7277 BFD_RELOC_EPIPHANY_IMM8
7279 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7286 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7291 bfd_reloc_type_lookup
7292 bfd_reloc_name_lookup
7295 reloc_howto_type *bfd_reloc_type_lookup
7296 (bfd *abfd, bfd_reloc_code_real_type code);
7297 reloc_howto_type *bfd_reloc_name_lookup
7298 (bfd *abfd, const char *reloc_name);
7301 Return a pointer to a howto structure which, when
7302 invoked, will perform the relocation @var{code} on data from the
7308 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7310 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
7314 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
7316 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
7319 static reloc_howto_type bfd_howto_32 =
7320 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
7324 bfd_default_reloc_type_lookup
7327 reloc_howto_type *bfd_default_reloc_type_lookup
7328 (bfd *abfd, bfd_reloc_code_real_type code);
7331 Provides a default relocation lookup routine for any architecture.
7336 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7340 case BFD_RELOC_CTOR:
7341 /* The type of reloc used in a ctor, which will be as wide as the
7342 address - so either a 64, 32, or 16 bitter. */
7343 switch (bfd_arch_bits_per_address (abfd))
7348 return &bfd_howto_32;
7362 bfd_get_reloc_code_name
7365 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7368 Provides a printable name for the supplied relocation code.
7369 Useful mainly for printing error messages.
7373 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
7375 if (code > BFD_RELOC_UNUSED)
7377 return bfd_reloc_code_real_names[code];
7382 bfd_generic_relax_section
7385 bfd_boolean bfd_generic_relax_section
7388 struct bfd_link_info *,
7392 Provides default handling for relaxing for back ends which
7397 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
7398 asection *section ATTRIBUTE_UNUSED,
7399 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
7402 if (link_info->relocatable)
7403 (*link_info->callbacks->einfo)
7404 (_("%P%F: --relax and -r may not be used together\n"));
7412 bfd_generic_gc_sections
7415 bfd_boolean bfd_generic_gc_sections
7416 (bfd *, struct bfd_link_info *);
7419 Provides default handling for relaxing for back ends which
7420 don't do section gc -- i.e., does nothing.
7424 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
7425 struct bfd_link_info *info ATTRIBUTE_UNUSED)
7432 bfd_generic_lookup_section_flags
7435 bfd_boolean bfd_generic_lookup_section_flags
7436 (struct bfd_link_info *, struct flag_info *, asection *);
7439 Provides default handling for section flags lookup
7440 -- i.e., does nothing.
7441 Returns FALSE if the section should be omitted, otherwise TRUE.
7445 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
7446 struct flag_info *flaginfo,
7447 asection *section ATTRIBUTE_UNUSED)
7449 if (flaginfo != NULL)
7451 (*_bfd_error_handler) (_("INPUT_SECTION_FLAGS are not supported.\n"));
7459 bfd_generic_merge_sections
7462 bfd_boolean bfd_generic_merge_sections
7463 (bfd *, struct bfd_link_info *);
7466 Provides default handling for SEC_MERGE section merging for back ends
7467 which don't have SEC_MERGE support -- i.e., does nothing.
7471 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
7472 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
7479 bfd_generic_get_relocated_section_contents
7482 bfd_byte *bfd_generic_get_relocated_section_contents
7484 struct bfd_link_info *link_info,
7485 struct bfd_link_order *link_order,
7487 bfd_boolean relocatable,
7491 Provides default handling of relocation effort for back ends
7492 which can't be bothered to do it efficiently.
7497 bfd_generic_get_relocated_section_contents (bfd *abfd,
7498 struct bfd_link_info *link_info,
7499 struct bfd_link_order *link_order,
7501 bfd_boolean relocatable,
7504 bfd *input_bfd = link_order->u.indirect.section->owner;
7505 asection *input_section = link_order->u.indirect.section;
7507 arelent **reloc_vector;
7510 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
7514 /* Read in the section. */
7515 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
7518 if (reloc_size == 0)
7521 reloc_vector = (arelent **) bfd_malloc (reloc_size);
7522 if (reloc_vector == NULL)
7525 reloc_count = bfd_canonicalize_reloc (input_bfd,
7529 if (reloc_count < 0)
7532 if (reloc_count > 0)
7535 for (parent = reloc_vector; *parent != NULL; parent++)
7537 char *error_message = NULL;
7539 bfd_reloc_status_type r;
7541 symbol = *(*parent)->sym_ptr_ptr;
7542 if (symbol->section && discarded_section (symbol->section))
7545 static reloc_howto_type none_howto
7546 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
7547 "unused", FALSE, 0, 0, FALSE);
7549 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
7550 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
7552 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
7553 (*parent)->addend = 0;
7554 (*parent)->howto = &none_howto;
7558 r = bfd_perform_relocation (input_bfd,
7562 relocatable ? abfd : NULL,
7567 asection *os = input_section->output_section;
7569 /* A partial link, so keep the relocs. */
7570 os->orelocation[os->reloc_count] = *parent;
7574 if (r != bfd_reloc_ok)
7578 case bfd_reloc_undefined:
7579 if (!((*link_info->callbacks->undefined_symbol)
7580 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
7581 input_bfd, input_section, (*parent)->address,
7585 case bfd_reloc_dangerous:
7586 BFD_ASSERT (error_message != NULL);
7587 if (!((*link_info->callbacks->reloc_dangerous)
7588 (link_info, error_message, input_bfd, input_section,
7589 (*parent)->address)))
7592 case bfd_reloc_overflow:
7593 if (!((*link_info->callbacks->reloc_overflow)
7595 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
7596 (*parent)->howto->name, (*parent)->addend,
7597 input_bfd, input_section, (*parent)->address)))
7600 case bfd_reloc_outofrange:
7602 This error can result when processing some partially
7603 complete binaries. Do not abort, but issue an error
7605 link_info->callbacks->einfo
7606 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
7607 abfd, input_section, * parent);
7619 free (reloc_vector);
7623 free (reloc_vector);