1 /* BFD support for handling relocation entries.
2 Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
6 Written by Cygnus Support.
8 This file is part of BFD, the Binary File Descriptor library.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
29 BFD maintains relocations in much the same way it maintains
30 symbols: they are left alone until required, then read in
31 en-masse and translated into an internal form. A common
32 routine <<bfd_perform_relocation>> acts upon the
33 canonical form to do the fixup.
35 Relocations are maintained on a per section basis,
36 while symbols are maintained on a per BFD basis.
38 All that a back end has to do to fit the BFD interface is to create
39 a <<struct reloc_cache_entry>> for each relocation
40 in a particular section, and fill in the right bits of the structures.
49 /* DO compile in the reloc_code name table from libbfd.h. */
50 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
59 typedef arelent, howto manager, Relocations, Relocations
64 This is the structure of a relocation entry:
68 .typedef enum bfd_reloc_status
70 . {* No errors detected. *}
73 . {* The relocation was performed, but there was an overflow. *}
76 . {* The address to relocate was not within the section supplied. *}
77 . bfd_reloc_outofrange,
79 . {* Used by special functions. *}
82 . {* Unsupported relocation size requested. *}
83 . bfd_reloc_notsupported,
88 . {* The symbol to relocate against was undefined. *}
89 . bfd_reloc_undefined,
91 . {* The relocation was performed, but may not be ok - presently
92 . generated only when linking i960 coff files with i960 b.out
93 . symbols. If this type is returned, the error_message argument
94 . to bfd_perform_relocation will be set. *}
97 . bfd_reloc_status_type;
100 .typedef struct reloc_cache_entry
102 . {* A pointer into the canonical table of pointers. *}
103 . struct bfd_symbol **sym_ptr_ptr;
105 . {* offset in section. *}
106 . bfd_size_type address;
108 . {* addend for relocation value. *}
111 . {* Pointer to how to perform the required relocation. *}
112 . reloc_howto_type *howto;
122 Here is a description of each of the fields within an <<arelent>>:
126 The symbol table pointer points to a pointer to the symbol
127 associated with the relocation request. It is the pointer
128 into the table returned by the back end's
129 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
130 referenced through a pointer to a pointer so that tools like
131 the linker can fix up all the symbols of the same name by
132 modifying only one pointer. The relocation routine looks in
133 the symbol and uses the base of the section the symbol is
134 attached to and the value of the symbol as the initial
135 relocation offset. If the symbol pointer is zero, then the
136 section provided is looked up.
140 The <<address>> field gives the offset in bytes from the base of
141 the section data which owns the relocation record to the first
142 byte of relocatable information. The actual data relocated
143 will be relative to this point; for example, a relocation
144 type which modifies the bottom two bytes of a four byte word
145 would not touch the first byte pointed to in a big endian
150 The <<addend>> is a value provided by the back end to be added (!)
151 to the relocation offset. Its interpretation is dependent upon
152 the howto. For example, on the 68k the code:
157 | return foo[0x12345678];
160 Could be compiled into:
163 | moveb @@#12345678,d0
168 This could create a reloc pointing to <<foo>>, but leave the
169 offset in the data, something like:
171 |RELOCATION RECORDS FOR [.text]:
175 |00000000 4e56 fffc ; linkw fp,#-4
176 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
177 |0000000a 49c0 ; extbl d0
178 |0000000c 4e5e ; unlk fp
181 Using coff and an 88k, some instructions don't have enough
182 space in them to represent the full address range, and
183 pointers have to be loaded in two parts. So you'd get something like:
185 | or.u r13,r0,hi16(_foo+0x12345678)
186 | ld.b r2,r13,lo16(_foo+0x12345678)
189 This should create two relocs, both pointing to <<_foo>>, and with
190 0x12340000 in their addend field. The data would consist of:
192 |RELOCATION RECORDS FOR [.text]:
194 |00000002 HVRT16 _foo+0x12340000
195 |00000006 LVRT16 _foo+0x12340000
197 |00000000 5da05678 ; or.u r13,r0,0x5678
198 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
199 |00000008 f400c001 ; jmp r1
201 The relocation routine digs out the value from the data, adds
202 it to the addend to get the original offset, and then adds the
203 value of <<_foo>>. Note that all 32 bits have to be kept around
204 somewhere, to cope with carry from bit 15 to bit 16.
206 One further example is the sparc and the a.out format. The
207 sparc has a similar problem to the 88k, in that some
208 instructions don't have room for an entire offset, but on the
209 sparc the parts are created in odd sized lumps. The designers of
210 the a.out format chose to not use the data within the section
211 for storing part of the offset; all the offset is kept within
212 the reloc. Anything in the data should be ignored.
215 | sethi %hi(_foo+0x12345678),%g2
216 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
220 Both relocs contain a pointer to <<foo>>, and the offsets
223 |RELOCATION RECORDS FOR [.text]:
225 |00000004 HI22 _foo+0x12345678
226 |00000008 LO10 _foo+0x12345678
228 |00000000 9de3bf90 ; save %sp,-112,%sp
229 |00000004 05000000 ; sethi %hi(_foo+0),%g2
230 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
231 |0000000c 81c7e008 ; ret
232 |00000010 81e80000 ; restore
236 The <<howto>> field can be imagined as a
237 relocation instruction. It is a pointer to a structure which
238 contains information on what to do with all of the other
239 information in the reloc record and data section. A back end
240 would normally have a relocation instruction set and turn
241 relocations into pointers to the correct structure on input -
242 but it would be possible to create each howto field on demand.
248 <<enum complain_overflow>>
250 Indicates what sort of overflow checking should be done when
251 performing a relocation.
255 .enum complain_overflow
257 . {* Do not complain on overflow. *}
258 . complain_overflow_dont,
260 . {* Complain if the value overflows when considered as a signed
261 . number one bit larger than the field. ie. A bitfield of N bits
262 . is allowed to represent -2**n to 2**n-1. *}
263 . complain_overflow_bitfield,
265 . {* Complain if the value overflows when considered as a signed
267 . complain_overflow_signed,
269 . {* Complain if the value overflows when considered as an
270 . unsigned number. *}
271 . complain_overflow_unsigned
280 The <<reloc_howto_type>> is a structure which contains all the
281 information that libbfd needs to know to tie up a back end's data.
284 .struct bfd_symbol; {* Forward declaration. *}
286 .struct reloc_howto_struct
288 . {* The type field has mainly a documentary use - the back end can
289 . do what it wants with it, though normally the back end's
290 . external idea of what a reloc number is stored
291 . in this field. For example, a PC relative word relocation
292 . in a coff environment has the type 023 - because that's
293 . what the outside world calls a R_PCRWORD reloc. *}
296 . {* The value the final relocation is shifted right by. This drops
297 . unwanted data from the relocation. *}
298 . unsigned int rightshift;
300 . {* The size of the item to be relocated. This is *not* a
301 . power-of-two measure. To get the number of bytes operated
302 . on by a type of relocation, use bfd_get_reloc_size. *}
305 . {* The number of bits in the item to be relocated. This is used
306 . when doing overflow checking. *}
307 . unsigned int bitsize;
309 . {* The relocation is relative to the field being relocated. *}
310 . bfd_boolean pc_relative;
312 . {* The bit position of the reloc value in the destination.
313 . The relocated value is left shifted by this amount. *}
314 . unsigned int bitpos;
316 . {* What type of overflow error should be checked for when
318 . enum complain_overflow complain_on_overflow;
320 . {* If this field is non null, then the supplied function is
321 . called rather than the normal function. This allows really
322 . strange relocation methods to be accommodated (e.g., i960 callj
324 . bfd_reloc_status_type (*special_function)
325 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
328 . {* The textual name of the relocation type. *}
331 . {* Some formats record a relocation addend in the section contents
332 . rather than with the relocation. For ELF formats this is the
333 . distinction between USE_REL and USE_RELA (though the code checks
334 . for USE_REL == 1/0). The value of this field is TRUE if the
335 . addend is recorded with the section contents; when performing a
336 . partial link (ld -r) the section contents (the data) will be
337 . modified. The value of this field is FALSE if addends are
338 . recorded with the relocation (in arelent.addend); when performing
339 . a partial link the relocation will be modified.
340 . All relocations for all ELF USE_RELA targets should set this field
341 . to FALSE (values of TRUE should be looked on with suspicion).
342 . However, the converse is not true: not all relocations of all ELF
343 . USE_REL targets set this field to TRUE. Why this is so is peculiar
344 . to each particular target. For relocs that aren't used in partial
345 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
346 . bfd_boolean partial_inplace;
348 . {* src_mask selects the part of the instruction (or data) to be used
349 . in the relocation sum. If the target relocations don't have an
350 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
351 . dst_mask to extract the addend from the section contents. If
352 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
353 . field should be zero. Non-zero values for ELF USE_RELA targets are
354 . bogus as in those cases the value in the dst_mask part of the
355 . section contents should be treated as garbage. *}
358 . {* dst_mask selects which parts of the instruction (or data) are
359 . replaced with a relocated value. *}
362 . {* When some formats create PC relative instructions, they leave
363 . the value of the pc of the place being relocated in the offset
364 . slot of the instruction, so that a PC relative relocation can
365 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
366 . Some formats leave the displacement part of an instruction
367 . empty (e.g., m88k bcs); this flag signals the fact. *}
368 . bfd_boolean pcrel_offset;
378 The HOWTO define is horrible and will go away.
380 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
381 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
384 And will be replaced with the totally magic way. But for the
385 moment, we are compatible, so do it this way.
387 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
388 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
389 . NAME, FALSE, 0, 0, IN)
393 This is used to fill in an empty howto entry in an array.
395 .#define EMPTY_HOWTO(C) \
396 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
397 . NULL, FALSE, 0, 0, FALSE)
401 Helper routine to turn a symbol into a relocation value.
403 .#define HOWTO_PREPARE(relocation, symbol) \
405 . if (symbol != NULL) \
407 . if (bfd_is_com_section (symbol->section)) \
413 . relocation = symbol->value; \
425 unsigned int bfd_get_reloc_size (reloc_howto_type *);
428 For a reloc_howto_type that operates on a fixed number of bytes,
429 this returns the number of bytes operated on.
433 bfd_get_reloc_size (reloc_howto_type *howto)
454 How relocs are tied together in an <<asection>>:
456 .typedef struct relent_chain
459 . struct relent_chain *next;
465 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
466 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
473 bfd_reloc_status_type bfd_check_overflow
474 (enum complain_overflow how,
475 unsigned int bitsize,
476 unsigned int rightshift,
477 unsigned int addrsize,
481 Perform overflow checking on @var{relocation} which has
482 @var{bitsize} significant bits and will be shifted right by
483 @var{rightshift} bits, on a machine with addresses containing
484 @var{addrsize} significant bits. The result is either of
485 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
489 bfd_reloc_status_type
490 bfd_check_overflow (enum complain_overflow how,
491 unsigned int bitsize,
492 unsigned int rightshift,
493 unsigned int addrsize,
496 bfd_vma fieldmask, addrmask, signmask, ss, a;
497 bfd_reloc_status_type flag = bfd_reloc_ok;
499 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
500 we'll be permissive: extra bits in the field mask will
501 automatically extend the address mask for purposes of the
503 fieldmask = N_ONES (bitsize);
504 signmask = ~fieldmask;
505 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
506 a = (relocation & addrmask) >> rightshift;
510 case complain_overflow_dont:
513 case complain_overflow_signed:
514 /* If any sign bits are set, all sign bits must be set. That
515 is, A must be a valid negative address after shifting. */
516 signmask = ~ (fieldmask >> 1);
519 case complain_overflow_bitfield:
520 /* Bitfields are sometimes signed, sometimes unsigned. We
521 explicitly allow an address wrap too, which means a bitfield
522 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
523 if the value has some, but not all, bits set outside the
526 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
527 flag = bfd_reloc_overflow;
530 case complain_overflow_unsigned:
531 /* We have an overflow if the address does not fit in the field. */
532 if ((a & signmask) != 0)
533 flag = bfd_reloc_overflow;
545 bfd_perform_relocation
548 bfd_reloc_status_type bfd_perform_relocation
550 arelent *reloc_entry,
552 asection *input_section,
554 char **error_message);
557 If @var{output_bfd} is supplied to this function, the
558 generated image will be relocatable; the relocations are
559 copied to the output file after they have been changed to
560 reflect the new state of the world. There are two ways of
561 reflecting the results of partial linkage in an output file:
562 by modifying the output data in place, and by modifying the
563 relocation record. Some native formats (e.g., basic a.out and
564 basic coff) have no way of specifying an addend in the
565 relocation type, so the addend has to go in the output data.
566 This is no big deal since in these formats the output data
567 slot will always be big enough for the addend. Complex reloc
568 types with addends were invented to solve just this problem.
569 The @var{error_message} argument is set to an error message if
570 this return @code{bfd_reloc_dangerous}.
574 bfd_reloc_status_type
575 bfd_perform_relocation (bfd *abfd,
576 arelent *reloc_entry,
578 asection *input_section,
580 char **error_message)
583 bfd_reloc_status_type flag = bfd_reloc_ok;
584 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
585 bfd_vma output_base = 0;
586 reloc_howto_type *howto = reloc_entry->howto;
587 asection *reloc_target_output_section;
590 symbol = *(reloc_entry->sym_ptr_ptr);
591 if (bfd_is_abs_section (symbol->section)
592 && output_bfd != NULL)
594 reloc_entry->address += input_section->output_offset;
598 /* If we are not producing relocatable output, return an error if
599 the symbol is not defined. An undefined weak symbol is
600 considered to have a value of zero (SVR4 ABI, p. 4-27). */
601 if (bfd_is_und_section (symbol->section)
602 && (symbol->flags & BSF_WEAK) == 0
603 && output_bfd == NULL)
604 flag = bfd_reloc_undefined;
606 /* If there is a function supplied to handle this relocation type,
607 call it. It'll return `bfd_reloc_continue' if further processing
609 if (howto->special_function)
611 bfd_reloc_status_type cont;
612 cont = howto->special_function (abfd, reloc_entry, symbol, data,
613 input_section, output_bfd,
615 if (cont != bfd_reloc_continue)
619 /* Is the address of the relocation really within the section? */
620 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
621 return bfd_reloc_outofrange;
623 /* Work out which section the relocation is targeted at and the
624 initial relocation command value. */
626 /* Get symbol value. (Common symbols are special.) */
627 if (bfd_is_com_section (symbol->section))
630 relocation = symbol->value;
632 reloc_target_output_section = symbol->section->output_section;
634 /* Convert input-section-relative symbol value to absolute. */
635 if ((output_bfd && ! howto->partial_inplace)
636 || reloc_target_output_section == NULL)
639 output_base = reloc_target_output_section->vma;
641 relocation += output_base + symbol->section->output_offset;
643 /* Add in supplied addend. */
644 relocation += reloc_entry->addend;
646 /* Here the variable relocation holds the final address of the
647 symbol we are relocating against, plus any addend. */
649 if (howto->pc_relative)
651 /* This is a PC relative relocation. We want to set RELOCATION
652 to the distance between the address of the symbol and the
653 location. RELOCATION is already the address of the symbol.
655 We start by subtracting the address of the section containing
658 If pcrel_offset is set, we must further subtract the position
659 of the location within the section. Some targets arrange for
660 the addend to be the negative of the position of the location
661 within the section; for example, i386-aout does this. For
662 i386-aout, pcrel_offset is FALSE. Some other targets do not
663 include the position of the location; for example, m88kbcs,
664 or ELF. For those targets, pcrel_offset is TRUE.
666 If we are producing relocatable output, then we must ensure
667 that this reloc will be correctly computed when the final
668 relocation is done. If pcrel_offset is FALSE we want to wind
669 up with the negative of the location within the section,
670 which means we must adjust the existing addend by the change
671 in the location within the section. If pcrel_offset is TRUE
672 we do not want to adjust the existing addend at all.
674 FIXME: This seems logical to me, but for the case of
675 producing relocatable output it is not what the code
676 actually does. I don't want to change it, because it seems
677 far too likely that something will break. */
680 input_section->output_section->vma + input_section->output_offset;
682 if (howto->pcrel_offset)
683 relocation -= reloc_entry->address;
686 if (output_bfd != NULL)
688 if (! howto->partial_inplace)
690 /* This is a partial relocation, and we want to apply the relocation
691 to the reloc entry rather than the raw data. Modify the reloc
692 inplace to reflect what we now know. */
693 reloc_entry->addend = relocation;
694 reloc_entry->address += input_section->output_offset;
699 /* This is a partial relocation, but inplace, so modify the
702 If we've relocated with a symbol with a section, change
703 into a ref to the section belonging to the symbol. */
705 reloc_entry->address += input_section->output_offset;
708 if (abfd->xvec->flavour == bfd_target_coff_flavour
709 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
710 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
712 /* For m68k-coff, the addend was being subtracted twice during
713 relocation with -r. Removing the line below this comment
714 fixes that problem; see PR 2953.
716 However, Ian wrote the following, regarding removing the line below,
717 which explains why it is still enabled: --djm
719 If you put a patch like that into BFD you need to check all the COFF
720 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
721 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
722 problem in a different way. There may very well be a reason that the
723 code works as it does.
725 Hmmm. The first obvious point is that bfd_perform_relocation should
726 not have any tests that depend upon the flavour. It's seem like
727 entirely the wrong place for such a thing. The second obvious point
728 is that the current code ignores the reloc addend when producing
729 relocatable output for COFF. That's peculiar. In fact, I really
730 have no idea what the point of the line you want to remove is.
732 A typical COFF reloc subtracts the old value of the symbol and adds in
733 the new value to the location in the object file (if it's a pc
734 relative reloc it adds the difference between the symbol value and the
735 location). When relocating we need to preserve that property.
737 BFD handles this by setting the addend to the negative of the old
738 value of the symbol. Unfortunately it handles common symbols in a
739 non-standard way (it doesn't subtract the old value) but that's a
740 different story (we can't change it without losing backward
741 compatibility with old object files) (coff-i386 does subtract the old
742 value, to be compatible with existing coff-i386 targets, like SCO).
744 So everything works fine when not producing relocatable output. When
745 we are producing relocatable output, logically we should do exactly
746 what we do when not producing relocatable output. Therefore, your
747 patch is correct. In fact, it should probably always just set
748 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
749 add the value into the object file. This won't hurt the COFF code,
750 which doesn't use the addend; I'm not sure what it will do to other
751 formats (the thing to check for would be whether any formats both use
752 the addend and set partial_inplace).
754 When I wanted to make coff-i386 produce relocatable output, I ran
755 into the problem that you are running into: I wanted to remove that
756 line. Rather than risk it, I made the coff-i386 relocs use a special
757 function; it's coff_i386_reloc in coff-i386.c. The function
758 specifically adds the addend field into the object file, knowing that
759 bfd_perform_relocation is not going to. If you remove that line, then
760 coff-i386.c will wind up adding the addend field in twice. It's
761 trivial to fix; it just needs to be done.
763 The problem with removing the line is just that it may break some
764 working code. With BFD it's hard to be sure of anything. The right
765 way to deal with this is simply to build and test at least all the
766 supported COFF targets. It should be straightforward if time and disk
767 space consuming. For each target:
769 2) generate some executable, and link it using -r (I would
770 probably use paranoia.o and link against newlib/libc.a, which
771 for all the supported targets would be available in
772 /usr/cygnus/progressive/H-host/target/lib/libc.a).
773 3) make the change to reloc.c
774 4) rebuild the linker
776 6) if the resulting object files are the same, you have at least
778 7) if they are different you have to figure out which version is
781 relocation -= reloc_entry->addend;
782 reloc_entry->addend = 0;
786 reloc_entry->addend = relocation;
792 reloc_entry->addend = 0;
795 /* FIXME: This overflow checking is incomplete, because the value
796 might have overflowed before we get here. For a correct check we
797 need to compute the value in a size larger than bitsize, but we
798 can't reasonably do that for a reloc the same size as a host
800 FIXME: We should also do overflow checking on the result after
801 adding in the value contained in the object file. */
802 if (howto->complain_on_overflow != complain_overflow_dont
803 && flag == bfd_reloc_ok)
804 flag = bfd_check_overflow (howto->complain_on_overflow,
807 bfd_arch_bits_per_address (abfd),
810 /* Either we are relocating all the way, or we don't want to apply
811 the relocation to the reloc entry (probably because there isn't
812 any room in the output format to describe addends to relocs). */
814 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
815 (OSF version 1.3, compiler version 3.11). It miscompiles the
829 x <<= (unsigned long) s.i0;
833 printf ("succeeded (%lx)\n", x);
837 relocation >>= (bfd_vma) howto->rightshift;
839 /* Shift everything up to where it's going to be used. */
840 relocation <<= (bfd_vma) howto->bitpos;
842 /* Wait for the day when all have the mask in them. */
845 i instruction to be left alone
846 o offset within instruction
847 r relocation offset to apply
856 (( i i i i i o o o o o from bfd_get<size>
857 and S S S S S) to get the size offset we want
858 + r r r r r r r r r r) to get the final value to place
859 and D D D D D to chop to right size
860 -----------------------
863 ( i i i i i o o o o o from bfd_get<size>
864 and N N N N N ) get instruction
865 -----------------------
871 -----------------------
872 = R R R R R R R R R R put into bfd_put<size>
876 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
882 char x = bfd_get_8 (abfd, (char *) data + octets);
884 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
890 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
892 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
897 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
899 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
904 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
905 relocation = -relocation;
907 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
913 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
914 relocation = -relocation;
916 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
927 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
929 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
936 return bfd_reloc_other;
944 bfd_install_relocation
947 bfd_reloc_status_type bfd_install_relocation
949 arelent *reloc_entry,
950 void *data, bfd_vma data_start,
951 asection *input_section,
952 char **error_message);
955 This looks remarkably like <<bfd_perform_relocation>>, except it
956 does not expect that the section contents have been filled in.
957 I.e., it's suitable for use when creating, rather than applying
960 For now, this function should be considered reserved for the
964 bfd_reloc_status_type
965 bfd_install_relocation (bfd *abfd,
966 arelent *reloc_entry,
968 bfd_vma data_start_offset,
969 asection *input_section,
970 char **error_message)
973 bfd_reloc_status_type flag = bfd_reloc_ok;
974 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
975 bfd_vma output_base = 0;
976 reloc_howto_type *howto = reloc_entry->howto;
977 asection *reloc_target_output_section;
981 symbol = *(reloc_entry->sym_ptr_ptr);
982 if (bfd_is_abs_section (symbol->section))
984 reloc_entry->address += input_section->output_offset;
988 /* If there is a function supplied to handle this relocation type,
989 call it. It'll return `bfd_reloc_continue' if further processing
991 if (howto->special_function)
993 bfd_reloc_status_type cont;
995 /* XXX - The special_function calls haven't been fixed up to deal
996 with creating new relocations and section contents. */
997 cont = howto->special_function (abfd, reloc_entry, symbol,
998 /* XXX - Non-portable! */
999 ((bfd_byte *) data_start
1000 - data_start_offset),
1001 input_section, abfd, error_message);
1002 if (cont != bfd_reloc_continue)
1006 /* Is the address of the relocation really within the section? */
1007 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
1008 return bfd_reloc_outofrange;
1010 /* Work out which section the relocation is targeted at and the
1011 initial relocation command value. */
1013 /* Get symbol value. (Common symbols are special.) */
1014 if (bfd_is_com_section (symbol->section))
1017 relocation = symbol->value;
1019 reloc_target_output_section = symbol->section->output_section;
1021 /* Convert input-section-relative symbol value to absolute. */
1022 if (! howto->partial_inplace)
1025 output_base = reloc_target_output_section->vma;
1027 relocation += output_base + symbol->section->output_offset;
1029 /* Add in supplied addend. */
1030 relocation += reloc_entry->addend;
1032 /* Here the variable relocation holds the final address of the
1033 symbol we are relocating against, plus any addend. */
1035 if (howto->pc_relative)
1037 /* This is a PC relative relocation. We want to set RELOCATION
1038 to the distance between the address of the symbol and the
1039 location. RELOCATION is already the address of the symbol.
1041 We start by subtracting the address of the section containing
1044 If pcrel_offset is set, we must further subtract the position
1045 of the location within the section. Some targets arrange for
1046 the addend to be the negative of the position of the location
1047 within the section; for example, i386-aout does this. For
1048 i386-aout, pcrel_offset is FALSE. Some other targets do not
1049 include the position of the location; for example, m88kbcs,
1050 or ELF. For those targets, pcrel_offset is TRUE.
1052 If we are producing relocatable output, then we must ensure
1053 that this reloc will be correctly computed when the final
1054 relocation is done. If pcrel_offset is FALSE we want to wind
1055 up with the negative of the location within the section,
1056 which means we must adjust the existing addend by the change
1057 in the location within the section. If pcrel_offset is TRUE
1058 we do not want to adjust the existing addend at all.
1060 FIXME: This seems logical to me, but for the case of
1061 producing relocatable output it is not what the code
1062 actually does. I don't want to change it, because it seems
1063 far too likely that something will break. */
1066 input_section->output_section->vma + input_section->output_offset;
1068 if (howto->pcrel_offset && howto->partial_inplace)
1069 relocation -= reloc_entry->address;
1072 if (! howto->partial_inplace)
1074 /* This is a partial relocation, and we want to apply the relocation
1075 to the reloc entry rather than the raw data. Modify the reloc
1076 inplace to reflect what we now know. */
1077 reloc_entry->addend = relocation;
1078 reloc_entry->address += input_section->output_offset;
1083 /* This is a partial relocation, but inplace, so modify the
1086 If we've relocated with a symbol with a section, change
1087 into a ref to the section belonging to the symbol. */
1088 reloc_entry->address += input_section->output_offset;
1091 if (abfd->xvec->flavour == bfd_target_coff_flavour
1092 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1093 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1096 /* For m68k-coff, the addend was being subtracted twice during
1097 relocation with -r. Removing the line below this comment
1098 fixes that problem; see PR 2953.
1100 However, Ian wrote the following, regarding removing the line below,
1101 which explains why it is still enabled: --djm
1103 If you put a patch like that into BFD you need to check all the COFF
1104 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1105 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1106 problem in a different way. There may very well be a reason that the
1107 code works as it does.
1109 Hmmm. The first obvious point is that bfd_install_relocation should
1110 not have any tests that depend upon the flavour. It's seem like
1111 entirely the wrong place for such a thing. The second obvious point
1112 is that the current code ignores the reloc addend when producing
1113 relocatable output for COFF. That's peculiar. In fact, I really
1114 have no idea what the point of the line you want to remove is.
1116 A typical COFF reloc subtracts the old value of the symbol and adds in
1117 the new value to the location in the object file (if it's a pc
1118 relative reloc it adds the difference between the symbol value and the
1119 location). When relocating we need to preserve that property.
1121 BFD handles this by setting the addend to the negative of the old
1122 value of the symbol. Unfortunately it handles common symbols in a
1123 non-standard way (it doesn't subtract the old value) but that's a
1124 different story (we can't change it without losing backward
1125 compatibility with old object files) (coff-i386 does subtract the old
1126 value, to be compatible with existing coff-i386 targets, like SCO).
1128 So everything works fine when not producing relocatable output. When
1129 we are producing relocatable output, logically we should do exactly
1130 what we do when not producing relocatable output. Therefore, your
1131 patch is correct. In fact, it should probably always just set
1132 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1133 add the value into the object file. This won't hurt the COFF code,
1134 which doesn't use the addend; I'm not sure what it will do to other
1135 formats (the thing to check for would be whether any formats both use
1136 the addend and set partial_inplace).
1138 When I wanted to make coff-i386 produce relocatable output, I ran
1139 into the problem that you are running into: I wanted to remove that
1140 line. Rather than risk it, I made the coff-i386 relocs use a special
1141 function; it's coff_i386_reloc in coff-i386.c. The function
1142 specifically adds the addend field into the object file, knowing that
1143 bfd_install_relocation is not going to. If you remove that line, then
1144 coff-i386.c will wind up adding the addend field in twice. It's
1145 trivial to fix; it just needs to be done.
1147 The problem with removing the line is just that it may break some
1148 working code. With BFD it's hard to be sure of anything. The right
1149 way to deal with this is simply to build and test at least all the
1150 supported COFF targets. It should be straightforward if time and disk
1151 space consuming. For each target:
1153 2) generate some executable, and link it using -r (I would
1154 probably use paranoia.o and link against newlib/libc.a, which
1155 for all the supported targets would be available in
1156 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1157 3) make the change to reloc.c
1158 4) rebuild the linker
1160 6) if the resulting object files are the same, you have at least
1162 7) if they are different you have to figure out which version is
1164 relocation -= reloc_entry->addend;
1165 /* FIXME: There should be no target specific code here... */
1166 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1167 reloc_entry->addend = 0;
1171 reloc_entry->addend = relocation;
1175 /* FIXME: This overflow checking is incomplete, because the value
1176 might have overflowed before we get here. For a correct check we
1177 need to compute the value in a size larger than bitsize, but we
1178 can't reasonably do that for a reloc the same size as a host
1180 FIXME: We should also do overflow checking on the result after
1181 adding in the value contained in the object file. */
1182 if (howto->complain_on_overflow != complain_overflow_dont)
1183 flag = bfd_check_overflow (howto->complain_on_overflow,
1186 bfd_arch_bits_per_address (abfd),
1189 /* Either we are relocating all the way, or we don't want to apply
1190 the relocation to the reloc entry (probably because there isn't
1191 any room in the output format to describe addends to relocs). */
1193 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1194 (OSF version 1.3, compiler version 3.11). It miscompiles the
1208 x <<= (unsigned long) s.i0;
1210 printf ("failed\n");
1212 printf ("succeeded (%lx)\n", x);
1216 relocation >>= (bfd_vma) howto->rightshift;
1218 /* Shift everything up to where it's going to be used. */
1219 relocation <<= (bfd_vma) howto->bitpos;
1221 /* Wait for the day when all have the mask in them. */
1224 i instruction to be left alone
1225 o offset within instruction
1226 r relocation offset to apply
1235 (( i i i i i o o o o o from bfd_get<size>
1236 and S S S S S) to get the size offset we want
1237 + r r r r r r r r r r) to get the final value to place
1238 and D D D D D to chop to right size
1239 -----------------------
1242 ( i i i i i o o o o o from bfd_get<size>
1243 and N N N N N ) get instruction
1244 -----------------------
1250 -----------------------
1251 = R R R R R R R R R R put into bfd_put<size>
1255 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1257 data = (bfd_byte *) data_start + (octets - data_start_offset);
1259 switch (howto->size)
1263 char x = bfd_get_8 (abfd, data);
1265 bfd_put_8 (abfd, x, data);
1271 short x = bfd_get_16 (abfd, data);
1273 bfd_put_16 (abfd, (bfd_vma) x, data);
1278 long x = bfd_get_32 (abfd, data);
1280 bfd_put_32 (abfd, (bfd_vma) x, data);
1285 long x = bfd_get_32 (abfd, data);
1286 relocation = -relocation;
1288 bfd_put_32 (abfd, (bfd_vma) x, data);
1298 bfd_vma x = bfd_get_64 (abfd, data);
1300 bfd_put_64 (abfd, x, data);
1304 return bfd_reloc_other;
1310 /* This relocation routine is used by some of the backend linkers.
1311 They do not construct asymbol or arelent structures, so there is no
1312 reason for them to use bfd_perform_relocation. Also,
1313 bfd_perform_relocation is so hacked up it is easier to write a new
1314 function than to try to deal with it.
1316 This routine does a final relocation. Whether it is useful for a
1317 relocatable link depends upon how the object format defines
1320 FIXME: This routine ignores any special_function in the HOWTO,
1321 since the existing special_function values have been written for
1322 bfd_perform_relocation.
1324 HOWTO is the reloc howto information.
1325 INPUT_BFD is the BFD which the reloc applies to.
1326 INPUT_SECTION is the section which the reloc applies to.
1327 CONTENTS is the contents of the section.
1328 ADDRESS is the address of the reloc within INPUT_SECTION.
1329 VALUE is the value of the symbol the reloc refers to.
1330 ADDEND is the addend of the reloc. */
1332 bfd_reloc_status_type
1333 _bfd_final_link_relocate (reloc_howto_type *howto,
1335 asection *input_section,
1343 /* Sanity check the address. */
1344 if (address > bfd_get_section_limit (input_bfd, input_section))
1345 return bfd_reloc_outofrange;
1347 /* This function assumes that we are dealing with a basic relocation
1348 against a symbol. We want to compute the value of the symbol to
1349 relocate to. This is just VALUE, the value of the symbol, plus
1350 ADDEND, any addend associated with the reloc. */
1351 relocation = value + addend;
1353 /* If the relocation is PC relative, we want to set RELOCATION to
1354 the distance between the symbol (currently in RELOCATION) and the
1355 location we are relocating. Some targets (e.g., i386-aout)
1356 arrange for the contents of the section to be the negative of the
1357 offset of the location within the section; for such targets
1358 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1359 simply leave the contents of the section as zero; for such
1360 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1361 need to subtract out the offset of the location within the
1362 section (which is just ADDRESS). */
1363 if (howto->pc_relative)
1365 relocation -= (input_section->output_section->vma
1366 + input_section->output_offset);
1367 if (howto->pcrel_offset)
1368 relocation -= address;
1371 return _bfd_relocate_contents (howto, input_bfd, relocation,
1372 contents + address);
1375 /* Relocate a given location using a given value and howto. */
1377 bfd_reloc_status_type
1378 _bfd_relocate_contents (reloc_howto_type *howto,
1385 bfd_reloc_status_type flag;
1386 unsigned int rightshift = howto->rightshift;
1387 unsigned int bitpos = howto->bitpos;
1389 /* If the size is negative, negate RELOCATION. This isn't very
1391 if (howto->size < 0)
1392 relocation = -relocation;
1394 /* Get the value we are going to relocate. */
1395 size = bfd_get_reloc_size (howto);
1402 x = bfd_get_8 (input_bfd, location);
1405 x = bfd_get_16 (input_bfd, location);
1408 x = bfd_get_32 (input_bfd, location);
1412 x = bfd_get_64 (input_bfd, location);
1419 /* Check for overflow. FIXME: We may drop bits during the addition
1420 which we don't check for. We must either check at every single
1421 operation, which would be tedious, or we must do the computations
1422 in a type larger than bfd_vma, which would be inefficient. */
1423 flag = bfd_reloc_ok;
1424 if (howto->complain_on_overflow != complain_overflow_dont)
1426 bfd_vma addrmask, fieldmask, signmask, ss;
1429 /* Get the values to be added together. For signed and unsigned
1430 relocations, we assume that all values should be truncated to
1431 the size of an address. For bitfields, all the bits matter.
1432 See also bfd_check_overflow. */
1433 fieldmask = N_ONES (howto->bitsize);
1434 signmask = ~fieldmask;
1435 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1436 | (fieldmask << rightshift));
1437 a = (relocation & addrmask) >> rightshift;
1438 b = (x & howto->src_mask & addrmask) >> bitpos;
1439 addrmask >>= rightshift;
1441 switch (howto->complain_on_overflow)
1443 case complain_overflow_signed:
1444 /* If any sign bits are set, all sign bits must be set.
1445 That is, A must be a valid negative address after
1447 signmask = ~(fieldmask >> 1);
1450 case complain_overflow_bitfield:
1451 /* Much like the signed check, but for a field one bit
1452 wider. We allow a bitfield to represent numbers in the
1453 range -2**n to 2**n-1, where n is the number of bits in the
1454 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1455 can't overflow, which is exactly what we want. */
1457 if (ss != 0 && ss != (addrmask & signmask))
1458 flag = bfd_reloc_overflow;
1460 /* We only need this next bit of code if the sign bit of B
1461 is below the sign bit of A. This would only happen if
1462 SRC_MASK had fewer bits than BITSIZE. Note that if
1463 SRC_MASK has more bits than BITSIZE, we can get into
1464 trouble; we would need to verify that B is in range, as
1465 we do for A above. */
1466 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1469 /* Set all the bits above the sign bit. */
1472 /* Now we can do the addition. */
1475 /* See if the result has the correct sign. Bits above the
1476 sign bit are junk now; ignore them. If the sum is
1477 positive, make sure we did not have all negative inputs;
1478 if the sum is negative, make sure we did not have all
1479 positive inputs. The test below looks only at the sign
1480 bits, and it really just
1481 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1483 We mask with addrmask here to explicitly allow an address
1484 wrap-around. The Linux kernel relies on it, and it is
1485 the only way to write assembler code which can run when
1486 loaded at a location 0x80000000 away from the location at
1487 which it is linked. */
1488 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1489 flag = bfd_reloc_overflow;
1492 case complain_overflow_unsigned:
1493 /* Checking for an unsigned overflow is relatively easy:
1494 trim the addresses and add, and trim the result as well.
1495 Overflow is normally indicated when the result does not
1496 fit in the field. However, we also need to consider the
1497 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1498 input is 0x80000000, and bfd_vma is only 32 bits; then we
1499 will get sum == 0, but there is an overflow, since the
1500 inputs did not fit in the field. Instead of doing a
1501 separate test, we can check for this by or-ing in the
1502 operands when testing for the sum overflowing its final
1504 sum = (a + b) & addrmask;
1505 if ((a | b | sum) & signmask)
1506 flag = bfd_reloc_overflow;
1514 /* Put RELOCATION in the right bits. */
1515 relocation >>= (bfd_vma) rightshift;
1516 relocation <<= (bfd_vma) bitpos;
1518 /* Add RELOCATION to the right bits of X. */
1519 x = ((x & ~howto->dst_mask)
1520 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1522 /* Put the relocated value back in the object file. */
1528 bfd_put_8 (input_bfd, x, location);
1531 bfd_put_16 (input_bfd, x, location);
1534 bfd_put_32 (input_bfd, x, location);
1538 bfd_put_64 (input_bfd, x, location);
1548 /* Clear a given location using a given howto, by applying a fixed relocation
1549 value and discarding any in-place addend. This is used for fixed-up
1550 relocations against discarded symbols, to make ignorable debug or unwind
1551 information more obvious. */
1554 _bfd_clear_contents (reloc_howto_type *howto,
1556 asection *input_section,
1562 /* Get the value we are going to relocate. */
1563 size = bfd_get_reloc_size (howto);
1570 x = bfd_get_8 (input_bfd, location);
1573 x = bfd_get_16 (input_bfd, location);
1576 x = bfd_get_32 (input_bfd, location);
1580 x = bfd_get_64 (input_bfd, location);
1587 /* Zero out the unwanted bits of X. */
1588 x &= ~howto->dst_mask;
1590 /* For a range list, use 1 instead of 0 as placeholder. 0
1591 would terminate the list, hiding any later entries. */
1592 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1593 ".debug_ranges") == 0
1594 && (howto->dst_mask & 1) != 0)
1597 /* Put the relocated value back in the object file. */
1604 bfd_put_8 (input_bfd, x, location);
1607 bfd_put_16 (input_bfd, x, location);
1610 bfd_put_32 (input_bfd, x, location);
1614 bfd_put_64 (input_bfd, x, location);
1625 howto manager, , typedef arelent, Relocations
1630 When an application wants to create a relocation, but doesn't
1631 know what the target machine might call it, it can find out by
1632 using this bit of code.
1641 The insides of a reloc code. The idea is that, eventually, there
1642 will be one enumerator for every type of relocation we ever do.
1643 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1644 return a howto pointer.
1646 This does mean that the application must determine the correct
1647 enumerator value; you can't get a howto pointer from a random set
1668 Basic absolute relocations of N bits.
1683 PC-relative relocations. Sometimes these are relative to the address
1684 of the relocation itself; sometimes they are relative to the start of
1685 the section containing the relocation. It depends on the specific target.
1687 The 24-bit relocation is used in some Intel 960 configurations.
1692 Section relative relocations. Some targets need this for DWARF2.
1695 BFD_RELOC_32_GOT_PCREL
1697 BFD_RELOC_16_GOT_PCREL
1699 BFD_RELOC_8_GOT_PCREL
1705 BFD_RELOC_LO16_GOTOFF
1707 BFD_RELOC_HI16_GOTOFF
1709 BFD_RELOC_HI16_S_GOTOFF
1713 BFD_RELOC_64_PLT_PCREL
1715 BFD_RELOC_32_PLT_PCREL
1717 BFD_RELOC_24_PLT_PCREL
1719 BFD_RELOC_16_PLT_PCREL
1721 BFD_RELOC_8_PLT_PCREL
1729 BFD_RELOC_LO16_PLTOFF
1731 BFD_RELOC_HI16_PLTOFF
1733 BFD_RELOC_HI16_S_PLTOFF
1740 BFD_RELOC_68K_GLOB_DAT
1742 BFD_RELOC_68K_JMP_SLOT
1744 BFD_RELOC_68K_RELATIVE
1746 BFD_RELOC_68K_TLS_GD32
1748 BFD_RELOC_68K_TLS_GD16
1750 BFD_RELOC_68K_TLS_GD8
1752 BFD_RELOC_68K_TLS_LDM32
1754 BFD_RELOC_68K_TLS_LDM16
1756 BFD_RELOC_68K_TLS_LDM8
1758 BFD_RELOC_68K_TLS_LDO32
1760 BFD_RELOC_68K_TLS_LDO16
1762 BFD_RELOC_68K_TLS_LDO8
1764 BFD_RELOC_68K_TLS_IE32
1766 BFD_RELOC_68K_TLS_IE16
1768 BFD_RELOC_68K_TLS_IE8
1770 BFD_RELOC_68K_TLS_LE32
1772 BFD_RELOC_68K_TLS_LE16
1774 BFD_RELOC_68K_TLS_LE8
1776 Relocations used by 68K ELF.
1779 BFD_RELOC_32_BASEREL
1781 BFD_RELOC_16_BASEREL
1783 BFD_RELOC_LO16_BASEREL
1785 BFD_RELOC_HI16_BASEREL
1787 BFD_RELOC_HI16_S_BASEREL
1793 Linkage-table relative.
1798 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1801 BFD_RELOC_32_PCREL_S2
1803 BFD_RELOC_16_PCREL_S2
1805 BFD_RELOC_23_PCREL_S2
1807 These PC-relative relocations are stored as word displacements --
1808 i.e., byte displacements shifted right two bits. The 30-bit word
1809 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1810 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1811 signed 16-bit displacement is used on the MIPS, and the 23-bit
1812 displacement is used on the Alpha.
1819 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1820 the target word. These are used on the SPARC.
1827 For systems that allocate a Global Pointer register, these are
1828 displacements off that register. These relocation types are
1829 handled specially, because the value the register will have is
1830 decided relatively late.
1833 BFD_RELOC_I960_CALLJ
1835 Reloc types used for i960/b.out.
1840 BFD_RELOC_SPARC_WDISP22
1846 BFD_RELOC_SPARC_GOT10
1848 BFD_RELOC_SPARC_GOT13
1850 BFD_RELOC_SPARC_GOT22
1852 BFD_RELOC_SPARC_PC10
1854 BFD_RELOC_SPARC_PC22
1856 BFD_RELOC_SPARC_WPLT30
1858 BFD_RELOC_SPARC_COPY
1860 BFD_RELOC_SPARC_GLOB_DAT
1862 BFD_RELOC_SPARC_JMP_SLOT
1864 BFD_RELOC_SPARC_RELATIVE
1866 BFD_RELOC_SPARC_UA16
1868 BFD_RELOC_SPARC_UA32
1870 BFD_RELOC_SPARC_UA64
1872 BFD_RELOC_SPARC_GOTDATA_HIX22
1874 BFD_RELOC_SPARC_GOTDATA_LOX10
1876 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1878 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1880 BFD_RELOC_SPARC_GOTDATA_OP
1882 BFD_RELOC_SPARC_JMP_IREL
1884 BFD_RELOC_SPARC_IRELATIVE
1886 SPARC ELF relocations. There is probably some overlap with other
1887 relocation types already defined.
1890 BFD_RELOC_SPARC_BASE13
1892 BFD_RELOC_SPARC_BASE22
1894 I think these are specific to SPARC a.out (e.g., Sun 4).
1904 BFD_RELOC_SPARC_OLO10
1906 BFD_RELOC_SPARC_HH22
1908 BFD_RELOC_SPARC_HM10
1910 BFD_RELOC_SPARC_LM22
1912 BFD_RELOC_SPARC_PC_HH22
1914 BFD_RELOC_SPARC_PC_HM10
1916 BFD_RELOC_SPARC_PC_LM22
1918 BFD_RELOC_SPARC_WDISP16
1920 BFD_RELOC_SPARC_WDISP19
1928 BFD_RELOC_SPARC_DISP64
1931 BFD_RELOC_SPARC_PLT32
1933 BFD_RELOC_SPARC_PLT64
1935 BFD_RELOC_SPARC_HIX22
1937 BFD_RELOC_SPARC_LOX10
1945 BFD_RELOC_SPARC_REGISTER
1949 BFD_RELOC_SPARC_SIZE32
1951 BFD_RELOC_SPARC_SIZE64
1953 BFD_RELOC_SPARC_WDISP10
1958 BFD_RELOC_SPARC_REV32
1960 SPARC little endian relocation
1962 BFD_RELOC_SPARC_TLS_GD_HI22
1964 BFD_RELOC_SPARC_TLS_GD_LO10
1966 BFD_RELOC_SPARC_TLS_GD_ADD
1968 BFD_RELOC_SPARC_TLS_GD_CALL
1970 BFD_RELOC_SPARC_TLS_LDM_HI22
1972 BFD_RELOC_SPARC_TLS_LDM_LO10
1974 BFD_RELOC_SPARC_TLS_LDM_ADD
1976 BFD_RELOC_SPARC_TLS_LDM_CALL
1978 BFD_RELOC_SPARC_TLS_LDO_HIX22
1980 BFD_RELOC_SPARC_TLS_LDO_LOX10
1982 BFD_RELOC_SPARC_TLS_LDO_ADD
1984 BFD_RELOC_SPARC_TLS_IE_HI22
1986 BFD_RELOC_SPARC_TLS_IE_LO10
1988 BFD_RELOC_SPARC_TLS_IE_LD
1990 BFD_RELOC_SPARC_TLS_IE_LDX
1992 BFD_RELOC_SPARC_TLS_IE_ADD
1994 BFD_RELOC_SPARC_TLS_LE_HIX22
1996 BFD_RELOC_SPARC_TLS_LE_LOX10
1998 BFD_RELOC_SPARC_TLS_DTPMOD32
2000 BFD_RELOC_SPARC_TLS_DTPMOD64
2002 BFD_RELOC_SPARC_TLS_DTPOFF32
2004 BFD_RELOC_SPARC_TLS_DTPOFF64
2006 BFD_RELOC_SPARC_TLS_TPOFF32
2008 BFD_RELOC_SPARC_TLS_TPOFF64
2010 SPARC TLS relocations
2019 BFD_RELOC_SPU_IMM10W
2023 BFD_RELOC_SPU_IMM16W
2027 BFD_RELOC_SPU_PCREL9a
2029 BFD_RELOC_SPU_PCREL9b
2031 BFD_RELOC_SPU_PCREL16
2041 BFD_RELOC_SPU_ADD_PIC
2046 BFD_RELOC_ALPHA_GPDISP_HI16
2048 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2049 "addend" in some special way.
2050 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2051 writing; when reading, it will be the absolute section symbol. The
2052 addend is the displacement in bytes of the "lda" instruction from
2053 the "ldah" instruction (which is at the address of this reloc).
2055 BFD_RELOC_ALPHA_GPDISP_LO16
2057 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2058 with GPDISP_HI16 relocs. The addend is ignored when writing the
2059 relocations out, and is filled in with the file's GP value on
2060 reading, for convenience.
2063 BFD_RELOC_ALPHA_GPDISP
2065 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2066 relocation except that there is no accompanying GPDISP_LO16
2070 BFD_RELOC_ALPHA_LITERAL
2072 BFD_RELOC_ALPHA_ELF_LITERAL
2074 BFD_RELOC_ALPHA_LITUSE
2076 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2077 the assembler turns it into a LDQ instruction to load the address of
2078 the symbol, and then fills in a register in the real instruction.
2080 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2081 section symbol. The addend is ignored when writing, but is filled
2082 in with the file's GP value on reading, for convenience, as with the
2085 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2086 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2087 but it generates output not based on the position within the .got
2088 section, but relative to the GP value chosen for the file during the
2091 The LITUSE reloc, on the instruction using the loaded address, gives
2092 information to the linker that it might be able to use to optimize
2093 away some literal section references. The symbol is ignored (read
2094 as the absolute section symbol), and the "addend" indicates the type
2095 of instruction using the register:
2096 1 - "memory" fmt insn
2097 2 - byte-manipulation (byte offset reg)
2098 3 - jsr (target of branch)
2101 BFD_RELOC_ALPHA_HINT
2103 The HINT relocation indicates a value that should be filled into the
2104 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2105 prediction logic which may be provided on some processors.
2108 BFD_RELOC_ALPHA_LINKAGE
2110 The LINKAGE relocation outputs a linkage pair in the object file,
2111 which is filled by the linker.
2114 BFD_RELOC_ALPHA_CODEADDR
2116 The CODEADDR relocation outputs a STO_CA in the object file,
2117 which is filled by the linker.
2120 BFD_RELOC_ALPHA_GPREL_HI16
2122 BFD_RELOC_ALPHA_GPREL_LO16
2124 The GPREL_HI/LO relocations together form a 32-bit offset from the
2128 BFD_RELOC_ALPHA_BRSGP
2130 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2131 share a common GP, and the target address is adjusted for
2132 STO_ALPHA_STD_GPLOAD.
2137 The NOP relocation outputs a NOP if the longword displacement
2138 between two procedure entry points is < 2^21.
2143 The BSR relocation outputs a BSR if the longword displacement
2144 between two procedure entry points is < 2^21.
2149 The LDA relocation outputs a LDA if the longword displacement
2150 between two procedure entry points is < 2^16.
2155 The BOH relocation outputs a BSR if the longword displacement
2156 between two procedure entry points is < 2^21, or else a hint.
2159 BFD_RELOC_ALPHA_TLSGD
2161 BFD_RELOC_ALPHA_TLSLDM
2163 BFD_RELOC_ALPHA_DTPMOD64
2165 BFD_RELOC_ALPHA_GOTDTPREL16
2167 BFD_RELOC_ALPHA_DTPREL64
2169 BFD_RELOC_ALPHA_DTPREL_HI16
2171 BFD_RELOC_ALPHA_DTPREL_LO16
2173 BFD_RELOC_ALPHA_DTPREL16
2175 BFD_RELOC_ALPHA_GOTTPREL16
2177 BFD_RELOC_ALPHA_TPREL64
2179 BFD_RELOC_ALPHA_TPREL_HI16
2181 BFD_RELOC_ALPHA_TPREL_LO16
2183 BFD_RELOC_ALPHA_TPREL16
2185 Alpha thread-local storage relocations.
2190 BFD_RELOC_MICROMIPS_JMP
2192 The MIPS jump instruction.
2195 BFD_RELOC_MIPS16_JMP
2197 The MIPS16 jump instruction.
2200 BFD_RELOC_MIPS16_GPREL
2202 MIPS16 GP relative reloc.
2207 High 16 bits of 32-bit value; simple reloc.
2212 High 16 bits of 32-bit value but the low 16 bits will be sign
2213 extended and added to form the final result. If the low 16
2214 bits form a negative number, we need to add one to the high value
2215 to compensate for the borrow when the low bits are added.
2223 BFD_RELOC_HI16_PCREL
2225 High 16 bits of 32-bit pc-relative value
2227 BFD_RELOC_HI16_S_PCREL
2229 High 16 bits of 32-bit pc-relative value, adjusted
2231 BFD_RELOC_LO16_PCREL
2233 Low 16 bits of pc-relative value
2236 BFD_RELOC_MIPS16_GOT16
2238 BFD_RELOC_MIPS16_CALL16
2240 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2241 16-bit immediate fields
2243 BFD_RELOC_MIPS16_HI16
2245 MIPS16 high 16 bits of 32-bit value.
2247 BFD_RELOC_MIPS16_HI16_S
2249 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2250 extended and added to form the final result. If the low 16
2251 bits form a negative number, we need to add one to the high value
2252 to compensate for the borrow when the low bits are added.
2254 BFD_RELOC_MIPS16_LO16
2259 BFD_RELOC_MIPS16_TLS_GD
2261 BFD_RELOC_MIPS16_TLS_LDM
2263 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2265 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2267 BFD_RELOC_MIPS16_TLS_GOTTPREL
2269 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2271 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2273 MIPS16 TLS relocations
2276 BFD_RELOC_MIPS_LITERAL
2278 BFD_RELOC_MICROMIPS_LITERAL
2280 Relocation against a MIPS literal section.
2283 BFD_RELOC_MICROMIPS_7_PCREL_S1
2285 BFD_RELOC_MICROMIPS_10_PCREL_S1
2287 BFD_RELOC_MICROMIPS_16_PCREL_S1
2289 microMIPS PC-relative relocations.
2292 BFD_RELOC_MICROMIPS_GPREL16
2294 BFD_RELOC_MICROMIPS_HI16
2296 BFD_RELOC_MICROMIPS_HI16_S
2298 BFD_RELOC_MICROMIPS_LO16
2300 microMIPS versions of generic BFD relocs.
2303 BFD_RELOC_MIPS_GOT16
2305 BFD_RELOC_MICROMIPS_GOT16
2307 BFD_RELOC_MIPS_CALL16
2309 BFD_RELOC_MICROMIPS_CALL16
2311 BFD_RELOC_MIPS_GOT_HI16
2313 BFD_RELOC_MICROMIPS_GOT_HI16
2315 BFD_RELOC_MIPS_GOT_LO16
2317 BFD_RELOC_MICROMIPS_GOT_LO16
2319 BFD_RELOC_MIPS_CALL_HI16
2321 BFD_RELOC_MICROMIPS_CALL_HI16
2323 BFD_RELOC_MIPS_CALL_LO16
2325 BFD_RELOC_MICROMIPS_CALL_LO16
2329 BFD_RELOC_MICROMIPS_SUB
2331 BFD_RELOC_MIPS_GOT_PAGE
2333 BFD_RELOC_MICROMIPS_GOT_PAGE
2335 BFD_RELOC_MIPS_GOT_OFST
2337 BFD_RELOC_MICROMIPS_GOT_OFST
2339 BFD_RELOC_MIPS_GOT_DISP
2341 BFD_RELOC_MICROMIPS_GOT_DISP
2343 BFD_RELOC_MIPS_SHIFT5
2345 BFD_RELOC_MIPS_SHIFT6
2347 BFD_RELOC_MIPS_INSERT_A
2349 BFD_RELOC_MIPS_INSERT_B
2351 BFD_RELOC_MIPS_DELETE
2353 BFD_RELOC_MIPS_HIGHEST
2355 BFD_RELOC_MICROMIPS_HIGHEST
2357 BFD_RELOC_MIPS_HIGHER
2359 BFD_RELOC_MICROMIPS_HIGHER
2361 BFD_RELOC_MIPS_SCN_DISP
2363 BFD_RELOC_MICROMIPS_SCN_DISP
2365 BFD_RELOC_MIPS_REL16
2367 BFD_RELOC_MIPS_RELGOT
2371 BFD_RELOC_MICROMIPS_JALR
2373 BFD_RELOC_MIPS_TLS_DTPMOD32
2375 BFD_RELOC_MIPS_TLS_DTPREL32
2377 BFD_RELOC_MIPS_TLS_DTPMOD64
2379 BFD_RELOC_MIPS_TLS_DTPREL64
2381 BFD_RELOC_MIPS_TLS_GD
2383 BFD_RELOC_MICROMIPS_TLS_GD
2385 BFD_RELOC_MIPS_TLS_LDM
2387 BFD_RELOC_MICROMIPS_TLS_LDM
2389 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2391 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2393 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2395 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2397 BFD_RELOC_MIPS_TLS_GOTTPREL
2399 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2401 BFD_RELOC_MIPS_TLS_TPREL32
2403 BFD_RELOC_MIPS_TLS_TPREL64
2405 BFD_RELOC_MIPS_TLS_TPREL_HI16
2407 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2409 BFD_RELOC_MIPS_TLS_TPREL_LO16
2411 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2413 MIPS ELF relocations.
2419 BFD_RELOC_MIPS_JUMP_SLOT
2421 MIPS ELF relocations (VxWorks and PLT extensions).
2425 BFD_RELOC_MOXIE_10_PCREL
2427 Moxie ELF relocations.
2431 BFD_RELOC_FRV_LABEL16
2433 BFD_RELOC_FRV_LABEL24
2439 BFD_RELOC_FRV_GPREL12
2441 BFD_RELOC_FRV_GPRELU12
2443 BFD_RELOC_FRV_GPREL32
2445 BFD_RELOC_FRV_GPRELHI
2447 BFD_RELOC_FRV_GPRELLO
2455 BFD_RELOC_FRV_FUNCDESC
2457 BFD_RELOC_FRV_FUNCDESC_GOT12
2459 BFD_RELOC_FRV_FUNCDESC_GOTHI
2461 BFD_RELOC_FRV_FUNCDESC_GOTLO
2463 BFD_RELOC_FRV_FUNCDESC_VALUE
2465 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2467 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2469 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2471 BFD_RELOC_FRV_GOTOFF12
2473 BFD_RELOC_FRV_GOTOFFHI
2475 BFD_RELOC_FRV_GOTOFFLO
2477 BFD_RELOC_FRV_GETTLSOFF
2479 BFD_RELOC_FRV_TLSDESC_VALUE
2481 BFD_RELOC_FRV_GOTTLSDESC12
2483 BFD_RELOC_FRV_GOTTLSDESCHI
2485 BFD_RELOC_FRV_GOTTLSDESCLO
2487 BFD_RELOC_FRV_TLSMOFF12
2489 BFD_RELOC_FRV_TLSMOFFHI
2491 BFD_RELOC_FRV_TLSMOFFLO
2493 BFD_RELOC_FRV_GOTTLSOFF12
2495 BFD_RELOC_FRV_GOTTLSOFFHI
2497 BFD_RELOC_FRV_GOTTLSOFFLO
2499 BFD_RELOC_FRV_TLSOFF
2501 BFD_RELOC_FRV_TLSDESC_RELAX
2503 BFD_RELOC_FRV_GETTLSOFF_RELAX
2505 BFD_RELOC_FRV_TLSOFF_RELAX
2507 BFD_RELOC_FRV_TLSMOFF
2509 Fujitsu Frv Relocations.
2513 BFD_RELOC_MN10300_GOTOFF24
2515 This is a 24bit GOT-relative reloc for the mn10300.
2517 BFD_RELOC_MN10300_GOT32
2519 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2522 BFD_RELOC_MN10300_GOT24
2524 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2527 BFD_RELOC_MN10300_GOT16
2529 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2532 BFD_RELOC_MN10300_COPY
2534 Copy symbol at runtime.
2536 BFD_RELOC_MN10300_GLOB_DAT
2540 BFD_RELOC_MN10300_JMP_SLOT
2544 BFD_RELOC_MN10300_RELATIVE
2546 Adjust by program base.
2548 BFD_RELOC_MN10300_SYM_DIFF
2550 Together with another reloc targeted at the same location,
2551 allows for a value that is the difference of two symbols
2552 in the same section.
2554 BFD_RELOC_MN10300_ALIGN
2556 The addend of this reloc is an alignment power that must
2557 be honoured at the offset's location, regardless of linker
2560 BFD_RELOC_MN10300_TLS_GD
2562 BFD_RELOC_MN10300_TLS_LD
2564 BFD_RELOC_MN10300_TLS_LDO
2566 BFD_RELOC_MN10300_TLS_GOTIE
2568 BFD_RELOC_MN10300_TLS_IE
2570 BFD_RELOC_MN10300_TLS_LE
2572 BFD_RELOC_MN10300_TLS_DTPMOD
2574 BFD_RELOC_MN10300_TLS_DTPOFF
2576 BFD_RELOC_MN10300_TLS_TPOFF
2578 Various TLS-related relocations.
2580 BFD_RELOC_MN10300_32_PCREL
2582 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2585 BFD_RELOC_MN10300_16_PCREL
2587 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2598 BFD_RELOC_386_GLOB_DAT
2600 BFD_RELOC_386_JUMP_SLOT
2602 BFD_RELOC_386_RELATIVE
2604 BFD_RELOC_386_GOTOFF
2608 BFD_RELOC_386_TLS_TPOFF
2610 BFD_RELOC_386_TLS_IE
2612 BFD_RELOC_386_TLS_GOTIE
2614 BFD_RELOC_386_TLS_LE
2616 BFD_RELOC_386_TLS_GD
2618 BFD_RELOC_386_TLS_LDM
2620 BFD_RELOC_386_TLS_LDO_32
2622 BFD_RELOC_386_TLS_IE_32
2624 BFD_RELOC_386_TLS_LE_32
2626 BFD_RELOC_386_TLS_DTPMOD32
2628 BFD_RELOC_386_TLS_DTPOFF32
2630 BFD_RELOC_386_TLS_TPOFF32
2632 BFD_RELOC_386_TLS_GOTDESC
2634 BFD_RELOC_386_TLS_DESC_CALL
2636 BFD_RELOC_386_TLS_DESC
2638 BFD_RELOC_386_IRELATIVE
2640 i386/elf relocations
2643 BFD_RELOC_X86_64_GOT32
2645 BFD_RELOC_X86_64_PLT32
2647 BFD_RELOC_X86_64_COPY
2649 BFD_RELOC_X86_64_GLOB_DAT
2651 BFD_RELOC_X86_64_JUMP_SLOT
2653 BFD_RELOC_X86_64_RELATIVE
2655 BFD_RELOC_X86_64_GOTPCREL
2657 BFD_RELOC_X86_64_32S
2659 BFD_RELOC_X86_64_DTPMOD64
2661 BFD_RELOC_X86_64_DTPOFF64
2663 BFD_RELOC_X86_64_TPOFF64
2665 BFD_RELOC_X86_64_TLSGD
2667 BFD_RELOC_X86_64_TLSLD
2669 BFD_RELOC_X86_64_DTPOFF32
2671 BFD_RELOC_X86_64_GOTTPOFF
2673 BFD_RELOC_X86_64_TPOFF32
2675 BFD_RELOC_X86_64_GOTOFF64
2677 BFD_RELOC_X86_64_GOTPC32
2679 BFD_RELOC_X86_64_GOT64
2681 BFD_RELOC_X86_64_GOTPCREL64
2683 BFD_RELOC_X86_64_GOTPC64
2685 BFD_RELOC_X86_64_GOTPLT64
2687 BFD_RELOC_X86_64_PLTOFF64
2689 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2691 BFD_RELOC_X86_64_TLSDESC_CALL
2693 BFD_RELOC_X86_64_TLSDESC
2695 BFD_RELOC_X86_64_IRELATIVE
2697 x86-64/elf relocations
2700 BFD_RELOC_NS32K_IMM_8
2702 BFD_RELOC_NS32K_IMM_16
2704 BFD_RELOC_NS32K_IMM_32
2706 BFD_RELOC_NS32K_IMM_8_PCREL
2708 BFD_RELOC_NS32K_IMM_16_PCREL
2710 BFD_RELOC_NS32K_IMM_32_PCREL
2712 BFD_RELOC_NS32K_DISP_8
2714 BFD_RELOC_NS32K_DISP_16
2716 BFD_RELOC_NS32K_DISP_32
2718 BFD_RELOC_NS32K_DISP_8_PCREL
2720 BFD_RELOC_NS32K_DISP_16_PCREL
2722 BFD_RELOC_NS32K_DISP_32_PCREL
2727 BFD_RELOC_PDP11_DISP_8_PCREL
2729 BFD_RELOC_PDP11_DISP_6_PCREL
2734 BFD_RELOC_PJ_CODE_HI16
2736 BFD_RELOC_PJ_CODE_LO16
2738 BFD_RELOC_PJ_CODE_DIR16
2740 BFD_RELOC_PJ_CODE_DIR32
2742 BFD_RELOC_PJ_CODE_REL16
2744 BFD_RELOC_PJ_CODE_REL32
2746 Picojava relocs. Not all of these appear in object files.
2757 BFD_RELOC_PPC_B16_BRTAKEN
2759 BFD_RELOC_PPC_B16_BRNTAKEN
2763 BFD_RELOC_PPC_BA16_BRTAKEN
2765 BFD_RELOC_PPC_BA16_BRNTAKEN
2769 BFD_RELOC_PPC_GLOB_DAT
2771 BFD_RELOC_PPC_JMP_SLOT
2773 BFD_RELOC_PPC_RELATIVE
2775 BFD_RELOC_PPC_LOCAL24PC
2777 BFD_RELOC_PPC_EMB_NADDR32
2779 BFD_RELOC_PPC_EMB_NADDR16
2781 BFD_RELOC_PPC_EMB_NADDR16_LO
2783 BFD_RELOC_PPC_EMB_NADDR16_HI
2785 BFD_RELOC_PPC_EMB_NADDR16_HA
2787 BFD_RELOC_PPC_EMB_SDAI16
2789 BFD_RELOC_PPC_EMB_SDA2I16
2791 BFD_RELOC_PPC_EMB_SDA2REL
2793 BFD_RELOC_PPC_EMB_SDA21
2795 BFD_RELOC_PPC_EMB_MRKREF
2797 BFD_RELOC_PPC_EMB_RELSEC16
2799 BFD_RELOC_PPC_EMB_RELST_LO
2801 BFD_RELOC_PPC_EMB_RELST_HI
2803 BFD_RELOC_PPC_EMB_RELST_HA
2805 BFD_RELOC_PPC_EMB_BIT_FLD
2807 BFD_RELOC_PPC_EMB_RELSDA
2809 BFD_RELOC_PPC_VLE_REL8
2811 BFD_RELOC_PPC_VLE_REL15
2813 BFD_RELOC_PPC_VLE_REL24
2815 BFD_RELOC_PPC_VLE_LO16A
2817 BFD_RELOC_PPC_VLE_LO16D
2819 BFD_RELOC_PPC_VLE_HI16A
2821 BFD_RELOC_PPC_VLE_HI16D
2823 BFD_RELOC_PPC_VLE_HA16A
2825 BFD_RELOC_PPC_VLE_HA16D
2827 BFD_RELOC_PPC_VLE_SDA21
2829 BFD_RELOC_PPC_VLE_SDA21_LO
2831 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2833 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2835 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2837 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2839 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2841 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2843 BFD_RELOC_PPC64_HIGHER
2845 BFD_RELOC_PPC64_HIGHER_S
2847 BFD_RELOC_PPC64_HIGHEST
2849 BFD_RELOC_PPC64_HIGHEST_S
2851 BFD_RELOC_PPC64_TOC16_LO
2853 BFD_RELOC_PPC64_TOC16_HI
2855 BFD_RELOC_PPC64_TOC16_HA
2859 BFD_RELOC_PPC64_PLTGOT16
2861 BFD_RELOC_PPC64_PLTGOT16_LO
2863 BFD_RELOC_PPC64_PLTGOT16_HI
2865 BFD_RELOC_PPC64_PLTGOT16_HA
2867 BFD_RELOC_PPC64_ADDR16_DS
2869 BFD_RELOC_PPC64_ADDR16_LO_DS
2871 BFD_RELOC_PPC64_GOT16_DS
2873 BFD_RELOC_PPC64_GOT16_LO_DS
2875 BFD_RELOC_PPC64_PLT16_LO_DS
2877 BFD_RELOC_PPC64_SECTOFF_DS
2879 BFD_RELOC_PPC64_SECTOFF_LO_DS
2881 BFD_RELOC_PPC64_TOC16_DS
2883 BFD_RELOC_PPC64_TOC16_LO_DS
2885 BFD_RELOC_PPC64_PLTGOT16_DS
2887 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2889 Power(rs6000) and PowerPC relocations.
2898 BFD_RELOC_PPC_DTPMOD
2900 BFD_RELOC_PPC_TPREL16
2902 BFD_RELOC_PPC_TPREL16_LO
2904 BFD_RELOC_PPC_TPREL16_HI
2906 BFD_RELOC_PPC_TPREL16_HA
2910 BFD_RELOC_PPC_DTPREL16
2912 BFD_RELOC_PPC_DTPREL16_LO
2914 BFD_RELOC_PPC_DTPREL16_HI
2916 BFD_RELOC_PPC_DTPREL16_HA
2918 BFD_RELOC_PPC_DTPREL
2920 BFD_RELOC_PPC_GOT_TLSGD16
2922 BFD_RELOC_PPC_GOT_TLSGD16_LO
2924 BFD_RELOC_PPC_GOT_TLSGD16_HI
2926 BFD_RELOC_PPC_GOT_TLSGD16_HA
2928 BFD_RELOC_PPC_GOT_TLSLD16
2930 BFD_RELOC_PPC_GOT_TLSLD16_LO
2932 BFD_RELOC_PPC_GOT_TLSLD16_HI
2934 BFD_RELOC_PPC_GOT_TLSLD16_HA
2936 BFD_RELOC_PPC_GOT_TPREL16
2938 BFD_RELOC_PPC_GOT_TPREL16_LO
2940 BFD_RELOC_PPC_GOT_TPREL16_HI
2942 BFD_RELOC_PPC_GOT_TPREL16_HA
2944 BFD_RELOC_PPC_GOT_DTPREL16
2946 BFD_RELOC_PPC_GOT_DTPREL16_LO
2948 BFD_RELOC_PPC_GOT_DTPREL16_HI
2950 BFD_RELOC_PPC_GOT_DTPREL16_HA
2952 BFD_RELOC_PPC64_TPREL16_DS
2954 BFD_RELOC_PPC64_TPREL16_LO_DS
2956 BFD_RELOC_PPC64_TPREL16_HIGHER
2958 BFD_RELOC_PPC64_TPREL16_HIGHERA
2960 BFD_RELOC_PPC64_TPREL16_HIGHEST
2962 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2964 BFD_RELOC_PPC64_DTPREL16_DS
2966 BFD_RELOC_PPC64_DTPREL16_LO_DS
2968 BFD_RELOC_PPC64_DTPREL16_HIGHER
2970 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2972 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2974 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2976 PowerPC and PowerPC64 thread-local storage relocations.
2981 IBM 370/390 relocations
2986 The type of reloc used to build a constructor table - at the moment
2987 probably a 32 bit wide absolute relocation, but the target can choose.
2988 It generally does map to one of the other relocation types.
2991 BFD_RELOC_ARM_PCREL_BRANCH
2993 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
2994 not stored in the instruction.
2996 BFD_RELOC_ARM_PCREL_BLX
2998 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
2999 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3000 field in the instruction.
3002 BFD_RELOC_THUMB_PCREL_BLX
3004 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3005 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3006 field in the instruction.
3008 BFD_RELOC_ARM_PCREL_CALL
3010 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3012 BFD_RELOC_ARM_PCREL_JUMP
3014 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3017 BFD_RELOC_THUMB_PCREL_BRANCH7
3019 BFD_RELOC_THUMB_PCREL_BRANCH9
3021 BFD_RELOC_THUMB_PCREL_BRANCH12
3023 BFD_RELOC_THUMB_PCREL_BRANCH20
3025 BFD_RELOC_THUMB_PCREL_BRANCH23
3027 BFD_RELOC_THUMB_PCREL_BRANCH25
3029 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3030 The lowest bit must be zero and is not stored in the instruction.
3031 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3032 "nn" one smaller in all cases. Note further that BRANCH23
3033 corresponds to R_ARM_THM_CALL.
3036 BFD_RELOC_ARM_OFFSET_IMM
3038 12-bit immediate offset, used in ARM-format ldr and str instructions.
3041 BFD_RELOC_ARM_THUMB_OFFSET
3043 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3046 BFD_RELOC_ARM_TARGET1
3048 Pc-relative or absolute relocation depending on target. Used for
3049 entries in .init_array sections.
3051 BFD_RELOC_ARM_ROSEGREL32
3053 Read-only segment base relative address.
3055 BFD_RELOC_ARM_SBREL32
3057 Data segment base relative address.
3059 BFD_RELOC_ARM_TARGET2
3061 This reloc is used for references to RTTI data from exception handling
3062 tables. The actual definition depends on the target. It may be a
3063 pc-relative or some form of GOT-indirect relocation.
3065 BFD_RELOC_ARM_PREL31
3067 31-bit PC relative address.
3073 BFD_RELOC_ARM_MOVW_PCREL
3075 BFD_RELOC_ARM_MOVT_PCREL
3077 BFD_RELOC_ARM_THUMB_MOVW
3079 BFD_RELOC_ARM_THUMB_MOVT
3081 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3083 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3085 Low and High halfword relocations for MOVW and MOVT instructions.
3088 BFD_RELOC_ARM_JUMP_SLOT
3090 BFD_RELOC_ARM_GLOB_DAT
3096 BFD_RELOC_ARM_RELATIVE
3098 BFD_RELOC_ARM_GOTOFF
3102 BFD_RELOC_ARM_GOT_PREL
3104 Relocations for setting up GOTs and PLTs for shared libraries.
3107 BFD_RELOC_ARM_TLS_GD32
3109 BFD_RELOC_ARM_TLS_LDO32
3111 BFD_RELOC_ARM_TLS_LDM32
3113 BFD_RELOC_ARM_TLS_DTPOFF32
3115 BFD_RELOC_ARM_TLS_DTPMOD32
3117 BFD_RELOC_ARM_TLS_TPOFF32
3119 BFD_RELOC_ARM_TLS_IE32
3121 BFD_RELOC_ARM_TLS_LE32
3123 BFD_RELOC_ARM_TLS_GOTDESC
3125 BFD_RELOC_ARM_TLS_CALL
3127 BFD_RELOC_ARM_THM_TLS_CALL
3129 BFD_RELOC_ARM_TLS_DESCSEQ
3131 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3133 BFD_RELOC_ARM_TLS_DESC
3135 ARM thread-local storage relocations.
3138 BFD_RELOC_ARM_ALU_PC_G0_NC
3140 BFD_RELOC_ARM_ALU_PC_G0
3142 BFD_RELOC_ARM_ALU_PC_G1_NC
3144 BFD_RELOC_ARM_ALU_PC_G1
3146 BFD_RELOC_ARM_ALU_PC_G2
3148 BFD_RELOC_ARM_LDR_PC_G0
3150 BFD_RELOC_ARM_LDR_PC_G1
3152 BFD_RELOC_ARM_LDR_PC_G2
3154 BFD_RELOC_ARM_LDRS_PC_G0
3156 BFD_RELOC_ARM_LDRS_PC_G1
3158 BFD_RELOC_ARM_LDRS_PC_G2
3160 BFD_RELOC_ARM_LDC_PC_G0
3162 BFD_RELOC_ARM_LDC_PC_G1
3164 BFD_RELOC_ARM_LDC_PC_G2
3166 BFD_RELOC_ARM_ALU_SB_G0_NC
3168 BFD_RELOC_ARM_ALU_SB_G0
3170 BFD_RELOC_ARM_ALU_SB_G1_NC
3172 BFD_RELOC_ARM_ALU_SB_G1
3174 BFD_RELOC_ARM_ALU_SB_G2
3176 BFD_RELOC_ARM_LDR_SB_G0
3178 BFD_RELOC_ARM_LDR_SB_G1
3180 BFD_RELOC_ARM_LDR_SB_G2
3182 BFD_RELOC_ARM_LDRS_SB_G0
3184 BFD_RELOC_ARM_LDRS_SB_G1
3186 BFD_RELOC_ARM_LDRS_SB_G2
3188 BFD_RELOC_ARM_LDC_SB_G0
3190 BFD_RELOC_ARM_LDC_SB_G1
3192 BFD_RELOC_ARM_LDC_SB_G2
3194 ARM group relocations.
3199 Annotation of BX instructions.
3202 BFD_RELOC_ARM_IRELATIVE
3204 ARM support for STT_GNU_IFUNC.
3207 BFD_RELOC_ARM_IMMEDIATE
3209 BFD_RELOC_ARM_ADRL_IMMEDIATE
3211 BFD_RELOC_ARM_T32_IMMEDIATE
3213 BFD_RELOC_ARM_T32_ADD_IMM
3215 BFD_RELOC_ARM_T32_IMM12
3217 BFD_RELOC_ARM_T32_ADD_PC12
3219 BFD_RELOC_ARM_SHIFT_IMM
3229 BFD_RELOC_ARM_CP_OFF_IMM
3231 BFD_RELOC_ARM_CP_OFF_IMM_S2
3233 BFD_RELOC_ARM_T32_CP_OFF_IMM
3235 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3237 BFD_RELOC_ARM_ADR_IMM
3239 BFD_RELOC_ARM_LDR_IMM
3241 BFD_RELOC_ARM_LITERAL
3243 BFD_RELOC_ARM_IN_POOL
3245 BFD_RELOC_ARM_OFFSET_IMM8
3247 BFD_RELOC_ARM_T32_OFFSET_U8
3249 BFD_RELOC_ARM_T32_OFFSET_IMM
3251 BFD_RELOC_ARM_HWLITERAL
3253 BFD_RELOC_ARM_THUMB_ADD
3255 BFD_RELOC_ARM_THUMB_IMM
3257 BFD_RELOC_ARM_THUMB_SHIFT
3259 These relocs are only used within the ARM assembler. They are not
3260 (at present) written to any object files.
3263 BFD_RELOC_SH_PCDISP8BY2
3265 BFD_RELOC_SH_PCDISP12BY2
3273 BFD_RELOC_SH_DISP12BY2
3275 BFD_RELOC_SH_DISP12BY4
3277 BFD_RELOC_SH_DISP12BY8
3281 BFD_RELOC_SH_DISP20BY8
3285 BFD_RELOC_SH_IMM4BY2
3287 BFD_RELOC_SH_IMM4BY4
3291 BFD_RELOC_SH_IMM8BY2
3293 BFD_RELOC_SH_IMM8BY4
3295 BFD_RELOC_SH_PCRELIMM8BY2
3297 BFD_RELOC_SH_PCRELIMM8BY4
3299 BFD_RELOC_SH_SWITCH16
3301 BFD_RELOC_SH_SWITCH32
3315 BFD_RELOC_SH_LOOP_START
3317 BFD_RELOC_SH_LOOP_END
3321 BFD_RELOC_SH_GLOB_DAT
3323 BFD_RELOC_SH_JMP_SLOT
3325 BFD_RELOC_SH_RELATIVE
3329 BFD_RELOC_SH_GOT_LOW16
3331 BFD_RELOC_SH_GOT_MEDLOW16
3333 BFD_RELOC_SH_GOT_MEDHI16
3335 BFD_RELOC_SH_GOT_HI16
3337 BFD_RELOC_SH_GOTPLT_LOW16
3339 BFD_RELOC_SH_GOTPLT_MEDLOW16
3341 BFD_RELOC_SH_GOTPLT_MEDHI16
3343 BFD_RELOC_SH_GOTPLT_HI16
3345 BFD_RELOC_SH_PLT_LOW16
3347 BFD_RELOC_SH_PLT_MEDLOW16
3349 BFD_RELOC_SH_PLT_MEDHI16
3351 BFD_RELOC_SH_PLT_HI16
3353 BFD_RELOC_SH_GOTOFF_LOW16
3355 BFD_RELOC_SH_GOTOFF_MEDLOW16
3357 BFD_RELOC_SH_GOTOFF_MEDHI16
3359 BFD_RELOC_SH_GOTOFF_HI16
3361 BFD_RELOC_SH_GOTPC_LOW16
3363 BFD_RELOC_SH_GOTPC_MEDLOW16
3365 BFD_RELOC_SH_GOTPC_MEDHI16
3367 BFD_RELOC_SH_GOTPC_HI16
3371 BFD_RELOC_SH_GLOB_DAT64
3373 BFD_RELOC_SH_JMP_SLOT64
3375 BFD_RELOC_SH_RELATIVE64
3377 BFD_RELOC_SH_GOT10BY4
3379 BFD_RELOC_SH_GOT10BY8
3381 BFD_RELOC_SH_GOTPLT10BY4
3383 BFD_RELOC_SH_GOTPLT10BY8
3385 BFD_RELOC_SH_GOTPLT32
3387 BFD_RELOC_SH_SHMEDIA_CODE
3393 BFD_RELOC_SH_IMMS6BY32
3399 BFD_RELOC_SH_IMMS10BY2
3401 BFD_RELOC_SH_IMMS10BY4
3403 BFD_RELOC_SH_IMMS10BY8
3409 BFD_RELOC_SH_IMM_LOW16
3411 BFD_RELOC_SH_IMM_LOW16_PCREL
3413 BFD_RELOC_SH_IMM_MEDLOW16
3415 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3417 BFD_RELOC_SH_IMM_MEDHI16
3419 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3421 BFD_RELOC_SH_IMM_HI16
3423 BFD_RELOC_SH_IMM_HI16_PCREL
3427 BFD_RELOC_SH_TLS_GD_32
3429 BFD_RELOC_SH_TLS_LD_32
3431 BFD_RELOC_SH_TLS_LDO_32
3433 BFD_RELOC_SH_TLS_IE_32
3435 BFD_RELOC_SH_TLS_LE_32
3437 BFD_RELOC_SH_TLS_DTPMOD32
3439 BFD_RELOC_SH_TLS_DTPOFF32
3441 BFD_RELOC_SH_TLS_TPOFF32
3445 BFD_RELOC_SH_GOTOFF20
3447 BFD_RELOC_SH_GOTFUNCDESC
3449 BFD_RELOC_SH_GOTFUNCDESC20
3451 BFD_RELOC_SH_GOTOFFFUNCDESC
3453 BFD_RELOC_SH_GOTOFFFUNCDESC20
3455 BFD_RELOC_SH_FUNCDESC
3457 Renesas / SuperH SH relocs. Not all of these appear in object files.
3460 BFD_RELOC_ARC_B22_PCREL
3463 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
3464 not stored in the instruction. The high 20 bits are installed in bits 26
3465 through 7 of the instruction.
3469 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
3470 stored in the instruction. The high 24 bits are installed in bits 23
3474 BFD_RELOC_BFIN_16_IMM
3476 ADI Blackfin 16 bit immediate absolute reloc.
3478 BFD_RELOC_BFIN_16_HIGH
3480 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3482 BFD_RELOC_BFIN_4_PCREL
3484 ADI Blackfin 'a' part of LSETUP.
3486 BFD_RELOC_BFIN_5_PCREL
3490 BFD_RELOC_BFIN_16_LOW
3492 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3494 BFD_RELOC_BFIN_10_PCREL
3498 BFD_RELOC_BFIN_11_PCREL
3500 ADI Blackfin 'b' part of LSETUP.
3502 BFD_RELOC_BFIN_12_PCREL_JUMP
3506 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3508 ADI Blackfin Short jump, pcrel.
3510 BFD_RELOC_BFIN_24_PCREL_CALL_X
3512 ADI Blackfin Call.x not implemented.
3514 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3516 ADI Blackfin Long Jump pcrel.
3518 BFD_RELOC_BFIN_GOT17M4
3520 BFD_RELOC_BFIN_GOTHI
3522 BFD_RELOC_BFIN_GOTLO
3524 BFD_RELOC_BFIN_FUNCDESC
3526 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3528 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3530 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3532 BFD_RELOC_BFIN_FUNCDESC_VALUE
3534 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3536 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3538 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3540 BFD_RELOC_BFIN_GOTOFF17M4
3542 BFD_RELOC_BFIN_GOTOFFHI
3544 BFD_RELOC_BFIN_GOTOFFLO
3546 ADI Blackfin FD-PIC relocations.
3550 ADI Blackfin GOT relocation.
3552 BFD_RELOC_BFIN_PLTPC
3554 ADI Blackfin PLTPC relocation.
3556 BFD_ARELOC_BFIN_PUSH
3558 ADI Blackfin arithmetic relocation.
3560 BFD_ARELOC_BFIN_CONST
3562 ADI Blackfin arithmetic relocation.
3566 ADI Blackfin arithmetic relocation.
3570 ADI Blackfin arithmetic relocation.
3572 BFD_ARELOC_BFIN_MULT
3574 ADI Blackfin arithmetic relocation.
3578 ADI Blackfin arithmetic relocation.
3582 ADI Blackfin arithmetic relocation.
3584 BFD_ARELOC_BFIN_LSHIFT
3586 ADI Blackfin arithmetic relocation.
3588 BFD_ARELOC_BFIN_RSHIFT
3590 ADI Blackfin arithmetic relocation.
3594 ADI Blackfin arithmetic relocation.
3598 ADI Blackfin arithmetic relocation.
3602 ADI Blackfin arithmetic relocation.
3604 BFD_ARELOC_BFIN_LAND
3606 ADI Blackfin arithmetic relocation.
3610 ADI Blackfin arithmetic relocation.
3614 ADI Blackfin arithmetic relocation.
3618 ADI Blackfin arithmetic relocation.
3620 BFD_ARELOC_BFIN_COMP
3622 ADI Blackfin arithmetic relocation.
3624 BFD_ARELOC_BFIN_PAGE
3626 ADI Blackfin arithmetic relocation.
3628 BFD_ARELOC_BFIN_HWPAGE
3630 ADI Blackfin arithmetic relocation.
3632 BFD_ARELOC_BFIN_ADDR
3634 ADI Blackfin arithmetic relocation.
3637 BFD_RELOC_D10V_10_PCREL_R
3639 Mitsubishi D10V relocs.
3640 This is a 10-bit reloc with the right 2 bits
3643 BFD_RELOC_D10V_10_PCREL_L
3645 Mitsubishi D10V relocs.
3646 This is a 10-bit reloc with the right 2 bits
3647 assumed to be 0. This is the same as the previous reloc
3648 except it is in the left container, i.e.,
3649 shifted left 15 bits.
3653 This is an 18-bit reloc with the right 2 bits
3656 BFD_RELOC_D10V_18_PCREL
3658 This is an 18-bit reloc with the right 2 bits
3664 Mitsubishi D30V relocs.
3665 This is a 6-bit absolute reloc.
3667 BFD_RELOC_D30V_9_PCREL
3669 This is a 6-bit pc-relative reloc with
3670 the right 3 bits assumed to be 0.
3672 BFD_RELOC_D30V_9_PCREL_R
3674 This is a 6-bit pc-relative reloc with
3675 the right 3 bits assumed to be 0. Same
3676 as the previous reloc but on the right side
3681 This is a 12-bit absolute reloc with the
3682 right 3 bitsassumed to be 0.
3684 BFD_RELOC_D30V_15_PCREL
3686 This is a 12-bit pc-relative reloc with
3687 the right 3 bits assumed to be 0.
3689 BFD_RELOC_D30V_15_PCREL_R
3691 This is a 12-bit pc-relative reloc with
3692 the right 3 bits assumed to be 0. Same
3693 as the previous reloc but on the right side
3698 This is an 18-bit absolute reloc with
3699 the right 3 bits assumed to be 0.
3701 BFD_RELOC_D30V_21_PCREL
3703 This is an 18-bit pc-relative reloc with
3704 the right 3 bits assumed to be 0.
3706 BFD_RELOC_D30V_21_PCREL_R
3708 This is an 18-bit pc-relative reloc with
3709 the right 3 bits assumed to be 0. Same
3710 as the previous reloc but on the right side
3715 This is a 32-bit absolute reloc.
3717 BFD_RELOC_D30V_32_PCREL
3719 This is a 32-bit pc-relative reloc.
3722 BFD_RELOC_DLX_HI16_S
3737 BFD_RELOC_M32C_RL_JUMP
3739 BFD_RELOC_M32C_RL_1ADDR
3741 BFD_RELOC_M32C_RL_2ADDR
3743 Renesas M16C/M32C Relocations.
3748 Renesas M32R (formerly Mitsubishi M32R) relocs.
3749 This is a 24 bit absolute address.
3751 BFD_RELOC_M32R_10_PCREL
3753 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3755 BFD_RELOC_M32R_18_PCREL
3757 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3759 BFD_RELOC_M32R_26_PCREL
3761 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3763 BFD_RELOC_M32R_HI16_ULO
3765 This is a 16-bit reloc containing the high 16 bits of an address
3766 used when the lower 16 bits are treated as unsigned.
3768 BFD_RELOC_M32R_HI16_SLO
3770 This is a 16-bit reloc containing the high 16 bits of an address
3771 used when the lower 16 bits are treated as signed.
3775 This is a 16-bit reloc containing the lower 16 bits of an address.
3777 BFD_RELOC_M32R_SDA16
3779 This is a 16-bit reloc containing the small data area offset for use in
3780 add3, load, and store instructions.
3782 BFD_RELOC_M32R_GOT24
3784 BFD_RELOC_M32R_26_PLTREL
3788 BFD_RELOC_M32R_GLOB_DAT
3790 BFD_RELOC_M32R_JMP_SLOT
3792 BFD_RELOC_M32R_RELATIVE
3794 BFD_RELOC_M32R_GOTOFF
3796 BFD_RELOC_M32R_GOTOFF_HI_ULO
3798 BFD_RELOC_M32R_GOTOFF_HI_SLO
3800 BFD_RELOC_M32R_GOTOFF_LO
3802 BFD_RELOC_M32R_GOTPC24
3804 BFD_RELOC_M32R_GOT16_HI_ULO
3806 BFD_RELOC_M32R_GOT16_HI_SLO
3808 BFD_RELOC_M32R_GOT16_LO
3810 BFD_RELOC_M32R_GOTPC_HI_ULO
3812 BFD_RELOC_M32R_GOTPC_HI_SLO
3814 BFD_RELOC_M32R_GOTPC_LO
3820 BFD_RELOC_V850_9_PCREL
3822 This is a 9-bit reloc
3824 BFD_RELOC_V850_22_PCREL
3826 This is a 22-bit reloc
3829 BFD_RELOC_V850_SDA_16_16_OFFSET
3831 This is a 16 bit offset from the short data area pointer.
3833 BFD_RELOC_V850_SDA_15_16_OFFSET
3835 This is a 16 bit offset (of which only 15 bits are used) from the
3836 short data area pointer.
3838 BFD_RELOC_V850_ZDA_16_16_OFFSET
3840 This is a 16 bit offset from the zero data area pointer.
3842 BFD_RELOC_V850_ZDA_15_16_OFFSET
3844 This is a 16 bit offset (of which only 15 bits are used) from the
3845 zero data area pointer.
3847 BFD_RELOC_V850_TDA_6_8_OFFSET
3849 This is an 8 bit offset (of which only 6 bits are used) from the
3850 tiny data area pointer.
3852 BFD_RELOC_V850_TDA_7_8_OFFSET
3854 This is an 8bit offset (of which only 7 bits are used) from the tiny
3857 BFD_RELOC_V850_TDA_7_7_OFFSET
3859 This is a 7 bit offset from the tiny data area pointer.
3861 BFD_RELOC_V850_TDA_16_16_OFFSET
3863 This is a 16 bit offset from the tiny data area pointer.
3866 BFD_RELOC_V850_TDA_4_5_OFFSET
3868 This is a 5 bit offset (of which only 4 bits are used) from the tiny
3871 BFD_RELOC_V850_TDA_4_4_OFFSET
3873 This is a 4 bit offset from the tiny data area pointer.
3875 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
3877 This is a 16 bit offset from the short data area pointer, with the
3878 bits placed non-contiguously in the instruction.
3880 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
3882 This is a 16 bit offset from the zero data area pointer, with the
3883 bits placed non-contiguously in the instruction.
3885 BFD_RELOC_V850_CALLT_6_7_OFFSET
3887 This is a 6 bit offset from the call table base pointer.
3889 BFD_RELOC_V850_CALLT_16_16_OFFSET
3891 This is a 16 bit offset from the call table base pointer.
3893 BFD_RELOC_V850_LONGCALL
3895 Used for relaxing indirect function calls.
3897 BFD_RELOC_V850_LONGJUMP
3899 Used for relaxing indirect jumps.
3901 BFD_RELOC_V850_ALIGN
3903 Used to maintain alignment whilst relaxing.
3905 BFD_RELOC_V850_LO16_SPLIT_OFFSET
3907 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
3910 BFD_RELOC_V850_16_PCREL
3912 This is a 16-bit reloc.
3914 BFD_RELOC_V850_17_PCREL
3916 This is a 17-bit reloc.
3920 This is a 23-bit reloc.
3922 BFD_RELOC_V850_32_PCREL
3924 This is a 32-bit reloc.
3926 BFD_RELOC_V850_32_ABS
3928 This is a 32-bit reloc.
3930 BFD_RELOC_V850_16_SPLIT_OFFSET
3932 This is a 16-bit reloc.
3934 BFD_RELOC_V850_16_S1
3936 This is a 16-bit reloc.
3938 BFD_RELOC_V850_LO16_S1
3940 Low 16 bits. 16 bit shifted by 1.
3942 BFD_RELOC_V850_CALLT_15_16_OFFSET
3944 This is a 16 bit offset from the call table base pointer.
3946 BFD_RELOC_V850_32_GOTPCREL
3950 BFD_RELOC_V850_16_GOT
3954 BFD_RELOC_V850_32_GOT
3958 BFD_RELOC_V850_22_PLT_PCREL
3962 BFD_RELOC_V850_32_PLT_PCREL
3970 BFD_RELOC_V850_GLOB_DAT
3974 BFD_RELOC_V850_JMP_SLOT
3978 BFD_RELOC_V850_RELATIVE
3982 BFD_RELOC_V850_16_GOTOFF
3986 BFD_RELOC_V850_32_GOTOFF
4001 This is a 8bit DP reloc for the tms320c30, where the most
4002 significant 8 bits of a 24 bit word are placed into the least
4003 significant 8 bits of the opcode.
4006 BFD_RELOC_TIC54X_PARTLS7
4008 This is a 7bit reloc for the tms320c54x, where the least
4009 significant 7 bits of a 16 bit word are placed into the least
4010 significant 7 bits of the opcode.
4013 BFD_RELOC_TIC54X_PARTMS9
4015 This is a 9bit DP reloc for the tms320c54x, where the most
4016 significant 9 bits of a 16 bit word are placed into the least
4017 significant 9 bits of the opcode.
4022 This is an extended address 23-bit reloc for the tms320c54x.
4025 BFD_RELOC_TIC54X_16_OF_23
4027 This is a 16-bit reloc for the tms320c54x, where the least
4028 significant 16 bits of a 23-bit extended address are placed into
4032 BFD_RELOC_TIC54X_MS7_OF_23
4034 This is a reloc for the tms320c54x, where the most
4035 significant 7 bits of a 23-bit extended address are placed into
4039 BFD_RELOC_C6000_PCR_S21
4041 BFD_RELOC_C6000_PCR_S12
4043 BFD_RELOC_C6000_PCR_S10
4045 BFD_RELOC_C6000_PCR_S7
4047 BFD_RELOC_C6000_ABS_S16
4049 BFD_RELOC_C6000_ABS_L16
4051 BFD_RELOC_C6000_ABS_H16
4053 BFD_RELOC_C6000_SBR_U15_B
4055 BFD_RELOC_C6000_SBR_U15_H
4057 BFD_RELOC_C6000_SBR_U15_W
4059 BFD_RELOC_C6000_SBR_S16
4061 BFD_RELOC_C6000_SBR_L16_B
4063 BFD_RELOC_C6000_SBR_L16_H
4065 BFD_RELOC_C6000_SBR_L16_W
4067 BFD_RELOC_C6000_SBR_H16_B
4069 BFD_RELOC_C6000_SBR_H16_H
4071 BFD_RELOC_C6000_SBR_H16_W
4073 BFD_RELOC_C6000_SBR_GOT_U15_W
4075 BFD_RELOC_C6000_SBR_GOT_L16_W
4077 BFD_RELOC_C6000_SBR_GOT_H16_W
4079 BFD_RELOC_C6000_DSBT_INDEX
4081 BFD_RELOC_C6000_PREL31
4083 BFD_RELOC_C6000_COPY
4085 BFD_RELOC_C6000_JUMP_SLOT
4087 BFD_RELOC_C6000_EHTYPE
4089 BFD_RELOC_C6000_PCR_H16
4091 BFD_RELOC_C6000_PCR_L16
4093 BFD_RELOC_C6000_ALIGN
4095 BFD_RELOC_C6000_FPHEAD
4097 BFD_RELOC_C6000_NOCMP
4099 TMS320C6000 relocations.
4104 This is a 48 bit reloc for the FR30 that stores 32 bits.
4108 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4111 BFD_RELOC_FR30_6_IN_4
4113 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4116 BFD_RELOC_FR30_8_IN_8
4118 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4121 BFD_RELOC_FR30_9_IN_8
4123 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4126 BFD_RELOC_FR30_10_IN_8
4128 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4131 BFD_RELOC_FR30_9_PCREL
4133 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4134 short offset into 8 bits.
4136 BFD_RELOC_FR30_12_PCREL
4138 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4139 short offset into 11 bits.
4142 BFD_RELOC_MCORE_PCREL_IMM8BY4
4144 BFD_RELOC_MCORE_PCREL_IMM11BY2
4146 BFD_RELOC_MCORE_PCREL_IMM4BY2
4148 BFD_RELOC_MCORE_PCREL_32
4150 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4154 Motorola Mcore relocations.
4163 BFD_RELOC_MEP_PCREL8A2
4165 BFD_RELOC_MEP_PCREL12A2
4167 BFD_RELOC_MEP_PCREL17A2
4169 BFD_RELOC_MEP_PCREL24A2
4171 BFD_RELOC_MEP_PCABS24A2
4183 BFD_RELOC_MEP_TPREL7
4185 BFD_RELOC_MEP_TPREL7A2
4187 BFD_RELOC_MEP_TPREL7A4
4189 BFD_RELOC_MEP_UIMM24
4191 BFD_RELOC_MEP_ADDR24A4
4193 BFD_RELOC_MEP_GNU_VTINHERIT
4195 BFD_RELOC_MEP_GNU_VTENTRY
4197 Toshiba Media Processor Relocations.
4201 BFD_RELOC_METAG_HIADDR16
4203 BFD_RELOC_METAG_LOADDR16
4205 BFD_RELOC_METAG_RELBRANCH
4207 BFD_RELOC_METAG_GETSETOFF
4209 BFD_RELOC_METAG_HIOG
4211 BFD_RELOC_METAG_LOOG
4213 BFD_RELOC_METAG_REL8
4215 BFD_RELOC_METAG_REL16
4217 BFD_RELOC_METAG_HI16_GOTOFF
4219 BFD_RELOC_METAG_LO16_GOTOFF
4221 BFD_RELOC_METAG_GETSET_GOTOFF
4223 BFD_RELOC_METAG_GETSET_GOT
4225 BFD_RELOC_METAG_HI16_GOTPC
4227 BFD_RELOC_METAG_LO16_GOTPC
4229 BFD_RELOC_METAG_HI16_PLT
4231 BFD_RELOC_METAG_LO16_PLT
4233 BFD_RELOC_METAG_RELBRANCH_PLT
4235 BFD_RELOC_METAG_GOTOFF
4239 BFD_RELOC_METAG_COPY
4241 BFD_RELOC_METAG_JMP_SLOT
4243 BFD_RELOC_METAG_RELATIVE
4245 BFD_RELOC_METAG_GLOB_DAT
4247 BFD_RELOC_METAG_TLS_GD
4249 BFD_RELOC_METAG_TLS_LDM
4251 BFD_RELOC_METAG_TLS_LDO_HI16
4253 BFD_RELOC_METAG_TLS_LDO_LO16
4255 BFD_RELOC_METAG_TLS_LDO
4257 BFD_RELOC_METAG_TLS_IE
4259 BFD_RELOC_METAG_TLS_IENONPIC
4261 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4263 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4265 BFD_RELOC_METAG_TLS_TPOFF
4267 BFD_RELOC_METAG_TLS_DTPMOD
4269 BFD_RELOC_METAG_TLS_DTPOFF
4271 BFD_RELOC_METAG_TLS_LE
4273 BFD_RELOC_METAG_TLS_LE_HI16
4275 BFD_RELOC_METAG_TLS_LE_LO16
4277 Imagination Technologies Meta relocations.
4282 BFD_RELOC_MMIX_GETA_1
4284 BFD_RELOC_MMIX_GETA_2
4286 BFD_RELOC_MMIX_GETA_3
4288 These are relocations for the GETA instruction.
4290 BFD_RELOC_MMIX_CBRANCH
4292 BFD_RELOC_MMIX_CBRANCH_J
4294 BFD_RELOC_MMIX_CBRANCH_1
4296 BFD_RELOC_MMIX_CBRANCH_2
4298 BFD_RELOC_MMIX_CBRANCH_3
4300 These are relocations for a conditional branch instruction.
4302 BFD_RELOC_MMIX_PUSHJ
4304 BFD_RELOC_MMIX_PUSHJ_1
4306 BFD_RELOC_MMIX_PUSHJ_2
4308 BFD_RELOC_MMIX_PUSHJ_3
4310 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4312 These are relocations for the PUSHJ instruction.
4316 BFD_RELOC_MMIX_JMP_1
4318 BFD_RELOC_MMIX_JMP_2
4320 BFD_RELOC_MMIX_JMP_3
4322 These are relocations for the JMP instruction.
4324 BFD_RELOC_MMIX_ADDR19
4326 This is a relocation for a relative address as in a GETA instruction or
4329 BFD_RELOC_MMIX_ADDR27
4331 This is a relocation for a relative address as in a JMP instruction.
4333 BFD_RELOC_MMIX_REG_OR_BYTE
4335 This is a relocation for an instruction field that may be a general
4336 register or a value 0..255.
4340 This is a relocation for an instruction field that may be a general
4343 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4345 This is a relocation for two instruction fields holding a register and
4346 an offset, the equivalent of the relocation.
4348 BFD_RELOC_MMIX_LOCAL
4350 This relocation is an assertion that the expression is not allocated as
4351 a global register. It does not modify contents.
4354 BFD_RELOC_AVR_7_PCREL
4356 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4357 short offset into 7 bits.
4359 BFD_RELOC_AVR_13_PCREL
4361 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4362 short offset into 12 bits.
4366 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4367 program memory address) into 16 bits.
4369 BFD_RELOC_AVR_LO8_LDI
4371 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4372 data memory address) into 8 bit immediate value of LDI insn.
4374 BFD_RELOC_AVR_HI8_LDI
4376 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4377 of data memory address) into 8 bit immediate value of LDI insn.
4379 BFD_RELOC_AVR_HH8_LDI
4381 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4382 of program memory address) into 8 bit immediate value of LDI insn.
4384 BFD_RELOC_AVR_MS8_LDI
4386 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4387 of 32 bit value) into 8 bit immediate value of LDI insn.
4389 BFD_RELOC_AVR_LO8_LDI_NEG
4391 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4392 (usually data memory address) into 8 bit immediate value of SUBI insn.
4394 BFD_RELOC_AVR_HI8_LDI_NEG
4396 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4397 (high 8 bit of data memory address) into 8 bit immediate value of
4400 BFD_RELOC_AVR_HH8_LDI_NEG
4402 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4403 (most high 8 bit of program memory address) into 8 bit immediate value
4404 of LDI or SUBI insn.
4406 BFD_RELOC_AVR_MS8_LDI_NEG
4408 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4409 of 32 bit value) into 8 bit immediate value of LDI insn.
4411 BFD_RELOC_AVR_LO8_LDI_PM
4413 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4414 command address) into 8 bit immediate value of LDI insn.
4416 BFD_RELOC_AVR_LO8_LDI_GS
4418 This is a 16 bit reloc for the AVR that stores 8 bit value
4419 (command address) into 8 bit immediate value of LDI insn. If the address
4420 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4423 BFD_RELOC_AVR_HI8_LDI_PM
4425 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4426 of command address) into 8 bit immediate value of LDI insn.
4428 BFD_RELOC_AVR_HI8_LDI_GS
4430 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4431 of command address) into 8 bit immediate value of LDI insn. If the address
4432 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4435 BFD_RELOC_AVR_HH8_LDI_PM
4437 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4438 of command address) into 8 bit immediate value of LDI insn.
4440 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4442 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4443 (usually command address) into 8 bit immediate value of SUBI insn.
4445 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4447 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4448 (high 8 bit of 16 bit command address) into 8 bit immediate value
4451 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4453 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4454 (high 6 bit of 22 bit command address) into 8 bit immediate
4459 This is a 32 bit reloc for the AVR that stores 23 bit value
4464 This is a 16 bit reloc for the AVR that stores all needed bits
4465 for absolute addressing with ldi with overflow check to linktime
4469 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4472 BFD_RELOC_AVR_6_ADIW
4474 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4479 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4480 in .byte lo8(symbol)
4484 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4485 in .byte hi8(symbol)
4489 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4490 in .byte hlo8(symbol)
4495 BFD_RELOC_RL78_NEG16
4497 BFD_RELOC_RL78_NEG24
4499 BFD_RELOC_RL78_NEG32
4501 BFD_RELOC_RL78_16_OP
4503 BFD_RELOC_RL78_24_OP
4505 BFD_RELOC_RL78_32_OP
4513 BFD_RELOC_RL78_DIR3U_PCREL
4517 BFD_RELOC_RL78_GPRELB
4519 BFD_RELOC_RL78_GPRELW
4521 BFD_RELOC_RL78_GPRELL
4525 BFD_RELOC_RL78_OP_SUBTRACT
4527 BFD_RELOC_RL78_OP_NEG
4529 BFD_RELOC_RL78_OP_AND
4531 BFD_RELOC_RL78_OP_SHRA
4535 BFD_RELOC_RL78_ABS16
4537 BFD_RELOC_RL78_ABS16_REV
4539 BFD_RELOC_RL78_ABS32
4541 BFD_RELOC_RL78_ABS32_REV
4543 BFD_RELOC_RL78_ABS16U
4545 BFD_RELOC_RL78_ABS16UW
4547 BFD_RELOC_RL78_ABS16UL
4549 BFD_RELOC_RL78_RELAX
4557 Renesas RL78 Relocations.
4580 BFD_RELOC_RX_DIR3U_PCREL
4592 BFD_RELOC_RX_OP_SUBTRACT
4600 BFD_RELOC_RX_ABS16_REV
4604 BFD_RELOC_RX_ABS32_REV
4608 BFD_RELOC_RX_ABS16UW
4610 BFD_RELOC_RX_ABS16UL
4614 Renesas RX Relocations.
4627 32 bit PC relative PLT address.
4631 Copy symbol at runtime.
4633 BFD_RELOC_390_GLOB_DAT
4637 BFD_RELOC_390_JMP_SLOT
4641 BFD_RELOC_390_RELATIVE
4643 Adjust by program base.
4647 32 bit PC relative offset to GOT.
4653 BFD_RELOC_390_PC16DBL
4655 PC relative 16 bit shifted by 1.
4657 BFD_RELOC_390_PLT16DBL
4659 16 bit PC rel. PLT shifted by 1.
4661 BFD_RELOC_390_PC32DBL
4663 PC relative 32 bit shifted by 1.
4665 BFD_RELOC_390_PLT32DBL
4667 32 bit PC rel. PLT shifted by 1.
4669 BFD_RELOC_390_GOTPCDBL
4671 32 bit PC rel. GOT shifted by 1.
4679 64 bit PC relative PLT address.
4681 BFD_RELOC_390_GOTENT
4683 32 bit rel. offset to GOT entry.
4685 BFD_RELOC_390_GOTOFF64
4687 64 bit offset to GOT.
4689 BFD_RELOC_390_GOTPLT12
4691 12-bit offset to symbol-entry within GOT, with PLT handling.
4693 BFD_RELOC_390_GOTPLT16
4695 16-bit offset to symbol-entry within GOT, with PLT handling.
4697 BFD_RELOC_390_GOTPLT32
4699 32-bit offset to symbol-entry within GOT, with PLT handling.
4701 BFD_RELOC_390_GOTPLT64
4703 64-bit offset to symbol-entry within GOT, with PLT handling.
4705 BFD_RELOC_390_GOTPLTENT
4707 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
4709 BFD_RELOC_390_PLTOFF16
4711 16-bit rel. offset from the GOT to a PLT entry.
4713 BFD_RELOC_390_PLTOFF32
4715 32-bit rel. offset from the GOT to a PLT entry.
4717 BFD_RELOC_390_PLTOFF64
4719 64-bit rel. offset from the GOT to a PLT entry.
4722 BFD_RELOC_390_TLS_LOAD
4724 BFD_RELOC_390_TLS_GDCALL
4726 BFD_RELOC_390_TLS_LDCALL
4728 BFD_RELOC_390_TLS_GD32
4730 BFD_RELOC_390_TLS_GD64
4732 BFD_RELOC_390_TLS_GOTIE12
4734 BFD_RELOC_390_TLS_GOTIE32
4736 BFD_RELOC_390_TLS_GOTIE64
4738 BFD_RELOC_390_TLS_LDM32
4740 BFD_RELOC_390_TLS_LDM64
4742 BFD_RELOC_390_TLS_IE32
4744 BFD_RELOC_390_TLS_IE64
4746 BFD_RELOC_390_TLS_IEENT
4748 BFD_RELOC_390_TLS_LE32
4750 BFD_RELOC_390_TLS_LE64
4752 BFD_RELOC_390_TLS_LDO32
4754 BFD_RELOC_390_TLS_LDO64
4756 BFD_RELOC_390_TLS_DTPMOD
4758 BFD_RELOC_390_TLS_DTPOFF
4760 BFD_RELOC_390_TLS_TPOFF
4762 s390 tls relocations.
4769 BFD_RELOC_390_GOTPLT20
4771 BFD_RELOC_390_TLS_GOTIE20
4773 Long displacement extension.
4776 BFD_RELOC_390_IRELATIVE
4778 STT_GNU_IFUNC relocation.
4781 BFD_RELOC_SCORE_GPREL15
4784 Low 16 bit for load/store
4786 BFD_RELOC_SCORE_DUMMY2
4790 This is a 24-bit reloc with the right 1 bit assumed to be 0
4792 BFD_RELOC_SCORE_BRANCH
4794 This is a 19-bit reloc with the right 1 bit assumed to be 0
4796 BFD_RELOC_SCORE_IMM30
4798 This is a 32-bit reloc for 48-bit instructions.
4800 BFD_RELOC_SCORE_IMM32
4802 This is a 32-bit reloc for 48-bit instructions.
4804 BFD_RELOC_SCORE16_JMP
4806 This is a 11-bit reloc with the right 1 bit assumed to be 0
4808 BFD_RELOC_SCORE16_BRANCH
4810 This is a 8-bit reloc with the right 1 bit assumed to be 0
4812 BFD_RELOC_SCORE_BCMP
4814 This is a 9-bit reloc with the right 1 bit assumed to be 0
4816 BFD_RELOC_SCORE_GOT15
4818 BFD_RELOC_SCORE_GOT_LO16
4820 BFD_RELOC_SCORE_CALL15
4822 BFD_RELOC_SCORE_DUMMY_HI16
4824 Undocumented Score relocs
4829 Scenix IP2K - 9-bit register number / data address
4833 Scenix IP2K - 4-bit register/data bank number
4835 BFD_RELOC_IP2K_ADDR16CJP
4837 Scenix IP2K - low 13 bits of instruction word address
4839 BFD_RELOC_IP2K_PAGE3
4841 Scenix IP2K - high 3 bits of instruction word address
4843 BFD_RELOC_IP2K_LO8DATA
4845 BFD_RELOC_IP2K_HI8DATA
4847 BFD_RELOC_IP2K_EX8DATA
4849 Scenix IP2K - ext/low/high 8 bits of data address
4851 BFD_RELOC_IP2K_LO8INSN
4853 BFD_RELOC_IP2K_HI8INSN
4855 Scenix IP2K - low/high 8 bits of instruction word address
4857 BFD_RELOC_IP2K_PC_SKIP
4859 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
4863 Scenix IP2K - 16 bit word address in text section.
4865 BFD_RELOC_IP2K_FR_OFFSET
4867 Scenix IP2K - 7-bit sp or dp offset
4869 BFD_RELOC_VPE4KMATH_DATA
4871 BFD_RELOC_VPE4KMATH_INSN
4873 Scenix VPE4K coprocessor - data/insn-space addressing
4876 BFD_RELOC_VTABLE_INHERIT
4878 BFD_RELOC_VTABLE_ENTRY
4880 These two relocations are used by the linker to determine which of
4881 the entries in a C++ virtual function table are actually used. When
4882 the --gc-sections option is given, the linker will zero out the entries
4883 that are not used, so that the code for those functions need not be
4884 included in the output.
4886 VTABLE_INHERIT is a zero-space relocation used to describe to the
4887 linker the inheritance tree of a C++ virtual function table. The
4888 relocation's symbol should be the parent class' vtable, and the
4889 relocation should be located at the child vtable.
4891 VTABLE_ENTRY is a zero-space relocation that describes the use of a
4892 virtual function table entry. The reloc's symbol should refer to the
4893 table of the class mentioned in the code. Off of that base, an offset
4894 describes the entry that is being used. For Rela hosts, this offset
4895 is stored in the reloc's addend. For Rel hosts, we are forced to put
4896 this offset in the reloc's section offset.
4899 BFD_RELOC_IA64_IMM14
4901 BFD_RELOC_IA64_IMM22
4903 BFD_RELOC_IA64_IMM64
4905 BFD_RELOC_IA64_DIR32MSB
4907 BFD_RELOC_IA64_DIR32LSB
4909 BFD_RELOC_IA64_DIR64MSB
4911 BFD_RELOC_IA64_DIR64LSB
4913 BFD_RELOC_IA64_GPREL22
4915 BFD_RELOC_IA64_GPREL64I
4917 BFD_RELOC_IA64_GPREL32MSB
4919 BFD_RELOC_IA64_GPREL32LSB
4921 BFD_RELOC_IA64_GPREL64MSB
4923 BFD_RELOC_IA64_GPREL64LSB
4925 BFD_RELOC_IA64_LTOFF22
4927 BFD_RELOC_IA64_LTOFF64I
4929 BFD_RELOC_IA64_PLTOFF22
4931 BFD_RELOC_IA64_PLTOFF64I
4933 BFD_RELOC_IA64_PLTOFF64MSB
4935 BFD_RELOC_IA64_PLTOFF64LSB
4937 BFD_RELOC_IA64_FPTR64I
4939 BFD_RELOC_IA64_FPTR32MSB
4941 BFD_RELOC_IA64_FPTR32LSB
4943 BFD_RELOC_IA64_FPTR64MSB
4945 BFD_RELOC_IA64_FPTR64LSB
4947 BFD_RELOC_IA64_PCREL21B
4949 BFD_RELOC_IA64_PCREL21BI
4951 BFD_RELOC_IA64_PCREL21M
4953 BFD_RELOC_IA64_PCREL21F
4955 BFD_RELOC_IA64_PCREL22
4957 BFD_RELOC_IA64_PCREL60B
4959 BFD_RELOC_IA64_PCREL64I
4961 BFD_RELOC_IA64_PCREL32MSB
4963 BFD_RELOC_IA64_PCREL32LSB
4965 BFD_RELOC_IA64_PCREL64MSB
4967 BFD_RELOC_IA64_PCREL64LSB
4969 BFD_RELOC_IA64_LTOFF_FPTR22
4971 BFD_RELOC_IA64_LTOFF_FPTR64I
4973 BFD_RELOC_IA64_LTOFF_FPTR32MSB
4975 BFD_RELOC_IA64_LTOFF_FPTR32LSB
4977 BFD_RELOC_IA64_LTOFF_FPTR64MSB
4979 BFD_RELOC_IA64_LTOFF_FPTR64LSB
4981 BFD_RELOC_IA64_SEGREL32MSB
4983 BFD_RELOC_IA64_SEGREL32LSB
4985 BFD_RELOC_IA64_SEGREL64MSB
4987 BFD_RELOC_IA64_SEGREL64LSB
4989 BFD_RELOC_IA64_SECREL32MSB
4991 BFD_RELOC_IA64_SECREL32LSB
4993 BFD_RELOC_IA64_SECREL64MSB
4995 BFD_RELOC_IA64_SECREL64LSB
4997 BFD_RELOC_IA64_REL32MSB
4999 BFD_RELOC_IA64_REL32LSB
5001 BFD_RELOC_IA64_REL64MSB
5003 BFD_RELOC_IA64_REL64LSB
5005 BFD_RELOC_IA64_LTV32MSB
5007 BFD_RELOC_IA64_LTV32LSB
5009 BFD_RELOC_IA64_LTV64MSB
5011 BFD_RELOC_IA64_LTV64LSB
5013 BFD_RELOC_IA64_IPLTMSB
5015 BFD_RELOC_IA64_IPLTLSB
5019 BFD_RELOC_IA64_LTOFF22X
5021 BFD_RELOC_IA64_LDXMOV
5023 BFD_RELOC_IA64_TPREL14
5025 BFD_RELOC_IA64_TPREL22
5027 BFD_RELOC_IA64_TPREL64I
5029 BFD_RELOC_IA64_TPREL64MSB
5031 BFD_RELOC_IA64_TPREL64LSB
5033 BFD_RELOC_IA64_LTOFF_TPREL22
5035 BFD_RELOC_IA64_DTPMOD64MSB
5037 BFD_RELOC_IA64_DTPMOD64LSB
5039 BFD_RELOC_IA64_LTOFF_DTPMOD22
5041 BFD_RELOC_IA64_DTPREL14
5043 BFD_RELOC_IA64_DTPREL22
5045 BFD_RELOC_IA64_DTPREL64I
5047 BFD_RELOC_IA64_DTPREL32MSB
5049 BFD_RELOC_IA64_DTPREL32LSB
5051 BFD_RELOC_IA64_DTPREL64MSB
5053 BFD_RELOC_IA64_DTPREL64LSB
5055 BFD_RELOC_IA64_LTOFF_DTPREL22
5057 Intel IA64 Relocations.
5060 BFD_RELOC_M68HC11_HI8
5062 Motorola 68HC11 reloc.
5063 This is the 8 bit high part of an absolute address.
5065 BFD_RELOC_M68HC11_LO8
5067 Motorola 68HC11 reloc.
5068 This is the 8 bit low part of an absolute address.
5070 BFD_RELOC_M68HC11_3B
5072 Motorola 68HC11 reloc.
5073 This is the 3 bit of a value.
5075 BFD_RELOC_M68HC11_RL_JUMP
5077 Motorola 68HC11 reloc.
5078 This reloc marks the beginning of a jump/call instruction.
5079 It is used for linker relaxation to correctly identify beginning
5080 of instruction and change some branches to use PC-relative
5083 BFD_RELOC_M68HC11_RL_GROUP
5085 Motorola 68HC11 reloc.
5086 This reloc marks a group of several instructions that gcc generates
5087 and for which the linker relaxation pass can modify and/or remove
5090 BFD_RELOC_M68HC11_LO16
5092 Motorola 68HC11 reloc.
5093 This is the 16-bit lower part of an address. It is used for 'call'
5094 instruction to specify the symbol address without any special
5095 transformation (due to memory bank window).
5097 BFD_RELOC_M68HC11_PAGE
5099 Motorola 68HC11 reloc.
5100 This is a 8-bit reloc that specifies the page number of an address.
5101 It is used by 'call' instruction to specify the page number of
5104 BFD_RELOC_M68HC11_24
5106 Motorola 68HC11 reloc.
5107 This is a 24-bit reloc that represents the address with a 16-bit
5108 value and a 8-bit page number. The symbol address is transformed
5109 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5111 BFD_RELOC_M68HC12_5B
5113 Motorola 68HC12 reloc.
5114 This is the 5 bits of a value.
5116 BFD_RELOC_XGATE_RL_JUMP
5118 Freescale XGATE reloc.
5119 This reloc marks the beginning of a bra/jal instruction.
5121 BFD_RELOC_XGATE_RL_GROUP
5123 Freescale XGATE reloc.
5124 This reloc marks a group of several instructions that gcc generates
5125 and for which the linker relaxation pass can modify and/or remove
5128 BFD_RELOC_XGATE_LO16
5130 Freescale XGATE reloc.
5131 This is the 16-bit lower part of an address. It is used for the '16-bit'
5134 BFD_RELOC_XGATE_GPAGE
5136 Freescale XGATE reloc.
5140 Freescale XGATE reloc.
5142 BFD_RELOC_XGATE_PCREL_9
5144 Freescale XGATE reloc.
5145 This is a 9-bit pc-relative reloc.
5147 BFD_RELOC_XGATE_PCREL_10
5149 Freescale XGATE reloc.
5150 This is a 10-bit pc-relative reloc.
5152 BFD_RELOC_XGATE_IMM8_LO
5154 Freescale XGATE reloc.
5155 This is the 16-bit lower part of an address. It is used for the '16-bit'
5158 BFD_RELOC_XGATE_IMM8_HI
5160 Freescale XGATE reloc.
5161 This is the 16-bit higher part of an address. It is used for the '16-bit'
5164 BFD_RELOC_XGATE_IMM3
5166 Freescale XGATE reloc.
5167 This is a 3-bit pc-relative reloc.
5169 BFD_RELOC_XGATE_IMM4
5171 Freescale XGATE reloc.
5172 This is a 4-bit pc-relative reloc.
5174 BFD_RELOC_XGATE_IMM5
5176 Freescale XGATE reloc.
5177 This is a 5-bit pc-relative reloc.
5179 BFD_RELOC_M68HC12_9B
5181 Motorola 68HC12 reloc.
5182 This is the 9 bits of a value.
5184 BFD_RELOC_M68HC12_16B
5186 Motorola 68HC12 reloc.
5187 This is the 16 bits of a value.
5189 BFD_RELOC_M68HC12_9_PCREL
5191 Motorola 68HC12/XGATE reloc.
5192 This is a PCREL9 branch.
5194 BFD_RELOC_M68HC12_10_PCREL
5196 Motorola 68HC12/XGATE reloc.
5197 This is a PCREL10 branch.
5199 BFD_RELOC_M68HC12_LO8XG
5201 Motorola 68HC12/XGATE reloc.
5202 This is the 8 bit low part of an absolute address and immediately precedes
5203 a matching HI8XG part.
5205 BFD_RELOC_M68HC12_HI8XG
5207 Motorola 68HC12/XGATE reloc.
5208 This is the 8 bit high part of an absolute address and immediately follows
5209 a matching LO8XG part.
5213 BFD_RELOC_16C_NUM08_C
5217 BFD_RELOC_16C_NUM16_C
5221 BFD_RELOC_16C_NUM32_C
5223 BFD_RELOC_16C_DISP04
5225 BFD_RELOC_16C_DISP04_C
5227 BFD_RELOC_16C_DISP08
5229 BFD_RELOC_16C_DISP08_C
5231 BFD_RELOC_16C_DISP16
5233 BFD_RELOC_16C_DISP16_C
5235 BFD_RELOC_16C_DISP24
5237 BFD_RELOC_16C_DISP24_C
5239 BFD_RELOC_16C_DISP24a
5241 BFD_RELOC_16C_DISP24a_C
5245 BFD_RELOC_16C_REG04_C
5247 BFD_RELOC_16C_REG04a
5249 BFD_RELOC_16C_REG04a_C
5253 BFD_RELOC_16C_REG14_C
5257 BFD_RELOC_16C_REG16_C
5261 BFD_RELOC_16C_REG20_C
5265 BFD_RELOC_16C_ABS20_C
5269 BFD_RELOC_16C_ABS24_C
5273 BFD_RELOC_16C_IMM04_C
5277 BFD_RELOC_16C_IMM16_C
5281 BFD_RELOC_16C_IMM20_C
5285 BFD_RELOC_16C_IMM24_C
5289 BFD_RELOC_16C_IMM32_C
5291 NS CR16C Relocations.
5296 BFD_RELOC_CR16_NUM16
5298 BFD_RELOC_CR16_NUM32
5300 BFD_RELOC_CR16_NUM32a
5302 BFD_RELOC_CR16_REGREL0
5304 BFD_RELOC_CR16_REGREL4
5306 BFD_RELOC_CR16_REGREL4a
5308 BFD_RELOC_CR16_REGREL14
5310 BFD_RELOC_CR16_REGREL14a
5312 BFD_RELOC_CR16_REGREL16
5314 BFD_RELOC_CR16_REGREL20
5316 BFD_RELOC_CR16_REGREL20a
5318 BFD_RELOC_CR16_ABS20
5320 BFD_RELOC_CR16_ABS24
5326 BFD_RELOC_CR16_IMM16
5328 BFD_RELOC_CR16_IMM20
5330 BFD_RELOC_CR16_IMM24
5332 BFD_RELOC_CR16_IMM32
5334 BFD_RELOC_CR16_IMM32a
5336 BFD_RELOC_CR16_DISP4
5338 BFD_RELOC_CR16_DISP8
5340 BFD_RELOC_CR16_DISP16
5342 BFD_RELOC_CR16_DISP20
5344 BFD_RELOC_CR16_DISP24
5346 BFD_RELOC_CR16_DISP24a
5348 BFD_RELOC_CR16_SWITCH8
5350 BFD_RELOC_CR16_SWITCH16
5352 BFD_RELOC_CR16_SWITCH32
5354 BFD_RELOC_CR16_GOT_REGREL20
5356 BFD_RELOC_CR16_GOTC_REGREL20
5358 BFD_RELOC_CR16_GLOB_DAT
5360 NS CR16 Relocations.
5367 BFD_RELOC_CRX_REL8_CMP
5375 BFD_RELOC_CRX_REGREL12
5377 BFD_RELOC_CRX_REGREL22
5379 BFD_RELOC_CRX_REGREL28
5381 BFD_RELOC_CRX_REGREL32
5397 BFD_RELOC_CRX_SWITCH8
5399 BFD_RELOC_CRX_SWITCH16
5401 BFD_RELOC_CRX_SWITCH32
5406 BFD_RELOC_CRIS_BDISP8
5408 BFD_RELOC_CRIS_UNSIGNED_5
5410 BFD_RELOC_CRIS_SIGNED_6
5412 BFD_RELOC_CRIS_UNSIGNED_6
5414 BFD_RELOC_CRIS_SIGNED_8
5416 BFD_RELOC_CRIS_UNSIGNED_8
5418 BFD_RELOC_CRIS_SIGNED_16
5420 BFD_RELOC_CRIS_UNSIGNED_16
5422 BFD_RELOC_CRIS_LAPCQ_OFFSET
5424 BFD_RELOC_CRIS_UNSIGNED_4
5426 These relocs are only used within the CRIS assembler. They are not
5427 (at present) written to any object files.
5431 BFD_RELOC_CRIS_GLOB_DAT
5433 BFD_RELOC_CRIS_JUMP_SLOT
5435 BFD_RELOC_CRIS_RELATIVE
5437 Relocs used in ELF shared libraries for CRIS.
5439 BFD_RELOC_CRIS_32_GOT
5441 32-bit offset to symbol-entry within GOT.
5443 BFD_RELOC_CRIS_16_GOT
5445 16-bit offset to symbol-entry within GOT.
5447 BFD_RELOC_CRIS_32_GOTPLT
5449 32-bit offset to symbol-entry within GOT, with PLT handling.
5451 BFD_RELOC_CRIS_16_GOTPLT
5453 16-bit offset to symbol-entry within GOT, with PLT handling.
5455 BFD_RELOC_CRIS_32_GOTREL
5457 32-bit offset to symbol, relative to GOT.
5459 BFD_RELOC_CRIS_32_PLT_GOTREL
5461 32-bit offset to symbol with PLT entry, relative to GOT.
5463 BFD_RELOC_CRIS_32_PLT_PCREL
5465 32-bit offset to symbol with PLT entry, relative to this relocation.
5468 BFD_RELOC_CRIS_32_GOT_GD
5470 BFD_RELOC_CRIS_16_GOT_GD
5472 BFD_RELOC_CRIS_32_GD
5476 BFD_RELOC_CRIS_32_DTPREL
5478 BFD_RELOC_CRIS_16_DTPREL
5480 BFD_RELOC_CRIS_32_GOT_TPREL
5482 BFD_RELOC_CRIS_16_GOT_TPREL
5484 BFD_RELOC_CRIS_32_TPREL
5486 BFD_RELOC_CRIS_16_TPREL
5488 BFD_RELOC_CRIS_DTPMOD
5490 BFD_RELOC_CRIS_32_IE
5492 Relocs used in TLS code for CRIS.
5497 BFD_RELOC_860_GLOB_DAT
5499 BFD_RELOC_860_JUMP_SLOT
5501 BFD_RELOC_860_RELATIVE
5511 BFD_RELOC_860_SPLIT0
5515 BFD_RELOC_860_SPLIT1
5519 BFD_RELOC_860_SPLIT2
5523 BFD_RELOC_860_LOGOT0
5525 BFD_RELOC_860_SPGOT0
5527 BFD_RELOC_860_LOGOT1
5529 BFD_RELOC_860_SPGOT1
5531 BFD_RELOC_860_LOGOTOFF0
5533 BFD_RELOC_860_SPGOTOFF0
5535 BFD_RELOC_860_LOGOTOFF1
5537 BFD_RELOC_860_SPGOTOFF1
5539 BFD_RELOC_860_LOGOTOFF2
5541 BFD_RELOC_860_LOGOTOFF3
5545 BFD_RELOC_860_HIGHADJ
5549 BFD_RELOC_860_HAGOTOFF
5557 BFD_RELOC_860_HIGOTOFF
5559 Intel i860 Relocations.
5562 BFD_RELOC_OPENRISC_ABS_26
5564 BFD_RELOC_OPENRISC_REL_26
5566 OpenRISC Relocations.
5569 BFD_RELOC_H8_DIR16A8
5571 BFD_RELOC_H8_DIR16R8
5573 BFD_RELOC_H8_DIR24A8
5575 BFD_RELOC_H8_DIR24R8
5577 BFD_RELOC_H8_DIR32A16
5582 BFD_RELOC_XSTORMY16_REL_12
5584 BFD_RELOC_XSTORMY16_12
5586 BFD_RELOC_XSTORMY16_24
5588 BFD_RELOC_XSTORMY16_FPTR16
5590 Sony Xstormy16 Relocations.
5595 Self-describing complex relocations.
5607 Infineon Relocations.
5610 BFD_RELOC_VAX_GLOB_DAT
5612 BFD_RELOC_VAX_JMP_SLOT
5614 BFD_RELOC_VAX_RELATIVE
5616 Relocations used by VAX ELF.
5621 Morpho MT - 16 bit immediate relocation.
5625 Morpho MT - Hi 16 bits of an address.
5629 Morpho MT - Low 16 bits of an address.
5631 BFD_RELOC_MT_GNU_VTINHERIT
5633 Morpho MT - Used to tell the linker which vtable entries are used.
5635 BFD_RELOC_MT_GNU_VTENTRY
5637 Morpho MT - Used to tell the linker which vtable entries are used.
5639 BFD_RELOC_MT_PCINSN8
5641 Morpho MT - 8 bit immediate relocation.
5644 BFD_RELOC_MSP430_10_PCREL
5646 BFD_RELOC_MSP430_16_PCREL
5650 BFD_RELOC_MSP430_16_PCREL_BYTE
5652 BFD_RELOC_MSP430_16_BYTE
5654 BFD_RELOC_MSP430_2X_PCREL
5656 BFD_RELOC_MSP430_RL_PCREL
5658 msp430 specific relocation codes
5661 BFD_RELOC_IQ2000_OFFSET_16
5663 BFD_RELOC_IQ2000_OFFSET_21
5665 BFD_RELOC_IQ2000_UHI16
5670 BFD_RELOC_XTENSA_RTLD
5672 Special Xtensa relocation used only by PLT entries in ELF shared
5673 objects to indicate that the runtime linker should set the value
5674 to one of its own internal functions or data structures.
5676 BFD_RELOC_XTENSA_GLOB_DAT
5678 BFD_RELOC_XTENSA_JMP_SLOT
5680 BFD_RELOC_XTENSA_RELATIVE
5682 Xtensa relocations for ELF shared objects.
5684 BFD_RELOC_XTENSA_PLT
5686 Xtensa relocation used in ELF object files for symbols that may require
5687 PLT entries. Otherwise, this is just a generic 32-bit relocation.
5689 BFD_RELOC_XTENSA_DIFF8
5691 BFD_RELOC_XTENSA_DIFF16
5693 BFD_RELOC_XTENSA_DIFF32
5695 Xtensa relocations to mark the difference of two local symbols.
5696 These are only needed to support linker relaxation and can be ignored
5697 when not relaxing. The field is set to the value of the difference
5698 assuming no relaxation. The relocation encodes the position of the
5699 first symbol so the linker can determine whether to adjust the field
5702 BFD_RELOC_XTENSA_SLOT0_OP
5704 BFD_RELOC_XTENSA_SLOT1_OP
5706 BFD_RELOC_XTENSA_SLOT2_OP
5708 BFD_RELOC_XTENSA_SLOT3_OP
5710 BFD_RELOC_XTENSA_SLOT4_OP
5712 BFD_RELOC_XTENSA_SLOT5_OP
5714 BFD_RELOC_XTENSA_SLOT6_OP
5716 BFD_RELOC_XTENSA_SLOT7_OP
5718 BFD_RELOC_XTENSA_SLOT8_OP
5720 BFD_RELOC_XTENSA_SLOT9_OP
5722 BFD_RELOC_XTENSA_SLOT10_OP
5724 BFD_RELOC_XTENSA_SLOT11_OP
5726 BFD_RELOC_XTENSA_SLOT12_OP
5728 BFD_RELOC_XTENSA_SLOT13_OP
5730 BFD_RELOC_XTENSA_SLOT14_OP
5732 Generic Xtensa relocations for instruction operands. Only the slot
5733 number is encoded in the relocation. The relocation applies to the
5734 last PC-relative immediate operand, or if there are no PC-relative
5735 immediates, to the last immediate operand.
5737 BFD_RELOC_XTENSA_SLOT0_ALT
5739 BFD_RELOC_XTENSA_SLOT1_ALT
5741 BFD_RELOC_XTENSA_SLOT2_ALT
5743 BFD_RELOC_XTENSA_SLOT3_ALT
5745 BFD_RELOC_XTENSA_SLOT4_ALT
5747 BFD_RELOC_XTENSA_SLOT5_ALT
5749 BFD_RELOC_XTENSA_SLOT6_ALT
5751 BFD_RELOC_XTENSA_SLOT7_ALT
5753 BFD_RELOC_XTENSA_SLOT8_ALT
5755 BFD_RELOC_XTENSA_SLOT9_ALT
5757 BFD_RELOC_XTENSA_SLOT10_ALT
5759 BFD_RELOC_XTENSA_SLOT11_ALT
5761 BFD_RELOC_XTENSA_SLOT12_ALT
5763 BFD_RELOC_XTENSA_SLOT13_ALT
5765 BFD_RELOC_XTENSA_SLOT14_ALT
5767 Alternate Xtensa relocations. Only the slot is encoded in the
5768 relocation. The meaning of these relocations is opcode-specific.
5770 BFD_RELOC_XTENSA_OP0
5772 BFD_RELOC_XTENSA_OP1
5774 BFD_RELOC_XTENSA_OP2
5776 Xtensa relocations for backward compatibility. These have all been
5777 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
5779 BFD_RELOC_XTENSA_ASM_EXPAND
5781 Xtensa relocation to mark that the assembler expanded the
5782 instructions from an original target. The expansion size is
5783 encoded in the reloc size.
5785 BFD_RELOC_XTENSA_ASM_SIMPLIFY
5787 Xtensa relocation to mark that the linker should simplify
5788 assembler-expanded instructions. This is commonly used
5789 internally by the linker after analysis of a
5790 BFD_RELOC_XTENSA_ASM_EXPAND.
5792 BFD_RELOC_XTENSA_TLSDESC_FN
5794 BFD_RELOC_XTENSA_TLSDESC_ARG
5796 BFD_RELOC_XTENSA_TLS_DTPOFF
5798 BFD_RELOC_XTENSA_TLS_TPOFF
5800 BFD_RELOC_XTENSA_TLS_FUNC
5802 BFD_RELOC_XTENSA_TLS_ARG
5804 BFD_RELOC_XTENSA_TLS_CALL
5806 Xtensa TLS relocations.
5811 8 bit signed offset in (ix+d) or (iy+d).
5829 BFD_RELOC_LM32_BRANCH
5831 BFD_RELOC_LM32_16_GOT
5833 BFD_RELOC_LM32_GOTOFF_HI16
5835 BFD_RELOC_LM32_GOTOFF_LO16
5839 BFD_RELOC_LM32_GLOB_DAT
5841 BFD_RELOC_LM32_JMP_SLOT
5843 BFD_RELOC_LM32_RELATIVE
5845 Lattice Mico32 relocations.
5848 BFD_RELOC_MACH_O_SECTDIFF
5850 Difference between two section addreses. Must be followed by a
5851 BFD_RELOC_MACH_O_PAIR.
5853 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
5855 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
5857 BFD_RELOC_MACH_O_PAIR
5859 Pair of relocation. Contains the first symbol.
5862 BFD_RELOC_MACH_O_X86_64_BRANCH32
5864 BFD_RELOC_MACH_O_X86_64_BRANCH8
5866 PCREL relocations. They are marked as branch to create PLT entry if
5869 BFD_RELOC_MACH_O_X86_64_GOT
5871 Used when referencing a GOT entry.
5873 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
5875 Used when loading a GOT entry with movq. It is specially marked so that
5876 the linker could optimize the movq to a leaq if possible.
5878 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
5880 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
5882 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
5884 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
5886 BFD_RELOC_MACH_O_X86_64_PCREL32_1
5888 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
5890 BFD_RELOC_MACH_O_X86_64_PCREL32_2
5892 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
5894 BFD_RELOC_MACH_O_X86_64_PCREL32_4
5896 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
5899 BFD_RELOC_MICROBLAZE_32_LO
5901 This is a 32 bit reloc for the microblaze that stores the
5902 low 16 bits of a value
5904 BFD_RELOC_MICROBLAZE_32_LO_PCREL
5906 This is a 32 bit pc-relative reloc for the microblaze that
5907 stores the low 16 bits of a value
5909 BFD_RELOC_MICROBLAZE_32_ROSDA
5911 This is a 32 bit reloc for the microblaze that stores a
5912 value relative to the read-only small data area anchor
5914 BFD_RELOC_MICROBLAZE_32_RWSDA
5916 This is a 32 bit reloc for the microblaze that stores a
5917 value relative to the read-write small data area anchor
5919 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
5921 This is a 32 bit reloc for the microblaze to handle
5922 expressions of the form "Symbol Op Symbol"
5924 BFD_RELOC_MICROBLAZE_64_NONE
5926 This is a 64 bit reloc that stores the 32 bit pc relative
5927 value in two words (with an imm instruction). No relocation is
5928 done here - only used for relaxing
5930 BFD_RELOC_MICROBLAZE_64_GOTPC
5932 This is a 64 bit reloc that stores the 32 bit pc relative
5933 value in two words (with an imm instruction). The relocation is
5934 PC-relative GOT offset
5936 BFD_RELOC_MICROBLAZE_64_GOT
5938 This is a 64 bit reloc that stores the 32 bit pc relative
5939 value in two words (with an imm instruction). The relocation is
5942 BFD_RELOC_MICROBLAZE_64_PLT
5944 This is a 64 bit reloc that stores the 32 bit pc relative
5945 value in two words (with an imm instruction). The relocation is
5946 PC-relative offset into PLT
5948 BFD_RELOC_MICROBLAZE_64_GOTOFF
5950 This is a 64 bit reloc that stores the 32 bit GOT relative
5951 value in two words (with an imm instruction). The relocation is
5952 relative offset from _GLOBAL_OFFSET_TABLE_
5954 BFD_RELOC_MICROBLAZE_32_GOTOFF
5956 This is a 32 bit reloc that stores the 32 bit GOT relative
5957 value in a word. The relocation is relative offset from
5958 _GLOBAL_OFFSET_TABLE_
5960 BFD_RELOC_MICROBLAZE_COPY
5962 This is used to tell the dynamic linker to copy the value out of
5963 the dynamic object into the runtime process image.
5965 BFD_RELOC_MICROBLAZE_64_TLS
5969 BFD_RELOC_MICROBLAZE_64_TLSGD
5971 This is a 64 bit reloc that stores the 32 bit GOT relative value
5972 of the GOT TLS GD info entry in two words (with an imm instruction). The
5973 relocation is GOT offset.
5975 BFD_RELOC_MICROBLAZE_64_TLSLD
5977 This is a 64 bit reloc that stores the 32 bit GOT relative value
5978 of the GOT TLS LD info entry in two words (with an imm instruction). The
5979 relocation is GOT offset.
5981 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
5983 This is a 32 bit reloc that stores the Module ID to GOT(n).
5985 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
5987 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
5989 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
5991 This is a 32 bit reloc for storing TLS offset to two words (uses imm
5994 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
5996 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
5997 to two words (uses imm instruction).
5999 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6001 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6002 to two words (uses imm instruction).
6005 BFD_RELOC_AARCH64_ADD_LO12
6007 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6008 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6010 BFD_RELOC_AARCH64_GOT_LD_PREL19
6012 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6013 offset of the global offset table entry for a symbol. The lowest two
6014 bits must be zero and are not stored in the instruction, giving a 21
6015 bit signed byte offset. This relocation type requires signed overflow
6018 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6020 Get to the page base of the global offset table entry for a symbol as
6021 part of an ADRP instruction using a 21 bit PC relative value.Used in
6022 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6024 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6026 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6027 offset, giving a 4KB aligned page base address.
6029 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6031 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6032 offset, giving a 4KB aligned page base address, but with no overflow
6035 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6037 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6039 BFD_RELOC_AARCH64_BRANCH19
6041 AArch64 19 bit pc-relative conditional branch and compare & branch.
6042 The lowest two bits must be zero and are not stored in the instruction,
6043 giving a 21 bit signed byte offset.
6045 BFD_RELOC_AARCH64_CALL26
6047 AArch64 26 bit pc-relative unconditional branch and link.
6048 The lowest two bits must be zero and are not stored in the instruction,
6049 giving a 28 bit signed byte offset.
6051 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
6053 AArch64 pseudo relocation code to be used internally by the AArch64
6054 assembler and not (currently) written to any object files.
6056 BFD_RELOC_AARCH64_JUMP26
6058 AArch64 26 bit pc-relative unconditional branch.
6059 The lowest two bits must be zero and are not stored in the instruction,
6060 giving a 28 bit signed byte offset.
6062 BFD_RELOC_AARCH64_LD_LO19_PCREL
6064 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6065 offset. The lowest two bits must be zero and are not stored in the
6066 instruction, giving a 21 bit signed byte offset.
6068 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6070 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6071 the GOT entry for this symbol. Used in conjunction with
6072 BFD_RELOC_AARCH64_ADR_GOTPAGE.
6074 BFD_RELOC_AARCH64_LDST_LO12
6076 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
6077 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6079 BFD_RELOC_AARCH64_LDST8_LO12
6081 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6082 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6084 BFD_RELOC_AARCH64_LDST16_LO12
6086 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6087 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6089 BFD_RELOC_AARCH64_LDST32_LO12
6091 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6092 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6094 BFD_RELOC_AARCH64_LDST64_LO12
6096 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6097 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6099 BFD_RELOC_AARCH64_LDST128_LO12
6101 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6102 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6104 BFD_RELOC_AARCH64_MOVW_G0
6106 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6107 of an unsigned address/value.
6109 BFD_RELOC_AARCH64_MOVW_G0_S
6111 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6112 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6115 BFD_RELOC_AARCH64_MOVW_G0_NC
6117 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6118 an address/value. No overflow checking.
6120 BFD_RELOC_AARCH64_MOVW_G1
6122 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6123 of an unsigned address/value.
6125 BFD_RELOC_AARCH64_MOVW_G1_NC
6127 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6128 of an address/value. No overflow checking.
6130 BFD_RELOC_AARCH64_MOVW_G1_S
6132 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6133 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6136 BFD_RELOC_AARCH64_MOVW_G2
6138 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6139 of an unsigned address/value.
6141 BFD_RELOC_AARCH64_MOVW_G2_NC
6143 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6144 of an address/value. No overflow checking.
6146 BFD_RELOC_AARCH64_MOVW_G2_S
6148 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6149 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6152 BFD_RELOC_AARCH64_MOVW_G3
6154 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6155 of a signed or unsigned address/value.
6157 BFD_RELOC_AARCH64_TLSDESC
6159 AArch64 TLS relocation.
6161 BFD_RELOC_AARCH64_TLSDESC_ADD
6163 AArch64 TLS DESC relocation.
6165 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
6167 AArch64 TLS DESC relocation.
6169 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE
6171 AArch64 TLS DESC relocation.
6173 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
6175 AArch64 TLS DESC relocation.
6177 BFD_RELOC_AARCH64_TLSDESC_CALL
6179 AArch64 TLS DESC relocation.
6181 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
6183 AArch64 TLS DESC relocation.
6185 BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19
6187 AArch64 TLS DESC relocation.
6189 BFD_RELOC_AARCH64_TLSDESC_LDR
6191 AArch64 TLS DESC relocation.
6193 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
6195 AArch64 TLS DESC relocation.
6197 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
6199 AArch64 TLS DESC relocation.
6201 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6203 Unsigned 12 bit byte offset to global offset table entry for a symbols
6204 tls_index structure. Used in conjunction with
6205 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
6207 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6209 Get to the page base of the global offset table entry for a symbols
6210 tls_index structure as part of an adrp instruction using a 21 bit PC
6211 relative value. Used in conjunction with
6212 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6214 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
6216 AArch64 TLS INITIAL EXEC relocation.
6218 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
6220 AArch64 TLS INITIAL EXEC relocation.
6222 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
6224 AArch64 TLS INITIAL EXEC relocation.
6226 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
6228 AArch64 TLS INITIAL EXEC relocation.
6230 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
6232 AArch64 TLS INITIAL EXEC relocation.
6234 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
6236 AArch64 TLS LOCAL EXEC relocation.
6238 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
6240 AArch64 TLS LOCAL EXEC relocation.
6242 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
6244 AArch64 TLS LOCAL EXEC relocation.
6246 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
6248 AArch64 TLS LOCAL EXEC relocation.
6250 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
6252 AArch64 TLS LOCAL EXEC relocation.
6254 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
6256 AArch64 TLS LOCAL EXEC relocation.
6258 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
6260 AArch64 TLS LOCAL EXEC relocation.
6262 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
6264 AArch64 TLS LOCAL EXEC relocation.
6266 BFD_RELOC_AARCH64_TLS_DTPMOD64
6268 AArch64 TLS relocation.
6270 BFD_RELOC_AARCH64_TLS_DTPREL64
6272 AArch64 TLS relocation.
6274 BFD_RELOC_AARCH64_TLS_TPREL64
6276 AArch64 TLS relocation.
6278 BFD_RELOC_AARCH64_TSTBR14
6280 AArch64 14 bit pc-relative test bit and branch.
6281 The lowest two bits must be zero and are not stored in the instruction,
6282 giving a 16 bit signed byte offset.
6285 BFD_RELOC_TILEPRO_COPY
6287 BFD_RELOC_TILEPRO_GLOB_DAT
6289 BFD_RELOC_TILEPRO_JMP_SLOT
6291 BFD_RELOC_TILEPRO_RELATIVE
6293 BFD_RELOC_TILEPRO_BROFF_X1
6295 BFD_RELOC_TILEPRO_JOFFLONG_X1
6297 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
6299 BFD_RELOC_TILEPRO_IMM8_X0
6301 BFD_RELOC_TILEPRO_IMM8_Y0
6303 BFD_RELOC_TILEPRO_IMM8_X1
6305 BFD_RELOC_TILEPRO_IMM8_Y1
6307 BFD_RELOC_TILEPRO_DEST_IMM8_X1
6309 BFD_RELOC_TILEPRO_MT_IMM15_X1
6311 BFD_RELOC_TILEPRO_MF_IMM15_X1
6313 BFD_RELOC_TILEPRO_IMM16_X0
6315 BFD_RELOC_TILEPRO_IMM16_X1
6317 BFD_RELOC_TILEPRO_IMM16_X0_LO
6319 BFD_RELOC_TILEPRO_IMM16_X1_LO
6321 BFD_RELOC_TILEPRO_IMM16_X0_HI
6323 BFD_RELOC_TILEPRO_IMM16_X1_HI
6325 BFD_RELOC_TILEPRO_IMM16_X0_HA
6327 BFD_RELOC_TILEPRO_IMM16_X1_HA
6329 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
6331 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
6333 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
6335 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
6337 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
6339 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
6341 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
6343 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
6345 BFD_RELOC_TILEPRO_IMM16_X0_GOT
6347 BFD_RELOC_TILEPRO_IMM16_X1_GOT
6349 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
6351 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
6353 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
6355 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
6357 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
6359 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
6361 BFD_RELOC_TILEPRO_MMSTART_X0
6363 BFD_RELOC_TILEPRO_MMEND_X0
6365 BFD_RELOC_TILEPRO_MMSTART_X1
6367 BFD_RELOC_TILEPRO_MMEND_X1
6369 BFD_RELOC_TILEPRO_SHAMT_X0
6371 BFD_RELOC_TILEPRO_SHAMT_X1
6373 BFD_RELOC_TILEPRO_SHAMT_Y0
6375 BFD_RELOC_TILEPRO_SHAMT_Y1
6377 BFD_RELOC_TILEPRO_TLS_GD_CALL
6379 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
6381 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
6383 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
6385 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
6387 BFD_RELOC_TILEPRO_TLS_IE_LOAD
6389 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
6391 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
6393 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
6395 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
6397 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
6399 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
6401 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
6403 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
6405 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
6407 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
6409 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
6411 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
6413 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
6415 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
6417 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
6419 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
6421 BFD_RELOC_TILEPRO_TLS_DTPMOD32
6423 BFD_RELOC_TILEPRO_TLS_DTPOFF32
6425 BFD_RELOC_TILEPRO_TLS_TPOFF32
6427 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
6429 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
6431 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
6433 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
6435 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
6437 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
6439 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
6441 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
6443 Tilera TILEPro Relocations.
6445 BFD_RELOC_TILEGX_HW0
6447 BFD_RELOC_TILEGX_HW1
6449 BFD_RELOC_TILEGX_HW2
6451 BFD_RELOC_TILEGX_HW3
6453 BFD_RELOC_TILEGX_HW0_LAST
6455 BFD_RELOC_TILEGX_HW1_LAST
6457 BFD_RELOC_TILEGX_HW2_LAST
6459 BFD_RELOC_TILEGX_COPY
6461 BFD_RELOC_TILEGX_GLOB_DAT
6463 BFD_RELOC_TILEGX_JMP_SLOT
6465 BFD_RELOC_TILEGX_RELATIVE
6467 BFD_RELOC_TILEGX_BROFF_X1
6469 BFD_RELOC_TILEGX_JUMPOFF_X1
6471 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
6473 BFD_RELOC_TILEGX_IMM8_X0
6475 BFD_RELOC_TILEGX_IMM8_Y0
6477 BFD_RELOC_TILEGX_IMM8_X1
6479 BFD_RELOC_TILEGX_IMM8_Y1
6481 BFD_RELOC_TILEGX_DEST_IMM8_X1
6483 BFD_RELOC_TILEGX_MT_IMM14_X1
6485 BFD_RELOC_TILEGX_MF_IMM14_X1
6487 BFD_RELOC_TILEGX_MMSTART_X0
6489 BFD_RELOC_TILEGX_MMEND_X0
6491 BFD_RELOC_TILEGX_SHAMT_X0
6493 BFD_RELOC_TILEGX_SHAMT_X1
6495 BFD_RELOC_TILEGX_SHAMT_Y0
6497 BFD_RELOC_TILEGX_SHAMT_Y1
6499 BFD_RELOC_TILEGX_IMM16_X0_HW0
6501 BFD_RELOC_TILEGX_IMM16_X1_HW0
6503 BFD_RELOC_TILEGX_IMM16_X0_HW1
6505 BFD_RELOC_TILEGX_IMM16_X1_HW1
6507 BFD_RELOC_TILEGX_IMM16_X0_HW2
6509 BFD_RELOC_TILEGX_IMM16_X1_HW2
6511 BFD_RELOC_TILEGX_IMM16_X0_HW3
6513 BFD_RELOC_TILEGX_IMM16_X1_HW3
6515 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
6517 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
6519 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
6521 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
6523 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
6525 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
6527 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
6529 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
6531 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
6533 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
6535 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
6537 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
6539 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
6541 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
6543 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
6545 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
6547 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
6549 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
6551 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
6553 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
6555 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
6557 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
6559 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
6561 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
6563 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
6565 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
6567 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
6569 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
6571 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
6573 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
6575 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
6577 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
6579 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
6581 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
6583 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
6585 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
6587 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
6589 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
6591 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
6593 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
6595 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
6597 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
6599 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
6601 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
6603 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
6605 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
6607 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
6609 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
6611 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
6613 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
6615 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
6617 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
6619 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
6621 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
6623 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
6625 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
6627 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
6629 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
6631 BFD_RELOC_TILEGX_TLS_DTPMOD64
6633 BFD_RELOC_TILEGX_TLS_DTPOFF64
6635 BFD_RELOC_TILEGX_TLS_TPOFF64
6637 BFD_RELOC_TILEGX_TLS_DTPMOD32
6639 BFD_RELOC_TILEGX_TLS_DTPOFF32
6641 BFD_RELOC_TILEGX_TLS_TPOFF32
6643 BFD_RELOC_TILEGX_TLS_GD_CALL
6645 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
6647 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
6649 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
6651 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
6653 BFD_RELOC_TILEGX_TLS_IE_LOAD
6655 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
6657 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
6659 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
6661 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
6663 Tilera TILE-Gx Relocations.
6665 BFD_RELOC_EPIPHANY_SIMM8
6667 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
6669 BFD_RELOC_EPIPHANY_SIMM24
6671 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
6673 BFD_RELOC_EPIPHANY_HIGH
6675 Adapteva EPIPHANY - 16 most-significant bits of absolute address
6677 BFD_RELOC_EPIPHANY_LOW
6679 Adapteva EPIPHANY - 16 least-significant bits of absolute address
6681 BFD_RELOC_EPIPHANY_SIMM11
6683 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
6685 BFD_RELOC_EPIPHANY_IMM11
6687 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
6689 BFD_RELOC_EPIPHANY_IMM8
6691 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
6698 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
6703 bfd_reloc_type_lookup
6704 bfd_reloc_name_lookup
6707 reloc_howto_type *bfd_reloc_type_lookup
6708 (bfd *abfd, bfd_reloc_code_real_type code);
6709 reloc_howto_type *bfd_reloc_name_lookup
6710 (bfd *abfd, const char *reloc_name);
6713 Return a pointer to a howto structure which, when
6714 invoked, will perform the relocation @var{code} on data from the
6720 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
6722 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
6726 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
6728 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
6731 static reloc_howto_type bfd_howto_32 =
6732 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
6736 bfd_default_reloc_type_lookup
6739 reloc_howto_type *bfd_default_reloc_type_lookup
6740 (bfd *abfd, bfd_reloc_code_real_type code);
6743 Provides a default relocation lookup routine for any architecture.
6748 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
6752 case BFD_RELOC_CTOR:
6753 /* The type of reloc used in a ctor, which will be as wide as the
6754 address - so either a 64, 32, or 16 bitter. */
6755 switch (bfd_arch_bits_per_address (abfd))
6760 return &bfd_howto_32;
6774 bfd_get_reloc_code_name
6777 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
6780 Provides a printable name for the supplied relocation code.
6781 Useful mainly for printing error messages.
6785 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
6787 if (code > BFD_RELOC_UNUSED)
6789 return bfd_reloc_code_real_names[code];
6794 bfd_generic_relax_section
6797 bfd_boolean bfd_generic_relax_section
6800 struct bfd_link_info *,
6804 Provides default handling for relaxing for back ends which
6809 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
6810 asection *section ATTRIBUTE_UNUSED,
6811 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
6814 if (link_info->relocatable)
6815 (*link_info->callbacks->einfo)
6816 (_("%P%F: --relax and -r may not be used together\n"));
6824 bfd_generic_gc_sections
6827 bfd_boolean bfd_generic_gc_sections
6828 (bfd *, struct bfd_link_info *);
6831 Provides default handling for relaxing for back ends which
6832 don't do section gc -- i.e., does nothing.
6836 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
6837 struct bfd_link_info *info ATTRIBUTE_UNUSED)
6844 bfd_generic_lookup_section_flags
6847 bfd_boolean bfd_generic_lookup_section_flags
6848 (struct bfd_link_info *, struct flag_info *, asection *);
6851 Provides default handling for section flags lookup
6852 -- i.e., does nothing.
6853 Returns FALSE if the section should be omitted, otherwise TRUE.
6857 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
6858 struct flag_info *flaginfo,
6859 asection *section ATTRIBUTE_UNUSED)
6861 if (flaginfo != NULL)
6863 (*_bfd_error_handler) (_("INPUT_SECTION_FLAGS are not supported.\n"));
6871 bfd_generic_merge_sections
6874 bfd_boolean bfd_generic_merge_sections
6875 (bfd *, struct bfd_link_info *);
6878 Provides default handling for SEC_MERGE section merging for back ends
6879 which don't have SEC_MERGE support -- i.e., does nothing.
6883 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
6884 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
6891 bfd_generic_get_relocated_section_contents
6894 bfd_byte *bfd_generic_get_relocated_section_contents
6896 struct bfd_link_info *link_info,
6897 struct bfd_link_order *link_order,
6899 bfd_boolean relocatable,
6903 Provides default handling of relocation effort for back ends
6904 which can't be bothered to do it efficiently.
6909 bfd_generic_get_relocated_section_contents (bfd *abfd,
6910 struct bfd_link_info *link_info,
6911 struct bfd_link_order *link_order,
6913 bfd_boolean relocatable,
6916 bfd *input_bfd = link_order->u.indirect.section->owner;
6917 asection *input_section = link_order->u.indirect.section;
6919 arelent **reloc_vector;
6922 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
6926 /* Read in the section. */
6927 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
6930 if (reloc_size == 0)
6933 reloc_vector = (arelent **) bfd_malloc (reloc_size);
6934 if (reloc_vector == NULL)
6937 reloc_count = bfd_canonicalize_reloc (input_bfd,
6941 if (reloc_count < 0)
6944 if (reloc_count > 0)
6947 for (parent = reloc_vector; *parent != NULL; parent++)
6949 char *error_message = NULL;
6951 bfd_reloc_status_type r;
6953 symbol = *(*parent)->sym_ptr_ptr;
6954 if (symbol->section && discarded_section (symbol->section))
6957 static reloc_howto_type none_howto
6958 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
6959 "unused", FALSE, 0, 0, FALSE);
6961 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
6962 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
6964 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
6965 (*parent)->addend = 0;
6966 (*parent)->howto = &none_howto;
6970 r = bfd_perform_relocation (input_bfd,
6974 relocatable ? abfd : NULL,
6979 asection *os = input_section->output_section;
6981 /* A partial link, so keep the relocs. */
6982 os->orelocation[os->reloc_count] = *parent;
6986 if (r != bfd_reloc_ok)
6990 case bfd_reloc_undefined:
6991 if (!((*link_info->callbacks->undefined_symbol)
6992 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
6993 input_bfd, input_section, (*parent)->address,
6997 case bfd_reloc_dangerous:
6998 BFD_ASSERT (error_message != NULL);
6999 if (!((*link_info->callbacks->reloc_dangerous)
7000 (link_info, error_message, input_bfd, input_section,
7001 (*parent)->address)))
7004 case bfd_reloc_overflow:
7005 if (!((*link_info->callbacks->reloc_overflow)
7007 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
7008 (*parent)->howto->name, (*parent)->addend,
7009 input_bfd, input_section, (*parent)->address)))
7012 case bfd_reloc_outofrange:
7014 This error can result when processing some partially
7015 complete binaries. Do not abort, but issue an error
7017 link_info->callbacks->einfo
7018 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
7019 abfd, input_section, * parent);
7031 free (reloc_vector);
7035 free (reloc_vector);