1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2016 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type *howto)
452 How relocs are tied together in an <<asection>>:
454 .typedef struct relent_chain
457 . struct relent_chain *next;
463 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
464 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
471 bfd_reloc_status_type bfd_check_overflow
472 (enum complain_overflow how,
473 unsigned int bitsize,
474 unsigned int rightshift,
475 unsigned int addrsize,
479 Perform overflow checking on @var{relocation} which has
480 @var{bitsize} significant bits and will be shifted right by
481 @var{rightshift} bits, on a machine with addresses containing
482 @var{addrsize} significant bits. The result is either of
483 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
487 bfd_reloc_status_type
488 bfd_check_overflow (enum complain_overflow how,
489 unsigned int bitsize,
490 unsigned int rightshift,
491 unsigned int addrsize,
494 bfd_vma fieldmask, addrmask, signmask, ss, a;
495 bfd_reloc_status_type flag = bfd_reloc_ok;
497 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
498 we'll be permissive: extra bits in the field mask will
499 automatically extend the address mask for purposes of the
501 fieldmask = N_ONES (bitsize);
502 signmask = ~fieldmask;
503 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
504 a = (relocation & addrmask) >> rightshift;
508 case complain_overflow_dont:
511 case complain_overflow_signed:
512 /* If any sign bits are set, all sign bits must be set. That
513 is, A must be a valid negative address after shifting. */
514 signmask = ~ (fieldmask >> 1);
517 case complain_overflow_bitfield:
518 /* Bitfields are sometimes signed, sometimes unsigned. We
519 explicitly allow an address wrap too, which means a bitfield
520 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
521 if the value has some, but not all, bits set outside the
524 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
525 flag = bfd_reloc_overflow;
528 case complain_overflow_unsigned:
529 /* We have an overflow if the address does not fit in the field. */
530 if ((a & signmask) != 0)
531 flag = bfd_reloc_overflow;
543 bfd_perform_relocation
546 bfd_reloc_status_type bfd_perform_relocation
548 arelent *reloc_entry,
550 asection *input_section,
552 char **error_message);
555 If @var{output_bfd} is supplied to this function, the
556 generated image will be relocatable; the relocations are
557 copied to the output file after they have been changed to
558 reflect the new state of the world. There are two ways of
559 reflecting the results of partial linkage in an output file:
560 by modifying the output data in place, and by modifying the
561 relocation record. Some native formats (e.g., basic a.out and
562 basic coff) have no way of specifying an addend in the
563 relocation type, so the addend has to go in the output data.
564 This is no big deal since in these formats the output data
565 slot will always be big enough for the addend. Complex reloc
566 types with addends were invented to solve just this problem.
567 The @var{error_message} argument is set to an error message if
568 this return @code{bfd_reloc_dangerous}.
572 bfd_reloc_status_type
573 bfd_perform_relocation (bfd *abfd,
574 arelent *reloc_entry,
576 asection *input_section,
578 char **error_message)
581 bfd_reloc_status_type flag = bfd_reloc_ok;
582 bfd_size_type octets;
583 bfd_vma output_base = 0;
584 reloc_howto_type *howto = reloc_entry->howto;
585 asection *reloc_target_output_section;
588 symbol = *(reloc_entry->sym_ptr_ptr);
589 if (bfd_is_abs_section (symbol->section)
590 && output_bfd != NULL)
592 reloc_entry->address += input_section->output_offset;
596 /* PR 17512: file: 0f67f69d. */
598 return bfd_reloc_undefined;
600 /* If we are not producing relocatable output, return an error if
601 the symbol is not defined. An undefined weak symbol is
602 considered to have a value of zero (SVR4 ABI, p. 4-27). */
603 if (bfd_is_und_section (symbol->section)
604 && (symbol->flags & BSF_WEAK) == 0
605 && output_bfd == NULL)
606 flag = bfd_reloc_undefined;
608 /* If there is a function supplied to handle this relocation type,
609 call it. It'll return `bfd_reloc_continue' if further processing
611 if (howto->special_function)
613 bfd_reloc_status_type cont;
614 cont = howto->special_function (abfd, reloc_entry, symbol, data,
615 input_section, output_bfd,
617 if (cont != bfd_reloc_continue)
621 /* Is the address of the relocation really within the section?
622 Include the size of the reloc in the test for out of range addresses.
623 PR 17512: file: c146ab8b, 46dff27f, 38e53ebf. */
624 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
625 if (octets + bfd_get_reloc_size (howto)
626 > bfd_get_section_limit_octets (abfd, input_section))
627 return bfd_reloc_outofrange;
629 /* Work out which section the relocation is targeted at and the
630 initial relocation command value. */
632 /* Get symbol value. (Common symbols are special.) */
633 if (bfd_is_com_section (symbol->section))
636 relocation = symbol->value;
638 reloc_target_output_section = symbol->section->output_section;
640 /* Convert input-section-relative symbol value to absolute. */
641 if ((output_bfd && ! howto->partial_inplace)
642 || reloc_target_output_section == NULL)
645 output_base = reloc_target_output_section->vma;
647 relocation += output_base + symbol->section->output_offset;
649 /* Add in supplied addend. */
650 relocation += reloc_entry->addend;
652 /* Here the variable relocation holds the final address of the
653 symbol we are relocating against, plus any addend. */
655 if (howto->pc_relative)
657 /* This is a PC relative relocation. We want to set RELOCATION
658 to the distance between the address of the symbol and the
659 location. RELOCATION is already the address of the symbol.
661 We start by subtracting the address of the section containing
664 If pcrel_offset is set, we must further subtract the position
665 of the location within the section. Some targets arrange for
666 the addend to be the negative of the position of the location
667 within the section; for example, i386-aout does this. For
668 i386-aout, pcrel_offset is FALSE. Some other targets do not
669 include the position of the location; for example, m88kbcs,
670 or ELF. For those targets, pcrel_offset is TRUE.
672 If we are producing relocatable output, then we must ensure
673 that this reloc will be correctly computed when the final
674 relocation is done. If pcrel_offset is FALSE we want to wind
675 up with the negative of the location within the section,
676 which means we must adjust the existing addend by the change
677 in the location within the section. If pcrel_offset is TRUE
678 we do not want to adjust the existing addend at all.
680 FIXME: This seems logical to me, but for the case of
681 producing relocatable output it is not what the code
682 actually does. I don't want to change it, because it seems
683 far too likely that something will break. */
686 input_section->output_section->vma + input_section->output_offset;
688 if (howto->pcrel_offset)
689 relocation -= reloc_entry->address;
692 if (output_bfd != NULL)
694 if (! howto->partial_inplace)
696 /* This is a partial relocation, and we want to apply the relocation
697 to the reloc entry rather than the raw data. Modify the reloc
698 inplace to reflect what we now know. */
699 reloc_entry->addend = relocation;
700 reloc_entry->address += input_section->output_offset;
705 /* This is a partial relocation, but inplace, so modify the
708 If we've relocated with a symbol with a section, change
709 into a ref to the section belonging to the symbol. */
711 reloc_entry->address += input_section->output_offset;
714 if (abfd->xvec->flavour == bfd_target_coff_flavour
715 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
716 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
718 /* For m68k-coff, the addend was being subtracted twice during
719 relocation with -r. Removing the line below this comment
720 fixes that problem; see PR 2953.
722 However, Ian wrote the following, regarding removing the line below,
723 which explains why it is still enabled: --djm
725 If you put a patch like that into BFD you need to check all the COFF
726 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
727 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
728 problem in a different way. There may very well be a reason that the
729 code works as it does.
731 Hmmm. The first obvious point is that bfd_perform_relocation should
732 not have any tests that depend upon the flavour. It's seem like
733 entirely the wrong place for such a thing. The second obvious point
734 is that the current code ignores the reloc addend when producing
735 relocatable output for COFF. That's peculiar. In fact, I really
736 have no idea what the point of the line you want to remove is.
738 A typical COFF reloc subtracts the old value of the symbol and adds in
739 the new value to the location in the object file (if it's a pc
740 relative reloc it adds the difference between the symbol value and the
741 location). When relocating we need to preserve that property.
743 BFD handles this by setting the addend to the negative of the old
744 value of the symbol. Unfortunately it handles common symbols in a
745 non-standard way (it doesn't subtract the old value) but that's a
746 different story (we can't change it without losing backward
747 compatibility with old object files) (coff-i386 does subtract the old
748 value, to be compatible with existing coff-i386 targets, like SCO).
750 So everything works fine when not producing relocatable output. When
751 we are producing relocatable output, logically we should do exactly
752 what we do when not producing relocatable output. Therefore, your
753 patch is correct. In fact, it should probably always just set
754 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
755 add the value into the object file. This won't hurt the COFF code,
756 which doesn't use the addend; I'm not sure what it will do to other
757 formats (the thing to check for would be whether any formats both use
758 the addend and set partial_inplace).
760 When I wanted to make coff-i386 produce relocatable output, I ran
761 into the problem that you are running into: I wanted to remove that
762 line. Rather than risk it, I made the coff-i386 relocs use a special
763 function; it's coff_i386_reloc in coff-i386.c. The function
764 specifically adds the addend field into the object file, knowing that
765 bfd_perform_relocation is not going to. If you remove that line, then
766 coff-i386.c will wind up adding the addend field in twice. It's
767 trivial to fix; it just needs to be done.
769 The problem with removing the line is just that it may break some
770 working code. With BFD it's hard to be sure of anything. The right
771 way to deal with this is simply to build and test at least all the
772 supported COFF targets. It should be straightforward if time and disk
773 space consuming. For each target:
775 2) generate some executable, and link it using -r (I would
776 probably use paranoia.o and link against newlib/libc.a, which
777 for all the supported targets would be available in
778 /usr/cygnus/progressive/H-host/target/lib/libc.a).
779 3) make the change to reloc.c
780 4) rebuild the linker
782 6) if the resulting object files are the same, you have at least
784 7) if they are different you have to figure out which version is
787 relocation -= reloc_entry->addend;
788 reloc_entry->addend = 0;
792 reloc_entry->addend = relocation;
797 /* FIXME: This overflow checking is incomplete, because the value
798 might have overflowed before we get here. For a correct check we
799 need to compute the value in a size larger than bitsize, but we
800 can't reasonably do that for a reloc the same size as a host
802 FIXME: We should also do overflow checking on the result after
803 adding in the value contained in the object file. */
804 if (howto->complain_on_overflow != complain_overflow_dont
805 && flag == bfd_reloc_ok)
806 flag = bfd_check_overflow (howto->complain_on_overflow,
809 bfd_arch_bits_per_address (abfd),
812 /* Either we are relocating all the way, or we don't want to apply
813 the relocation to the reloc entry (probably because there isn't
814 any room in the output format to describe addends to relocs). */
816 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
817 (OSF version 1.3, compiler version 3.11). It miscompiles the
831 x <<= (unsigned long) s.i0;
835 printf ("succeeded (%lx)\n", x);
839 relocation >>= (bfd_vma) howto->rightshift;
841 /* Shift everything up to where it's going to be used. */
842 relocation <<= (bfd_vma) howto->bitpos;
844 /* Wait for the day when all have the mask in them. */
847 i instruction to be left alone
848 o offset within instruction
849 r relocation offset to apply
858 (( i i i i i o o o o o from bfd_get<size>
859 and S S S S S) to get the size offset we want
860 + r r r r r r r r r r) to get the final value to place
861 and D D D D D to chop to right size
862 -----------------------
865 ( i i i i i o o o o o from bfd_get<size>
866 and N N N N N ) get instruction
867 -----------------------
873 -----------------------
874 = R R R R R R R R R R put into bfd_put<size>
878 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
884 char x = bfd_get_8 (abfd, (char *) data + octets);
886 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
892 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
894 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
899 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
901 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
906 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
907 relocation = -relocation;
909 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
915 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
916 relocation = -relocation;
918 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
929 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
931 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
938 return bfd_reloc_other;
946 bfd_install_relocation
949 bfd_reloc_status_type bfd_install_relocation
951 arelent *reloc_entry,
952 void *data, bfd_vma data_start,
953 asection *input_section,
954 char **error_message);
957 This looks remarkably like <<bfd_perform_relocation>>, except it
958 does not expect that the section contents have been filled in.
959 I.e., it's suitable for use when creating, rather than applying
962 For now, this function should be considered reserved for the
966 bfd_reloc_status_type
967 bfd_install_relocation (bfd *abfd,
968 arelent *reloc_entry,
970 bfd_vma data_start_offset,
971 asection *input_section,
972 char **error_message)
975 bfd_reloc_status_type flag = bfd_reloc_ok;
976 bfd_size_type octets;
977 bfd_vma output_base = 0;
978 reloc_howto_type *howto = reloc_entry->howto;
979 asection *reloc_target_output_section;
983 symbol = *(reloc_entry->sym_ptr_ptr);
984 if (bfd_is_abs_section (symbol->section))
986 reloc_entry->address += input_section->output_offset;
990 /* If there is a function supplied to handle this relocation type,
991 call it. It'll return `bfd_reloc_continue' if further processing
993 if (howto->special_function)
995 bfd_reloc_status_type cont;
997 /* XXX - The special_function calls haven't been fixed up to deal
998 with creating new relocations and section contents. */
999 cont = howto->special_function (abfd, reloc_entry, symbol,
1000 /* XXX - Non-portable! */
1001 ((bfd_byte *) data_start
1002 - data_start_offset),
1003 input_section, abfd, error_message);
1004 if (cont != bfd_reloc_continue)
1008 /* Is the address of the relocation really within the section? */
1009 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
1010 if (octets + bfd_get_reloc_size (howto)
1011 > bfd_get_section_limit_octets (abfd, input_section))
1012 return bfd_reloc_outofrange;
1014 /* Work out which section the relocation is targeted at and the
1015 initial relocation command value. */
1017 /* Get symbol value. (Common symbols are special.) */
1018 if (bfd_is_com_section (symbol->section))
1021 relocation = symbol->value;
1023 reloc_target_output_section = symbol->section->output_section;
1025 /* Convert input-section-relative symbol value to absolute. */
1026 if (! howto->partial_inplace)
1029 output_base = reloc_target_output_section->vma;
1031 relocation += output_base + symbol->section->output_offset;
1033 /* Add in supplied addend. */
1034 relocation += reloc_entry->addend;
1036 /* Here the variable relocation holds the final address of the
1037 symbol we are relocating against, plus any addend. */
1039 if (howto->pc_relative)
1041 /* This is a PC relative relocation. We want to set RELOCATION
1042 to the distance between the address of the symbol and the
1043 location. RELOCATION is already the address of the symbol.
1045 We start by subtracting the address of the section containing
1048 If pcrel_offset is set, we must further subtract the position
1049 of the location within the section. Some targets arrange for
1050 the addend to be the negative of the position of the location
1051 within the section; for example, i386-aout does this. For
1052 i386-aout, pcrel_offset is FALSE. Some other targets do not
1053 include the position of the location; for example, m88kbcs,
1054 or ELF. For those targets, pcrel_offset is TRUE.
1056 If we are producing relocatable output, then we must ensure
1057 that this reloc will be correctly computed when the final
1058 relocation is done. If pcrel_offset is FALSE we want to wind
1059 up with the negative of the location within the section,
1060 which means we must adjust the existing addend by the change
1061 in the location within the section. If pcrel_offset is TRUE
1062 we do not want to adjust the existing addend at all.
1064 FIXME: This seems logical to me, but for the case of
1065 producing relocatable output it is not what the code
1066 actually does. I don't want to change it, because it seems
1067 far too likely that something will break. */
1070 input_section->output_section->vma + input_section->output_offset;
1072 if (howto->pcrel_offset && howto->partial_inplace)
1073 relocation -= reloc_entry->address;
1076 if (! howto->partial_inplace)
1078 /* This is a partial relocation, and we want to apply the relocation
1079 to the reloc entry rather than the raw data. Modify the reloc
1080 inplace to reflect what we now know. */
1081 reloc_entry->addend = relocation;
1082 reloc_entry->address += input_section->output_offset;
1087 /* This is a partial relocation, but inplace, so modify the
1090 If we've relocated with a symbol with a section, change
1091 into a ref to the section belonging to the symbol. */
1092 reloc_entry->address += input_section->output_offset;
1095 if (abfd->xvec->flavour == bfd_target_coff_flavour
1096 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1097 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1100 /* For m68k-coff, the addend was being subtracted twice during
1101 relocation with -r. Removing the line below this comment
1102 fixes that problem; see PR 2953.
1104 However, Ian wrote the following, regarding removing the line below,
1105 which explains why it is still enabled: --djm
1107 If you put a patch like that into BFD you need to check all the COFF
1108 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1109 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1110 problem in a different way. There may very well be a reason that the
1111 code works as it does.
1113 Hmmm. The first obvious point is that bfd_install_relocation should
1114 not have any tests that depend upon the flavour. It's seem like
1115 entirely the wrong place for such a thing. The second obvious point
1116 is that the current code ignores the reloc addend when producing
1117 relocatable output for COFF. That's peculiar. In fact, I really
1118 have no idea what the point of the line you want to remove is.
1120 A typical COFF reloc subtracts the old value of the symbol and adds in
1121 the new value to the location in the object file (if it's a pc
1122 relative reloc it adds the difference between the symbol value and the
1123 location). When relocating we need to preserve that property.
1125 BFD handles this by setting the addend to the negative of the old
1126 value of the symbol. Unfortunately it handles common symbols in a
1127 non-standard way (it doesn't subtract the old value) but that's a
1128 different story (we can't change it without losing backward
1129 compatibility with old object files) (coff-i386 does subtract the old
1130 value, to be compatible with existing coff-i386 targets, like SCO).
1132 So everything works fine when not producing relocatable output. When
1133 we are producing relocatable output, logically we should do exactly
1134 what we do when not producing relocatable output. Therefore, your
1135 patch is correct. In fact, it should probably always just set
1136 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1137 add the value into the object file. This won't hurt the COFF code,
1138 which doesn't use the addend; I'm not sure what it will do to other
1139 formats (the thing to check for would be whether any formats both use
1140 the addend and set partial_inplace).
1142 When I wanted to make coff-i386 produce relocatable output, I ran
1143 into the problem that you are running into: I wanted to remove that
1144 line. Rather than risk it, I made the coff-i386 relocs use a special
1145 function; it's coff_i386_reloc in coff-i386.c. The function
1146 specifically adds the addend field into the object file, knowing that
1147 bfd_install_relocation is not going to. If you remove that line, then
1148 coff-i386.c will wind up adding the addend field in twice. It's
1149 trivial to fix; it just needs to be done.
1151 The problem with removing the line is just that it may break some
1152 working code. With BFD it's hard to be sure of anything. The right
1153 way to deal with this is simply to build and test at least all the
1154 supported COFF targets. It should be straightforward if time and disk
1155 space consuming. For each target:
1157 2) generate some executable, and link it using -r (I would
1158 probably use paranoia.o and link against newlib/libc.a, which
1159 for all the supported targets would be available in
1160 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1161 3) make the change to reloc.c
1162 4) rebuild the linker
1164 6) if the resulting object files are the same, you have at least
1166 7) if they are different you have to figure out which version is
1168 relocation -= reloc_entry->addend;
1169 /* FIXME: There should be no target specific code here... */
1170 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1171 reloc_entry->addend = 0;
1175 reloc_entry->addend = relocation;
1179 /* FIXME: This overflow checking is incomplete, because the value
1180 might have overflowed before we get here. For a correct check we
1181 need to compute the value in a size larger than bitsize, but we
1182 can't reasonably do that for a reloc the same size as a host
1184 FIXME: We should also do overflow checking on the result after
1185 adding in the value contained in the object file. */
1186 if (howto->complain_on_overflow != complain_overflow_dont)
1187 flag = bfd_check_overflow (howto->complain_on_overflow,
1190 bfd_arch_bits_per_address (abfd),
1193 /* Either we are relocating all the way, or we don't want to apply
1194 the relocation to the reloc entry (probably because there isn't
1195 any room in the output format to describe addends to relocs). */
1197 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1198 (OSF version 1.3, compiler version 3.11). It miscompiles the
1212 x <<= (unsigned long) s.i0;
1214 printf ("failed\n");
1216 printf ("succeeded (%lx)\n", x);
1220 relocation >>= (bfd_vma) howto->rightshift;
1222 /* Shift everything up to where it's going to be used. */
1223 relocation <<= (bfd_vma) howto->bitpos;
1225 /* Wait for the day when all have the mask in them. */
1228 i instruction to be left alone
1229 o offset within instruction
1230 r relocation offset to apply
1239 (( i i i i i o o o o o from bfd_get<size>
1240 and S S S S S) to get the size offset we want
1241 + r r r r r r r r r r) to get the final value to place
1242 and D D D D D to chop to right size
1243 -----------------------
1246 ( i i i i i o o o o o from bfd_get<size>
1247 and N N N N N ) get instruction
1248 -----------------------
1254 -----------------------
1255 = R R R R R R R R R R put into bfd_put<size>
1259 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1261 data = (bfd_byte *) data_start + (octets - data_start_offset);
1263 switch (howto->size)
1267 char x = bfd_get_8 (abfd, data);
1269 bfd_put_8 (abfd, x, data);
1275 short x = bfd_get_16 (abfd, data);
1277 bfd_put_16 (abfd, (bfd_vma) x, data);
1282 long x = bfd_get_32 (abfd, data);
1284 bfd_put_32 (abfd, (bfd_vma) x, data);
1289 long x = bfd_get_32 (abfd, data);
1290 relocation = -relocation;
1292 bfd_put_32 (abfd, (bfd_vma) x, data);
1302 bfd_vma x = bfd_get_64 (abfd, data);
1304 bfd_put_64 (abfd, x, data);
1308 return bfd_reloc_other;
1314 /* This relocation routine is used by some of the backend linkers.
1315 They do not construct asymbol or arelent structures, so there is no
1316 reason for them to use bfd_perform_relocation. Also,
1317 bfd_perform_relocation is so hacked up it is easier to write a new
1318 function than to try to deal with it.
1320 This routine does a final relocation. Whether it is useful for a
1321 relocatable link depends upon how the object format defines
1324 FIXME: This routine ignores any special_function in the HOWTO,
1325 since the existing special_function values have been written for
1326 bfd_perform_relocation.
1328 HOWTO is the reloc howto information.
1329 INPUT_BFD is the BFD which the reloc applies to.
1330 INPUT_SECTION is the section which the reloc applies to.
1331 CONTENTS is the contents of the section.
1332 ADDRESS is the address of the reloc within INPUT_SECTION.
1333 VALUE is the value of the symbol the reloc refers to.
1334 ADDEND is the addend of the reloc. */
1336 bfd_reloc_status_type
1337 _bfd_final_link_relocate (reloc_howto_type *howto,
1339 asection *input_section,
1346 bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
1348 /* Sanity check the address. */
1349 if (octets + bfd_get_reloc_size (howto)
1350 > bfd_get_section_limit_octets (input_bfd, input_section))
1351 return bfd_reloc_outofrange;
1353 /* This function assumes that we are dealing with a basic relocation
1354 against a symbol. We want to compute the value of the symbol to
1355 relocate to. This is just VALUE, the value of the symbol, plus
1356 ADDEND, any addend associated with the reloc. */
1357 relocation = value + addend;
1359 /* If the relocation is PC relative, we want to set RELOCATION to
1360 the distance between the symbol (currently in RELOCATION) and the
1361 location we are relocating. Some targets (e.g., i386-aout)
1362 arrange for the contents of the section to be the negative of the
1363 offset of the location within the section; for such targets
1364 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1365 simply leave the contents of the section as zero; for such
1366 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1367 need to subtract out the offset of the location within the
1368 section (which is just ADDRESS). */
1369 if (howto->pc_relative)
1371 relocation -= (input_section->output_section->vma
1372 + input_section->output_offset);
1373 if (howto->pcrel_offset)
1374 relocation -= address;
1377 return _bfd_relocate_contents (howto, input_bfd, relocation,
1379 + address * bfd_octets_per_byte (input_bfd));
1382 /* Relocate a given location using a given value and howto. */
1384 bfd_reloc_status_type
1385 _bfd_relocate_contents (reloc_howto_type *howto,
1392 bfd_reloc_status_type flag;
1393 unsigned int rightshift = howto->rightshift;
1394 unsigned int bitpos = howto->bitpos;
1396 /* If the size is negative, negate RELOCATION. This isn't very
1398 if (howto->size < 0)
1399 relocation = -relocation;
1401 /* Get the value we are going to relocate. */
1402 size = bfd_get_reloc_size (howto);
1408 return bfd_reloc_ok;
1410 x = bfd_get_8 (input_bfd, location);
1413 x = bfd_get_16 (input_bfd, location);
1416 x = bfd_get_32 (input_bfd, location);
1420 x = bfd_get_64 (input_bfd, location);
1427 /* Check for overflow. FIXME: We may drop bits during the addition
1428 which we don't check for. We must either check at every single
1429 operation, which would be tedious, or we must do the computations
1430 in a type larger than bfd_vma, which would be inefficient. */
1431 flag = bfd_reloc_ok;
1432 if (howto->complain_on_overflow != complain_overflow_dont)
1434 bfd_vma addrmask, fieldmask, signmask, ss;
1437 /* Get the values to be added together. For signed and unsigned
1438 relocations, we assume that all values should be truncated to
1439 the size of an address. For bitfields, all the bits matter.
1440 See also bfd_check_overflow. */
1441 fieldmask = N_ONES (howto->bitsize);
1442 signmask = ~fieldmask;
1443 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1444 | (fieldmask << rightshift));
1445 a = (relocation & addrmask) >> rightshift;
1446 b = (x & howto->src_mask & addrmask) >> bitpos;
1447 addrmask >>= rightshift;
1449 switch (howto->complain_on_overflow)
1451 case complain_overflow_signed:
1452 /* If any sign bits are set, all sign bits must be set.
1453 That is, A must be a valid negative address after
1455 signmask = ~(fieldmask >> 1);
1458 case complain_overflow_bitfield:
1459 /* Much like the signed check, but for a field one bit
1460 wider. We allow a bitfield to represent numbers in the
1461 range -2**n to 2**n-1, where n is the number of bits in the
1462 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1463 can't overflow, which is exactly what we want. */
1465 if (ss != 0 && ss != (addrmask & signmask))
1466 flag = bfd_reloc_overflow;
1468 /* We only need this next bit of code if the sign bit of B
1469 is below the sign bit of A. This would only happen if
1470 SRC_MASK had fewer bits than BITSIZE. Note that if
1471 SRC_MASK has more bits than BITSIZE, we can get into
1472 trouble; we would need to verify that B is in range, as
1473 we do for A above. */
1474 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1477 /* Set all the bits above the sign bit. */
1480 /* Now we can do the addition. */
1483 /* See if the result has the correct sign. Bits above the
1484 sign bit are junk now; ignore them. If the sum is
1485 positive, make sure we did not have all negative inputs;
1486 if the sum is negative, make sure we did not have all
1487 positive inputs. The test below looks only at the sign
1488 bits, and it really just
1489 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1491 We mask with addrmask here to explicitly allow an address
1492 wrap-around. The Linux kernel relies on it, and it is
1493 the only way to write assembler code which can run when
1494 loaded at a location 0x80000000 away from the location at
1495 which it is linked. */
1496 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1497 flag = bfd_reloc_overflow;
1500 case complain_overflow_unsigned:
1501 /* Checking for an unsigned overflow is relatively easy:
1502 trim the addresses and add, and trim the result as well.
1503 Overflow is normally indicated when the result does not
1504 fit in the field. However, we also need to consider the
1505 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1506 input is 0x80000000, and bfd_vma is only 32 bits; then we
1507 will get sum == 0, but there is an overflow, since the
1508 inputs did not fit in the field. Instead of doing a
1509 separate test, we can check for this by or-ing in the
1510 operands when testing for the sum overflowing its final
1512 sum = (a + b) & addrmask;
1513 if ((a | b | sum) & signmask)
1514 flag = bfd_reloc_overflow;
1522 /* Put RELOCATION in the right bits. */
1523 relocation >>= (bfd_vma) rightshift;
1524 relocation <<= (bfd_vma) bitpos;
1526 /* Add RELOCATION to the right bits of X. */
1527 x = ((x & ~howto->dst_mask)
1528 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1530 /* Put the relocated value back in the object file. */
1536 bfd_put_8 (input_bfd, x, location);
1539 bfd_put_16 (input_bfd, x, location);
1542 bfd_put_32 (input_bfd, x, location);
1546 bfd_put_64 (input_bfd, x, location);
1556 /* Clear a given location using a given howto, by applying a fixed relocation
1557 value and discarding any in-place addend. This is used for fixed-up
1558 relocations against discarded symbols, to make ignorable debug or unwind
1559 information more obvious. */
1562 _bfd_clear_contents (reloc_howto_type *howto,
1564 asection *input_section,
1570 /* Get the value we are going to relocate. */
1571 size = bfd_get_reloc_size (howto);
1579 x = bfd_get_8 (input_bfd, location);
1582 x = bfd_get_16 (input_bfd, location);
1585 x = bfd_get_32 (input_bfd, location);
1589 x = bfd_get_64 (input_bfd, location);
1596 /* Zero out the unwanted bits of X. */
1597 x &= ~howto->dst_mask;
1599 /* For a range list, use 1 instead of 0 as placeholder. 0
1600 would terminate the list, hiding any later entries. */
1601 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1602 ".debug_ranges") == 0
1603 && (howto->dst_mask & 1) != 0)
1606 /* Put the relocated value back in the object file. */
1613 bfd_put_8 (input_bfd, x, location);
1616 bfd_put_16 (input_bfd, x, location);
1619 bfd_put_32 (input_bfd, x, location);
1623 bfd_put_64 (input_bfd, x, location);
1634 howto manager, , typedef arelent, Relocations
1639 When an application wants to create a relocation, but doesn't
1640 know what the target machine might call it, it can find out by
1641 using this bit of code.
1650 The insides of a reloc code. The idea is that, eventually, there
1651 will be one enumerator for every type of relocation we ever do.
1652 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1653 return a howto pointer.
1655 This does mean that the application must determine the correct
1656 enumerator value; you can't get a howto pointer from a random set
1677 Basic absolute relocations of N bits.
1692 PC-relative relocations. Sometimes these are relative to the address
1693 of the relocation itself; sometimes they are relative to the start of
1694 the section containing the relocation. It depends on the specific target.
1696 The 24-bit relocation is used in some Intel 960 configurations.
1701 Section relative relocations. Some targets need this for DWARF2.
1704 BFD_RELOC_32_GOT_PCREL
1706 BFD_RELOC_16_GOT_PCREL
1708 BFD_RELOC_8_GOT_PCREL
1714 BFD_RELOC_LO16_GOTOFF
1716 BFD_RELOC_HI16_GOTOFF
1718 BFD_RELOC_HI16_S_GOTOFF
1722 BFD_RELOC_64_PLT_PCREL
1724 BFD_RELOC_32_PLT_PCREL
1726 BFD_RELOC_24_PLT_PCREL
1728 BFD_RELOC_16_PLT_PCREL
1730 BFD_RELOC_8_PLT_PCREL
1738 BFD_RELOC_LO16_PLTOFF
1740 BFD_RELOC_HI16_PLTOFF
1742 BFD_RELOC_HI16_S_PLTOFF
1756 BFD_RELOC_68K_GLOB_DAT
1758 BFD_RELOC_68K_JMP_SLOT
1760 BFD_RELOC_68K_RELATIVE
1762 BFD_RELOC_68K_TLS_GD32
1764 BFD_RELOC_68K_TLS_GD16
1766 BFD_RELOC_68K_TLS_GD8
1768 BFD_RELOC_68K_TLS_LDM32
1770 BFD_RELOC_68K_TLS_LDM16
1772 BFD_RELOC_68K_TLS_LDM8
1774 BFD_RELOC_68K_TLS_LDO32
1776 BFD_RELOC_68K_TLS_LDO16
1778 BFD_RELOC_68K_TLS_LDO8
1780 BFD_RELOC_68K_TLS_IE32
1782 BFD_RELOC_68K_TLS_IE16
1784 BFD_RELOC_68K_TLS_IE8
1786 BFD_RELOC_68K_TLS_LE32
1788 BFD_RELOC_68K_TLS_LE16
1790 BFD_RELOC_68K_TLS_LE8
1792 Relocations used by 68K ELF.
1795 BFD_RELOC_32_BASEREL
1797 BFD_RELOC_16_BASEREL
1799 BFD_RELOC_LO16_BASEREL
1801 BFD_RELOC_HI16_BASEREL
1803 BFD_RELOC_HI16_S_BASEREL
1809 Linkage-table relative.
1814 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1817 BFD_RELOC_32_PCREL_S2
1819 BFD_RELOC_16_PCREL_S2
1821 BFD_RELOC_23_PCREL_S2
1823 These PC-relative relocations are stored as word displacements --
1824 i.e., byte displacements shifted right two bits. The 30-bit word
1825 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1826 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1827 signed 16-bit displacement is used on the MIPS, and the 23-bit
1828 displacement is used on the Alpha.
1835 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1836 the target word. These are used on the SPARC.
1843 For systems that allocate a Global Pointer register, these are
1844 displacements off that register. These relocation types are
1845 handled specially, because the value the register will have is
1846 decided relatively late.
1849 BFD_RELOC_I960_CALLJ
1851 Reloc types used for i960/b.out.
1856 BFD_RELOC_SPARC_WDISP22
1862 BFD_RELOC_SPARC_GOT10
1864 BFD_RELOC_SPARC_GOT13
1866 BFD_RELOC_SPARC_GOT22
1868 BFD_RELOC_SPARC_PC10
1870 BFD_RELOC_SPARC_PC22
1872 BFD_RELOC_SPARC_WPLT30
1874 BFD_RELOC_SPARC_COPY
1876 BFD_RELOC_SPARC_GLOB_DAT
1878 BFD_RELOC_SPARC_JMP_SLOT
1880 BFD_RELOC_SPARC_RELATIVE
1882 BFD_RELOC_SPARC_UA16
1884 BFD_RELOC_SPARC_UA32
1886 BFD_RELOC_SPARC_UA64
1888 BFD_RELOC_SPARC_GOTDATA_HIX22
1890 BFD_RELOC_SPARC_GOTDATA_LOX10
1892 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1894 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1896 BFD_RELOC_SPARC_GOTDATA_OP
1898 BFD_RELOC_SPARC_JMP_IREL
1900 BFD_RELOC_SPARC_IRELATIVE
1902 SPARC ELF relocations. There is probably some overlap with other
1903 relocation types already defined.
1906 BFD_RELOC_SPARC_BASE13
1908 BFD_RELOC_SPARC_BASE22
1910 I think these are specific to SPARC a.out (e.g., Sun 4).
1920 BFD_RELOC_SPARC_OLO10
1922 BFD_RELOC_SPARC_HH22
1924 BFD_RELOC_SPARC_HM10
1926 BFD_RELOC_SPARC_LM22
1928 BFD_RELOC_SPARC_PC_HH22
1930 BFD_RELOC_SPARC_PC_HM10
1932 BFD_RELOC_SPARC_PC_LM22
1934 BFD_RELOC_SPARC_WDISP16
1936 BFD_RELOC_SPARC_WDISP19
1944 BFD_RELOC_SPARC_DISP64
1947 BFD_RELOC_SPARC_PLT32
1949 BFD_RELOC_SPARC_PLT64
1951 BFD_RELOC_SPARC_HIX22
1953 BFD_RELOC_SPARC_LOX10
1961 BFD_RELOC_SPARC_REGISTER
1965 BFD_RELOC_SPARC_SIZE32
1967 BFD_RELOC_SPARC_SIZE64
1969 BFD_RELOC_SPARC_WDISP10
1974 BFD_RELOC_SPARC_REV32
1976 SPARC little endian relocation
1978 BFD_RELOC_SPARC_TLS_GD_HI22
1980 BFD_RELOC_SPARC_TLS_GD_LO10
1982 BFD_RELOC_SPARC_TLS_GD_ADD
1984 BFD_RELOC_SPARC_TLS_GD_CALL
1986 BFD_RELOC_SPARC_TLS_LDM_HI22
1988 BFD_RELOC_SPARC_TLS_LDM_LO10
1990 BFD_RELOC_SPARC_TLS_LDM_ADD
1992 BFD_RELOC_SPARC_TLS_LDM_CALL
1994 BFD_RELOC_SPARC_TLS_LDO_HIX22
1996 BFD_RELOC_SPARC_TLS_LDO_LOX10
1998 BFD_RELOC_SPARC_TLS_LDO_ADD
2000 BFD_RELOC_SPARC_TLS_IE_HI22
2002 BFD_RELOC_SPARC_TLS_IE_LO10
2004 BFD_RELOC_SPARC_TLS_IE_LD
2006 BFD_RELOC_SPARC_TLS_IE_LDX
2008 BFD_RELOC_SPARC_TLS_IE_ADD
2010 BFD_RELOC_SPARC_TLS_LE_HIX22
2012 BFD_RELOC_SPARC_TLS_LE_LOX10
2014 BFD_RELOC_SPARC_TLS_DTPMOD32
2016 BFD_RELOC_SPARC_TLS_DTPMOD64
2018 BFD_RELOC_SPARC_TLS_DTPOFF32
2020 BFD_RELOC_SPARC_TLS_DTPOFF64
2022 BFD_RELOC_SPARC_TLS_TPOFF32
2024 BFD_RELOC_SPARC_TLS_TPOFF64
2026 SPARC TLS relocations
2035 BFD_RELOC_SPU_IMM10W
2039 BFD_RELOC_SPU_IMM16W
2043 BFD_RELOC_SPU_PCREL9a
2045 BFD_RELOC_SPU_PCREL9b
2047 BFD_RELOC_SPU_PCREL16
2057 BFD_RELOC_SPU_ADD_PIC
2062 BFD_RELOC_ALPHA_GPDISP_HI16
2064 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2065 "addend" in some special way.
2066 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2067 writing; when reading, it will be the absolute section symbol. The
2068 addend is the displacement in bytes of the "lda" instruction from
2069 the "ldah" instruction (which is at the address of this reloc).
2071 BFD_RELOC_ALPHA_GPDISP_LO16
2073 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2074 with GPDISP_HI16 relocs. The addend is ignored when writing the
2075 relocations out, and is filled in with the file's GP value on
2076 reading, for convenience.
2079 BFD_RELOC_ALPHA_GPDISP
2081 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2082 relocation except that there is no accompanying GPDISP_LO16
2086 BFD_RELOC_ALPHA_LITERAL
2088 BFD_RELOC_ALPHA_ELF_LITERAL
2090 BFD_RELOC_ALPHA_LITUSE
2092 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2093 the assembler turns it into a LDQ instruction to load the address of
2094 the symbol, and then fills in a register in the real instruction.
2096 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2097 section symbol. The addend is ignored when writing, but is filled
2098 in with the file's GP value on reading, for convenience, as with the
2101 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2102 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2103 but it generates output not based on the position within the .got
2104 section, but relative to the GP value chosen for the file during the
2107 The LITUSE reloc, on the instruction using the loaded address, gives
2108 information to the linker that it might be able to use to optimize
2109 away some literal section references. The symbol is ignored (read
2110 as the absolute section symbol), and the "addend" indicates the type
2111 of instruction using the register:
2112 1 - "memory" fmt insn
2113 2 - byte-manipulation (byte offset reg)
2114 3 - jsr (target of branch)
2117 BFD_RELOC_ALPHA_HINT
2119 The HINT relocation indicates a value that should be filled into the
2120 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2121 prediction logic which may be provided on some processors.
2124 BFD_RELOC_ALPHA_LINKAGE
2126 The LINKAGE relocation outputs a linkage pair in the object file,
2127 which is filled by the linker.
2130 BFD_RELOC_ALPHA_CODEADDR
2132 The CODEADDR relocation outputs a STO_CA in the object file,
2133 which is filled by the linker.
2136 BFD_RELOC_ALPHA_GPREL_HI16
2138 BFD_RELOC_ALPHA_GPREL_LO16
2140 The GPREL_HI/LO relocations together form a 32-bit offset from the
2144 BFD_RELOC_ALPHA_BRSGP
2146 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2147 share a common GP, and the target address is adjusted for
2148 STO_ALPHA_STD_GPLOAD.
2153 The NOP relocation outputs a NOP if the longword displacement
2154 between two procedure entry points is < 2^21.
2159 The BSR relocation outputs a BSR if the longword displacement
2160 between two procedure entry points is < 2^21.
2165 The LDA relocation outputs a LDA if the longword displacement
2166 between two procedure entry points is < 2^16.
2171 The BOH relocation outputs a BSR if the longword displacement
2172 between two procedure entry points is < 2^21, or else a hint.
2175 BFD_RELOC_ALPHA_TLSGD
2177 BFD_RELOC_ALPHA_TLSLDM
2179 BFD_RELOC_ALPHA_DTPMOD64
2181 BFD_RELOC_ALPHA_GOTDTPREL16
2183 BFD_RELOC_ALPHA_DTPREL64
2185 BFD_RELOC_ALPHA_DTPREL_HI16
2187 BFD_RELOC_ALPHA_DTPREL_LO16
2189 BFD_RELOC_ALPHA_DTPREL16
2191 BFD_RELOC_ALPHA_GOTTPREL16
2193 BFD_RELOC_ALPHA_TPREL64
2195 BFD_RELOC_ALPHA_TPREL_HI16
2197 BFD_RELOC_ALPHA_TPREL_LO16
2199 BFD_RELOC_ALPHA_TPREL16
2201 Alpha thread-local storage relocations.
2206 BFD_RELOC_MICROMIPS_JMP
2208 The MIPS jump instruction.
2211 BFD_RELOC_MIPS16_JMP
2213 The MIPS16 jump instruction.
2216 BFD_RELOC_MIPS16_GPREL
2218 MIPS16 GP relative reloc.
2223 High 16 bits of 32-bit value; simple reloc.
2228 High 16 bits of 32-bit value but the low 16 bits will be sign
2229 extended and added to form the final result. If the low 16
2230 bits form a negative number, we need to add one to the high value
2231 to compensate for the borrow when the low bits are added.
2239 BFD_RELOC_HI16_PCREL
2241 High 16 bits of 32-bit pc-relative value
2243 BFD_RELOC_HI16_S_PCREL
2245 High 16 bits of 32-bit pc-relative value, adjusted
2247 BFD_RELOC_LO16_PCREL
2249 Low 16 bits of pc-relative value
2252 BFD_RELOC_MIPS16_GOT16
2254 BFD_RELOC_MIPS16_CALL16
2256 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2257 16-bit immediate fields
2259 BFD_RELOC_MIPS16_HI16
2261 MIPS16 high 16 bits of 32-bit value.
2263 BFD_RELOC_MIPS16_HI16_S
2265 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2266 extended and added to form the final result. If the low 16
2267 bits form a negative number, we need to add one to the high value
2268 to compensate for the borrow when the low bits are added.
2270 BFD_RELOC_MIPS16_LO16
2275 BFD_RELOC_MIPS16_TLS_GD
2277 BFD_RELOC_MIPS16_TLS_LDM
2279 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2281 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2283 BFD_RELOC_MIPS16_TLS_GOTTPREL
2285 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2287 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2289 MIPS16 TLS relocations
2292 BFD_RELOC_MIPS_LITERAL
2294 BFD_RELOC_MICROMIPS_LITERAL
2296 Relocation against a MIPS literal section.
2299 BFD_RELOC_MICROMIPS_7_PCREL_S1
2301 BFD_RELOC_MICROMIPS_10_PCREL_S1
2303 BFD_RELOC_MICROMIPS_16_PCREL_S1
2305 microMIPS PC-relative relocations.
2308 BFD_RELOC_MIPS_21_PCREL_S2
2310 BFD_RELOC_MIPS_26_PCREL_S2
2312 BFD_RELOC_MIPS_18_PCREL_S3
2314 BFD_RELOC_MIPS_19_PCREL_S2
2316 MIPS PC-relative relocations.
2319 BFD_RELOC_MICROMIPS_GPREL16
2321 BFD_RELOC_MICROMIPS_HI16
2323 BFD_RELOC_MICROMIPS_HI16_S
2325 BFD_RELOC_MICROMIPS_LO16
2327 microMIPS versions of generic BFD relocs.
2330 BFD_RELOC_MIPS_GOT16
2332 BFD_RELOC_MICROMIPS_GOT16
2334 BFD_RELOC_MIPS_CALL16
2336 BFD_RELOC_MICROMIPS_CALL16
2338 BFD_RELOC_MIPS_GOT_HI16
2340 BFD_RELOC_MICROMIPS_GOT_HI16
2342 BFD_RELOC_MIPS_GOT_LO16
2344 BFD_RELOC_MICROMIPS_GOT_LO16
2346 BFD_RELOC_MIPS_CALL_HI16
2348 BFD_RELOC_MICROMIPS_CALL_HI16
2350 BFD_RELOC_MIPS_CALL_LO16
2352 BFD_RELOC_MICROMIPS_CALL_LO16
2356 BFD_RELOC_MICROMIPS_SUB
2358 BFD_RELOC_MIPS_GOT_PAGE
2360 BFD_RELOC_MICROMIPS_GOT_PAGE
2362 BFD_RELOC_MIPS_GOT_OFST
2364 BFD_RELOC_MICROMIPS_GOT_OFST
2366 BFD_RELOC_MIPS_GOT_DISP
2368 BFD_RELOC_MICROMIPS_GOT_DISP
2370 BFD_RELOC_MIPS_SHIFT5
2372 BFD_RELOC_MIPS_SHIFT6
2374 BFD_RELOC_MIPS_INSERT_A
2376 BFD_RELOC_MIPS_INSERT_B
2378 BFD_RELOC_MIPS_DELETE
2380 BFD_RELOC_MIPS_HIGHEST
2382 BFD_RELOC_MICROMIPS_HIGHEST
2384 BFD_RELOC_MIPS_HIGHER
2386 BFD_RELOC_MICROMIPS_HIGHER
2388 BFD_RELOC_MIPS_SCN_DISP
2390 BFD_RELOC_MICROMIPS_SCN_DISP
2392 BFD_RELOC_MIPS_REL16
2394 BFD_RELOC_MIPS_RELGOT
2398 BFD_RELOC_MICROMIPS_JALR
2400 BFD_RELOC_MIPS_TLS_DTPMOD32
2402 BFD_RELOC_MIPS_TLS_DTPREL32
2404 BFD_RELOC_MIPS_TLS_DTPMOD64
2406 BFD_RELOC_MIPS_TLS_DTPREL64
2408 BFD_RELOC_MIPS_TLS_GD
2410 BFD_RELOC_MICROMIPS_TLS_GD
2412 BFD_RELOC_MIPS_TLS_LDM
2414 BFD_RELOC_MICROMIPS_TLS_LDM
2416 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2418 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2420 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2422 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2424 BFD_RELOC_MIPS_TLS_GOTTPREL
2426 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2428 BFD_RELOC_MIPS_TLS_TPREL32
2430 BFD_RELOC_MIPS_TLS_TPREL64
2432 BFD_RELOC_MIPS_TLS_TPREL_HI16
2434 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2436 BFD_RELOC_MIPS_TLS_TPREL_LO16
2438 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2442 MIPS ELF relocations.
2448 BFD_RELOC_MIPS_JUMP_SLOT
2450 MIPS ELF relocations (VxWorks and PLT extensions).
2454 BFD_RELOC_MOXIE_10_PCREL
2456 Moxie ELF relocations.
2468 FT32 ELF relocations.
2472 BFD_RELOC_FRV_LABEL16
2474 BFD_RELOC_FRV_LABEL24
2480 BFD_RELOC_FRV_GPREL12
2482 BFD_RELOC_FRV_GPRELU12
2484 BFD_RELOC_FRV_GPREL32
2486 BFD_RELOC_FRV_GPRELHI
2488 BFD_RELOC_FRV_GPRELLO
2496 BFD_RELOC_FRV_FUNCDESC
2498 BFD_RELOC_FRV_FUNCDESC_GOT12
2500 BFD_RELOC_FRV_FUNCDESC_GOTHI
2502 BFD_RELOC_FRV_FUNCDESC_GOTLO
2504 BFD_RELOC_FRV_FUNCDESC_VALUE
2506 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2508 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2510 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2512 BFD_RELOC_FRV_GOTOFF12
2514 BFD_RELOC_FRV_GOTOFFHI
2516 BFD_RELOC_FRV_GOTOFFLO
2518 BFD_RELOC_FRV_GETTLSOFF
2520 BFD_RELOC_FRV_TLSDESC_VALUE
2522 BFD_RELOC_FRV_GOTTLSDESC12
2524 BFD_RELOC_FRV_GOTTLSDESCHI
2526 BFD_RELOC_FRV_GOTTLSDESCLO
2528 BFD_RELOC_FRV_TLSMOFF12
2530 BFD_RELOC_FRV_TLSMOFFHI
2532 BFD_RELOC_FRV_TLSMOFFLO
2534 BFD_RELOC_FRV_GOTTLSOFF12
2536 BFD_RELOC_FRV_GOTTLSOFFHI
2538 BFD_RELOC_FRV_GOTTLSOFFLO
2540 BFD_RELOC_FRV_TLSOFF
2542 BFD_RELOC_FRV_TLSDESC_RELAX
2544 BFD_RELOC_FRV_GETTLSOFF_RELAX
2546 BFD_RELOC_FRV_TLSOFF_RELAX
2548 BFD_RELOC_FRV_TLSMOFF
2550 Fujitsu Frv Relocations.
2554 BFD_RELOC_MN10300_GOTOFF24
2556 This is a 24bit GOT-relative reloc for the mn10300.
2558 BFD_RELOC_MN10300_GOT32
2560 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2563 BFD_RELOC_MN10300_GOT24
2565 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2568 BFD_RELOC_MN10300_GOT16
2570 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2573 BFD_RELOC_MN10300_COPY
2575 Copy symbol at runtime.
2577 BFD_RELOC_MN10300_GLOB_DAT
2581 BFD_RELOC_MN10300_JMP_SLOT
2585 BFD_RELOC_MN10300_RELATIVE
2587 Adjust by program base.
2589 BFD_RELOC_MN10300_SYM_DIFF
2591 Together with another reloc targeted at the same location,
2592 allows for a value that is the difference of two symbols
2593 in the same section.
2595 BFD_RELOC_MN10300_ALIGN
2597 The addend of this reloc is an alignment power that must
2598 be honoured at the offset's location, regardless of linker
2601 BFD_RELOC_MN10300_TLS_GD
2603 BFD_RELOC_MN10300_TLS_LD
2605 BFD_RELOC_MN10300_TLS_LDO
2607 BFD_RELOC_MN10300_TLS_GOTIE
2609 BFD_RELOC_MN10300_TLS_IE
2611 BFD_RELOC_MN10300_TLS_LE
2613 BFD_RELOC_MN10300_TLS_DTPMOD
2615 BFD_RELOC_MN10300_TLS_DTPOFF
2617 BFD_RELOC_MN10300_TLS_TPOFF
2619 Various TLS-related relocations.
2621 BFD_RELOC_MN10300_32_PCREL
2623 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2626 BFD_RELOC_MN10300_16_PCREL
2628 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2639 BFD_RELOC_386_GLOB_DAT
2641 BFD_RELOC_386_JUMP_SLOT
2643 BFD_RELOC_386_RELATIVE
2645 BFD_RELOC_386_GOTOFF
2649 BFD_RELOC_386_TLS_TPOFF
2651 BFD_RELOC_386_TLS_IE
2653 BFD_RELOC_386_TLS_GOTIE
2655 BFD_RELOC_386_TLS_LE
2657 BFD_RELOC_386_TLS_GD
2659 BFD_RELOC_386_TLS_LDM
2661 BFD_RELOC_386_TLS_LDO_32
2663 BFD_RELOC_386_TLS_IE_32
2665 BFD_RELOC_386_TLS_LE_32
2667 BFD_RELOC_386_TLS_DTPMOD32
2669 BFD_RELOC_386_TLS_DTPOFF32
2671 BFD_RELOC_386_TLS_TPOFF32
2673 BFD_RELOC_386_TLS_GOTDESC
2675 BFD_RELOC_386_TLS_DESC_CALL
2677 BFD_RELOC_386_TLS_DESC
2679 BFD_RELOC_386_IRELATIVE
2681 BFD_RELOC_386_GOT32X
2683 i386/elf relocations
2686 BFD_RELOC_X86_64_GOT32
2688 BFD_RELOC_X86_64_PLT32
2690 BFD_RELOC_X86_64_COPY
2692 BFD_RELOC_X86_64_GLOB_DAT
2694 BFD_RELOC_X86_64_JUMP_SLOT
2696 BFD_RELOC_X86_64_RELATIVE
2698 BFD_RELOC_X86_64_GOTPCREL
2700 BFD_RELOC_X86_64_32S
2702 BFD_RELOC_X86_64_DTPMOD64
2704 BFD_RELOC_X86_64_DTPOFF64
2706 BFD_RELOC_X86_64_TPOFF64
2708 BFD_RELOC_X86_64_TLSGD
2710 BFD_RELOC_X86_64_TLSLD
2712 BFD_RELOC_X86_64_DTPOFF32
2714 BFD_RELOC_X86_64_GOTTPOFF
2716 BFD_RELOC_X86_64_TPOFF32
2718 BFD_RELOC_X86_64_GOTOFF64
2720 BFD_RELOC_X86_64_GOTPC32
2722 BFD_RELOC_X86_64_GOT64
2724 BFD_RELOC_X86_64_GOTPCREL64
2726 BFD_RELOC_X86_64_GOTPC64
2728 BFD_RELOC_X86_64_GOTPLT64
2730 BFD_RELOC_X86_64_PLTOFF64
2732 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2734 BFD_RELOC_X86_64_TLSDESC_CALL
2736 BFD_RELOC_X86_64_TLSDESC
2738 BFD_RELOC_X86_64_IRELATIVE
2740 BFD_RELOC_X86_64_PC32_BND
2742 BFD_RELOC_X86_64_PLT32_BND
2744 BFD_RELOC_X86_64_GOTPCRELX
2746 BFD_RELOC_X86_64_REX_GOTPCRELX
2748 x86-64/elf relocations
2751 BFD_RELOC_NS32K_IMM_8
2753 BFD_RELOC_NS32K_IMM_16
2755 BFD_RELOC_NS32K_IMM_32
2757 BFD_RELOC_NS32K_IMM_8_PCREL
2759 BFD_RELOC_NS32K_IMM_16_PCREL
2761 BFD_RELOC_NS32K_IMM_32_PCREL
2763 BFD_RELOC_NS32K_DISP_8
2765 BFD_RELOC_NS32K_DISP_16
2767 BFD_RELOC_NS32K_DISP_32
2769 BFD_RELOC_NS32K_DISP_8_PCREL
2771 BFD_RELOC_NS32K_DISP_16_PCREL
2773 BFD_RELOC_NS32K_DISP_32_PCREL
2778 BFD_RELOC_PDP11_DISP_8_PCREL
2780 BFD_RELOC_PDP11_DISP_6_PCREL
2785 BFD_RELOC_PJ_CODE_HI16
2787 BFD_RELOC_PJ_CODE_LO16
2789 BFD_RELOC_PJ_CODE_DIR16
2791 BFD_RELOC_PJ_CODE_DIR32
2793 BFD_RELOC_PJ_CODE_REL16
2795 BFD_RELOC_PJ_CODE_REL32
2797 Picojava relocs. Not all of these appear in object files.
2808 BFD_RELOC_PPC_B16_BRTAKEN
2810 BFD_RELOC_PPC_B16_BRNTAKEN
2814 BFD_RELOC_PPC_BA16_BRTAKEN
2816 BFD_RELOC_PPC_BA16_BRNTAKEN
2820 BFD_RELOC_PPC_GLOB_DAT
2822 BFD_RELOC_PPC_JMP_SLOT
2824 BFD_RELOC_PPC_RELATIVE
2826 BFD_RELOC_PPC_LOCAL24PC
2828 BFD_RELOC_PPC_EMB_NADDR32
2830 BFD_RELOC_PPC_EMB_NADDR16
2832 BFD_RELOC_PPC_EMB_NADDR16_LO
2834 BFD_RELOC_PPC_EMB_NADDR16_HI
2836 BFD_RELOC_PPC_EMB_NADDR16_HA
2838 BFD_RELOC_PPC_EMB_SDAI16
2840 BFD_RELOC_PPC_EMB_SDA2I16
2842 BFD_RELOC_PPC_EMB_SDA2REL
2844 BFD_RELOC_PPC_EMB_SDA21
2846 BFD_RELOC_PPC_EMB_MRKREF
2848 BFD_RELOC_PPC_EMB_RELSEC16
2850 BFD_RELOC_PPC_EMB_RELST_LO
2852 BFD_RELOC_PPC_EMB_RELST_HI
2854 BFD_RELOC_PPC_EMB_RELST_HA
2856 BFD_RELOC_PPC_EMB_BIT_FLD
2858 BFD_RELOC_PPC_EMB_RELSDA
2860 BFD_RELOC_PPC_VLE_REL8
2862 BFD_RELOC_PPC_VLE_REL15
2864 BFD_RELOC_PPC_VLE_REL24
2866 BFD_RELOC_PPC_VLE_LO16A
2868 BFD_RELOC_PPC_VLE_LO16D
2870 BFD_RELOC_PPC_VLE_HI16A
2872 BFD_RELOC_PPC_VLE_HI16D
2874 BFD_RELOC_PPC_VLE_HA16A
2876 BFD_RELOC_PPC_VLE_HA16D
2878 BFD_RELOC_PPC_VLE_SDA21
2880 BFD_RELOC_PPC_VLE_SDA21_LO
2882 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2884 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2886 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2888 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2890 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2892 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2894 BFD_RELOC_PPC_REL16DX_HA
2896 BFD_RELOC_PPC64_HIGHER
2898 BFD_RELOC_PPC64_HIGHER_S
2900 BFD_RELOC_PPC64_HIGHEST
2902 BFD_RELOC_PPC64_HIGHEST_S
2904 BFD_RELOC_PPC64_TOC16_LO
2906 BFD_RELOC_PPC64_TOC16_HI
2908 BFD_RELOC_PPC64_TOC16_HA
2912 BFD_RELOC_PPC64_PLTGOT16
2914 BFD_RELOC_PPC64_PLTGOT16_LO
2916 BFD_RELOC_PPC64_PLTGOT16_HI
2918 BFD_RELOC_PPC64_PLTGOT16_HA
2920 BFD_RELOC_PPC64_ADDR16_DS
2922 BFD_RELOC_PPC64_ADDR16_LO_DS
2924 BFD_RELOC_PPC64_GOT16_DS
2926 BFD_RELOC_PPC64_GOT16_LO_DS
2928 BFD_RELOC_PPC64_PLT16_LO_DS
2930 BFD_RELOC_PPC64_SECTOFF_DS
2932 BFD_RELOC_PPC64_SECTOFF_LO_DS
2934 BFD_RELOC_PPC64_TOC16_DS
2936 BFD_RELOC_PPC64_TOC16_LO_DS
2938 BFD_RELOC_PPC64_PLTGOT16_DS
2940 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2942 BFD_RELOC_PPC64_ADDR16_HIGH
2944 BFD_RELOC_PPC64_ADDR16_HIGHA
2946 BFD_RELOC_PPC64_ADDR64_LOCAL
2948 BFD_RELOC_PPC64_ENTRY
2950 Power(rs6000) and PowerPC relocations.
2959 BFD_RELOC_PPC_DTPMOD
2961 BFD_RELOC_PPC_TPREL16
2963 BFD_RELOC_PPC_TPREL16_LO
2965 BFD_RELOC_PPC_TPREL16_HI
2967 BFD_RELOC_PPC_TPREL16_HA
2971 BFD_RELOC_PPC_DTPREL16
2973 BFD_RELOC_PPC_DTPREL16_LO
2975 BFD_RELOC_PPC_DTPREL16_HI
2977 BFD_RELOC_PPC_DTPREL16_HA
2979 BFD_RELOC_PPC_DTPREL
2981 BFD_RELOC_PPC_GOT_TLSGD16
2983 BFD_RELOC_PPC_GOT_TLSGD16_LO
2985 BFD_RELOC_PPC_GOT_TLSGD16_HI
2987 BFD_RELOC_PPC_GOT_TLSGD16_HA
2989 BFD_RELOC_PPC_GOT_TLSLD16
2991 BFD_RELOC_PPC_GOT_TLSLD16_LO
2993 BFD_RELOC_PPC_GOT_TLSLD16_HI
2995 BFD_RELOC_PPC_GOT_TLSLD16_HA
2997 BFD_RELOC_PPC_GOT_TPREL16
2999 BFD_RELOC_PPC_GOT_TPREL16_LO
3001 BFD_RELOC_PPC_GOT_TPREL16_HI
3003 BFD_RELOC_PPC_GOT_TPREL16_HA
3005 BFD_RELOC_PPC_GOT_DTPREL16
3007 BFD_RELOC_PPC_GOT_DTPREL16_LO
3009 BFD_RELOC_PPC_GOT_DTPREL16_HI
3011 BFD_RELOC_PPC_GOT_DTPREL16_HA
3013 BFD_RELOC_PPC64_TPREL16_DS
3015 BFD_RELOC_PPC64_TPREL16_LO_DS
3017 BFD_RELOC_PPC64_TPREL16_HIGHER
3019 BFD_RELOC_PPC64_TPREL16_HIGHERA
3021 BFD_RELOC_PPC64_TPREL16_HIGHEST
3023 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3025 BFD_RELOC_PPC64_DTPREL16_DS
3027 BFD_RELOC_PPC64_DTPREL16_LO_DS
3029 BFD_RELOC_PPC64_DTPREL16_HIGHER
3031 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3033 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3035 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3037 BFD_RELOC_PPC64_TPREL16_HIGH
3039 BFD_RELOC_PPC64_TPREL16_HIGHA
3041 BFD_RELOC_PPC64_DTPREL16_HIGH
3043 BFD_RELOC_PPC64_DTPREL16_HIGHA
3045 PowerPC and PowerPC64 thread-local storage relocations.
3050 IBM 370/390 relocations
3055 The type of reloc used to build a constructor table - at the moment
3056 probably a 32 bit wide absolute relocation, but the target can choose.
3057 It generally does map to one of the other relocation types.
3060 BFD_RELOC_ARM_PCREL_BRANCH
3062 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3063 not stored in the instruction.
3065 BFD_RELOC_ARM_PCREL_BLX
3067 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3068 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3069 field in the instruction.
3071 BFD_RELOC_THUMB_PCREL_BLX
3073 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3074 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3075 field in the instruction.
3077 BFD_RELOC_ARM_PCREL_CALL
3079 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3081 BFD_RELOC_ARM_PCREL_JUMP
3083 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3086 BFD_RELOC_THUMB_PCREL_BRANCH7
3088 BFD_RELOC_THUMB_PCREL_BRANCH9
3090 BFD_RELOC_THUMB_PCREL_BRANCH12
3092 BFD_RELOC_THUMB_PCREL_BRANCH20
3094 BFD_RELOC_THUMB_PCREL_BRANCH23
3096 BFD_RELOC_THUMB_PCREL_BRANCH25
3098 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3099 The lowest bit must be zero and is not stored in the instruction.
3100 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3101 "nn" one smaller in all cases. Note further that BRANCH23
3102 corresponds to R_ARM_THM_CALL.
3105 BFD_RELOC_ARM_OFFSET_IMM
3107 12-bit immediate offset, used in ARM-format ldr and str instructions.
3110 BFD_RELOC_ARM_THUMB_OFFSET
3112 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3115 BFD_RELOC_ARM_TARGET1
3117 Pc-relative or absolute relocation depending on target. Used for
3118 entries in .init_array sections.
3120 BFD_RELOC_ARM_ROSEGREL32
3122 Read-only segment base relative address.
3124 BFD_RELOC_ARM_SBREL32
3126 Data segment base relative address.
3128 BFD_RELOC_ARM_TARGET2
3130 This reloc is used for references to RTTI data from exception handling
3131 tables. The actual definition depends on the target. It may be a
3132 pc-relative or some form of GOT-indirect relocation.
3134 BFD_RELOC_ARM_PREL31
3136 31-bit PC relative address.
3142 BFD_RELOC_ARM_MOVW_PCREL
3144 BFD_RELOC_ARM_MOVT_PCREL
3146 BFD_RELOC_ARM_THUMB_MOVW
3148 BFD_RELOC_ARM_THUMB_MOVT
3150 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3152 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3154 Low and High halfword relocations for MOVW and MOVT instructions.
3157 BFD_RELOC_ARM_JUMP_SLOT
3159 BFD_RELOC_ARM_GLOB_DAT
3165 BFD_RELOC_ARM_RELATIVE
3167 BFD_RELOC_ARM_GOTOFF
3171 BFD_RELOC_ARM_GOT_PREL
3173 Relocations for setting up GOTs and PLTs for shared libraries.
3176 BFD_RELOC_ARM_TLS_GD32
3178 BFD_RELOC_ARM_TLS_LDO32
3180 BFD_RELOC_ARM_TLS_LDM32
3182 BFD_RELOC_ARM_TLS_DTPOFF32
3184 BFD_RELOC_ARM_TLS_DTPMOD32
3186 BFD_RELOC_ARM_TLS_TPOFF32
3188 BFD_RELOC_ARM_TLS_IE32
3190 BFD_RELOC_ARM_TLS_LE32
3192 BFD_RELOC_ARM_TLS_GOTDESC
3194 BFD_RELOC_ARM_TLS_CALL
3196 BFD_RELOC_ARM_THM_TLS_CALL
3198 BFD_RELOC_ARM_TLS_DESCSEQ
3200 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3202 BFD_RELOC_ARM_TLS_DESC
3204 ARM thread-local storage relocations.
3207 BFD_RELOC_ARM_ALU_PC_G0_NC
3209 BFD_RELOC_ARM_ALU_PC_G0
3211 BFD_RELOC_ARM_ALU_PC_G1_NC
3213 BFD_RELOC_ARM_ALU_PC_G1
3215 BFD_RELOC_ARM_ALU_PC_G2
3217 BFD_RELOC_ARM_LDR_PC_G0
3219 BFD_RELOC_ARM_LDR_PC_G1
3221 BFD_RELOC_ARM_LDR_PC_G2
3223 BFD_RELOC_ARM_LDRS_PC_G0
3225 BFD_RELOC_ARM_LDRS_PC_G1
3227 BFD_RELOC_ARM_LDRS_PC_G2
3229 BFD_RELOC_ARM_LDC_PC_G0
3231 BFD_RELOC_ARM_LDC_PC_G1
3233 BFD_RELOC_ARM_LDC_PC_G2
3235 BFD_RELOC_ARM_ALU_SB_G0_NC
3237 BFD_RELOC_ARM_ALU_SB_G0
3239 BFD_RELOC_ARM_ALU_SB_G1_NC
3241 BFD_RELOC_ARM_ALU_SB_G1
3243 BFD_RELOC_ARM_ALU_SB_G2
3245 BFD_RELOC_ARM_LDR_SB_G0
3247 BFD_RELOC_ARM_LDR_SB_G1
3249 BFD_RELOC_ARM_LDR_SB_G2
3251 BFD_RELOC_ARM_LDRS_SB_G0
3253 BFD_RELOC_ARM_LDRS_SB_G1
3255 BFD_RELOC_ARM_LDRS_SB_G2
3257 BFD_RELOC_ARM_LDC_SB_G0
3259 BFD_RELOC_ARM_LDC_SB_G1
3261 BFD_RELOC_ARM_LDC_SB_G2
3263 ARM group relocations.
3268 Annotation of BX instructions.
3271 BFD_RELOC_ARM_IRELATIVE
3273 ARM support for STT_GNU_IFUNC.
3276 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3278 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3280 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3282 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3284 Thumb1 relocations to support execute-only code.
3287 BFD_RELOC_ARM_IMMEDIATE
3289 BFD_RELOC_ARM_ADRL_IMMEDIATE
3291 BFD_RELOC_ARM_T32_IMMEDIATE
3293 BFD_RELOC_ARM_T32_ADD_IMM
3295 BFD_RELOC_ARM_T32_IMM12
3297 BFD_RELOC_ARM_T32_ADD_PC12
3299 BFD_RELOC_ARM_SHIFT_IMM
3309 BFD_RELOC_ARM_CP_OFF_IMM
3311 BFD_RELOC_ARM_CP_OFF_IMM_S2
3313 BFD_RELOC_ARM_T32_CP_OFF_IMM
3315 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3317 BFD_RELOC_ARM_ADR_IMM
3319 BFD_RELOC_ARM_LDR_IMM
3321 BFD_RELOC_ARM_LITERAL
3323 BFD_RELOC_ARM_IN_POOL
3325 BFD_RELOC_ARM_OFFSET_IMM8
3327 BFD_RELOC_ARM_T32_OFFSET_U8
3329 BFD_RELOC_ARM_T32_OFFSET_IMM
3331 BFD_RELOC_ARM_HWLITERAL
3333 BFD_RELOC_ARM_THUMB_ADD
3335 BFD_RELOC_ARM_THUMB_IMM
3337 BFD_RELOC_ARM_THUMB_SHIFT
3339 These relocs are only used within the ARM assembler. They are not
3340 (at present) written to any object files.
3343 BFD_RELOC_SH_PCDISP8BY2
3345 BFD_RELOC_SH_PCDISP12BY2
3353 BFD_RELOC_SH_DISP12BY2
3355 BFD_RELOC_SH_DISP12BY4
3357 BFD_RELOC_SH_DISP12BY8
3361 BFD_RELOC_SH_DISP20BY8
3365 BFD_RELOC_SH_IMM4BY2
3367 BFD_RELOC_SH_IMM4BY4
3371 BFD_RELOC_SH_IMM8BY2
3373 BFD_RELOC_SH_IMM8BY4
3375 BFD_RELOC_SH_PCRELIMM8BY2
3377 BFD_RELOC_SH_PCRELIMM8BY4
3379 BFD_RELOC_SH_SWITCH16
3381 BFD_RELOC_SH_SWITCH32
3395 BFD_RELOC_SH_LOOP_START
3397 BFD_RELOC_SH_LOOP_END
3401 BFD_RELOC_SH_GLOB_DAT
3403 BFD_RELOC_SH_JMP_SLOT
3405 BFD_RELOC_SH_RELATIVE
3409 BFD_RELOC_SH_GOT_LOW16
3411 BFD_RELOC_SH_GOT_MEDLOW16
3413 BFD_RELOC_SH_GOT_MEDHI16
3415 BFD_RELOC_SH_GOT_HI16
3417 BFD_RELOC_SH_GOTPLT_LOW16
3419 BFD_RELOC_SH_GOTPLT_MEDLOW16
3421 BFD_RELOC_SH_GOTPLT_MEDHI16
3423 BFD_RELOC_SH_GOTPLT_HI16
3425 BFD_RELOC_SH_PLT_LOW16
3427 BFD_RELOC_SH_PLT_MEDLOW16
3429 BFD_RELOC_SH_PLT_MEDHI16
3431 BFD_RELOC_SH_PLT_HI16
3433 BFD_RELOC_SH_GOTOFF_LOW16
3435 BFD_RELOC_SH_GOTOFF_MEDLOW16
3437 BFD_RELOC_SH_GOTOFF_MEDHI16
3439 BFD_RELOC_SH_GOTOFF_HI16
3441 BFD_RELOC_SH_GOTPC_LOW16
3443 BFD_RELOC_SH_GOTPC_MEDLOW16
3445 BFD_RELOC_SH_GOTPC_MEDHI16
3447 BFD_RELOC_SH_GOTPC_HI16
3451 BFD_RELOC_SH_GLOB_DAT64
3453 BFD_RELOC_SH_JMP_SLOT64
3455 BFD_RELOC_SH_RELATIVE64
3457 BFD_RELOC_SH_GOT10BY4
3459 BFD_RELOC_SH_GOT10BY8
3461 BFD_RELOC_SH_GOTPLT10BY4
3463 BFD_RELOC_SH_GOTPLT10BY8
3465 BFD_RELOC_SH_GOTPLT32
3467 BFD_RELOC_SH_SHMEDIA_CODE
3473 BFD_RELOC_SH_IMMS6BY32
3479 BFD_RELOC_SH_IMMS10BY2
3481 BFD_RELOC_SH_IMMS10BY4
3483 BFD_RELOC_SH_IMMS10BY8
3489 BFD_RELOC_SH_IMM_LOW16
3491 BFD_RELOC_SH_IMM_LOW16_PCREL
3493 BFD_RELOC_SH_IMM_MEDLOW16
3495 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3497 BFD_RELOC_SH_IMM_MEDHI16
3499 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3501 BFD_RELOC_SH_IMM_HI16
3503 BFD_RELOC_SH_IMM_HI16_PCREL
3507 BFD_RELOC_SH_TLS_GD_32
3509 BFD_RELOC_SH_TLS_LD_32
3511 BFD_RELOC_SH_TLS_LDO_32
3513 BFD_RELOC_SH_TLS_IE_32
3515 BFD_RELOC_SH_TLS_LE_32
3517 BFD_RELOC_SH_TLS_DTPMOD32
3519 BFD_RELOC_SH_TLS_DTPOFF32
3521 BFD_RELOC_SH_TLS_TPOFF32
3525 BFD_RELOC_SH_GOTOFF20
3527 BFD_RELOC_SH_GOTFUNCDESC
3529 BFD_RELOC_SH_GOTFUNCDESC20
3531 BFD_RELOC_SH_GOTOFFFUNCDESC
3533 BFD_RELOC_SH_GOTOFFFUNCDESC20
3535 BFD_RELOC_SH_FUNCDESC
3537 Renesas / SuperH SH relocs. Not all of these appear in object files.
3560 BFD_RELOC_ARC_SECTOFF
3562 BFD_RELOC_ARC_S21H_PCREL
3564 BFD_RELOC_ARC_S21W_PCREL
3566 BFD_RELOC_ARC_S25H_PCREL
3568 BFD_RELOC_ARC_S25W_PCREL
3572 BFD_RELOC_ARC_SDA_LDST
3574 BFD_RELOC_ARC_SDA_LDST1
3576 BFD_RELOC_ARC_SDA_LDST2
3578 BFD_RELOC_ARC_SDA16_LD
3580 BFD_RELOC_ARC_SDA16_LD1
3582 BFD_RELOC_ARC_SDA16_LD2
3584 BFD_RELOC_ARC_S13_PCREL
3590 BFD_RELOC_ARC_32_ME_S
3592 BFD_RELOC_ARC_N32_ME
3594 BFD_RELOC_ARC_SECTOFF_ME
3596 BFD_RELOC_ARC_SDA32_ME
3600 BFD_RELOC_AC_SECTOFF_U8
3602 BFD_RELOC_AC_SECTOFF_U8_1
3604 BFD_RELOC_AC_SECTOFF_U8_2
3606 BFD_RELOC_AC_SECTFOFF_S9
3608 BFD_RELOC_AC_SECTFOFF_S9_1
3610 BFD_RELOC_AC_SECTFOFF_S9_2
3612 BFD_RELOC_ARC_SECTOFF_ME_1
3614 BFD_RELOC_ARC_SECTOFF_ME_2
3616 BFD_RELOC_ARC_SECTOFF_1
3618 BFD_RELOC_ARC_SECTOFF_2
3620 BFD_RELOC_ARC_SDA16_ST2
3622 BFD_RELOC_ARC_32_PCREL
3628 BFD_RELOC_ARC_GOTPC32
3634 BFD_RELOC_ARC_GLOB_DAT
3636 BFD_RELOC_ARC_JMP_SLOT
3638 BFD_RELOC_ARC_RELATIVE
3640 BFD_RELOC_ARC_GOTOFF
3644 BFD_RELOC_ARC_S21W_PCREL_PLT
3646 BFD_RELOC_ARC_S25H_PCREL_PLT
3648 BFD_RELOC_ARC_TLS_DTPMOD
3650 BFD_RELOC_ARC_TLS_TPOFF
3652 BFD_RELOC_ARC_TLS_GD_GOT
3654 BFD_RELOC_ARC_TLS_GD_LD
3656 BFD_RELOC_ARC_TLS_GD_CALL
3658 BFD_RELOC_ARC_TLS_IE_GOT
3660 BFD_RELOC_ARC_TLS_DTPOFF
3662 BFD_RELOC_ARC_TLS_DTPOFF_S9
3664 BFD_RELOC_ARC_TLS_LE_S9
3666 BFD_RELOC_ARC_TLS_LE_32
3668 BFD_RELOC_ARC_S25W_PCREL_PLT
3670 BFD_RELOC_ARC_S21H_PCREL_PLT
3672 BFD_RELOC_ARC_NPS_CMEM16
3677 BFD_RELOC_BFIN_16_IMM
3679 ADI Blackfin 16 bit immediate absolute reloc.
3681 BFD_RELOC_BFIN_16_HIGH
3683 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3685 BFD_RELOC_BFIN_4_PCREL
3687 ADI Blackfin 'a' part of LSETUP.
3689 BFD_RELOC_BFIN_5_PCREL
3693 BFD_RELOC_BFIN_16_LOW
3695 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3697 BFD_RELOC_BFIN_10_PCREL
3701 BFD_RELOC_BFIN_11_PCREL
3703 ADI Blackfin 'b' part of LSETUP.
3705 BFD_RELOC_BFIN_12_PCREL_JUMP
3709 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3711 ADI Blackfin Short jump, pcrel.
3713 BFD_RELOC_BFIN_24_PCREL_CALL_X
3715 ADI Blackfin Call.x not implemented.
3717 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3719 ADI Blackfin Long Jump pcrel.
3721 BFD_RELOC_BFIN_GOT17M4
3723 BFD_RELOC_BFIN_GOTHI
3725 BFD_RELOC_BFIN_GOTLO
3727 BFD_RELOC_BFIN_FUNCDESC
3729 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3731 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3733 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3735 BFD_RELOC_BFIN_FUNCDESC_VALUE
3737 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3739 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3741 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3743 BFD_RELOC_BFIN_GOTOFF17M4
3745 BFD_RELOC_BFIN_GOTOFFHI
3747 BFD_RELOC_BFIN_GOTOFFLO
3749 ADI Blackfin FD-PIC relocations.
3753 ADI Blackfin GOT relocation.
3755 BFD_RELOC_BFIN_PLTPC
3757 ADI Blackfin PLTPC relocation.
3759 BFD_ARELOC_BFIN_PUSH
3761 ADI Blackfin arithmetic relocation.
3763 BFD_ARELOC_BFIN_CONST
3765 ADI Blackfin arithmetic relocation.
3769 ADI Blackfin arithmetic relocation.
3773 ADI Blackfin arithmetic relocation.
3775 BFD_ARELOC_BFIN_MULT
3777 ADI Blackfin arithmetic relocation.
3781 ADI Blackfin arithmetic relocation.
3785 ADI Blackfin arithmetic relocation.
3787 BFD_ARELOC_BFIN_LSHIFT
3789 ADI Blackfin arithmetic relocation.
3791 BFD_ARELOC_BFIN_RSHIFT
3793 ADI Blackfin arithmetic relocation.
3797 ADI Blackfin arithmetic relocation.
3801 ADI Blackfin arithmetic relocation.
3805 ADI Blackfin arithmetic relocation.
3807 BFD_ARELOC_BFIN_LAND
3809 ADI Blackfin arithmetic relocation.
3813 ADI Blackfin arithmetic relocation.
3817 ADI Blackfin arithmetic relocation.
3821 ADI Blackfin arithmetic relocation.
3823 BFD_ARELOC_BFIN_COMP
3825 ADI Blackfin arithmetic relocation.
3827 BFD_ARELOC_BFIN_PAGE
3829 ADI Blackfin arithmetic relocation.
3831 BFD_ARELOC_BFIN_HWPAGE
3833 ADI Blackfin arithmetic relocation.
3835 BFD_ARELOC_BFIN_ADDR
3837 ADI Blackfin arithmetic relocation.
3840 BFD_RELOC_D10V_10_PCREL_R
3842 Mitsubishi D10V relocs.
3843 This is a 10-bit reloc with the right 2 bits
3846 BFD_RELOC_D10V_10_PCREL_L
3848 Mitsubishi D10V relocs.
3849 This is a 10-bit reloc with the right 2 bits
3850 assumed to be 0. This is the same as the previous reloc
3851 except it is in the left container, i.e.,
3852 shifted left 15 bits.
3856 This is an 18-bit reloc with the right 2 bits
3859 BFD_RELOC_D10V_18_PCREL
3861 This is an 18-bit reloc with the right 2 bits
3867 Mitsubishi D30V relocs.
3868 This is a 6-bit absolute reloc.
3870 BFD_RELOC_D30V_9_PCREL
3872 This is a 6-bit pc-relative reloc with
3873 the right 3 bits assumed to be 0.
3875 BFD_RELOC_D30V_9_PCREL_R
3877 This is a 6-bit pc-relative reloc with
3878 the right 3 bits assumed to be 0. Same
3879 as the previous reloc but on the right side
3884 This is a 12-bit absolute reloc with the
3885 right 3 bitsassumed to be 0.
3887 BFD_RELOC_D30V_15_PCREL
3889 This is a 12-bit pc-relative reloc with
3890 the right 3 bits assumed to be 0.
3892 BFD_RELOC_D30V_15_PCREL_R
3894 This is a 12-bit pc-relative reloc with
3895 the right 3 bits assumed to be 0. Same
3896 as the previous reloc but on the right side
3901 This is an 18-bit absolute reloc with
3902 the right 3 bits assumed to be 0.
3904 BFD_RELOC_D30V_21_PCREL
3906 This is an 18-bit pc-relative reloc with
3907 the right 3 bits assumed to be 0.
3909 BFD_RELOC_D30V_21_PCREL_R
3911 This is an 18-bit pc-relative reloc with
3912 the right 3 bits assumed to be 0. Same
3913 as the previous reloc but on the right side
3918 This is a 32-bit absolute reloc.
3920 BFD_RELOC_D30V_32_PCREL
3922 This is a 32-bit pc-relative reloc.
3925 BFD_RELOC_DLX_HI16_S
3940 BFD_RELOC_M32C_RL_JUMP
3942 BFD_RELOC_M32C_RL_1ADDR
3944 BFD_RELOC_M32C_RL_2ADDR
3946 Renesas M16C/M32C Relocations.
3951 Renesas M32R (formerly Mitsubishi M32R) relocs.
3952 This is a 24 bit absolute address.
3954 BFD_RELOC_M32R_10_PCREL
3956 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3958 BFD_RELOC_M32R_18_PCREL
3960 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3962 BFD_RELOC_M32R_26_PCREL
3964 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3966 BFD_RELOC_M32R_HI16_ULO
3968 This is a 16-bit reloc containing the high 16 bits of an address
3969 used when the lower 16 bits are treated as unsigned.
3971 BFD_RELOC_M32R_HI16_SLO
3973 This is a 16-bit reloc containing the high 16 bits of an address
3974 used when the lower 16 bits are treated as signed.
3978 This is a 16-bit reloc containing the lower 16 bits of an address.
3980 BFD_RELOC_M32R_SDA16
3982 This is a 16-bit reloc containing the small data area offset for use in
3983 add3, load, and store instructions.
3985 BFD_RELOC_M32R_GOT24
3987 BFD_RELOC_M32R_26_PLTREL
3991 BFD_RELOC_M32R_GLOB_DAT
3993 BFD_RELOC_M32R_JMP_SLOT
3995 BFD_RELOC_M32R_RELATIVE
3997 BFD_RELOC_M32R_GOTOFF
3999 BFD_RELOC_M32R_GOTOFF_HI_ULO
4001 BFD_RELOC_M32R_GOTOFF_HI_SLO
4003 BFD_RELOC_M32R_GOTOFF_LO
4005 BFD_RELOC_M32R_GOTPC24
4007 BFD_RELOC_M32R_GOT16_HI_ULO
4009 BFD_RELOC_M32R_GOT16_HI_SLO
4011 BFD_RELOC_M32R_GOT16_LO
4013 BFD_RELOC_M32R_GOTPC_HI_ULO
4015 BFD_RELOC_M32R_GOTPC_HI_SLO
4017 BFD_RELOC_M32R_GOTPC_LO
4026 This is a 20 bit absolute address.
4028 BFD_RELOC_NDS32_9_PCREL
4030 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4032 BFD_RELOC_NDS32_WORD_9_PCREL
4034 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4036 BFD_RELOC_NDS32_15_PCREL
4038 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4040 BFD_RELOC_NDS32_17_PCREL
4042 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4044 BFD_RELOC_NDS32_25_PCREL
4046 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4048 BFD_RELOC_NDS32_HI20
4050 This is a 20-bit reloc containing the high 20 bits of an address
4051 used with the lower 12 bits
4053 BFD_RELOC_NDS32_LO12S3
4055 This is a 12-bit reloc containing the lower 12 bits of an address
4056 then shift right by 3. This is used with ldi,sdi...
4058 BFD_RELOC_NDS32_LO12S2
4060 This is a 12-bit reloc containing the lower 12 bits of an address
4061 then shift left by 2. This is used with lwi,swi...
4063 BFD_RELOC_NDS32_LO12S1
4065 This is a 12-bit reloc containing the lower 12 bits of an address
4066 then shift left by 1. This is used with lhi,shi...
4068 BFD_RELOC_NDS32_LO12S0
4070 This is a 12-bit reloc containing the lower 12 bits of an address
4071 then shift left by 0. This is used with lbisbi...
4073 BFD_RELOC_NDS32_LO12S0_ORI
4075 This is a 12-bit reloc containing the lower 12 bits of an address
4076 then shift left by 0. This is only used with branch relaxations
4078 BFD_RELOC_NDS32_SDA15S3
4080 This is a 15-bit reloc containing the small data area 18-bit signed offset
4081 and shift left by 3 for use in ldi, sdi...
4083 BFD_RELOC_NDS32_SDA15S2
4085 This is a 15-bit reloc containing the small data area 17-bit signed offset
4086 and shift left by 2 for use in lwi, swi...
4088 BFD_RELOC_NDS32_SDA15S1
4090 This is a 15-bit reloc containing the small data area 16-bit signed offset
4091 and shift left by 1 for use in lhi, shi...
4093 BFD_RELOC_NDS32_SDA15S0
4095 This is a 15-bit reloc containing the small data area 15-bit signed offset
4096 and shift left by 0 for use in lbi, sbi...
4098 BFD_RELOC_NDS32_SDA16S3
4100 This is a 16-bit reloc containing the small data area 16-bit signed offset
4103 BFD_RELOC_NDS32_SDA17S2
4105 This is a 17-bit reloc containing the small data area 17-bit signed offset
4106 and shift left by 2 for use in lwi.gp, swi.gp...
4108 BFD_RELOC_NDS32_SDA18S1
4110 This is a 18-bit reloc containing the small data area 18-bit signed offset
4111 and shift left by 1 for use in lhi.gp, shi.gp...
4113 BFD_RELOC_NDS32_SDA19S0
4115 This is a 19-bit reloc containing the small data area 19-bit signed offset
4116 and shift left by 0 for use in lbi.gp, sbi.gp...
4118 BFD_RELOC_NDS32_GOT20
4120 BFD_RELOC_NDS32_9_PLTREL
4122 BFD_RELOC_NDS32_25_PLTREL
4124 BFD_RELOC_NDS32_COPY
4126 BFD_RELOC_NDS32_GLOB_DAT
4128 BFD_RELOC_NDS32_JMP_SLOT
4130 BFD_RELOC_NDS32_RELATIVE
4132 BFD_RELOC_NDS32_GOTOFF
4134 BFD_RELOC_NDS32_GOTOFF_HI20
4136 BFD_RELOC_NDS32_GOTOFF_LO12
4138 BFD_RELOC_NDS32_GOTPC20
4140 BFD_RELOC_NDS32_GOT_HI20
4142 BFD_RELOC_NDS32_GOT_LO12
4144 BFD_RELOC_NDS32_GOTPC_HI20
4146 BFD_RELOC_NDS32_GOTPC_LO12
4150 BFD_RELOC_NDS32_INSN16
4152 BFD_RELOC_NDS32_LABEL
4154 BFD_RELOC_NDS32_LONGCALL1
4156 BFD_RELOC_NDS32_LONGCALL2
4158 BFD_RELOC_NDS32_LONGCALL3
4160 BFD_RELOC_NDS32_LONGJUMP1
4162 BFD_RELOC_NDS32_LONGJUMP2
4164 BFD_RELOC_NDS32_LONGJUMP3
4166 BFD_RELOC_NDS32_LOADSTORE
4168 BFD_RELOC_NDS32_9_FIXED
4170 BFD_RELOC_NDS32_15_FIXED
4172 BFD_RELOC_NDS32_17_FIXED
4174 BFD_RELOC_NDS32_25_FIXED
4176 BFD_RELOC_NDS32_LONGCALL4
4178 BFD_RELOC_NDS32_LONGCALL5
4180 BFD_RELOC_NDS32_LONGCALL6
4182 BFD_RELOC_NDS32_LONGJUMP4
4184 BFD_RELOC_NDS32_LONGJUMP5
4186 BFD_RELOC_NDS32_LONGJUMP6
4188 BFD_RELOC_NDS32_LONGJUMP7
4192 BFD_RELOC_NDS32_PLTREL_HI20
4194 BFD_RELOC_NDS32_PLTREL_LO12
4196 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4198 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4202 BFD_RELOC_NDS32_SDA12S2_DP
4204 BFD_RELOC_NDS32_SDA12S2_SP
4206 BFD_RELOC_NDS32_LO12S2_DP
4208 BFD_RELOC_NDS32_LO12S2_SP
4212 BFD_RELOC_NDS32_DWARF2_OP1
4214 BFD_RELOC_NDS32_DWARF2_OP2
4216 BFD_RELOC_NDS32_DWARF2_LEB
4218 for dwarf2 debug_line.
4220 BFD_RELOC_NDS32_UPDATE_TA
4222 for eliminate 16-bit instructions
4224 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4226 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4228 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4230 BFD_RELOC_NDS32_GOT_LO15
4232 BFD_RELOC_NDS32_GOT_LO19
4234 BFD_RELOC_NDS32_GOTOFF_LO15
4236 BFD_RELOC_NDS32_GOTOFF_LO19
4238 BFD_RELOC_NDS32_GOT15S2
4240 BFD_RELOC_NDS32_GOT17S2
4242 for PIC object relaxation
4247 This is a 5 bit absolute address.
4249 BFD_RELOC_NDS32_10_UPCREL
4251 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4253 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4255 If fp were omitted, fp can used as another gp.
4257 BFD_RELOC_NDS32_RELAX_ENTRY
4259 BFD_RELOC_NDS32_GOT_SUFF
4261 BFD_RELOC_NDS32_GOTOFF_SUFF
4263 BFD_RELOC_NDS32_PLT_GOT_SUFF
4265 BFD_RELOC_NDS32_MULCALL_SUFF
4269 BFD_RELOC_NDS32_PTR_COUNT
4271 BFD_RELOC_NDS32_PTR_RESOLVED
4273 BFD_RELOC_NDS32_PLTBLOCK
4275 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4277 BFD_RELOC_NDS32_RELAX_REGION_END
4279 BFD_RELOC_NDS32_MINUEND
4281 BFD_RELOC_NDS32_SUBTRAHEND
4283 BFD_RELOC_NDS32_DIFF8
4285 BFD_RELOC_NDS32_DIFF16
4287 BFD_RELOC_NDS32_DIFF32
4289 BFD_RELOC_NDS32_DIFF_ULEB128
4291 BFD_RELOC_NDS32_EMPTY
4293 relaxation relative relocation types
4295 BFD_RELOC_NDS32_25_ABS
4297 This is a 25 bit absolute address.
4299 BFD_RELOC_NDS32_DATA
4301 BFD_RELOC_NDS32_TRAN
4303 BFD_RELOC_NDS32_17IFC_PCREL
4305 BFD_RELOC_NDS32_10IFCU_PCREL
4307 For ex9 and ifc using.
4309 BFD_RELOC_NDS32_TPOFF
4311 BFD_RELOC_NDS32_TLS_LE_HI20
4313 BFD_RELOC_NDS32_TLS_LE_LO12
4315 BFD_RELOC_NDS32_TLS_LE_ADD
4317 BFD_RELOC_NDS32_TLS_LE_LS
4319 BFD_RELOC_NDS32_GOTTPOFF
4321 BFD_RELOC_NDS32_TLS_IE_HI20
4323 BFD_RELOC_NDS32_TLS_IE_LO12S2
4325 BFD_RELOC_NDS32_TLS_TPOFF
4327 BFD_RELOC_NDS32_TLS_LE_20
4329 BFD_RELOC_NDS32_TLS_LE_15S0
4331 BFD_RELOC_NDS32_TLS_LE_15S1
4333 BFD_RELOC_NDS32_TLS_LE_15S2
4339 BFD_RELOC_V850_9_PCREL
4341 This is a 9-bit reloc
4343 BFD_RELOC_V850_22_PCREL
4345 This is a 22-bit reloc
4348 BFD_RELOC_V850_SDA_16_16_OFFSET
4350 This is a 16 bit offset from the short data area pointer.
4352 BFD_RELOC_V850_SDA_15_16_OFFSET
4354 This is a 16 bit offset (of which only 15 bits are used) from the
4355 short data area pointer.
4357 BFD_RELOC_V850_ZDA_16_16_OFFSET
4359 This is a 16 bit offset from the zero data area pointer.
4361 BFD_RELOC_V850_ZDA_15_16_OFFSET
4363 This is a 16 bit offset (of which only 15 bits are used) from the
4364 zero data area pointer.
4366 BFD_RELOC_V850_TDA_6_8_OFFSET
4368 This is an 8 bit offset (of which only 6 bits are used) from the
4369 tiny data area pointer.
4371 BFD_RELOC_V850_TDA_7_8_OFFSET
4373 This is an 8bit offset (of which only 7 bits are used) from the tiny
4376 BFD_RELOC_V850_TDA_7_7_OFFSET
4378 This is a 7 bit offset from the tiny data area pointer.
4380 BFD_RELOC_V850_TDA_16_16_OFFSET
4382 This is a 16 bit offset from the tiny data area pointer.
4385 BFD_RELOC_V850_TDA_4_5_OFFSET
4387 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4390 BFD_RELOC_V850_TDA_4_4_OFFSET
4392 This is a 4 bit offset from the tiny data area pointer.
4394 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4396 This is a 16 bit offset from the short data area pointer, with the
4397 bits placed non-contiguously in the instruction.
4399 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4401 This is a 16 bit offset from the zero data area pointer, with the
4402 bits placed non-contiguously in the instruction.
4404 BFD_RELOC_V850_CALLT_6_7_OFFSET
4406 This is a 6 bit offset from the call table base pointer.
4408 BFD_RELOC_V850_CALLT_16_16_OFFSET
4410 This is a 16 bit offset from the call table base pointer.
4412 BFD_RELOC_V850_LONGCALL
4414 Used for relaxing indirect function calls.
4416 BFD_RELOC_V850_LONGJUMP
4418 Used for relaxing indirect jumps.
4420 BFD_RELOC_V850_ALIGN
4422 Used to maintain alignment whilst relaxing.
4424 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4426 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4429 BFD_RELOC_V850_16_PCREL
4431 This is a 16-bit reloc.
4433 BFD_RELOC_V850_17_PCREL
4435 This is a 17-bit reloc.
4439 This is a 23-bit reloc.
4441 BFD_RELOC_V850_32_PCREL
4443 This is a 32-bit reloc.
4445 BFD_RELOC_V850_32_ABS
4447 This is a 32-bit reloc.
4449 BFD_RELOC_V850_16_SPLIT_OFFSET
4451 This is a 16-bit reloc.
4453 BFD_RELOC_V850_16_S1
4455 This is a 16-bit reloc.
4457 BFD_RELOC_V850_LO16_S1
4459 Low 16 bits. 16 bit shifted by 1.
4461 BFD_RELOC_V850_CALLT_15_16_OFFSET
4463 This is a 16 bit offset from the call table base pointer.
4465 BFD_RELOC_V850_32_GOTPCREL
4469 BFD_RELOC_V850_16_GOT
4473 BFD_RELOC_V850_32_GOT
4477 BFD_RELOC_V850_22_PLT_PCREL
4481 BFD_RELOC_V850_32_PLT_PCREL
4489 BFD_RELOC_V850_GLOB_DAT
4493 BFD_RELOC_V850_JMP_SLOT
4497 BFD_RELOC_V850_RELATIVE
4501 BFD_RELOC_V850_16_GOTOFF
4505 BFD_RELOC_V850_32_GOTOFF
4520 This is a 8bit DP reloc for the tms320c30, where the most
4521 significant 8 bits of a 24 bit word are placed into the least
4522 significant 8 bits of the opcode.
4525 BFD_RELOC_TIC54X_PARTLS7
4527 This is a 7bit reloc for the tms320c54x, where the least
4528 significant 7 bits of a 16 bit word are placed into the least
4529 significant 7 bits of the opcode.
4532 BFD_RELOC_TIC54X_PARTMS9
4534 This is a 9bit DP reloc for the tms320c54x, where the most
4535 significant 9 bits of a 16 bit word are placed into the least
4536 significant 9 bits of the opcode.
4541 This is an extended address 23-bit reloc for the tms320c54x.
4544 BFD_RELOC_TIC54X_16_OF_23
4546 This is a 16-bit reloc for the tms320c54x, where the least
4547 significant 16 bits of a 23-bit extended address are placed into
4551 BFD_RELOC_TIC54X_MS7_OF_23
4553 This is a reloc for the tms320c54x, where the most
4554 significant 7 bits of a 23-bit extended address are placed into
4558 BFD_RELOC_C6000_PCR_S21
4560 BFD_RELOC_C6000_PCR_S12
4562 BFD_RELOC_C6000_PCR_S10
4564 BFD_RELOC_C6000_PCR_S7
4566 BFD_RELOC_C6000_ABS_S16
4568 BFD_RELOC_C6000_ABS_L16
4570 BFD_RELOC_C6000_ABS_H16
4572 BFD_RELOC_C6000_SBR_U15_B
4574 BFD_RELOC_C6000_SBR_U15_H
4576 BFD_RELOC_C6000_SBR_U15_W
4578 BFD_RELOC_C6000_SBR_S16
4580 BFD_RELOC_C6000_SBR_L16_B
4582 BFD_RELOC_C6000_SBR_L16_H
4584 BFD_RELOC_C6000_SBR_L16_W
4586 BFD_RELOC_C6000_SBR_H16_B
4588 BFD_RELOC_C6000_SBR_H16_H
4590 BFD_RELOC_C6000_SBR_H16_W
4592 BFD_RELOC_C6000_SBR_GOT_U15_W
4594 BFD_RELOC_C6000_SBR_GOT_L16_W
4596 BFD_RELOC_C6000_SBR_GOT_H16_W
4598 BFD_RELOC_C6000_DSBT_INDEX
4600 BFD_RELOC_C6000_PREL31
4602 BFD_RELOC_C6000_COPY
4604 BFD_RELOC_C6000_JUMP_SLOT
4606 BFD_RELOC_C6000_EHTYPE
4608 BFD_RELOC_C6000_PCR_H16
4610 BFD_RELOC_C6000_PCR_L16
4612 BFD_RELOC_C6000_ALIGN
4614 BFD_RELOC_C6000_FPHEAD
4616 BFD_RELOC_C6000_NOCMP
4618 TMS320C6000 relocations.
4623 This is a 48 bit reloc for the FR30 that stores 32 bits.
4627 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4630 BFD_RELOC_FR30_6_IN_4
4632 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4635 BFD_RELOC_FR30_8_IN_8
4637 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4640 BFD_RELOC_FR30_9_IN_8
4642 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4645 BFD_RELOC_FR30_10_IN_8
4647 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4650 BFD_RELOC_FR30_9_PCREL
4652 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4653 short offset into 8 bits.
4655 BFD_RELOC_FR30_12_PCREL
4657 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4658 short offset into 11 bits.
4661 BFD_RELOC_MCORE_PCREL_IMM8BY4
4663 BFD_RELOC_MCORE_PCREL_IMM11BY2
4665 BFD_RELOC_MCORE_PCREL_IMM4BY2
4667 BFD_RELOC_MCORE_PCREL_32
4669 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4673 Motorola Mcore relocations.
4682 BFD_RELOC_MEP_PCREL8A2
4684 BFD_RELOC_MEP_PCREL12A2
4686 BFD_RELOC_MEP_PCREL17A2
4688 BFD_RELOC_MEP_PCREL24A2
4690 BFD_RELOC_MEP_PCABS24A2
4702 BFD_RELOC_MEP_TPREL7
4704 BFD_RELOC_MEP_TPREL7A2
4706 BFD_RELOC_MEP_TPREL7A4
4708 BFD_RELOC_MEP_UIMM24
4710 BFD_RELOC_MEP_ADDR24A4
4712 BFD_RELOC_MEP_GNU_VTINHERIT
4714 BFD_RELOC_MEP_GNU_VTENTRY
4716 Toshiba Media Processor Relocations.
4720 BFD_RELOC_METAG_HIADDR16
4722 BFD_RELOC_METAG_LOADDR16
4724 BFD_RELOC_METAG_RELBRANCH
4726 BFD_RELOC_METAG_GETSETOFF
4728 BFD_RELOC_METAG_HIOG
4730 BFD_RELOC_METAG_LOOG
4732 BFD_RELOC_METAG_REL8
4734 BFD_RELOC_METAG_REL16
4736 BFD_RELOC_METAG_HI16_GOTOFF
4738 BFD_RELOC_METAG_LO16_GOTOFF
4740 BFD_RELOC_METAG_GETSET_GOTOFF
4742 BFD_RELOC_METAG_GETSET_GOT
4744 BFD_RELOC_METAG_HI16_GOTPC
4746 BFD_RELOC_METAG_LO16_GOTPC
4748 BFD_RELOC_METAG_HI16_PLT
4750 BFD_RELOC_METAG_LO16_PLT
4752 BFD_RELOC_METAG_RELBRANCH_PLT
4754 BFD_RELOC_METAG_GOTOFF
4758 BFD_RELOC_METAG_COPY
4760 BFD_RELOC_METAG_JMP_SLOT
4762 BFD_RELOC_METAG_RELATIVE
4764 BFD_RELOC_METAG_GLOB_DAT
4766 BFD_RELOC_METAG_TLS_GD
4768 BFD_RELOC_METAG_TLS_LDM
4770 BFD_RELOC_METAG_TLS_LDO_HI16
4772 BFD_RELOC_METAG_TLS_LDO_LO16
4774 BFD_RELOC_METAG_TLS_LDO
4776 BFD_RELOC_METAG_TLS_IE
4778 BFD_RELOC_METAG_TLS_IENONPIC
4780 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4782 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4784 BFD_RELOC_METAG_TLS_TPOFF
4786 BFD_RELOC_METAG_TLS_DTPMOD
4788 BFD_RELOC_METAG_TLS_DTPOFF
4790 BFD_RELOC_METAG_TLS_LE
4792 BFD_RELOC_METAG_TLS_LE_HI16
4794 BFD_RELOC_METAG_TLS_LE_LO16
4796 Imagination Technologies Meta relocations.
4801 BFD_RELOC_MMIX_GETA_1
4803 BFD_RELOC_MMIX_GETA_2
4805 BFD_RELOC_MMIX_GETA_3
4807 These are relocations for the GETA instruction.
4809 BFD_RELOC_MMIX_CBRANCH
4811 BFD_RELOC_MMIX_CBRANCH_J
4813 BFD_RELOC_MMIX_CBRANCH_1
4815 BFD_RELOC_MMIX_CBRANCH_2
4817 BFD_RELOC_MMIX_CBRANCH_3
4819 These are relocations for a conditional branch instruction.
4821 BFD_RELOC_MMIX_PUSHJ
4823 BFD_RELOC_MMIX_PUSHJ_1
4825 BFD_RELOC_MMIX_PUSHJ_2
4827 BFD_RELOC_MMIX_PUSHJ_3
4829 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4831 These are relocations for the PUSHJ instruction.
4835 BFD_RELOC_MMIX_JMP_1
4837 BFD_RELOC_MMIX_JMP_2
4839 BFD_RELOC_MMIX_JMP_3
4841 These are relocations for the JMP instruction.
4843 BFD_RELOC_MMIX_ADDR19
4845 This is a relocation for a relative address as in a GETA instruction or
4848 BFD_RELOC_MMIX_ADDR27
4850 This is a relocation for a relative address as in a JMP instruction.
4852 BFD_RELOC_MMIX_REG_OR_BYTE
4854 This is a relocation for an instruction field that may be a general
4855 register or a value 0..255.
4859 This is a relocation for an instruction field that may be a general
4862 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4864 This is a relocation for two instruction fields holding a register and
4865 an offset, the equivalent of the relocation.
4867 BFD_RELOC_MMIX_LOCAL
4869 This relocation is an assertion that the expression is not allocated as
4870 a global register. It does not modify contents.
4873 BFD_RELOC_AVR_7_PCREL
4875 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4876 short offset into 7 bits.
4878 BFD_RELOC_AVR_13_PCREL
4880 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4881 short offset into 12 bits.
4885 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4886 program memory address) into 16 bits.
4888 BFD_RELOC_AVR_LO8_LDI
4890 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4891 data memory address) into 8 bit immediate value of LDI insn.
4893 BFD_RELOC_AVR_HI8_LDI
4895 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4896 of data memory address) into 8 bit immediate value of LDI insn.
4898 BFD_RELOC_AVR_HH8_LDI
4900 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4901 of program memory address) into 8 bit immediate value of LDI insn.
4903 BFD_RELOC_AVR_MS8_LDI
4905 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4906 of 32 bit value) into 8 bit immediate value of LDI insn.
4908 BFD_RELOC_AVR_LO8_LDI_NEG
4910 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4911 (usually data memory address) into 8 bit immediate value of SUBI insn.
4913 BFD_RELOC_AVR_HI8_LDI_NEG
4915 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4916 (high 8 bit of data memory address) into 8 bit immediate value of
4919 BFD_RELOC_AVR_HH8_LDI_NEG
4921 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4922 (most high 8 bit of program memory address) into 8 bit immediate value
4923 of LDI or SUBI insn.
4925 BFD_RELOC_AVR_MS8_LDI_NEG
4927 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4928 of 32 bit value) into 8 bit immediate value of LDI insn.
4930 BFD_RELOC_AVR_LO8_LDI_PM
4932 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4933 command address) into 8 bit immediate value of LDI insn.
4935 BFD_RELOC_AVR_LO8_LDI_GS
4937 This is a 16 bit reloc for the AVR that stores 8 bit value
4938 (command address) into 8 bit immediate value of LDI insn. If the address
4939 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4942 BFD_RELOC_AVR_HI8_LDI_PM
4944 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4945 of command address) into 8 bit immediate value of LDI insn.
4947 BFD_RELOC_AVR_HI8_LDI_GS
4949 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4950 of command address) into 8 bit immediate value of LDI insn. If the address
4951 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4954 BFD_RELOC_AVR_HH8_LDI_PM
4956 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4957 of command address) into 8 bit immediate value of LDI insn.
4959 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4961 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4962 (usually command address) into 8 bit immediate value of SUBI insn.
4964 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4966 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4967 (high 8 bit of 16 bit command address) into 8 bit immediate value
4970 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4972 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4973 (high 6 bit of 22 bit command address) into 8 bit immediate
4978 This is a 32 bit reloc for the AVR that stores 23 bit value
4983 This is a 16 bit reloc for the AVR that stores all needed bits
4984 for absolute addressing with ldi with overflow check to linktime
4988 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4991 BFD_RELOC_AVR_6_ADIW
4993 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4998 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4999 in .byte lo8(symbol)
5003 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5004 in .byte hi8(symbol)
5008 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5009 in .byte hlo8(symbol)
5013 BFD_RELOC_AVR_DIFF16
5015 BFD_RELOC_AVR_DIFF32
5017 AVR relocations to mark the difference of two local symbols.
5018 These are only needed to support linker relaxation and can be ignored
5019 when not relaxing. The field is set to the value of the difference
5020 assuming no relaxation. The relocation encodes the position of the
5021 second symbol so the linker can determine whether to adjust the field
5024 BFD_RELOC_AVR_LDS_STS_16
5026 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5027 lds and sts instructions supported only tiny core.
5031 This is a 6 bit reloc for the AVR that stores an I/O register
5032 number for the IN and OUT instructions
5036 This is a 5 bit reloc for the AVR that stores an I/O register
5037 number for the SBIC, SBIS, SBI and CBI instructions
5041 BFD_RELOC_RL78_NEG16
5043 BFD_RELOC_RL78_NEG24
5045 BFD_RELOC_RL78_NEG32
5047 BFD_RELOC_RL78_16_OP
5049 BFD_RELOC_RL78_24_OP
5051 BFD_RELOC_RL78_32_OP
5059 BFD_RELOC_RL78_DIR3U_PCREL
5063 BFD_RELOC_RL78_GPRELB
5065 BFD_RELOC_RL78_GPRELW
5067 BFD_RELOC_RL78_GPRELL
5071 BFD_RELOC_RL78_OP_SUBTRACT
5073 BFD_RELOC_RL78_OP_NEG
5075 BFD_RELOC_RL78_OP_AND
5077 BFD_RELOC_RL78_OP_SHRA
5081 BFD_RELOC_RL78_ABS16
5083 BFD_RELOC_RL78_ABS16_REV
5085 BFD_RELOC_RL78_ABS32
5087 BFD_RELOC_RL78_ABS32_REV
5089 BFD_RELOC_RL78_ABS16U
5091 BFD_RELOC_RL78_ABS16UW
5093 BFD_RELOC_RL78_ABS16UL
5095 BFD_RELOC_RL78_RELAX
5105 BFD_RELOC_RL78_SADDR
5107 Renesas RL78 Relocations.
5130 BFD_RELOC_RX_DIR3U_PCREL
5142 BFD_RELOC_RX_OP_SUBTRACT
5150 BFD_RELOC_RX_ABS16_REV
5154 BFD_RELOC_RX_ABS32_REV
5158 BFD_RELOC_RX_ABS16UW
5160 BFD_RELOC_RX_ABS16UL
5164 Renesas RX Relocations.
5177 32 bit PC relative PLT address.
5181 Copy symbol at runtime.
5183 BFD_RELOC_390_GLOB_DAT
5187 BFD_RELOC_390_JMP_SLOT
5191 BFD_RELOC_390_RELATIVE
5193 Adjust by program base.
5197 32 bit PC relative offset to GOT.
5203 BFD_RELOC_390_PC12DBL
5205 PC relative 12 bit shifted by 1.
5207 BFD_RELOC_390_PLT12DBL
5209 12 bit PC rel. PLT shifted by 1.
5211 BFD_RELOC_390_PC16DBL
5213 PC relative 16 bit shifted by 1.
5215 BFD_RELOC_390_PLT16DBL
5217 16 bit PC rel. PLT shifted by 1.
5219 BFD_RELOC_390_PC24DBL
5221 PC relative 24 bit shifted by 1.
5223 BFD_RELOC_390_PLT24DBL
5225 24 bit PC rel. PLT shifted by 1.
5227 BFD_RELOC_390_PC32DBL
5229 PC relative 32 bit shifted by 1.
5231 BFD_RELOC_390_PLT32DBL
5233 32 bit PC rel. PLT shifted by 1.
5235 BFD_RELOC_390_GOTPCDBL
5237 32 bit PC rel. GOT shifted by 1.
5245 64 bit PC relative PLT address.
5247 BFD_RELOC_390_GOTENT
5249 32 bit rel. offset to GOT entry.
5251 BFD_RELOC_390_GOTOFF64
5253 64 bit offset to GOT.
5255 BFD_RELOC_390_GOTPLT12
5257 12-bit offset to symbol-entry within GOT, with PLT handling.
5259 BFD_RELOC_390_GOTPLT16
5261 16-bit offset to symbol-entry within GOT, with PLT handling.
5263 BFD_RELOC_390_GOTPLT32
5265 32-bit offset to symbol-entry within GOT, with PLT handling.
5267 BFD_RELOC_390_GOTPLT64
5269 64-bit offset to symbol-entry within GOT, with PLT handling.
5271 BFD_RELOC_390_GOTPLTENT
5273 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5275 BFD_RELOC_390_PLTOFF16
5277 16-bit rel. offset from the GOT to a PLT entry.
5279 BFD_RELOC_390_PLTOFF32
5281 32-bit rel. offset from the GOT to a PLT entry.
5283 BFD_RELOC_390_PLTOFF64
5285 64-bit rel. offset from the GOT to a PLT entry.
5288 BFD_RELOC_390_TLS_LOAD
5290 BFD_RELOC_390_TLS_GDCALL
5292 BFD_RELOC_390_TLS_LDCALL
5294 BFD_RELOC_390_TLS_GD32
5296 BFD_RELOC_390_TLS_GD64
5298 BFD_RELOC_390_TLS_GOTIE12
5300 BFD_RELOC_390_TLS_GOTIE32
5302 BFD_RELOC_390_TLS_GOTIE64
5304 BFD_RELOC_390_TLS_LDM32
5306 BFD_RELOC_390_TLS_LDM64
5308 BFD_RELOC_390_TLS_IE32
5310 BFD_RELOC_390_TLS_IE64
5312 BFD_RELOC_390_TLS_IEENT
5314 BFD_RELOC_390_TLS_LE32
5316 BFD_RELOC_390_TLS_LE64
5318 BFD_RELOC_390_TLS_LDO32
5320 BFD_RELOC_390_TLS_LDO64
5322 BFD_RELOC_390_TLS_DTPMOD
5324 BFD_RELOC_390_TLS_DTPOFF
5326 BFD_RELOC_390_TLS_TPOFF
5328 s390 tls relocations.
5335 BFD_RELOC_390_GOTPLT20
5337 BFD_RELOC_390_TLS_GOTIE20
5339 Long displacement extension.
5342 BFD_RELOC_390_IRELATIVE
5344 STT_GNU_IFUNC relocation.
5347 BFD_RELOC_SCORE_GPREL15
5350 Low 16 bit for load/store
5352 BFD_RELOC_SCORE_DUMMY2
5356 This is a 24-bit reloc with the right 1 bit assumed to be 0
5358 BFD_RELOC_SCORE_BRANCH
5360 This is a 19-bit reloc with the right 1 bit assumed to be 0
5362 BFD_RELOC_SCORE_IMM30
5364 This is a 32-bit reloc for 48-bit instructions.
5366 BFD_RELOC_SCORE_IMM32
5368 This is a 32-bit reloc for 48-bit instructions.
5370 BFD_RELOC_SCORE16_JMP
5372 This is a 11-bit reloc with the right 1 bit assumed to be 0
5374 BFD_RELOC_SCORE16_BRANCH
5376 This is a 8-bit reloc with the right 1 bit assumed to be 0
5378 BFD_RELOC_SCORE_BCMP
5380 This is a 9-bit reloc with the right 1 bit assumed to be 0
5382 BFD_RELOC_SCORE_GOT15
5384 BFD_RELOC_SCORE_GOT_LO16
5386 BFD_RELOC_SCORE_CALL15
5388 BFD_RELOC_SCORE_DUMMY_HI16
5390 Undocumented Score relocs
5395 Scenix IP2K - 9-bit register number / data address
5399 Scenix IP2K - 4-bit register/data bank number
5401 BFD_RELOC_IP2K_ADDR16CJP
5403 Scenix IP2K - low 13 bits of instruction word address
5405 BFD_RELOC_IP2K_PAGE3
5407 Scenix IP2K - high 3 bits of instruction word address
5409 BFD_RELOC_IP2K_LO8DATA
5411 BFD_RELOC_IP2K_HI8DATA
5413 BFD_RELOC_IP2K_EX8DATA
5415 Scenix IP2K - ext/low/high 8 bits of data address
5417 BFD_RELOC_IP2K_LO8INSN
5419 BFD_RELOC_IP2K_HI8INSN
5421 Scenix IP2K - low/high 8 bits of instruction word address
5423 BFD_RELOC_IP2K_PC_SKIP
5425 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5429 Scenix IP2K - 16 bit word address in text section.
5431 BFD_RELOC_IP2K_FR_OFFSET
5433 Scenix IP2K - 7-bit sp or dp offset
5435 BFD_RELOC_VPE4KMATH_DATA
5437 BFD_RELOC_VPE4KMATH_INSN
5439 Scenix VPE4K coprocessor - data/insn-space addressing
5442 BFD_RELOC_VTABLE_INHERIT
5444 BFD_RELOC_VTABLE_ENTRY
5446 These two relocations are used by the linker to determine which of
5447 the entries in a C++ virtual function table are actually used. When
5448 the --gc-sections option is given, the linker will zero out the entries
5449 that are not used, so that the code for those functions need not be
5450 included in the output.
5452 VTABLE_INHERIT is a zero-space relocation used to describe to the
5453 linker the inheritance tree of a C++ virtual function table. The
5454 relocation's symbol should be the parent class' vtable, and the
5455 relocation should be located at the child vtable.
5457 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5458 virtual function table entry. The reloc's symbol should refer to the
5459 table of the class mentioned in the code. Off of that base, an offset
5460 describes the entry that is being used. For Rela hosts, this offset
5461 is stored in the reloc's addend. For Rel hosts, we are forced to put
5462 this offset in the reloc's section offset.
5465 BFD_RELOC_IA64_IMM14
5467 BFD_RELOC_IA64_IMM22
5469 BFD_RELOC_IA64_IMM64
5471 BFD_RELOC_IA64_DIR32MSB
5473 BFD_RELOC_IA64_DIR32LSB
5475 BFD_RELOC_IA64_DIR64MSB
5477 BFD_RELOC_IA64_DIR64LSB
5479 BFD_RELOC_IA64_GPREL22
5481 BFD_RELOC_IA64_GPREL64I
5483 BFD_RELOC_IA64_GPREL32MSB
5485 BFD_RELOC_IA64_GPREL32LSB
5487 BFD_RELOC_IA64_GPREL64MSB
5489 BFD_RELOC_IA64_GPREL64LSB
5491 BFD_RELOC_IA64_LTOFF22
5493 BFD_RELOC_IA64_LTOFF64I
5495 BFD_RELOC_IA64_PLTOFF22
5497 BFD_RELOC_IA64_PLTOFF64I
5499 BFD_RELOC_IA64_PLTOFF64MSB
5501 BFD_RELOC_IA64_PLTOFF64LSB
5503 BFD_RELOC_IA64_FPTR64I
5505 BFD_RELOC_IA64_FPTR32MSB
5507 BFD_RELOC_IA64_FPTR32LSB
5509 BFD_RELOC_IA64_FPTR64MSB
5511 BFD_RELOC_IA64_FPTR64LSB
5513 BFD_RELOC_IA64_PCREL21B
5515 BFD_RELOC_IA64_PCREL21BI
5517 BFD_RELOC_IA64_PCREL21M
5519 BFD_RELOC_IA64_PCREL21F
5521 BFD_RELOC_IA64_PCREL22
5523 BFD_RELOC_IA64_PCREL60B
5525 BFD_RELOC_IA64_PCREL64I
5527 BFD_RELOC_IA64_PCREL32MSB
5529 BFD_RELOC_IA64_PCREL32LSB
5531 BFD_RELOC_IA64_PCREL64MSB
5533 BFD_RELOC_IA64_PCREL64LSB
5535 BFD_RELOC_IA64_LTOFF_FPTR22
5537 BFD_RELOC_IA64_LTOFF_FPTR64I
5539 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5541 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5543 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5545 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5547 BFD_RELOC_IA64_SEGREL32MSB
5549 BFD_RELOC_IA64_SEGREL32LSB
5551 BFD_RELOC_IA64_SEGREL64MSB
5553 BFD_RELOC_IA64_SEGREL64LSB
5555 BFD_RELOC_IA64_SECREL32MSB
5557 BFD_RELOC_IA64_SECREL32LSB
5559 BFD_RELOC_IA64_SECREL64MSB
5561 BFD_RELOC_IA64_SECREL64LSB
5563 BFD_RELOC_IA64_REL32MSB
5565 BFD_RELOC_IA64_REL32LSB
5567 BFD_RELOC_IA64_REL64MSB
5569 BFD_RELOC_IA64_REL64LSB
5571 BFD_RELOC_IA64_LTV32MSB
5573 BFD_RELOC_IA64_LTV32LSB
5575 BFD_RELOC_IA64_LTV64MSB
5577 BFD_RELOC_IA64_LTV64LSB
5579 BFD_RELOC_IA64_IPLTMSB
5581 BFD_RELOC_IA64_IPLTLSB
5585 BFD_RELOC_IA64_LTOFF22X
5587 BFD_RELOC_IA64_LDXMOV
5589 BFD_RELOC_IA64_TPREL14
5591 BFD_RELOC_IA64_TPREL22
5593 BFD_RELOC_IA64_TPREL64I
5595 BFD_RELOC_IA64_TPREL64MSB
5597 BFD_RELOC_IA64_TPREL64LSB
5599 BFD_RELOC_IA64_LTOFF_TPREL22
5601 BFD_RELOC_IA64_DTPMOD64MSB
5603 BFD_RELOC_IA64_DTPMOD64LSB
5605 BFD_RELOC_IA64_LTOFF_DTPMOD22
5607 BFD_RELOC_IA64_DTPREL14
5609 BFD_RELOC_IA64_DTPREL22
5611 BFD_RELOC_IA64_DTPREL64I
5613 BFD_RELOC_IA64_DTPREL32MSB
5615 BFD_RELOC_IA64_DTPREL32LSB
5617 BFD_RELOC_IA64_DTPREL64MSB
5619 BFD_RELOC_IA64_DTPREL64LSB
5621 BFD_RELOC_IA64_LTOFF_DTPREL22
5623 Intel IA64 Relocations.
5626 BFD_RELOC_M68HC11_HI8
5628 Motorola 68HC11 reloc.
5629 This is the 8 bit high part of an absolute address.
5631 BFD_RELOC_M68HC11_LO8
5633 Motorola 68HC11 reloc.
5634 This is the 8 bit low part of an absolute address.
5636 BFD_RELOC_M68HC11_3B
5638 Motorola 68HC11 reloc.
5639 This is the 3 bit of a value.
5641 BFD_RELOC_M68HC11_RL_JUMP
5643 Motorola 68HC11 reloc.
5644 This reloc marks the beginning of a jump/call instruction.
5645 It is used for linker relaxation to correctly identify beginning
5646 of instruction and change some branches to use PC-relative
5649 BFD_RELOC_M68HC11_RL_GROUP
5651 Motorola 68HC11 reloc.
5652 This reloc marks a group of several instructions that gcc generates
5653 and for which the linker relaxation pass can modify and/or remove
5656 BFD_RELOC_M68HC11_LO16
5658 Motorola 68HC11 reloc.
5659 This is the 16-bit lower part of an address. It is used for 'call'
5660 instruction to specify the symbol address without any special
5661 transformation (due to memory bank window).
5663 BFD_RELOC_M68HC11_PAGE
5665 Motorola 68HC11 reloc.
5666 This is a 8-bit reloc that specifies the page number of an address.
5667 It is used by 'call' instruction to specify the page number of
5670 BFD_RELOC_M68HC11_24
5672 Motorola 68HC11 reloc.
5673 This is a 24-bit reloc that represents the address with a 16-bit
5674 value and a 8-bit page number. The symbol address is transformed
5675 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5677 BFD_RELOC_M68HC12_5B
5679 Motorola 68HC12 reloc.
5680 This is the 5 bits of a value.
5682 BFD_RELOC_XGATE_RL_JUMP
5684 Freescale XGATE reloc.
5685 This reloc marks the beginning of a bra/jal instruction.
5687 BFD_RELOC_XGATE_RL_GROUP
5689 Freescale XGATE reloc.
5690 This reloc marks a group of several instructions that gcc generates
5691 and for which the linker relaxation pass can modify and/or remove
5694 BFD_RELOC_XGATE_LO16
5696 Freescale XGATE reloc.
5697 This is the 16-bit lower part of an address. It is used for the '16-bit'
5700 BFD_RELOC_XGATE_GPAGE
5702 Freescale XGATE reloc.
5706 Freescale XGATE reloc.
5708 BFD_RELOC_XGATE_PCREL_9
5710 Freescale XGATE reloc.
5711 This is a 9-bit pc-relative reloc.
5713 BFD_RELOC_XGATE_PCREL_10
5715 Freescale XGATE reloc.
5716 This is a 10-bit pc-relative reloc.
5718 BFD_RELOC_XGATE_IMM8_LO
5720 Freescale XGATE reloc.
5721 This is the 16-bit lower part of an address. It is used for the '16-bit'
5724 BFD_RELOC_XGATE_IMM8_HI
5726 Freescale XGATE reloc.
5727 This is the 16-bit higher part of an address. It is used for the '16-bit'
5730 BFD_RELOC_XGATE_IMM3
5732 Freescale XGATE reloc.
5733 This is a 3-bit pc-relative reloc.
5735 BFD_RELOC_XGATE_IMM4
5737 Freescale XGATE reloc.
5738 This is a 4-bit pc-relative reloc.
5740 BFD_RELOC_XGATE_IMM5
5742 Freescale XGATE reloc.
5743 This is a 5-bit pc-relative reloc.
5745 BFD_RELOC_M68HC12_9B
5747 Motorola 68HC12 reloc.
5748 This is the 9 bits of a value.
5750 BFD_RELOC_M68HC12_16B
5752 Motorola 68HC12 reloc.
5753 This is the 16 bits of a value.
5755 BFD_RELOC_M68HC12_9_PCREL
5757 Motorola 68HC12/XGATE reloc.
5758 This is a PCREL9 branch.
5760 BFD_RELOC_M68HC12_10_PCREL
5762 Motorola 68HC12/XGATE reloc.
5763 This is a PCREL10 branch.
5765 BFD_RELOC_M68HC12_LO8XG
5767 Motorola 68HC12/XGATE reloc.
5768 This is the 8 bit low part of an absolute address and immediately precedes
5769 a matching HI8XG part.
5771 BFD_RELOC_M68HC12_HI8XG
5773 Motorola 68HC12/XGATE reloc.
5774 This is the 8 bit high part of an absolute address and immediately follows
5775 a matching LO8XG part.
5779 BFD_RELOC_16C_NUM08_C
5783 BFD_RELOC_16C_NUM16_C
5787 BFD_RELOC_16C_NUM32_C
5789 BFD_RELOC_16C_DISP04
5791 BFD_RELOC_16C_DISP04_C
5793 BFD_RELOC_16C_DISP08
5795 BFD_RELOC_16C_DISP08_C
5797 BFD_RELOC_16C_DISP16
5799 BFD_RELOC_16C_DISP16_C
5801 BFD_RELOC_16C_DISP24
5803 BFD_RELOC_16C_DISP24_C
5805 BFD_RELOC_16C_DISP24a
5807 BFD_RELOC_16C_DISP24a_C
5811 BFD_RELOC_16C_REG04_C
5813 BFD_RELOC_16C_REG04a
5815 BFD_RELOC_16C_REG04a_C
5819 BFD_RELOC_16C_REG14_C
5823 BFD_RELOC_16C_REG16_C
5827 BFD_RELOC_16C_REG20_C
5831 BFD_RELOC_16C_ABS20_C
5835 BFD_RELOC_16C_ABS24_C
5839 BFD_RELOC_16C_IMM04_C
5843 BFD_RELOC_16C_IMM16_C
5847 BFD_RELOC_16C_IMM20_C
5851 BFD_RELOC_16C_IMM24_C
5855 BFD_RELOC_16C_IMM32_C
5857 NS CR16C Relocations.
5862 BFD_RELOC_CR16_NUM16
5864 BFD_RELOC_CR16_NUM32
5866 BFD_RELOC_CR16_NUM32a
5868 BFD_RELOC_CR16_REGREL0
5870 BFD_RELOC_CR16_REGREL4
5872 BFD_RELOC_CR16_REGREL4a
5874 BFD_RELOC_CR16_REGREL14
5876 BFD_RELOC_CR16_REGREL14a
5878 BFD_RELOC_CR16_REGREL16
5880 BFD_RELOC_CR16_REGREL20
5882 BFD_RELOC_CR16_REGREL20a
5884 BFD_RELOC_CR16_ABS20
5886 BFD_RELOC_CR16_ABS24
5892 BFD_RELOC_CR16_IMM16
5894 BFD_RELOC_CR16_IMM20
5896 BFD_RELOC_CR16_IMM24
5898 BFD_RELOC_CR16_IMM32
5900 BFD_RELOC_CR16_IMM32a
5902 BFD_RELOC_CR16_DISP4
5904 BFD_RELOC_CR16_DISP8
5906 BFD_RELOC_CR16_DISP16
5908 BFD_RELOC_CR16_DISP20
5910 BFD_RELOC_CR16_DISP24
5912 BFD_RELOC_CR16_DISP24a
5914 BFD_RELOC_CR16_SWITCH8
5916 BFD_RELOC_CR16_SWITCH16
5918 BFD_RELOC_CR16_SWITCH32
5920 BFD_RELOC_CR16_GOT_REGREL20
5922 BFD_RELOC_CR16_GOTC_REGREL20
5924 BFD_RELOC_CR16_GLOB_DAT
5926 NS CR16 Relocations.
5933 BFD_RELOC_CRX_REL8_CMP
5941 BFD_RELOC_CRX_REGREL12
5943 BFD_RELOC_CRX_REGREL22
5945 BFD_RELOC_CRX_REGREL28
5947 BFD_RELOC_CRX_REGREL32
5963 BFD_RELOC_CRX_SWITCH8
5965 BFD_RELOC_CRX_SWITCH16
5967 BFD_RELOC_CRX_SWITCH32
5972 BFD_RELOC_CRIS_BDISP8
5974 BFD_RELOC_CRIS_UNSIGNED_5
5976 BFD_RELOC_CRIS_SIGNED_6
5978 BFD_RELOC_CRIS_UNSIGNED_6
5980 BFD_RELOC_CRIS_SIGNED_8
5982 BFD_RELOC_CRIS_UNSIGNED_8
5984 BFD_RELOC_CRIS_SIGNED_16
5986 BFD_RELOC_CRIS_UNSIGNED_16
5988 BFD_RELOC_CRIS_LAPCQ_OFFSET
5990 BFD_RELOC_CRIS_UNSIGNED_4
5992 These relocs are only used within the CRIS assembler. They are not
5993 (at present) written to any object files.
5997 BFD_RELOC_CRIS_GLOB_DAT
5999 BFD_RELOC_CRIS_JUMP_SLOT
6001 BFD_RELOC_CRIS_RELATIVE
6003 Relocs used in ELF shared libraries for CRIS.
6005 BFD_RELOC_CRIS_32_GOT
6007 32-bit offset to symbol-entry within GOT.
6009 BFD_RELOC_CRIS_16_GOT
6011 16-bit offset to symbol-entry within GOT.
6013 BFD_RELOC_CRIS_32_GOTPLT
6015 32-bit offset to symbol-entry within GOT, with PLT handling.
6017 BFD_RELOC_CRIS_16_GOTPLT
6019 16-bit offset to symbol-entry within GOT, with PLT handling.
6021 BFD_RELOC_CRIS_32_GOTREL
6023 32-bit offset to symbol, relative to GOT.
6025 BFD_RELOC_CRIS_32_PLT_GOTREL
6027 32-bit offset to symbol with PLT entry, relative to GOT.
6029 BFD_RELOC_CRIS_32_PLT_PCREL
6031 32-bit offset to symbol with PLT entry, relative to this relocation.
6034 BFD_RELOC_CRIS_32_GOT_GD
6036 BFD_RELOC_CRIS_16_GOT_GD
6038 BFD_RELOC_CRIS_32_GD
6042 BFD_RELOC_CRIS_32_DTPREL
6044 BFD_RELOC_CRIS_16_DTPREL
6046 BFD_RELOC_CRIS_32_GOT_TPREL
6048 BFD_RELOC_CRIS_16_GOT_TPREL
6050 BFD_RELOC_CRIS_32_TPREL
6052 BFD_RELOC_CRIS_16_TPREL
6054 BFD_RELOC_CRIS_DTPMOD
6056 BFD_RELOC_CRIS_32_IE
6058 Relocs used in TLS code for CRIS.
6063 BFD_RELOC_860_GLOB_DAT
6065 BFD_RELOC_860_JUMP_SLOT
6067 BFD_RELOC_860_RELATIVE
6077 BFD_RELOC_860_SPLIT0
6081 BFD_RELOC_860_SPLIT1
6085 BFD_RELOC_860_SPLIT2
6089 BFD_RELOC_860_LOGOT0
6091 BFD_RELOC_860_SPGOT0
6093 BFD_RELOC_860_LOGOT1
6095 BFD_RELOC_860_SPGOT1
6097 BFD_RELOC_860_LOGOTOFF0
6099 BFD_RELOC_860_SPGOTOFF0
6101 BFD_RELOC_860_LOGOTOFF1
6103 BFD_RELOC_860_SPGOTOFF1
6105 BFD_RELOC_860_LOGOTOFF2
6107 BFD_RELOC_860_LOGOTOFF3
6111 BFD_RELOC_860_HIGHADJ
6115 BFD_RELOC_860_HAGOTOFF
6123 BFD_RELOC_860_HIGOTOFF
6125 Intel i860 Relocations.
6128 BFD_RELOC_OR1K_REL_26
6130 BFD_RELOC_OR1K_GOTPC_HI16
6132 BFD_RELOC_OR1K_GOTPC_LO16
6134 BFD_RELOC_OR1K_GOT16
6136 BFD_RELOC_OR1K_PLT26
6138 BFD_RELOC_OR1K_GOTOFF_HI16
6140 BFD_RELOC_OR1K_GOTOFF_LO16
6144 BFD_RELOC_OR1K_GLOB_DAT
6146 BFD_RELOC_OR1K_JMP_SLOT
6148 BFD_RELOC_OR1K_RELATIVE
6150 BFD_RELOC_OR1K_TLS_GD_HI16
6152 BFD_RELOC_OR1K_TLS_GD_LO16
6154 BFD_RELOC_OR1K_TLS_LDM_HI16
6156 BFD_RELOC_OR1K_TLS_LDM_LO16
6158 BFD_RELOC_OR1K_TLS_LDO_HI16
6160 BFD_RELOC_OR1K_TLS_LDO_LO16
6162 BFD_RELOC_OR1K_TLS_IE_HI16
6164 BFD_RELOC_OR1K_TLS_IE_LO16
6166 BFD_RELOC_OR1K_TLS_LE_HI16
6168 BFD_RELOC_OR1K_TLS_LE_LO16
6170 BFD_RELOC_OR1K_TLS_TPOFF
6172 BFD_RELOC_OR1K_TLS_DTPOFF
6174 BFD_RELOC_OR1K_TLS_DTPMOD
6176 OpenRISC 1000 Relocations.
6179 BFD_RELOC_H8_DIR16A8
6181 BFD_RELOC_H8_DIR16R8
6183 BFD_RELOC_H8_DIR24A8
6185 BFD_RELOC_H8_DIR24R8
6187 BFD_RELOC_H8_DIR32A16
6189 BFD_RELOC_H8_DISP32A16
6194 BFD_RELOC_XSTORMY16_REL_12
6196 BFD_RELOC_XSTORMY16_12
6198 BFD_RELOC_XSTORMY16_24
6200 BFD_RELOC_XSTORMY16_FPTR16
6202 Sony Xstormy16 Relocations.
6207 Self-describing complex relocations.
6219 Infineon Relocations.
6222 BFD_RELOC_VAX_GLOB_DAT
6224 BFD_RELOC_VAX_JMP_SLOT
6226 BFD_RELOC_VAX_RELATIVE
6228 Relocations used by VAX ELF.
6233 Morpho MT - 16 bit immediate relocation.
6237 Morpho MT - Hi 16 bits of an address.
6241 Morpho MT - Low 16 bits of an address.
6243 BFD_RELOC_MT_GNU_VTINHERIT
6245 Morpho MT - Used to tell the linker which vtable entries are used.
6247 BFD_RELOC_MT_GNU_VTENTRY
6249 Morpho MT - Used to tell the linker which vtable entries are used.
6251 BFD_RELOC_MT_PCINSN8
6253 Morpho MT - 8 bit immediate relocation.
6256 BFD_RELOC_MSP430_10_PCREL
6258 BFD_RELOC_MSP430_16_PCREL
6262 BFD_RELOC_MSP430_16_PCREL_BYTE
6264 BFD_RELOC_MSP430_16_BYTE
6266 BFD_RELOC_MSP430_2X_PCREL
6268 BFD_RELOC_MSP430_RL_PCREL
6270 BFD_RELOC_MSP430_ABS8
6272 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6274 BFD_RELOC_MSP430X_PCR20_EXT_DST
6276 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6278 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6280 BFD_RELOC_MSP430X_ABS20_EXT_DST
6282 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6284 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6286 BFD_RELOC_MSP430X_ABS20_ADR_DST
6288 BFD_RELOC_MSP430X_PCR16
6290 BFD_RELOC_MSP430X_PCR20_CALL
6292 BFD_RELOC_MSP430X_ABS16
6294 BFD_RELOC_MSP430_ABS_HI16
6296 BFD_RELOC_MSP430_PREL31
6298 BFD_RELOC_MSP430_SYM_DIFF
6300 msp430 specific relocation codes
6307 BFD_RELOC_NIOS2_CALL26
6309 BFD_RELOC_NIOS2_IMM5
6311 BFD_RELOC_NIOS2_CACHE_OPX
6313 BFD_RELOC_NIOS2_IMM6
6315 BFD_RELOC_NIOS2_IMM8
6317 BFD_RELOC_NIOS2_HI16
6319 BFD_RELOC_NIOS2_LO16
6321 BFD_RELOC_NIOS2_HIADJ16
6323 BFD_RELOC_NIOS2_GPREL
6325 BFD_RELOC_NIOS2_UJMP
6327 BFD_RELOC_NIOS2_CJMP
6329 BFD_RELOC_NIOS2_CALLR
6331 BFD_RELOC_NIOS2_ALIGN
6333 BFD_RELOC_NIOS2_GOT16
6335 BFD_RELOC_NIOS2_CALL16
6337 BFD_RELOC_NIOS2_GOTOFF_LO
6339 BFD_RELOC_NIOS2_GOTOFF_HA
6341 BFD_RELOC_NIOS2_PCREL_LO
6343 BFD_RELOC_NIOS2_PCREL_HA
6345 BFD_RELOC_NIOS2_TLS_GD16
6347 BFD_RELOC_NIOS2_TLS_LDM16
6349 BFD_RELOC_NIOS2_TLS_LDO16
6351 BFD_RELOC_NIOS2_TLS_IE16
6353 BFD_RELOC_NIOS2_TLS_LE16
6355 BFD_RELOC_NIOS2_TLS_DTPMOD
6357 BFD_RELOC_NIOS2_TLS_DTPREL
6359 BFD_RELOC_NIOS2_TLS_TPREL
6361 BFD_RELOC_NIOS2_COPY
6363 BFD_RELOC_NIOS2_GLOB_DAT
6365 BFD_RELOC_NIOS2_JUMP_SLOT
6367 BFD_RELOC_NIOS2_RELATIVE
6369 BFD_RELOC_NIOS2_GOTOFF
6371 BFD_RELOC_NIOS2_CALL26_NOAT
6373 BFD_RELOC_NIOS2_GOT_LO
6375 BFD_RELOC_NIOS2_GOT_HA
6377 BFD_RELOC_NIOS2_CALL_LO
6379 BFD_RELOC_NIOS2_CALL_HA
6381 BFD_RELOC_NIOS2_R2_S12
6383 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6385 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6387 BFD_RELOC_NIOS2_R2_T1I7_2
6389 BFD_RELOC_NIOS2_R2_T2I4
6391 BFD_RELOC_NIOS2_R2_T2I4_1
6393 BFD_RELOC_NIOS2_R2_T2I4_2
6395 BFD_RELOC_NIOS2_R2_X1I7_2
6397 BFD_RELOC_NIOS2_R2_X2L5
6399 BFD_RELOC_NIOS2_R2_F1I5_2
6401 BFD_RELOC_NIOS2_R2_L5I4X1
6403 BFD_RELOC_NIOS2_R2_T1X1I6
6405 BFD_RELOC_NIOS2_R2_T1X1I6_2
6407 Relocations used by the Altera Nios II core.
6410 BFD_RELOC_IQ2000_OFFSET_16
6412 BFD_RELOC_IQ2000_OFFSET_21
6414 BFD_RELOC_IQ2000_UHI16
6419 BFD_RELOC_XTENSA_RTLD
6421 Special Xtensa relocation used only by PLT entries in ELF shared
6422 objects to indicate that the runtime linker should set the value
6423 to one of its own internal functions or data structures.
6425 BFD_RELOC_XTENSA_GLOB_DAT
6427 BFD_RELOC_XTENSA_JMP_SLOT
6429 BFD_RELOC_XTENSA_RELATIVE
6431 Xtensa relocations for ELF shared objects.
6433 BFD_RELOC_XTENSA_PLT
6435 Xtensa relocation used in ELF object files for symbols that may require
6436 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6438 BFD_RELOC_XTENSA_DIFF8
6440 BFD_RELOC_XTENSA_DIFF16
6442 BFD_RELOC_XTENSA_DIFF32
6444 Xtensa relocations to mark the difference of two local symbols.
6445 These are only needed to support linker relaxation and can be ignored
6446 when not relaxing. The field is set to the value of the difference
6447 assuming no relaxation. The relocation encodes the position of the
6448 first symbol so the linker can determine whether to adjust the field
6451 BFD_RELOC_XTENSA_SLOT0_OP
6453 BFD_RELOC_XTENSA_SLOT1_OP
6455 BFD_RELOC_XTENSA_SLOT2_OP
6457 BFD_RELOC_XTENSA_SLOT3_OP
6459 BFD_RELOC_XTENSA_SLOT4_OP
6461 BFD_RELOC_XTENSA_SLOT5_OP
6463 BFD_RELOC_XTENSA_SLOT6_OP
6465 BFD_RELOC_XTENSA_SLOT7_OP
6467 BFD_RELOC_XTENSA_SLOT8_OP
6469 BFD_RELOC_XTENSA_SLOT9_OP
6471 BFD_RELOC_XTENSA_SLOT10_OP
6473 BFD_RELOC_XTENSA_SLOT11_OP
6475 BFD_RELOC_XTENSA_SLOT12_OP
6477 BFD_RELOC_XTENSA_SLOT13_OP
6479 BFD_RELOC_XTENSA_SLOT14_OP
6481 Generic Xtensa relocations for instruction operands. Only the slot
6482 number is encoded in the relocation. The relocation applies to the
6483 last PC-relative immediate operand, or if there are no PC-relative
6484 immediates, to the last immediate operand.
6486 BFD_RELOC_XTENSA_SLOT0_ALT
6488 BFD_RELOC_XTENSA_SLOT1_ALT
6490 BFD_RELOC_XTENSA_SLOT2_ALT
6492 BFD_RELOC_XTENSA_SLOT3_ALT
6494 BFD_RELOC_XTENSA_SLOT4_ALT
6496 BFD_RELOC_XTENSA_SLOT5_ALT
6498 BFD_RELOC_XTENSA_SLOT6_ALT
6500 BFD_RELOC_XTENSA_SLOT7_ALT
6502 BFD_RELOC_XTENSA_SLOT8_ALT
6504 BFD_RELOC_XTENSA_SLOT9_ALT
6506 BFD_RELOC_XTENSA_SLOT10_ALT
6508 BFD_RELOC_XTENSA_SLOT11_ALT
6510 BFD_RELOC_XTENSA_SLOT12_ALT
6512 BFD_RELOC_XTENSA_SLOT13_ALT
6514 BFD_RELOC_XTENSA_SLOT14_ALT
6516 Alternate Xtensa relocations. Only the slot is encoded in the
6517 relocation. The meaning of these relocations is opcode-specific.
6519 BFD_RELOC_XTENSA_OP0
6521 BFD_RELOC_XTENSA_OP1
6523 BFD_RELOC_XTENSA_OP2
6525 Xtensa relocations for backward compatibility. These have all been
6526 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6528 BFD_RELOC_XTENSA_ASM_EXPAND
6530 Xtensa relocation to mark that the assembler expanded the
6531 instructions from an original target. The expansion size is
6532 encoded in the reloc size.
6534 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6536 Xtensa relocation to mark that the linker should simplify
6537 assembler-expanded instructions. This is commonly used
6538 internally by the linker after analysis of a
6539 BFD_RELOC_XTENSA_ASM_EXPAND.
6541 BFD_RELOC_XTENSA_TLSDESC_FN
6543 BFD_RELOC_XTENSA_TLSDESC_ARG
6545 BFD_RELOC_XTENSA_TLS_DTPOFF
6547 BFD_RELOC_XTENSA_TLS_TPOFF
6549 BFD_RELOC_XTENSA_TLS_FUNC
6551 BFD_RELOC_XTENSA_TLS_ARG
6553 BFD_RELOC_XTENSA_TLS_CALL
6555 Xtensa TLS relocations.
6560 8 bit signed offset in (ix+d) or (iy+d).
6578 BFD_RELOC_LM32_BRANCH
6580 BFD_RELOC_LM32_16_GOT
6582 BFD_RELOC_LM32_GOTOFF_HI16
6584 BFD_RELOC_LM32_GOTOFF_LO16
6588 BFD_RELOC_LM32_GLOB_DAT
6590 BFD_RELOC_LM32_JMP_SLOT
6592 BFD_RELOC_LM32_RELATIVE
6594 Lattice Mico32 relocations.
6597 BFD_RELOC_MACH_O_SECTDIFF
6599 Difference between two section addreses. Must be followed by a
6600 BFD_RELOC_MACH_O_PAIR.
6602 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6604 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6606 BFD_RELOC_MACH_O_PAIR
6608 Pair of relocation. Contains the first symbol.
6610 BFD_RELOC_MACH_O_SUBTRACTOR32
6612 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6614 BFD_RELOC_MACH_O_SUBTRACTOR64
6616 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6619 BFD_RELOC_MACH_O_X86_64_BRANCH32
6621 BFD_RELOC_MACH_O_X86_64_BRANCH8
6623 PCREL relocations. They are marked as branch to create PLT entry if
6626 BFD_RELOC_MACH_O_X86_64_GOT
6628 Used when referencing a GOT entry.
6630 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6632 Used when loading a GOT entry with movq. It is specially marked so that
6633 the linker could optimize the movq to a leaq if possible.
6635 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6637 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6639 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6641 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6643 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6645 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6649 BFD_RELOC_MACH_O_ARM64_ADDEND
6651 Addend for PAGE or PAGEOFF.
6653 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6655 Relative offset to page of GOT slot.
6657 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6659 Relative offset within page of GOT slot.
6661 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6663 Address of a GOT entry.
6666 BFD_RELOC_MICROBLAZE_32_LO
6668 This is a 32 bit reloc for the microblaze that stores the
6669 low 16 bits of a value
6671 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6673 This is a 32 bit pc-relative reloc for the microblaze that
6674 stores the low 16 bits of a value
6676 BFD_RELOC_MICROBLAZE_32_ROSDA
6678 This is a 32 bit reloc for the microblaze that stores a
6679 value relative to the read-only small data area anchor
6681 BFD_RELOC_MICROBLAZE_32_RWSDA
6683 This is a 32 bit reloc for the microblaze that stores a
6684 value relative to the read-write small data area anchor
6686 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6688 This is a 32 bit reloc for the microblaze to handle
6689 expressions of the form "Symbol Op Symbol"
6691 BFD_RELOC_MICROBLAZE_64_NONE
6693 This is a 64 bit reloc that stores the 32 bit pc relative
6694 value in two words (with an imm instruction). No relocation is
6695 done here - only used for relaxing
6697 BFD_RELOC_MICROBLAZE_64_GOTPC
6699 This is a 64 bit reloc that stores the 32 bit pc relative
6700 value in two words (with an imm instruction). The relocation is
6701 PC-relative GOT offset
6703 BFD_RELOC_MICROBLAZE_64_GOT
6705 This is a 64 bit reloc that stores the 32 bit pc relative
6706 value in two words (with an imm instruction). The relocation is
6709 BFD_RELOC_MICROBLAZE_64_PLT
6711 This is a 64 bit reloc that stores the 32 bit pc relative
6712 value in two words (with an imm instruction). The relocation is
6713 PC-relative offset into PLT
6715 BFD_RELOC_MICROBLAZE_64_GOTOFF
6717 This is a 64 bit reloc that stores the 32 bit GOT relative
6718 value in two words (with an imm instruction). The relocation is
6719 relative offset from _GLOBAL_OFFSET_TABLE_
6721 BFD_RELOC_MICROBLAZE_32_GOTOFF
6723 This is a 32 bit reloc that stores the 32 bit GOT relative
6724 value in a word. The relocation is relative offset from
6725 _GLOBAL_OFFSET_TABLE_
6727 BFD_RELOC_MICROBLAZE_COPY
6729 This is used to tell the dynamic linker to copy the value out of
6730 the dynamic object into the runtime process image.
6732 BFD_RELOC_MICROBLAZE_64_TLS
6736 BFD_RELOC_MICROBLAZE_64_TLSGD
6738 This is a 64 bit reloc that stores the 32 bit GOT relative value
6739 of the GOT TLS GD info entry in two words (with an imm instruction). The
6740 relocation is GOT offset.
6742 BFD_RELOC_MICROBLAZE_64_TLSLD
6744 This is a 64 bit reloc that stores the 32 bit GOT relative value
6745 of the GOT TLS LD info entry in two words (with an imm instruction). The
6746 relocation is GOT offset.
6748 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6750 This is a 32 bit reloc that stores the Module ID to GOT(n).
6752 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6754 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6756 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6758 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6761 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6763 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6764 to two words (uses imm instruction).
6766 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6768 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6769 to two words (uses imm instruction).
6772 BFD_RELOC_AARCH64_RELOC_START
6774 AArch64 pseudo relocation code to mark the start of the AArch64
6775 relocation enumerators. N.B. the order of the enumerators is
6776 important as several tables in the AArch64 bfd backend are indexed
6777 by these enumerators; make sure they are all synced.
6779 BFD_RELOC_AARCH64_NULL
6781 Deprecated AArch64 null relocation code.
6783 BFD_RELOC_AARCH64_NONE
6785 AArch64 null relocation code.
6787 BFD_RELOC_AARCH64_64
6789 BFD_RELOC_AARCH64_32
6791 BFD_RELOC_AARCH64_16
6793 Basic absolute relocations of N bits. These are equivalent to
6794 BFD_RELOC_N and they were added to assist the indexing of the howto
6797 BFD_RELOC_AARCH64_64_PCREL
6799 BFD_RELOC_AARCH64_32_PCREL
6801 BFD_RELOC_AARCH64_16_PCREL
6803 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6804 and they were added to assist the indexing of the howto table.
6806 BFD_RELOC_AARCH64_MOVW_G0
6808 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6809 of an unsigned address/value.
6811 BFD_RELOC_AARCH64_MOVW_G0_NC
6813 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6814 an address/value. No overflow checking.
6816 BFD_RELOC_AARCH64_MOVW_G1
6818 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6819 of an unsigned address/value.
6821 BFD_RELOC_AARCH64_MOVW_G1_NC
6823 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6824 of an address/value. No overflow checking.
6826 BFD_RELOC_AARCH64_MOVW_G2
6828 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6829 of an unsigned address/value.
6831 BFD_RELOC_AARCH64_MOVW_G2_NC
6833 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6834 of an address/value. No overflow checking.
6836 BFD_RELOC_AARCH64_MOVW_G3
6838 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6839 of a signed or unsigned address/value.
6841 BFD_RELOC_AARCH64_MOVW_G0_S
6843 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6844 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6847 BFD_RELOC_AARCH64_MOVW_G1_S
6849 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6850 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6853 BFD_RELOC_AARCH64_MOVW_G2_S
6855 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6856 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6859 BFD_RELOC_AARCH64_LD_LO19_PCREL
6861 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6862 offset. The lowest two bits must be zero and are not stored in the
6863 instruction, giving a 21 bit signed byte offset.
6865 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6867 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6869 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6871 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6872 offset, giving a 4KB aligned page base address.
6874 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6876 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6877 offset, giving a 4KB aligned page base address, but with no overflow
6880 BFD_RELOC_AARCH64_ADD_LO12
6882 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6883 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6885 BFD_RELOC_AARCH64_LDST8_LO12
6887 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6888 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6890 BFD_RELOC_AARCH64_TSTBR14
6892 AArch64 14 bit pc-relative test bit and branch.
6893 The lowest two bits must be zero and are not stored in the instruction,
6894 giving a 16 bit signed byte offset.
6896 BFD_RELOC_AARCH64_BRANCH19
6898 AArch64 19 bit pc-relative conditional branch and compare & branch.
6899 The lowest two bits must be zero and are not stored in the instruction,
6900 giving a 21 bit signed byte offset.
6902 BFD_RELOC_AARCH64_JUMP26
6904 AArch64 26 bit pc-relative unconditional branch.
6905 The lowest two bits must be zero and are not stored in the instruction,
6906 giving a 28 bit signed byte offset.
6908 BFD_RELOC_AARCH64_CALL26
6910 AArch64 26 bit pc-relative unconditional branch and link.
6911 The lowest two bits must be zero and are not stored in the instruction,
6912 giving a 28 bit signed byte offset.
6914 BFD_RELOC_AARCH64_LDST16_LO12
6916 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6917 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6919 BFD_RELOC_AARCH64_LDST32_LO12
6921 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6922 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6924 BFD_RELOC_AARCH64_LDST64_LO12
6926 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6927 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6929 BFD_RELOC_AARCH64_LDST128_LO12
6931 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6932 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6934 BFD_RELOC_AARCH64_GOT_LD_PREL19
6936 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6937 offset of the global offset table entry for a symbol. The lowest two
6938 bits must be zero and are not stored in the instruction, giving a 21
6939 bit signed byte offset. This relocation type requires signed overflow
6942 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6944 Get to the page base of the global offset table entry for a symbol as
6945 part of an ADRP instruction using a 21 bit PC relative value.Used in
6946 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6948 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6950 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6951 the GOT entry for this symbol. Used in conjunction with
6952 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
6954 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6956 Unsigned 12 bit byte offset for 32 bit load/store from the page of
6957 the GOT entry for this symbol. Used in conjunction with
6958 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
6960 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
6962 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
6963 for this symbol. Valid in LP64 ABI only.
6965 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
6967 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
6968 for this symbol. Valid in LP64 ABI only.
6970 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
6972 Unsigned 15 bit byte offset for 64 bit load/store from the page of
6973 the GOT entry for this symbol. Valid in LP64 ABI only.
6975 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
6977 Scaled 14 bit byte offset to the page base of the global offset table.
6979 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
6981 Scaled 15 bit byte offset to the page base of the global offset table.
6983 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6985 Get to the page base of the global offset table entry for a symbols
6986 tls_index structure as part of an adrp instruction using a 21 bit PC
6987 relative value. Used in conjunction with
6988 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6990 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
6992 AArch64 TLS General Dynamic
6994 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6996 Unsigned 12 bit byte offset to global offset table entry for a symbols
6997 tls_index structure. Used in conjunction with
6998 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7000 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7002 AArch64 TLS General Dynamic relocation.
7004 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7006 AArch64 TLS General Dynamic relocation.
7008 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7010 AArch64 TLS INITIAL EXEC relocation.
7012 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7014 AArch64 TLS INITIAL EXEC relocation.
7016 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7018 AArch64 TLS INITIAL EXEC relocation.
7020 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7022 AArch64 TLS INITIAL EXEC relocation.
7024 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7026 AArch64 TLS INITIAL EXEC relocation.
7028 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7030 AArch64 TLS INITIAL EXEC relocation.
7032 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7034 bit[23:12] of byte offset to module TLS base address.
7036 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7038 Unsigned 12 bit byte offset to module TLS base address.
7040 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7042 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7044 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7046 Unsigned 12 bit byte offset to global offset table entry for a symbols
7047 tls_index structure. Used in conjunction with
7048 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7050 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7052 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7055 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7057 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7059 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7061 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7064 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7066 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7068 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7070 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7073 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7075 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7077 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7079 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7082 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7084 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7086 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7088 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7091 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7093 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7095 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7097 bit[15:0] of byte offset to module TLS base address.
7099 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7101 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7103 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7105 bit[31:16] of byte offset to module TLS base address.
7107 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7109 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7111 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7113 bit[47:32] of byte offset to module TLS base address.
7115 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7117 AArch64 TLS LOCAL EXEC relocation.
7119 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7121 AArch64 TLS LOCAL EXEC relocation.
7123 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7125 AArch64 TLS LOCAL EXEC relocation.
7127 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7129 AArch64 TLS LOCAL EXEC relocation.
7131 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7133 AArch64 TLS LOCAL EXEC relocation.
7135 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7137 AArch64 TLS LOCAL EXEC relocation.
7139 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7141 AArch64 TLS LOCAL EXEC relocation.
7143 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7145 AArch64 TLS LOCAL EXEC relocation.
7147 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7149 AArch64 TLS DESC relocation.
7151 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7153 AArch64 TLS DESC relocation.
7155 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7157 AArch64 TLS DESC relocation.
7159 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
7161 AArch64 TLS DESC relocation.
7163 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7165 AArch64 TLS DESC relocation.
7167 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
7169 AArch64 TLS DESC relocation.
7171 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7173 AArch64 TLS DESC relocation.
7175 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7177 AArch64 TLS DESC relocation.
7179 BFD_RELOC_AARCH64_TLSDESC_LDR
7181 AArch64 TLS DESC relocation.
7183 BFD_RELOC_AARCH64_TLSDESC_ADD
7185 AArch64 TLS DESC relocation.
7187 BFD_RELOC_AARCH64_TLSDESC_CALL
7189 AArch64 TLS DESC relocation.
7191 BFD_RELOC_AARCH64_COPY
7193 AArch64 TLS relocation.
7195 BFD_RELOC_AARCH64_GLOB_DAT
7197 AArch64 TLS relocation.
7199 BFD_RELOC_AARCH64_JUMP_SLOT
7201 AArch64 TLS relocation.
7203 BFD_RELOC_AARCH64_RELATIVE
7205 AArch64 TLS relocation.
7207 BFD_RELOC_AARCH64_TLS_DTPMOD
7209 AArch64 TLS relocation.
7211 BFD_RELOC_AARCH64_TLS_DTPREL
7213 AArch64 TLS relocation.
7215 BFD_RELOC_AARCH64_TLS_TPREL
7217 AArch64 TLS relocation.
7219 BFD_RELOC_AARCH64_TLSDESC
7221 AArch64 TLS relocation.
7223 BFD_RELOC_AARCH64_IRELATIVE
7225 AArch64 support for STT_GNU_IFUNC.
7227 BFD_RELOC_AARCH64_RELOC_END
7229 AArch64 pseudo relocation code to mark the end of the AArch64
7230 relocation enumerators that have direct mapping to ELF reloc codes.
7231 There are a few more enumerators after this one; those are mainly
7232 used by the AArch64 assembler for the internal fixup or to select
7233 one of the above enumerators.
7235 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7237 AArch64 pseudo relocation code to be used internally by the AArch64
7238 assembler and not (currently) written to any object files.
7240 BFD_RELOC_AARCH64_LDST_LO12
7242 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7243 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7245 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7247 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7248 used internally by the AArch64 assembler and not (currently) written to
7251 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7253 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7255 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7257 AArch64 pseudo relocation code to be used internally by the AArch64
7258 assembler and not (currently) written to any object files.
7260 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7262 AArch64 pseudo relocation code to be used internally by the AArch64
7263 assembler and not (currently) written to any object files.
7265 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7267 AArch64 pseudo relocation code to be used internally by the AArch64
7268 assembler and not (currently) written to any object files.
7270 BFD_RELOC_TILEPRO_COPY
7272 BFD_RELOC_TILEPRO_GLOB_DAT
7274 BFD_RELOC_TILEPRO_JMP_SLOT
7276 BFD_RELOC_TILEPRO_RELATIVE
7278 BFD_RELOC_TILEPRO_BROFF_X1
7280 BFD_RELOC_TILEPRO_JOFFLONG_X1
7282 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7284 BFD_RELOC_TILEPRO_IMM8_X0
7286 BFD_RELOC_TILEPRO_IMM8_Y0
7288 BFD_RELOC_TILEPRO_IMM8_X1
7290 BFD_RELOC_TILEPRO_IMM8_Y1
7292 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7294 BFD_RELOC_TILEPRO_MT_IMM15_X1
7296 BFD_RELOC_TILEPRO_MF_IMM15_X1
7298 BFD_RELOC_TILEPRO_IMM16_X0
7300 BFD_RELOC_TILEPRO_IMM16_X1
7302 BFD_RELOC_TILEPRO_IMM16_X0_LO
7304 BFD_RELOC_TILEPRO_IMM16_X1_LO
7306 BFD_RELOC_TILEPRO_IMM16_X0_HI
7308 BFD_RELOC_TILEPRO_IMM16_X1_HI
7310 BFD_RELOC_TILEPRO_IMM16_X0_HA
7312 BFD_RELOC_TILEPRO_IMM16_X1_HA
7314 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7316 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7318 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7320 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7322 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7324 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7326 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7328 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7330 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7332 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7334 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7336 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7338 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7340 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7342 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7344 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7346 BFD_RELOC_TILEPRO_MMSTART_X0
7348 BFD_RELOC_TILEPRO_MMEND_X0
7350 BFD_RELOC_TILEPRO_MMSTART_X1
7352 BFD_RELOC_TILEPRO_MMEND_X1
7354 BFD_RELOC_TILEPRO_SHAMT_X0
7356 BFD_RELOC_TILEPRO_SHAMT_X1
7358 BFD_RELOC_TILEPRO_SHAMT_Y0
7360 BFD_RELOC_TILEPRO_SHAMT_Y1
7362 BFD_RELOC_TILEPRO_TLS_GD_CALL
7364 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7366 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7368 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7370 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7372 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7374 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7376 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7378 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7380 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7382 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7384 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7386 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7388 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7390 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7392 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7394 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7396 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7398 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7400 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7402 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7404 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7406 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7408 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7410 BFD_RELOC_TILEPRO_TLS_TPOFF32
7412 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7414 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7416 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7418 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7420 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7422 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7424 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7426 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7428 Tilera TILEPro Relocations.
7430 BFD_RELOC_TILEGX_HW0
7432 BFD_RELOC_TILEGX_HW1
7434 BFD_RELOC_TILEGX_HW2
7436 BFD_RELOC_TILEGX_HW3
7438 BFD_RELOC_TILEGX_HW0_LAST
7440 BFD_RELOC_TILEGX_HW1_LAST
7442 BFD_RELOC_TILEGX_HW2_LAST
7444 BFD_RELOC_TILEGX_COPY
7446 BFD_RELOC_TILEGX_GLOB_DAT
7448 BFD_RELOC_TILEGX_JMP_SLOT
7450 BFD_RELOC_TILEGX_RELATIVE
7452 BFD_RELOC_TILEGX_BROFF_X1
7454 BFD_RELOC_TILEGX_JUMPOFF_X1
7456 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7458 BFD_RELOC_TILEGX_IMM8_X0
7460 BFD_RELOC_TILEGX_IMM8_Y0
7462 BFD_RELOC_TILEGX_IMM8_X1
7464 BFD_RELOC_TILEGX_IMM8_Y1
7466 BFD_RELOC_TILEGX_DEST_IMM8_X1
7468 BFD_RELOC_TILEGX_MT_IMM14_X1
7470 BFD_RELOC_TILEGX_MF_IMM14_X1
7472 BFD_RELOC_TILEGX_MMSTART_X0
7474 BFD_RELOC_TILEGX_MMEND_X0
7476 BFD_RELOC_TILEGX_SHAMT_X0
7478 BFD_RELOC_TILEGX_SHAMT_X1
7480 BFD_RELOC_TILEGX_SHAMT_Y0
7482 BFD_RELOC_TILEGX_SHAMT_Y1
7484 BFD_RELOC_TILEGX_IMM16_X0_HW0
7486 BFD_RELOC_TILEGX_IMM16_X1_HW0
7488 BFD_RELOC_TILEGX_IMM16_X0_HW1
7490 BFD_RELOC_TILEGX_IMM16_X1_HW1
7492 BFD_RELOC_TILEGX_IMM16_X0_HW2
7494 BFD_RELOC_TILEGX_IMM16_X1_HW2
7496 BFD_RELOC_TILEGX_IMM16_X0_HW3
7498 BFD_RELOC_TILEGX_IMM16_X1_HW3
7500 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7502 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7504 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7506 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7508 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7510 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7512 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7514 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7516 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7518 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7520 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7522 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7524 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7526 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7528 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7530 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7532 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7534 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7536 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7538 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7540 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7542 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7544 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7546 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7548 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7550 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7552 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7554 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7556 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7558 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7560 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7562 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7564 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7566 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7568 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7570 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7572 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7574 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7576 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7578 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7580 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7582 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7584 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7586 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7588 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7590 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7592 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7594 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7596 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7598 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7600 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7602 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7604 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7606 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7608 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7610 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7612 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7614 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7616 BFD_RELOC_TILEGX_TLS_DTPMOD64
7618 BFD_RELOC_TILEGX_TLS_DTPOFF64
7620 BFD_RELOC_TILEGX_TLS_TPOFF64
7622 BFD_RELOC_TILEGX_TLS_DTPMOD32
7624 BFD_RELOC_TILEGX_TLS_DTPOFF32
7626 BFD_RELOC_TILEGX_TLS_TPOFF32
7628 BFD_RELOC_TILEGX_TLS_GD_CALL
7630 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7632 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7634 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7636 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7638 BFD_RELOC_TILEGX_TLS_IE_LOAD
7640 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7642 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7644 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7646 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7648 Tilera TILE-Gx Relocations.
7651 BFD_RELOC_EPIPHANY_SIMM8
7653 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7655 BFD_RELOC_EPIPHANY_SIMM24
7657 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7659 BFD_RELOC_EPIPHANY_HIGH
7661 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7663 BFD_RELOC_EPIPHANY_LOW
7665 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7667 BFD_RELOC_EPIPHANY_SIMM11
7669 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7671 BFD_RELOC_EPIPHANY_IMM11
7673 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7675 BFD_RELOC_EPIPHANY_IMM8
7677 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7680 BFD_RELOC_VISIUM_HI16
7682 BFD_RELOC_VISIUM_LO16
7684 BFD_RELOC_VISIUM_IM16
7686 BFD_RELOC_VISIUM_REL16
7688 BFD_RELOC_VISIUM_HI16_PCREL
7690 BFD_RELOC_VISIUM_LO16_PCREL
7692 BFD_RELOC_VISIUM_IM16_PCREL
7700 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7705 bfd_reloc_type_lookup
7706 bfd_reloc_name_lookup
7709 reloc_howto_type *bfd_reloc_type_lookup
7710 (bfd *abfd, bfd_reloc_code_real_type code);
7711 reloc_howto_type *bfd_reloc_name_lookup
7712 (bfd *abfd, const char *reloc_name);
7715 Return a pointer to a howto structure which, when
7716 invoked, will perform the relocation @var{code} on data from the
7722 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7724 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
7728 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
7730 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
7733 static reloc_howto_type bfd_howto_32 =
7734 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
7738 bfd_default_reloc_type_lookup
7741 reloc_howto_type *bfd_default_reloc_type_lookup
7742 (bfd *abfd, bfd_reloc_code_real_type code);
7745 Provides a default relocation lookup routine for any architecture.
7750 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7754 case BFD_RELOC_CTOR:
7755 /* The type of reloc used in a ctor, which will be as wide as the
7756 address - so either a 64, 32, or 16 bitter. */
7757 switch (bfd_arch_bits_per_address (abfd))
7762 return &bfd_howto_32;
7776 bfd_get_reloc_code_name
7779 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7782 Provides a printable name for the supplied relocation code.
7783 Useful mainly for printing error messages.
7787 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
7789 if (code > BFD_RELOC_UNUSED)
7791 return bfd_reloc_code_real_names[code];
7796 bfd_generic_relax_section
7799 bfd_boolean bfd_generic_relax_section
7802 struct bfd_link_info *,
7806 Provides default handling for relaxing for back ends which
7811 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
7812 asection *section ATTRIBUTE_UNUSED,
7813 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
7816 if (bfd_link_relocatable (link_info))
7817 (*link_info->callbacks->einfo)
7818 (_("%P%F: --relax and -r may not be used together\n"));
7826 bfd_generic_gc_sections
7829 bfd_boolean bfd_generic_gc_sections
7830 (bfd *, struct bfd_link_info *);
7833 Provides default handling for relaxing for back ends which
7834 don't do section gc -- i.e., does nothing.
7838 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
7839 struct bfd_link_info *info ATTRIBUTE_UNUSED)
7846 bfd_generic_lookup_section_flags
7849 bfd_boolean bfd_generic_lookup_section_flags
7850 (struct bfd_link_info *, struct flag_info *, asection *);
7853 Provides default handling for section flags lookup
7854 -- i.e., does nothing.
7855 Returns FALSE if the section should be omitted, otherwise TRUE.
7859 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
7860 struct flag_info *flaginfo,
7861 asection *section ATTRIBUTE_UNUSED)
7863 if (flaginfo != NULL)
7865 (*_bfd_error_handler) (_("INPUT_SECTION_FLAGS are not supported.\n"));
7873 bfd_generic_merge_sections
7876 bfd_boolean bfd_generic_merge_sections
7877 (bfd *, struct bfd_link_info *);
7880 Provides default handling for SEC_MERGE section merging for back ends
7881 which don't have SEC_MERGE support -- i.e., does nothing.
7885 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
7886 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
7893 bfd_generic_get_relocated_section_contents
7896 bfd_byte *bfd_generic_get_relocated_section_contents
7898 struct bfd_link_info *link_info,
7899 struct bfd_link_order *link_order,
7901 bfd_boolean relocatable,
7905 Provides default handling of relocation effort for back ends
7906 which can't be bothered to do it efficiently.
7911 bfd_generic_get_relocated_section_contents (bfd *abfd,
7912 struct bfd_link_info *link_info,
7913 struct bfd_link_order *link_order,
7915 bfd_boolean relocatable,
7918 bfd *input_bfd = link_order->u.indirect.section->owner;
7919 asection *input_section = link_order->u.indirect.section;
7921 arelent **reloc_vector;
7924 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
7928 /* Read in the section. */
7929 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
7932 if (reloc_size == 0)
7935 reloc_vector = (arelent **) bfd_malloc (reloc_size);
7936 if (reloc_vector == NULL)
7939 reloc_count = bfd_canonicalize_reloc (input_bfd,
7943 if (reloc_count < 0)
7946 if (reloc_count > 0)
7950 for (parent = reloc_vector; *parent != NULL; parent++)
7952 char *error_message = NULL;
7954 bfd_reloc_status_type r;
7956 symbol = *(*parent)->sym_ptr_ptr;
7957 /* PR ld/19628: A specially crafted input file
7958 can result in a NULL symbol pointer here. */
7961 link_info->callbacks->einfo
7962 (_("%X%P: %B(%A): error: relocation for offset %V has no value\n"),
7963 abfd, input_section, (* parent)->address);
7967 if (symbol->section && discarded_section (symbol->section))
7970 static reloc_howto_type none_howto
7971 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
7972 "unused", FALSE, 0, 0, FALSE);
7974 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
7975 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
7977 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
7978 (*parent)->addend = 0;
7979 (*parent)->howto = &none_howto;
7983 r = bfd_perform_relocation (input_bfd,
7987 relocatable ? abfd : NULL,
7992 asection *os = input_section->output_section;
7994 /* A partial link, so keep the relocs. */
7995 os->orelocation[os->reloc_count] = *parent;
7999 if (r != bfd_reloc_ok)
8003 case bfd_reloc_undefined:
8004 (*link_info->callbacks->undefined_symbol)
8005 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8006 input_bfd, input_section, (*parent)->address, TRUE);
8008 case bfd_reloc_dangerous:
8009 BFD_ASSERT (error_message != NULL);
8010 (*link_info->callbacks->reloc_dangerous)
8011 (link_info, error_message,
8012 input_bfd, input_section, (*parent)->address);
8014 case bfd_reloc_overflow:
8015 (*link_info->callbacks->reloc_overflow)
8017 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8018 (*parent)->howto->name, (*parent)->addend,
8019 input_bfd, input_section, (*parent)->address);
8021 case bfd_reloc_outofrange:
8023 This error can result when processing some partially
8024 complete binaries. Do not abort, but issue an error
8026 link_info->callbacks->einfo
8027 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
8028 abfd, input_section, * parent);
8031 case bfd_reloc_notsupported:
8033 This error can result when processing a corrupt binary.
8034 Do not abort. Issue an error message instead. */
8035 link_info->callbacks->einfo
8036 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
8037 abfd, input_section, * parent);
8041 /* PR 17512; file: 90c2a92e.
8042 Report unexpected results, without aborting. */
8043 link_info->callbacks->einfo
8044 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
8045 abfd, input_section, * parent, r);
8053 free (reloc_vector);
8057 free (reloc_vector);