1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2018 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
98 .typedef struct reloc_cache_entry
100 . {* A pointer into the canonical table of pointers. *}
101 . struct bfd_symbol **sym_ptr_ptr;
103 . {* offset in section. *}
104 . bfd_size_type address;
106 . {* addend for relocation value. *}
109 . {* Pointer to how to perform the required relocation. *}
110 . reloc_howto_type *howto;
120 Here is a description of each of the fields within an <<arelent>>:
124 The symbol table pointer points to a pointer to the symbol
125 associated with the relocation request. It is the pointer
126 into the table returned by the back end's
127 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
128 referenced through a pointer to a pointer so that tools like
129 the linker can fix up all the symbols of the same name by
130 modifying only one pointer. The relocation routine looks in
131 the symbol and uses the base of the section the symbol is
132 attached to and the value of the symbol as the initial
133 relocation offset. If the symbol pointer is zero, then the
134 section provided is looked up.
138 The <<address>> field gives the offset in bytes from the base of
139 the section data which owns the relocation record to the first
140 byte of relocatable information. The actual data relocated
141 will be relative to this point; for example, a relocation
142 type which modifies the bottom two bytes of a four byte word
143 would not touch the first byte pointed to in a big endian
148 The <<addend>> is a value provided by the back end to be added (!)
149 to the relocation offset. Its interpretation is dependent upon
150 the howto. For example, on the 68k the code:
155 | return foo[0x12345678];
158 Could be compiled into:
161 | moveb @@#12345678,d0
166 This could create a reloc pointing to <<foo>>, but leave the
167 offset in the data, something like:
169 |RELOCATION RECORDS FOR [.text]:
173 |00000000 4e56 fffc ; linkw fp,#-4
174 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
175 |0000000a 49c0 ; extbl d0
176 |0000000c 4e5e ; unlk fp
179 Using coff and an 88k, some instructions don't have enough
180 space in them to represent the full address range, and
181 pointers have to be loaded in two parts. So you'd get something like:
183 | or.u r13,r0,hi16(_foo+0x12345678)
184 | ld.b r2,r13,lo16(_foo+0x12345678)
187 This should create two relocs, both pointing to <<_foo>>, and with
188 0x12340000 in their addend field. The data would consist of:
190 |RELOCATION RECORDS FOR [.text]:
192 |00000002 HVRT16 _foo+0x12340000
193 |00000006 LVRT16 _foo+0x12340000
195 |00000000 5da05678 ; or.u r13,r0,0x5678
196 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
197 |00000008 f400c001 ; jmp r1
199 The relocation routine digs out the value from the data, adds
200 it to the addend to get the original offset, and then adds the
201 value of <<_foo>>. Note that all 32 bits have to be kept around
202 somewhere, to cope with carry from bit 15 to bit 16.
204 One further example is the sparc and the a.out format. The
205 sparc has a similar problem to the 88k, in that some
206 instructions don't have room for an entire offset, but on the
207 sparc the parts are created in odd sized lumps. The designers of
208 the a.out format chose to not use the data within the section
209 for storing part of the offset; all the offset is kept within
210 the reloc. Anything in the data should be ignored.
213 | sethi %hi(_foo+0x12345678),%g2
214 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
218 Both relocs contain a pointer to <<foo>>, and the offsets
221 |RELOCATION RECORDS FOR [.text]:
223 |00000004 HI22 _foo+0x12345678
224 |00000008 LO10 _foo+0x12345678
226 |00000000 9de3bf90 ; save %sp,-112,%sp
227 |00000004 05000000 ; sethi %hi(_foo+0),%g2
228 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
229 |0000000c 81c7e008 ; ret
230 |00000010 81e80000 ; restore
234 The <<howto>> field can be imagined as a
235 relocation instruction. It is a pointer to a structure which
236 contains information on what to do with all of the other
237 information in the reloc record and data section. A back end
238 would normally have a relocation instruction set and turn
239 relocations into pointers to the correct structure on input -
240 but it would be possible to create each howto field on demand.
246 <<enum complain_overflow>>
248 Indicates what sort of overflow checking should be done when
249 performing a relocation.
253 .enum complain_overflow
255 . {* Do not complain on overflow. *}
256 . complain_overflow_dont,
258 . {* Complain if the value overflows when considered as a signed
259 . number one bit larger than the field. ie. A bitfield of N bits
260 . is allowed to represent -2**n to 2**n-1. *}
261 . complain_overflow_bitfield,
263 . {* Complain if the value overflows when considered as a signed
265 . complain_overflow_signed,
267 . {* Complain if the value overflows when considered as an
268 . unsigned number. *}
269 . complain_overflow_unsigned
278 The <<reloc_howto_type>> is a structure which contains all the
279 information that libbfd needs to know to tie up a back end's data.
282 .struct bfd_symbol; {* Forward declaration. *}
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's
288 . external idea of what a reloc number is stored
289 . in this field. For example, a PC relative word relocation
290 . in a coff environment has the type 023 - because that's
291 . what the outside world calls a R_PCRWORD reloc. *}
294 . {* The value the final relocation is shifted right by. This drops
295 . unwanted data from the relocation. *}
296 . unsigned int rightshift;
298 . {* The size of the item to be relocated. This is *not* a
299 . power-of-two measure. To get the number of bytes operated
300 . on by a type of relocation, use bfd_get_reloc_size. *}
303 . {* The number of bits in the item to be relocated. This is used
304 . when doing overflow checking. *}
305 . unsigned int bitsize;
307 . {* The relocation is relative to the field being relocated. *}
308 . bfd_boolean pc_relative;
310 . {* The bit position of the reloc value in the destination.
311 . The relocated value is left shifted by this amount. *}
312 . unsigned int bitpos;
314 . {* What type of overflow error should be checked for when
316 . enum complain_overflow complain_on_overflow;
318 . {* If this field is non null, then the supplied function is
319 . called rather than the normal function. This allows really
320 . strange relocation methods to be accommodated. *}
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., ELF); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type *howto)
452 How relocs are tied together in an <<asection>>:
454 .typedef struct relent_chain
457 . struct relent_chain *next;
463 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
464 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
471 bfd_reloc_status_type bfd_check_overflow
472 (enum complain_overflow how,
473 unsigned int bitsize,
474 unsigned int rightshift,
475 unsigned int addrsize,
479 Perform overflow checking on @var{relocation} which has
480 @var{bitsize} significant bits and will be shifted right by
481 @var{rightshift} bits, on a machine with addresses containing
482 @var{addrsize} significant bits. The result is either of
483 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
487 bfd_reloc_status_type
488 bfd_check_overflow (enum complain_overflow how,
489 unsigned int bitsize,
490 unsigned int rightshift,
491 unsigned int addrsize,
494 bfd_vma fieldmask, addrmask, signmask, ss, a;
495 bfd_reloc_status_type flag = bfd_reloc_ok;
497 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
498 we'll be permissive: extra bits in the field mask will
499 automatically extend the address mask for purposes of the
501 fieldmask = N_ONES (bitsize);
502 signmask = ~fieldmask;
503 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
504 a = (relocation & addrmask) >> rightshift;
508 case complain_overflow_dont:
511 case complain_overflow_signed:
512 /* If any sign bits are set, all sign bits must be set. That
513 is, A must be a valid negative address after shifting. */
514 signmask = ~ (fieldmask >> 1);
517 case complain_overflow_bitfield:
518 /* Bitfields are sometimes signed, sometimes unsigned. We
519 explicitly allow an address wrap too, which means a bitfield
520 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
521 if the value has some, but not all, bits set outside the
524 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
525 flag = bfd_reloc_overflow;
528 case complain_overflow_unsigned:
529 /* We have an overflow if the address does not fit in the field. */
530 if ((a & signmask) != 0)
531 flag = bfd_reloc_overflow;
543 bfd_reloc_offset_in_range
546 bfd_boolean bfd_reloc_offset_in_range
547 (reloc_howto_type *howto,
550 bfd_size_type offset);
553 Returns TRUE if the reloc described by @var{HOWTO} can be
554 applied at @var{OFFSET} octets in @var{SECTION}.
558 /* HOWTO describes a relocation, at offset OCTET. Return whether the
559 relocation field is within SECTION of ABFD. */
562 bfd_reloc_offset_in_range (reloc_howto_type *howto,
567 bfd_size_type octet_end = bfd_get_section_limit_octets (abfd, section);
568 bfd_size_type reloc_size = bfd_get_reloc_size (howto);
570 /* The reloc field must be contained entirely within the section.
571 Allow zero length fields (marker relocs or NONE relocs where no
572 relocation will be performed) at the end of the section. */
573 return octet <= octet_end && octet + reloc_size <= octet_end;
578 bfd_perform_relocation
581 bfd_reloc_status_type bfd_perform_relocation
583 arelent *reloc_entry,
585 asection *input_section,
587 char **error_message);
590 If @var{output_bfd} is supplied to this function, the
591 generated image will be relocatable; the relocations are
592 copied to the output file after they have been changed to
593 reflect the new state of the world. There are two ways of
594 reflecting the results of partial linkage in an output file:
595 by modifying the output data in place, and by modifying the
596 relocation record. Some native formats (e.g., basic a.out and
597 basic coff) have no way of specifying an addend in the
598 relocation type, so the addend has to go in the output data.
599 This is no big deal since in these formats the output data
600 slot will always be big enough for the addend. Complex reloc
601 types with addends were invented to solve just this problem.
602 The @var{error_message} argument is set to an error message if
603 this return @code{bfd_reloc_dangerous}.
607 bfd_reloc_status_type
608 bfd_perform_relocation (bfd *abfd,
609 arelent *reloc_entry,
611 asection *input_section,
613 char **error_message)
616 bfd_reloc_status_type flag = bfd_reloc_ok;
617 bfd_size_type octets;
618 bfd_vma output_base = 0;
619 reloc_howto_type *howto = reloc_entry->howto;
620 asection *reloc_target_output_section;
623 symbol = *(reloc_entry->sym_ptr_ptr);
625 /* If we are not producing relocatable output, return an error if
626 the symbol is not defined. An undefined weak symbol is
627 considered to have a value of zero (SVR4 ABI, p. 4-27). */
628 if (bfd_is_und_section (symbol->section)
629 && (symbol->flags & BSF_WEAK) == 0
630 && output_bfd == NULL)
631 flag = bfd_reloc_undefined;
633 /* If there is a function supplied to handle this relocation type,
634 call it. It'll return `bfd_reloc_continue' if further processing
636 if (howto && howto->special_function)
638 bfd_reloc_status_type cont;
640 /* Note - we do not call bfd_reloc_offset_in_range here as the
641 reloc_entry->address field might actually be valid for the
642 backend concerned. It is up to the special_function itself
643 to call bfd_reloc_offset_in_range if needed. */
644 cont = howto->special_function (abfd, reloc_entry, symbol, data,
645 input_section, output_bfd,
647 if (cont != bfd_reloc_continue)
651 if (bfd_is_abs_section (symbol->section)
652 && output_bfd != NULL)
654 reloc_entry->address += input_section->output_offset;
658 /* PR 17512: file: 0f67f69d. */
660 return bfd_reloc_undefined;
662 /* Is the address of the relocation really within the section? */
663 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
664 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
665 return bfd_reloc_outofrange;
667 /* Work out which section the relocation is targeted at and the
668 initial relocation command value. */
670 /* Get symbol value. (Common symbols are special.) */
671 if (bfd_is_com_section (symbol->section))
674 relocation = symbol->value;
676 reloc_target_output_section = symbol->section->output_section;
678 /* Convert input-section-relative symbol value to absolute. */
679 if ((output_bfd && ! howto->partial_inplace)
680 || reloc_target_output_section == NULL)
683 output_base = reloc_target_output_section->vma;
685 relocation += output_base + symbol->section->output_offset;
687 /* Add in supplied addend. */
688 relocation += reloc_entry->addend;
690 /* Here the variable relocation holds the final address of the
691 symbol we are relocating against, plus any addend. */
693 if (howto->pc_relative)
695 /* This is a PC relative relocation. We want to set RELOCATION
696 to the distance between the address of the symbol and the
697 location. RELOCATION is already the address of the symbol.
699 We start by subtracting the address of the section containing
702 If pcrel_offset is set, we must further subtract the position
703 of the location within the section. Some targets arrange for
704 the addend to be the negative of the position of the location
705 within the section; for example, i386-aout does this. For
706 i386-aout, pcrel_offset is FALSE. Some other targets do not
707 include the position of the location; for example, ELF.
708 For those targets, pcrel_offset is TRUE.
710 If we are producing relocatable output, then we must ensure
711 that this reloc will be correctly computed when the final
712 relocation is done. If pcrel_offset is FALSE we want to wind
713 up with the negative of the location within the section,
714 which means we must adjust the existing addend by the change
715 in the location within the section. If pcrel_offset is TRUE
716 we do not want to adjust the existing addend at all.
718 FIXME: This seems logical to me, but for the case of
719 producing relocatable output it is not what the code
720 actually does. I don't want to change it, because it seems
721 far too likely that something will break. */
724 input_section->output_section->vma + input_section->output_offset;
726 if (howto->pcrel_offset)
727 relocation -= reloc_entry->address;
730 if (output_bfd != NULL)
732 if (! howto->partial_inplace)
734 /* This is a partial relocation, and we want to apply the relocation
735 to the reloc entry rather than the raw data. Modify the reloc
736 inplace to reflect what we now know. */
737 reloc_entry->addend = relocation;
738 reloc_entry->address += input_section->output_offset;
743 /* This is a partial relocation, but inplace, so modify the
746 If we've relocated with a symbol with a section, change
747 into a ref to the section belonging to the symbol. */
749 reloc_entry->address += input_section->output_offset;
752 if (abfd->xvec->flavour == bfd_target_coff_flavour
753 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
754 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
756 /* For m68k-coff, the addend was being subtracted twice during
757 relocation with -r. Removing the line below this comment
758 fixes that problem; see PR 2953.
760 However, Ian wrote the following, regarding removing the line below,
761 which explains why it is still enabled: --djm
763 If you put a patch like that into BFD you need to check all the COFF
764 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
765 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
766 problem in a different way. There may very well be a reason that the
767 code works as it does.
769 Hmmm. The first obvious point is that bfd_perform_relocation should
770 not have any tests that depend upon the flavour. It's seem like
771 entirely the wrong place for such a thing. The second obvious point
772 is that the current code ignores the reloc addend when producing
773 relocatable output for COFF. That's peculiar. In fact, I really
774 have no idea what the point of the line you want to remove is.
776 A typical COFF reloc subtracts the old value of the symbol and adds in
777 the new value to the location in the object file (if it's a pc
778 relative reloc it adds the difference between the symbol value and the
779 location). When relocating we need to preserve that property.
781 BFD handles this by setting the addend to the negative of the old
782 value of the symbol. Unfortunately it handles common symbols in a
783 non-standard way (it doesn't subtract the old value) but that's a
784 different story (we can't change it without losing backward
785 compatibility with old object files) (coff-i386 does subtract the old
786 value, to be compatible with existing coff-i386 targets, like SCO).
788 So everything works fine when not producing relocatable output. When
789 we are producing relocatable output, logically we should do exactly
790 what we do when not producing relocatable output. Therefore, your
791 patch is correct. In fact, it should probably always just set
792 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
793 add the value into the object file. This won't hurt the COFF code,
794 which doesn't use the addend; I'm not sure what it will do to other
795 formats (the thing to check for would be whether any formats both use
796 the addend and set partial_inplace).
798 When I wanted to make coff-i386 produce relocatable output, I ran
799 into the problem that you are running into: I wanted to remove that
800 line. Rather than risk it, I made the coff-i386 relocs use a special
801 function; it's coff_i386_reloc in coff-i386.c. The function
802 specifically adds the addend field into the object file, knowing that
803 bfd_perform_relocation is not going to. If you remove that line, then
804 coff-i386.c will wind up adding the addend field in twice. It's
805 trivial to fix; it just needs to be done.
807 The problem with removing the line is just that it may break some
808 working code. With BFD it's hard to be sure of anything. The right
809 way to deal with this is simply to build and test at least all the
810 supported COFF targets. It should be straightforward if time and disk
811 space consuming. For each target:
813 2) generate some executable, and link it using -r (I would
814 probably use paranoia.o and link against newlib/libc.a, which
815 for all the supported targets would be available in
816 /usr/cygnus/progressive/H-host/target/lib/libc.a).
817 3) make the change to reloc.c
818 4) rebuild the linker
820 6) if the resulting object files are the same, you have at least
822 7) if they are different you have to figure out which version is
825 relocation -= reloc_entry->addend;
826 reloc_entry->addend = 0;
830 reloc_entry->addend = relocation;
835 /* FIXME: This overflow checking is incomplete, because the value
836 might have overflowed before we get here. For a correct check we
837 need to compute the value in a size larger than bitsize, but we
838 can't reasonably do that for a reloc the same size as a host
840 FIXME: We should also do overflow checking on the result after
841 adding in the value contained in the object file. */
842 if (howto->complain_on_overflow != complain_overflow_dont
843 && flag == bfd_reloc_ok)
844 flag = bfd_check_overflow (howto->complain_on_overflow,
847 bfd_arch_bits_per_address (abfd),
850 /* Either we are relocating all the way, or we don't want to apply
851 the relocation to the reloc entry (probably because there isn't
852 any room in the output format to describe addends to relocs). */
854 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
855 (OSF version 1.3, compiler version 3.11). It miscompiles the
869 x <<= (unsigned long) s.i0;
873 printf ("succeeded (%lx)\n", x);
877 relocation >>= (bfd_vma) howto->rightshift;
879 /* Shift everything up to where it's going to be used. */
880 relocation <<= (bfd_vma) howto->bitpos;
882 /* Wait for the day when all have the mask in them. */
885 i instruction to be left alone
886 o offset within instruction
887 r relocation offset to apply
896 (( i i i i i o o o o o from bfd_get<size>
897 and S S S S S) to get the size offset we want
898 + r r r r r r r r r r) to get the final value to place
899 and D D D D D to chop to right size
900 -----------------------
903 ( i i i i i o o o o o from bfd_get<size>
904 and N N N N N ) get instruction
905 -----------------------
911 -----------------------
912 = R R R R R R R R R R put into bfd_put<size>
916 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
922 char x = bfd_get_8 (abfd, (char *) data + octets);
924 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
930 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
932 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
937 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
939 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
944 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
945 relocation = -relocation;
947 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
953 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
954 relocation = -relocation;
956 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
967 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
969 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
976 return bfd_reloc_other;
984 bfd_install_relocation
987 bfd_reloc_status_type bfd_install_relocation
989 arelent *reloc_entry,
990 void *data, bfd_vma data_start,
991 asection *input_section,
992 char **error_message);
995 This looks remarkably like <<bfd_perform_relocation>>, except it
996 does not expect that the section contents have been filled in.
997 I.e., it's suitable for use when creating, rather than applying
1000 For now, this function should be considered reserved for the
1004 bfd_reloc_status_type
1005 bfd_install_relocation (bfd *abfd,
1006 arelent *reloc_entry,
1008 bfd_vma data_start_offset,
1009 asection *input_section,
1010 char **error_message)
1013 bfd_reloc_status_type flag = bfd_reloc_ok;
1014 bfd_size_type octets;
1015 bfd_vma output_base = 0;
1016 reloc_howto_type *howto = reloc_entry->howto;
1017 asection *reloc_target_output_section;
1021 symbol = *(reloc_entry->sym_ptr_ptr);
1023 /* If there is a function supplied to handle this relocation type,
1024 call it. It'll return `bfd_reloc_continue' if further processing
1026 if (howto && howto->special_function)
1028 bfd_reloc_status_type cont;
1030 /* Note - we do not call bfd_reloc_offset_in_range here as the
1031 reloc_entry->address field might actually be valid for the
1032 backend concerned. It is up to the special_function itself
1033 to call bfd_reloc_offset_in_range if needed. */
1034 /* XXX - The special_function calls haven't been fixed up to deal
1035 with creating new relocations and section contents. */
1036 cont = howto->special_function (abfd, reloc_entry, symbol,
1037 /* XXX - Non-portable! */
1038 ((bfd_byte *) data_start
1039 - data_start_offset),
1040 input_section, abfd, error_message);
1041 if (cont != bfd_reloc_continue)
1045 if (bfd_is_abs_section (symbol->section))
1047 reloc_entry->address += input_section->output_offset;
1048 return bfd_reloc_ok;
1051 /* No need to check for howto != NULL if !bfd_is_abs_section as
1052 it will have been checked in `bfd_perform_relocation already'. */
1054 /* Is the address of the relocation really within the section? */
1055 octets = reloc_entry->address * bfd_octets_per_byte (abfd);
1056 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
1057 return bfd_reloc_outofrange;
1059 /* Work out which section the relocation is targeted at and the
1060 initial relocation command value. */
1062 /* Get symbol value. (Common symbols are special.) */
1063 if (bfd_is_com_section (symbol->section))
1066 relocation = symbol->value;
1068 reloc_target_output_section = symbol->section->output_section;
1070 /* Convert input-section-relative symbol value to absolute. */
1071 if (! howto->partial_inplace)
1074 output_base = reloc_target_output_section->vma;
1076 relocation += output_base + symbol->section->output_offset;
1078 /* Add in supplied addend. */
1079 relocation += reloc_entry->addend;
1081 /* Here the variable relocation holds the final address of the
1082 symbol we are relocating against, plus any addend. */
1084 if (howto->pc_relative)
1086 /* This is a PC relative relocation. We want to set RELOCATION
1087 to the distance between the address of the symbol and the
1088 location. RELOCATION is already the address of the symbol.
1090 We start by subtracting the address of the section containing
1093 If pcrel_offset is set, we must further subtract the position
1094 of the location within the section. Some targets arrange for
1095 the addend to be the negative of the position of the location
1096 within the section; for example, i386-aout does this. For
1097 i386-aout, pcrel_offset is FALSE. Some other targets do not
1098 include the position of the location; for example, ELF.
1099 For those targets, pcrel_offset is TRUE.
1101 If we are producing relocatable output, then we must ensure
1102 that this reloc will be correctly computed when the final
1103 relocation is done. If pcrel_offset is FALSE we want to wind
1104 up with the negative of the location within the section,
1105 which means we must adjust the existing addend by the change
1106 in the location within the section. If pcrel_offset is TRUE
1107 we do not want to adjust the existing addend at all.
1109 FIXME: This seems logical to me, but for the case of
1110 producing relocatable output it is not what the code
1111 actually does. I don't want to change it, because it seems
1112 far too likely that something will break. */
1115 input_section->output_section->vma + input_section->output_offset;
1117 if (howto->pcrel_offset && howto->partial_inplace)
1118 relocation -= reloc_entry->address;
1121 if (! howto->partial_inplace)
1123 /* This is a partial relocation, and we want to apply the relocation
1124 to the reloc entry rather than the raw data. Modify the reloc
1125 inplace to reflect what we now know. */
1126 reloc_entry->addend = relocation;
1127 reloc_entry->address += input_section->output_offset;
1132 /* This is a partial relocation, but inplace, so modify the
1135 If we've relocated with a symbol with a section, change
1136 into a ref to the section belonging to the symbol. */
1137 reloc_entry->address += input_section->output_offset;
1140 if (abfd->xvec->flavour == bfd_target_coff_flavour
1141 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1142 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1145 /* For m68k-coff, the addend was being subtracted twice during
1146 relocation with -r. Removing the line below this comment
1147 fixes that problem; see PR 2953.
1149 However, Ian wrote the following, regarding removing the line below,
1150 which explains why it is still enabled: --djm
1152 If you put a patch like that into BFD you need to check all the COFF
1153 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1154 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1155 problem in a different way. There may very well be a reason that the
1156 code works as it does.
1158 Hmmm. The first obvious point is that bfd_install_relocation should
1159 not have any tests that depend upon the flavour. It's seem like
1160 entirely the wrong place for such a thing. The second obvious point
1161 is that the current code ignores the reloc addend when producing
1162 relocatable output for COFF. That's peculiar. In fact, I really
1163 have no idea what the point of the line you want to remove is.
1165 A typical COFF reloc subtracts the old value of the symbol and adds in
1166 the new value to the location in the object file (if it's a pc
1167 relative reloc it adds the difference between the symbol value and the
1168 location). When relocating we need to preserve that property.
1170 BFD handles this by setting the addend to the negative of the old
1171 value of the symbol. Unfortunately it handles common symbols in a
1172 non-standard way (it doesn't subtract the old value) but that's a
1173 different story (we can't change it without losing backward
1174 compatibility with old object files) (coff-i386 does subtract the old
1175 value, to be compatible with existing coff-i386 targets, like SCO).
1177 So everything works fine when not producing relocatable output. When
1178 we are producing relocatable output, logically we should do exactly
1179 what we do when not producing relocatable output. Therefore, your
1180 patch is correct. In fact, it should probably always just set
1181 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1182 add the value into the object file. This won't hurt the COFF code,
1183 which doesn't use the addend; I'm not sure what it will do to other
1184 formats (the thing to check for would be whether any formats both use
1185 the addend and set partial_inplace).
1187 When I wanted to make coff-i386 produce relocatable output, I ran
1188 into the problem that you are running into: I wanted to remove that
1189 line. Rather than risk it, I made the coff-i386 relocs use a special
1190 function; it's coff_i386_reloc in coff-i386.c. The function
1191 specifically adds the addend field into the object file, knowing that
1192 bfd_install_relocation is not going to. If you remove that line, then
1193 coff-i386.c will wind up adding the addend field in twice. It's
1194 trivial to fix; it just needs to be done.
1196 The problem with removing the line is just that it may break some
1197 working code. With BFD it's hard to be sure of anything. The right
1198 way to deal with this is simply to build and test at least all the
1199 supported COFF targets. It should be straightforward if time and disk
1200 space consuming. For each target:
1202 2) generate some executable, and link it using -r (I would
1203 probably use paranoia.o and link against newlib/libc.a, which
1204 for all the supported targets would be available in
1205 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1206 3) make the change to reloc.c
1207 4) rebuild the linker
1209 6) if the resulting object files are the same, you have at least
1211 7) if they are different you have to figure out which version is
1213 relocation -= reloc_entry->addend;
1214 /* FIXME: There should be no target specific code here... */
1215 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1216 reloc_entry->addend = 0;
1220 reloc_entry->addend = relocation;
1224 /* FIXME: This overflow checking is incomplete, because the value
1225 might have overflowed before we get here. For a correct check we
1226 need to compute the value in a size larger than bitsize, but we
1227 can't reasonably do that for a reloc the same size as a host
1229 FIXME: We should also do overflow checking on the result after
1230 adding in the value contained in the object file. */
1231 if (howto->complain_on_overflow != complain_overflow_dont)
1232 flag = bfd_check_overflow (howto->complain_on_overflow,
1235 bfd_arch_bits_per_address (abfd),
1238 /* Either we are relocating all the way, or we don't want to apply
1239 the relocation to the reloc entry (probably because there isn't
1240 any room in the output format to describe addends to relocs). */
1242 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1243 (OSF version 1.3, compiler version 3.11). It miscompiles the
1257 x <<= (unsigned long) s.i0;
1259 printf ("failed\n");
1261 printf ("succeeded (%lx)\n", x);
1265 relocation >>= (bfd_vma) howto->rightshift;
1267 /* Shift everything up to where it's going to be used. */
1268 relocation <<= (bfd_vma) howto->bitpos;
1270 /* Wait for the day when all have the mask in them. */
1273 i instruction to be left alone
1274 o offset within instruction
1275 r relocation offset to apply
1284 (( i i i i i o o o o o from bfd_get<size>
1285 and S S S S S) to get the size offset we want
1286 + r r r r r r r r r r) to get the final value to place
1287 and D D D D D to chop to right size
1288 -----------------------
1291 ( i i i i i o o o o o from bfd_get<size>
1292 and N N N N N ) get instruction
1293 -----------------------
1299 -----------------------
1300 = R R R R R R R R R R put into bfd_put<size>
1304 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1306 data = (bfd_byte *) data_start + (octets - data_start_offset);
1308 switch (howto->size)
1312 char x = bfd_get_8 (abfd, data);
1314 bfd_put_8 (abfd, x, data);
1320 short x = bfd_get_16 (abfd, data);
1322 bfd_put_16 (abfd, (bfd_vma) x, data);
1327 long x = bfd_get_32 (abfd, data);
1329 bfd_put_32 (abfd, (bfd_vma) x, data);
1334 long x = bfd_get_32 (abfd, data);
1335 relocation = -relocation;
1337 bfd_put_32 (abfd, (bfd_vma) x, data);
1347 bfd_vma x = bfd_get_64 (abfd, data);
1349 bfd_put_64 (abfd, x, data);
1353 return bfd_reloc_other;
1359 /* This relocation routine is used by some of the backend linkers.
1360 They do not construct asymbol or arelent structures, so there is no
1361 reason for them to use bfd_perform_relocation. Also,
1362 bfd_perform_relocation is so hacked up it is easier to write a new
1363 function than to try to deal with it.
1365 This routine does a final relocation. Whether it is useful for a
1366 relocatable link depends upon how the object format defines
1369 FIXME: This routine ignores any special_function in the HOWTO,
1370 since the existing special_function values have been written for
1371 bfd_perform_relocation.
1373 HOWTO is the reloc howto information.
1374 INPUT_BFD is the BFD which the reloc applies to.
1375 INPUT_SECTION is the section which the reloc applies to.
1376 CONTENTS is the contents of the section.
1377 ADDRESS is the address of the reloc within INPUT_SECTION.
1378 VALUE is the value of the symbol the reloc refers to.
1379 ADDEND is the addend of the reloc. */
1381 bfd_reloc_status_type
1382 _bfd_final_link_relocate (reloc_howto_type *howto,
1384 asection *input_section,
1391 bfd_size_type octets = address * bfd_octets_per_byte (input_bfd);
1393 /* Sanity check the address. */
1394 if (!bfd_reloc_offset_in_range (howto, input_bfd, input_section, octets))
1395 return bfd_reloc_outofrange;
1397 /* This function assumes that we are dealing with a basic relocation
1398 against a symbol. We want to compute the value of the symbol to
1399 relocate to. This is just VALUE, the value of the symbol, plus
1400 ADDEND, any addend associated with the reloc. */
1401 relocation = value + addend;
1403 /* If the relocation is PC relative, we want to set RELOCATION to
1404 the distance between the symbol (currently in RELOCATION) and the
1405 location we are relocating. Some targets (e.g., i386-aout)
1406 arrange for the contents of the section to be the negative of the
1407 offset of the location within the section; for such targets
1408 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1409 the contents of the section as zero; for such targets
1410 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1411 subtract out the offset of the location within the section (which
1412 is just ADDRESS). */
1413 if (howto->pc_relative)
1415 relocation -= (input_section->output_section->vma
1416 + input_section->output_offset);
1417 if (howto->pcrel_offset)
1418 relocation -= address;
1421 return _bfd_relocate_contents (howto, input_bfd, relocation,
1423 + address * bfd_octets_per_byte (input_bfd));
1426 /* Relocate a given location using a given value and howto. */
1428 bfd_reloc_status_type
1429 _bfd_relocate_contents (reloc_howto_type *howto,
1436 bfd_reloc_status_type flag;
1437 unsigned int rightshift = howto->rightshift;
1438 unsigned int bitpos = howto->bitpos;
1440 /* If the size is negative, negate RELOCATION. This isn't very
1442 if (howto->size < 0)
1443 relocation = -relocation;
1445 /* Get the value we are going to relocate. */
1446 size = bfd_get_reloc_size (howto);
1452 return bfd_reloc_ok;
1454 x = bfd_get_8 (input_bfd, location);
1457 x = bfd_get_16 (input_bfd, location);
1460 x = bfd_get_32 (input_bfd, location);
1464 x = bfd_get_64 (input_bfd, location);
1471 /* Check for overflow. FIXME: We may drop bits during the addition
1472 which we don't check for. We must either check at every single
1473 operation, which would be tedious, or we must do the computations
1474 in a type larger than bfd_vma, which would be inefficient. */
1475 flag = bfd_reloc_ok;
1476 if (howto->complain_on_overflow != complain_overflow_dont)
1478 bfd_vma addrmask, fieldmask, signmask, ss;
1481 /* Get the values to be added together. For signed and unsigned
1482 relocations, we assume that all values should be truncated to
1483 the size of an address. For bitfields, all the bits matter.
1484 See also bfd_check_overflow. */
1485 fieldmask = N_ONES (howto->bitsize);
1486 signmask = ~fieldmask;
1487 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1488 | (fieldmask << rightshift));
1489 a = (relocation & addrmask) >> rightshift;
1490 b = (x & howto->src_mask & addrmask) >> bitpos;
1491 addrmask >>= rightshift;
1493 switch (howto->complain_on_overflow)
1495 case complain_overflow_signed:
1496 /* If any sign bits are set, all sign bits must be set.
1497 That is, A must be a valid negative address after
1499 signmask = ~(fieldmask >> 1);
1502 case complain_overflow_bitfield:
1503 /* Much like the signed check, but for a field one bit
1504 wider. We allow a bitfield to represent numbers in the
1505 range -2**n to 2**n-1, where n is the number of bits in the
1506 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1507 can't overflow, which is exactly what we want. */
1509 if (ss != 0 && ss != (addrmask & signmask))
1510 flag = bfd_reloc_overflow;
1512 /* We only need this next bit of code if the sign bit of B
1513 is below the sign bit of A. This would only happen if
1514 SRC_MASK had fewer bits than BITSIZE. Note that if
1515 SRC_MASK has more bits than BITSIZE, we can get into
1516 trouble; we would need to verify that B is in range, as
1517 we do for A above. */
1518 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1521 /* Set all the bits above the sign bit. */
1524 /* Now we can do the addition. */
1527 /* See if the result has the correct sign. Bits above the
1528 sign bit are junk now; ignore them. If the sum is
1529 positive, make sure we did not have all negative inputs;
1530 if the sum is negative, make sure we did not have all
1531 positive inputs. The test below looks only at the sign
1532 bits, and it really just
1533 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1535 We mask with addrmask here to explicitly allow an address
1536 wrap-around. The Linux kernel relies on it, and it is
1537 the only way to write assembler code which can run when
1538 loaded at a location 0x80000000 away from the location at
1539 which it is linked. */
1540 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1541 flag = bfd_reloc_overflow;
1544 case complain_overflow_unsigned:
1545 /* Checking for an unsigned overflow is relatively easy:
1546 trim the addresses and add, and trim the result as well.
1547 Overflow is normally indicated when the result does not
1548 fit in the field. However, we also need to consider the
1549 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1550 input is 0x80000000, and bfd_vma is only 32 bits; then we
1551 will get sum == 0, but there is an overflow, since the
1552 inputs did not fit in the field. Instead of doing a
1553 separate test, we can check for this by or-ing in the
1554 operands when testing for the sum overflowing its final
1556 sum = (a + b) & addrmask;
1557 if ((a | b | sum) & signmask)
1558 flag = bfd_reloc_overflow;
1566 /* Put RELOCATION in the right bits. */
1567 relocation >>= (bfd_vma) rightshift;
1568 relocation <<= (bfd_vma) bitpos;
1570 /* Add RELOCATION to the right bits of X. */
1571 x = ((x & ~howto->dst_mask)
1572 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1574 /* Put the relocated value back in the object file. */
1580 bfd_put_8 (input_bfd, x, location);
1583 bfd_put_16 (input_bfd, x, location);
1586 bfd_put_32 (input_bfd, x, location);
1590 bfd_put_64 (input_bfd, x, location);
1600 /* Clear a given location using a given howto, by applying a fixed relocation
1601 value and discarding any in-place addend. This is used for fixed-up
1602 relocations against discarded symbols, to make ignorable debug or unwind
1603 information more obvious. */
1606 _bfd_clear_contents (reloc_howto_type *howto,
1608 asection *input_section,
1614 /* Get the value we are going to relocate. */
1615 size = bfd_get_reloc_size (howto);
1623 x = bfd_get_8 (input_bfd, location);
1626 x = bfd_get_16 (input_bfd, location);
1629 x = bfd_get_32 (input_bfd, location);
1633 x = bfd_get_64 (input_bfd, location);
1640 /* Zero out the unwanted bits of X. */
1641 x &= ~howto->dst_mask;
1643 /* For a range list, use 1 instead of 0 as placeholder. 0
1644 would terminate the list, hiding any later entries. */
1645 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1646 ".debug_ranges") == 0
1647 && (howto->dst_mask & 1) != 0)
1650 /* Put the relocated value back in the object file. */
1657 bfd_put_8 (input_bfd, x, location);
1660 bfd_put_16 (input_bfd, x, location);
1663 bfd_put_32 (input_bfd, x, location);
1667 bfd_put_64 (input_bfd, x, location);
1678 howto manager, , typedef arelent, Relocations
1683 When an application wants to create a relocation, but doesn't
1684 know what the target machine might call it, it can find out by
1685 using this bit of code.
1694 The insides of a reloc code. The idea is that, eventually, there
1695 will be one enumerator for every type of relocation we ever do.
1696 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1697 return a howto pointer.
1699 This does mean that the application must determine the correct
1700 enumerator value; you can't get a howto pointer from a random set
1721 Basic absolute relocations of N bits.
1736 PC-relative relocations. Sometimes these are relative to the address
1737 of the relocation itself; sometimes they are relative to the start of
1738 the section containing the relocation. It depends on the specific target.
1743 Section relative relocations. Some targets need this for DWARF2.
1746 BFD_RELOC_32_GOT_PCREL
1748 BFD_RELOC_16_GOT_PCREL
1750 BFD_RELOC_8_GOT_PCREL
1756 BFD_RELOC_LO16_GOTOFF
1758 BFD_RELOC_HI16_GOTOFF
1760 BFD_RELOC_HI16_S_GOTOFF
1764 BFD_RELOC_64_PLT_PCREL
1766 BFD_RELOC_32_PLT_PCREL
1768 BFD_RELOC_24_PLT_PCREL
1770 BFD_RELOC_16_PLT_PCREL
1772 BFD_RELOC_8_PLT_PCREL
1780 BFD_RELOC_LO16_PLTOFF
1782 BFD_RELOC_HI16_PLTOFF
1784 BFD_RELOC_HI16_S_PLTOFF
1798 BFD_RELOC_68K_GLOB_DAT
1800 BFD_RELOC_68K_JMP_SLOT
1802 BFD_RELOC_68K_RELATIVE
1804 BFD_RELOC_68K_TLS_GD32
1806 BFD_RELOC_68K_TLS_GD16
1808 BFD_RELOC_68K_TLS_GD8
1810 BFD_RELOC_68K_TLS_LDM32
1812 BFD_RELOC_68K_TLS_LDM16
1814 BFD_RELOC_68K_TLS_LDM8
1816 BFD_RELOC_68K_TLS_LDO32
1818 BFD_RELOC_68K_TLS_LDO16
1820 BFD_RELOC_68K_TLS_LDO8
1822 BFD_RELOC_68K_TLS_IE32
1824 BFD_RELOC_68K_TLS_IE16
1826 BFD_RELOC_68K_TLS_IE8
1828 BFD_RELOC_68K_TLS_LE32
1830 BFD_RELOC_68K_TLS_LE16
1832 BFD_RELOC_68K_TLS_LE8
1834 Relocations used by 68K ELF.
1837 BFD_RELOC_32_BASEREL
1839 BFD_RELOC_16_BASEREL
1841 BFD_RELOC_LO16_BASEREL
1843 BFD_RELOC_HI16_BASEREL
1845 BFD_RELOC_HI16_S_BASEREL
1851 Linkage-table relative.
1856 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1859 BFD_RELOC_32_PCREL_S2
1861 BFD_RELOC_16_PCREL_S2
1863 BFD_RELOC_23_PCREL_S2
1865 These PC-relative relocations are stored as word displacements --
1866 i.e., byte displacements shifted right two bits. The 30-bit word
1867 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1868 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1869 signed 16-bit displacement is used on the MIPS, and the 23-bit
1870 displacement is used on the Alpha.
1877 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1878 the target word. These are used on the SPARC.
1885 For systems that allocate a Global Pointer register, these are
1886 displacements off that register. These relocation types are
1887 handled specially, because the value the register will have is
1888 decided relatively late.
1893 BFD_RELOC_SPARC_WDISP22
1899 BFD_RELOC_SPARC_GOT10
1901 BFD_RELOC_SPARC_GOT13
1903 BFD_RELOC_SPARC_GOT22
1905 BFD_RELOC_SPARC_PC10
1907 BFD_RELOC_SPARC_PC22
1909 BFD_RELOC_SPARC_WPLT30
1911 BFD_RELOC_SPARC_COPY
1913 BFD_RELOC_SPARC_GLOB_DAT
1915 BFD_RELOC_SPARC_JMP_SLOT
1917 BFD_RELOC_SPARC_RELATIVE
1919 BFD_RELOC_SPARC_UA16
1921 BFD_RELOC_SPARC_UA32
1923 BFD_RELOC_SPARC_UA64
1925 BFD_RELOC_SPARC_GOTDATA_HIX22
1927 BFD_RELOC_SPARC_GOTDATA_LOX10
1929 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1931 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1933 BFD_RELOC_SPARC_GOTDATA_OP
1935 BFD_RELOC_SPARC_JMP_IREL
1937 BFD_RELOC_SPARC_IRELATIVE
1939 SPARC ELF relocations. There is probably some overlap with other
1940 relocation types already defined.
1943 BFD_RELOC_SPARC_BASE13
1945 BFD_RELOC_SPARC_BASE22
1947 I think these are specific to SPARC a.out (e.g., Sun 4).
1957 BFD_RELOC_SPARC_OLO10
1959 BFD_RELOC_SPARC_HH22
1961 BFD_RELOC_SPARC_HM10
1963 BFD_RELOC_SPARC_LM22
1965 BFD_RELOC_SPARC_PC_HH22
1967 BFD_RELOC_SPARC_PC_HM10
1969 BFD_RELOC_SPARC_PC_LM22
1971 BFD_RELOC_SPARC_WDISP16
1973 BFD_RELOC_SPARC_WDISP19
1981 BFD_RELOC_SPARC_DISP64
1984 BFD_RELOC_SPARC_PLT32
1986 BFD_RELOC_SPARC_PLT64
1988 BFD_RELOC_SPARC_HIX22
1990 BFD_RELOC_SPARC_LOX10
1998 BFD_RELOC_SPARC_REGISTER
2002 BFD_RELOC_SPARC_SIZE32
2004 BFD_RELOC_SPARC_SIZE64
2006 BFD_RELOC_SPARC_WDISP10
2011 BFD_RELOC_SPARC_REV32
2013 SPARC little endian relocation
2015 BFD_RELOC_SPARC_TLS_GD_HI22
2017 BFD_RELOC_SPARC_TLS_GD_LO10
2019 BFD_RELOC_SPARC_TLS_GD_ADD
2021 BFD_RELOC_SPARC_TLS_GD_CALL
2023 BFD_RELOC_SPARC_TLS_LDM_HI22
2025 BFD_RELOC_SPARC_TLS_LDM_LO10
2027 BFD_RELOC_SPARC_TLS_LDM_ADD
2029 BFD_RELOC_SPARC_TLS_LDM_CALL
2031 BFD_RELOC_SPARC_TLS_LDO_HIX22
2033 BFD_RELOC_SPARC_TLS_LDO_LOX10
2035 BFD_RELOC_SPARC_TLS_LDO_ADD
2037 BFD_RELOC_SPARC_TLS_IE_HI22
2039 BFD_RELOC_SPARC_TLS_IE_LO10
2041 BFD_RELOC_SPARC_TLS_IE_LD
2043 BFD_RELOC_SPARC_TLS_IE_LDX
2045 BFD_RELOC_SPARC_TLS_IE_ADD
2047 BFD_RELOC_SPARC_TLS_LE_HIX22
2049 BFD_RELOC_SPARC_TLS_LE_LOX10
2051 BFD_RELOC_SPARC_TLS_DTPMOD32
2053 BFD_RELOC_SPARC_TLS_DTPMOD64
2055 BFD_RELOC_SPARC_TLS_DTPOFF32
2057 BFD_RELOC_SPARC_TLS_DTPOFF64
2059 BFD_RELOC_SPARC_TLS_TPOFF32
2061 BFD_RELOC_SPARC_TLS_TPOFF64
2063 SPARC TLS relocations
2072 BFD_RELOC_SPU_IMM10W
2076 BFD_RELOC_SPU_IMM16W
2080 BFD_RELOC_SPU_PCREL9a
2082 BFD_RELOC_SPU_PCREL9b
2084 BFD_RELOC_SPU_PCREL16
2094 BFD_RELOC_SPU_ADD_PIC
2099 BFD_RELOC_ALPHA_GPDISP_HI16
2101 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2102 "addend" in some special way.
2103 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2104 writing; when reading, it will be the absolute section symbol. The
2105 addend is the displacement in bytes of the "lda" instruction from
2106 the "ldah" instruction (which is at the address of this reloc).
2108 BFD_RELOC_ALPHA_GPDISP_LO16
2110 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2111 with GPDISP_HI16 relocs. The addend is ignored when writing the
2112 relocations out, and is filled in with the file's GP value on
2113 reading, for convenience.
2116 BFD_RELOC_ALPHA_GPDISP
2118 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2119 relocation except that there is no accompanying GPDISP_LO16
2123 BFD_RELOC_ALPHA_LITERAL
2125 BFD_RELOC_ALPHA_ELF_LITERAL
2127 BFD_RELOC_ALPHA_LITUSE
2129 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2130 the assembler turns it into a LDQ instruction to load the address of
2131 the symbol, and then fills in a register in the real instruction.
2133 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2134 section symbol. The addend is ignored when writing, but is filled
2135 in with the file's GP value on reading, for convenience, as with the
2138 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2139 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2140 but it generates output not based on the position within the .got
2141 section, but relative to the GP value chosen for the file during the
2144 The LITUSE reloc, on the instruction using the loaded address, gives
2145 information to the linker that it might be able to use to optimize
2146 away some literal section references. The symbol is ignored (read
2147 as the absolute section symbol), and the "addend" indicates the type
2148 of instruction using the register:
2149 1 - "memory" fmt insn
2150 2 - byte-manipulation (byte offset reg)
2151 3 - jsr (target of branch)
2154 BFD_RELOC_ALPHA_HINT
2156 The HINT relocation indicates a value that should be filled into the
2157 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2158 prediction logic which may be provided on some processors.
2161 BFD_RELOC_ALPHA_LINKAGE
2163 The LINKAGE relocation outputs a linkage pair in the object file,
2164 which is filled by the linker.
2167 BFD_RELOC_ALPHA_CODEADDR
2169 The CODEADDR relocation outputs a STO_CA in the object file,
2170 which is filled by the linker.
2173 BFD_RELOC_ALPHA_GPREL_HI16
2175 BFD_RELOC_ALPHA_GPREL_LO16
2177 The GPREL_HI/LO relocations together form a 32-bit offset from the
2181 BFD_RELOC_ALPHA_BRSGP
2183 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2184 share a common GP, and the target address is adjusted for
2185 STO_ALPHA_STD_GPLOAD.
2190 The NOP relocation outputs a NOP if the longword displacement
2191 between two procedure entry points is < 2^21.
2196 The BSR relocation outputs a BSR if the longword displacement
2197 between two procedure entry points is < 2^21.
2202 The LDA relocation outputs a LDA if the longword displacement
2203 between two procedure entry points is < 2^16.
2208 The BOH relocation outputs a BSR if the longword displacement
2209 between two procedure entry points is < 2^21, or else a hint.
2212 BFD_RELOC_ALPHA_TLSGD
2214 BFD_RELOC_ALPHA_TLSLDM
2216 BFD_RELOC_ALPHA_DTPMOD64
2218 BFD_RELOC_ALPHA_GOTDTPREL16
2220 BFD_RELOC_ALPHA_DTPREL64
2222 BFD_RELOC_ALPHA_DTPREL_HI16
2224 BFD_RELOC_ALPHA_DTPREL_LO16
2226 BFD_RELOC_ALPHA_DTPREL16
2228 BFD_RELOC_ALPHA_GOTTPREL16
2230 BFD_RELOC_ALPHA_TPREL64
2232 BFD_RELOC_ALPHA_TPREL_HI16
2234 BFD_RELOC_ALPHA_TPREL_LO16
2236 BFD_RELOC_ALPHA_TPREL16
2238 Alpha thread-local storage relocations.
2243 BFD_RELOC_MICROMIPS_JMP
2245 The MIPS jump instruction.
2248 BFD_RELOC_MIPS16_JMP
2250 The MIPS16 jump instruction.
2253 BFD_RELOC_MIPS16_GPREL
2255 MIPS16 GP relative reloc.
2260 High 16 bits of 32-bit value; simple reloc.
2265 High 16 bits of 32-bit value but the low 16 bits will be sign
2266 extended and added to form the final result. If the low 16
2267 bits form a negative number, we need to add one to the high value
2268 to compensate for the borrow when the low bits are added.
2276 BFD_RELOC_HI16_PCREL
2278 High 16 bits of 32-bit pc-relative value
2280 BFD_RELOC_HI16_S_PCREL
2282 High 16 bits of 32-bit pc-relative value, adjusted
2284 BFD_RELOC_LO16_PCREL
2286 Low 16 bits of pc-relative value
2289 BFD_RELOC_MIPS16_GOT16
2291 BFD_RELOC_MIPS16_CALL16
2293 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2294 16-bit immediate fields
2296 BFD_RELOC_MIPS16_HI16
2298 MIPS16 high 16 bits of 32-bit value.
2300 BFD_RELOC_MIPS16_HI16_S
2302 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2303 extended and added to form the final result. If the low 16
2304 bits form a negative number, we need to add one to the high value
2305 to compensate for the borrow when the low bits are added.
2307 BFD_RELOC_MIPS16_LO16
2312 BFD_RELOC_MIPS16_TLS_GD
2314 BFD_RELOC_MIPS16_TLS_LDM
2316 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2318 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2320 BFD_RELOC_MIPS16_TLS_GOTTPREL
2322 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2324 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2326 MIPS16 TLS relocations
2329 BFD_RELOC_MIPS_LITERAL
2331 BFD_RELOC_MICROMIPS_LITERAL
2333 Relocation against a MIPS literal section.
2336 BFD_RELOC_MICROMIPS_7_PCREL_S1
2338 BFD_RELOC_MICROMIPS_10_PCREL_S1
2340 BFD_RELOC_MICROMIPS_16_PCREL_S1
2342 microMIPS PC-relative relocations.
2345 BFD_RELOC_MIPS16_16_PCREL_S1
2347 MIPS16 PC-relative relocation.
2350 BFD_RELOC_MIPS_21_PCREL_S2
2352 BFD_RELOC_MIPS_26_PCREL_S2
2354 BFD_RELOC_MIPS_18_PCREL_S3
2356 BFD_RELOC_MIPS_19_PCREL_S2
2358 MIPS PC-relative relocations.
2361 BFD_RELOC_MICROMIPS_GPREL16
2363 BFD_RELOC_MICROMIPS_HI16
2365 BFD_RELOC_MICROMIPS_HI16_S
2367 BFD_RELOC_MICROMIPS_LO16
2369 microMIPS versions of generic BFD relocs.
2372 BFD_RELOC_MIPS_GOT16
2374 BFD_RELOC_MICROMIPS_GOT16
2376 BFD_RELOC_MIPS_CALL16
2378 BFD_RELOC_MICROMIPS_CALL16
2380 BFD_RELOC_MIPS_GOT_HI16
2382 BFD_RELOC_MICROMIPS_GOT_HI16
2384 BFD_RELOC_MIPS_GOT_LO16
2386 BFD_RELOC_MICROMIPS_GOT_LO16
2388 BFD_RELOC_MIPS_CALL_HI16
2390 BFD_RELOC_MICROMIPS_CALL_HI16
2392 BFD_RELOC_MIPS_CALL_LO16
2394 BFD_RELOC_MICROMIPS_CALL_LO16
2398 BFD_RELOC_MICROMIPS_SUB
2400 BFD_RELOC_MIPS_GOT_PAGE
2402 BFD_RELOC_MICROMIPS_GOT_PAGE
2404 BFD_RELOC_MIPS_GOT_OFST
2406 BFD_RELOC_MICROMIPS_GOT_OFST
2408 BFD_RELOC_MIPS_GOT_DISP
2410 BFD_RELOC_MICROMIPS_GOT_DISP
2412 BFD_RELOC_MIPS_SHIFT5
2414 BFD_RELOC_MIPS_SHIFT6
2416 BFD_RELOC_MIPS_INSERT_A
2418 BFD_RELOC_MIPS_INSERT_B
2420 BFD_RELOC_MIPS_DELETE
2422 BFD_RELOC_MIPS_HIGHEST
2424 BFD_RELOC_MICROMIPS_HIGHEST
2426 BFD_RELOC_MIPS_HIGHER
2428 BFD_RELOC_MICROMIPS_HIGHER
2430 BFD_RELOC_MIPS_SCN_DISP
2432 BFD_RELOC_MICROMIPS_SCN_DISP
2434 BFD_RELOC_MIPS_REL16
2436 BFD_RELOC_MIPS_RELGOT
2440 BFD_RELOC_MICROMIPS_JALR
2442 BFD_RELOC_MIPS_TLS_DTPMOD32
2444 BFD_RELOC_MIPS_TLS_DTPREL32
2446 BFD_RELOC_MIPS_TLS_DTPMOD64
2448 BFD_RELOC_MIPS_TLS_DTPREL64
2450 BFD_RELOC_MIPS_TLS_GD
2452 BFD_RELOC_MICROMIPS_TLS_GD
2454 BFD_RELOC_MIPS_TLS_LDM
2456 BFD_RELOC_MICROMIPS_TLS_LDM
2458 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2460 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2462 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2464 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2466 BFD_RELOC_MIPS_TLS_GOTTPREL
2468 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2470 BFD_RELOC_MIPS_TLS_TPREL32
2472 BFD_RELOC_MIPS_TLS_TPREL64
2474 BFD_RELOC_MIPS_TLS_TPREL_HI16
2476 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2478 BFD_RELOC_MIPS_TLS_TPREL_LO16
2480 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2484 MIPS ELF relocations.
2490 BFD_RELOC_MIPS_JUMP_SLOT
2492 MIPS ELF relocations (VxWorks and PLT extensions).
2496 BFD_RELOC_MOXIE_10_PCREL
2498 Moxie ELF relocations.
2510 BFD_RELOC_FT32_RELAX
2518 BFD_RELOC_FT32_DIFF32
2520 FT32 ELF relocations.
2524 BFD_RELOC_FRV_LABEL16
2526 BFD_RELOC_FRV_LABEL24
2532 BFD_RELOC_FRV_GPREL12
2534 BFD_RELOC_FRV_GPRELU12
2536 BFD_RELOC_FRV_GPREL32
2538 BFD_RELOC_FRV_GPRELHI
2540 BFD_RELOC_FRV_GPRELLO
2548 BFD_RELOC_FRV_FUNCDESC
2550 BFD_RELOC_FRV_FUNCDESC_GOT12
2552 BFD_RELOC_FRV_FUNCDESC_GOTHI
2554 BFD_RELOC_FRV_FUNCDESC_GOTLO
2556 BFD_RELOC_FRV_FUNCDESC_VALUE
2558 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2560 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2562 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2564 BFD_RELOC_FRV_GOTOFF12
2566 BFD_RELOC_FRV_GOTOFFHI
2568 BFD_RELOC_FRV_GOTOFFLO
2570 BFD_RELOC_FRV_GETTLSOFF
2572 BFD_RELOC_FRV_TLSDESC_VALUE
2574 BFD_RELOC_FRV_GOTTLSDESC12
2576 BFD_RELOC_FRV_GOTTLSDESCHI
2578 BFD_RELOC_FRV_GOTTLSDESCLO
2580 BFD_RELOC_FRV_TLSMOFF12
2582 BFD_RELOC_FRV_TLSMOFFHI
2584 BFD_RELOC_FRV_TLSMOFFLO
2586 BFD_RELOC_FRV_GOTTLSOFF12
2588 BFD_RELOC_FRV_GOTTLSOFFHI
2590 BFD_RELOC_FRV_GOTTLSOFFLO
2592 BFD_RELOC_FRV_TLSOFF
2594 BFD_RELOC_FRV_TLSDESC_RELAX
2596 BFD_RELOC_FRV_GETTLSOFF_RELAX
2598 BFD_RELOC_FRV_TLSOFF_RELAX
2600 BFD_RELOC_FRV_TLSMOFF
2602 Fujitsu Frv Relocations.
2606 BFD_RELOC_MN10300_GOTOFF24
2608 This is a 24bit GOT-relative reloc for the mn10300.
2610 BFD_RELOC_MN10300_GOT32
2612 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2615 BFD_RELOC_MN10300_GOT24
2617 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2620 BFD_RELOC_MN10300_GOT16
2622 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2625 BFD_RELOC_MN10300_COPY
2627 Copy symbol at runtime.
2629 BFD_RELOC_MN10300_GLOB_DAT
2633 BFD_RELOC_MN10300_JMP_SLOT
2637 BFD_RELOC_MN10300_RELATIVE
2639 Adjust by program base.
2641 BFD_RELOC_MN10300_SYM_DIFF
2643 Together with another reloc targeted at the same location,
2644 allows for a value that is the difference of two symbols
2645 in the same section.
2647 BFD_RELOC_MN10300_ALIGN
2649 The addend of this reloc is an alignment power that must
2650 be honoured at the offset's location, regardless of linker
2653 BFD_RELOC_MN10300_TLS_GD
2655 BFD_RELOC_MN10300_TLS_LD
2657 BFD_RELOC_MN10300_TLS_LDO
2659 BFD_RELOC_MN10300_TLS_GOTIE
2661 BFD_RELOC_MN10300_TLS_IE
2663 BFD_RELOC_MN10300_TLS_LE
2665 BFD_RELOC_MN10300_TLS_DTPMOD
2667 BFD_RELOC_MN10300_TLS_DTPOFF
2669 BFD_RELOC_MN10300_TLS_TPOFF
2671 Various TLS-related relocations.
2673 BFD_RELOC_MN10300_32_PCREL
2675 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2678 BFD_RELOC_MN10300_16_PCREL
2680 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2691 BFD_RELOC_386_GLOB_DAT
2693 BFD_RELOC_386_JUMP_SLOT
2695 BFD_RELOC_386_RELATIVE
2697 BFD_RELOC_386_GOTOFF
2701 BFD_RELOC_386_TLS_TPOFF
2703 BFD_RELOC_386_TLS_IE
2705 BFD_RELOC_386_TLS_GOTIE
2707 BFD_RELOC_386_TLS_LE
2709 BFD_RELOC_386_TLS_GD
2711 BFD_RELOC_386_TLS_LDM
2713 BFD_RELOC_386_TLS_LDO_32
2715 BFD_RELOC_386_TLS_IE_32
2717 BFD_RELOC_386_TLS_LE_32
2719 BFD_RELOC_386_TLS_DTPMOD32
2721 BFD_RELOC_386_TLS_DTPOFF32
2723 BFD_RELOC_386_TLS_TPOFF32
2725 BFD_RELOC_386_TLS_GOTDESC
2727 BFD_RELOC_386_TLS_DESC_CALL
2729 BFD_RELOC_386_TLS_DESC
2731 BFD_RELOC_386_IRELATIVE
2733 BFD_RELOC_386_GOT32X
2735 i386/elf relocations
2738 BFD_RELOC_X86_64_GOT32
2740 BFD_RELOC_X86_64_PLT32
2742 BFD_RELOC_X86_64_COPY
2744 BFD_RELOC_X86_64_GLOB_DAT
2746 BFD_RELOC_X86_64_JUMP_SLOT
2748 BFD_RELOC_X86_64_RELATIVE
2750 BFD_RELOC_X86_64_GOTPCREL
2752 BFD_RELOC_X86_64_32S
2754 BFD_RELOC_X86_64_DTPMOD64
2756 BFD_RELOC_X86_64_DTPOFF64
2758 BFD_RELOC_X86_64_TPOFF64
2760 BFD_RELOC_X86_64_TLSGD
2762 BFD_RELOC_X86_64_TLSLD
2764 BFD_RELOC_X86_64_DTPOFF32
2766 BFD_RELOC_X86_64_GOTTPOFF
2768 BFD_RELOC_X86_64_TPOFF32
2770 BFD_RELOC_X86_64_GOTOFF64
2772 BFD_RELOC_X86_64_GOTPC32
2774 BFD_RELOC_X86_64_GOT64
2776 BFD_RELOC_X86_64_GOTPCREL64
2778 BFD_RELOC_X86_64_GOTPC64
2780 BFD_RELOC_X86_64_GOTPLT64
2782 BFD_RELOC_X86_64_PLTOFF64
2784 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2786 BFD_RELOC_X86_64_TLSDESC_CALL
2788 BFD_RELOC_X86_64_TLSDESC
2790 BFD_RELOC_X86_64_IRELATIVE
2792 BFD_RELOC_X86_64_PC32_BND
2794 BFD_RELOC_X86_64_PLT32_BND
2796 BFD_RELOC_X86_64_GOTPCRELX
2798 BFD_RELOC_X86_64_REX_GOTPCRELX
2800 x86-64/elf relocations
2803 BFD_RELOC_NS32K_IMM_8
2805 BFD_RELOC_NS32K_IMM_16
2807 BFD_RELOC_NS32K_IMM_32
2809 BFD_RELOC_NS32K_IMM_8_PCREL
2811 BFD_RELOC_NS32K_IMM_16_PCREL
2813 BFD_RELOC_NS32K_IMM_32_PCREL
2815 BFD_RELOC_NS32K_DISP_8
2817 BFD_RELOC_NS32K_DISP_16
2819 BFD_RELOC_NS32K_DISP_32
2821 BFD_RELOC_NS32K_DISP_8_PCREL
2823 BFD_RELOC_NS32K_DISP_16_PCREL
2825 BFD_RELOC_NS32K_DISP_32_PCREL
2830 BFD_RELOC_PDP11_DISP_8_PCREL
2832 BFD_RELOC_PDP11_DISP_6_PCREL
2837 BFD_RELOC_PJ_CODE_HI16
2839 BFD_RELOC_PJ_CODE_LO16
2841 BFD_RELOC_PJ_CODE_DIR16
2843 BFD_RELOC_PJ_CODE_DIR32
2845 BFD_RELOC_PJ_CODE_REL16
2847 BFD_RELOC_PJ_CODE_REL32
2849 Picojava relocs. Not all of these appear in object files.
2860 BFD_RELOC_PPC_B16_BRTAKEN
2862 BFD_RELOC_PPC_B16_BRNTAKEN
2866 BFD_RELOC_PPC_BA16_BRTAKEN
2868 BFD_RELOC_PPC_BA16_BRNTAKEN
2872 BFD_RELOC_PPC_GLOB_DAT
2874 BFD_RELOC_PPC_JMP_SLOT
2876 BFD_RELOC_PPC_RELATIVE
2878 BFD_RELOC_PPC_LOCAL24PC
2880 BFD_RELOC_PPC_EMB_NADDR32
2882 BFD_RELOC_PPC_EMB_NADDR16
2884 BFD_RELOC_PPC_EMB_NADDR16_LO
2886 BFD_RELOC_PPC_EMB_NADDR16_HI
2888 BFD_RELOC_PPC_EMB_NADDR16_HA
2890 BFD_RELOC_PPC_EMB_SDAI16
2892 BFD_RELOC_PPC_EMB_SDA2I16
2894 BFD_RELOC_PPC_EMB_SDA2REL
2896 BFD_RELOC_PPC_EMB_SDA21
2898 BFD_RELOC_PPC_EMB_MRKREF
2900 BFD_RELOC_PPC_EMB_RELSEC16
2902 BFD_RELOC_PPC_EMB_RELST_LO
2904 BFD_RELOC_PPC_EMB_RELST_HI
2906 BFD_RELOC_PPC_EMB_RELST_HA
2908 BFD_RELOC_PPC_EMB_BIT_FLD
2910 BFD_RELOC_PPC_EMB_RELSDA
2912 BFD_RELOC_PPC_VLE_REL8
2914 BFD_RELOC_PPC_VLE_REL15
2916 BFD_RELOC_PPC_VLE_REL24
2918 BFD_RELOC_PPC_VLE_LO16A
2920 BFD_RELOC_PPC_VLE_LO16D
2922 BFD_RELOC_PPC_VLE_HI16A
2924 BFD_RELOC_PPC_VLE_HI16D
2926 BFD_RELOC_PPC_VLE_HA16A
2928 BFD_RELOC_PPC_VLE_HA16D
2930 BFD_RELOC_PPC_VLE_SDA21
2932 BFD_RELOC_PPC_VLE_SDA21_LO
2934 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2936 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2938 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2940 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2942 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2944 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2946 BFD_RELOC_PPC_16DX_HA
2948 BFD_RELOC_PPC_REL16DX_HA
2950 BFD_RELOC_PPC64_HIGHER
2952 BFD_RELOC_PPC64_HIGHER_S
2954 BFD_RELOC_PPC64_HIGHEST
2956 BFD_RELOC_PPC64_HIGHEST_S
2958 BFD_RELOC_PPC64_TOC16_LO
2960 BFD_RELOC_PPC64_TOC16_HI
2962 BFD_RELOC_PPC64_TOC16_HA
2966 BFD_RELOC_PPC64_PLTGOT16
2968 BFD_RELOC_PPC64_PLTGOT16_LO
2970 BFD_RELOC_PPC64_PLTGOT16_HI
2972 BFD_RELOC_PPC64_PLTGOT16_HA
2974 BFD_RELOC_PPC64_ADDR16_DS
2976 BFD_RELOC_PPC64_ADDR16_LO_DS
2978 BFD_RELOC_PPC64_GOT16_DS
2980 BFD_RELOC_PPC64_GOT16_LO_DS
2982 BFD_RELOC_PPC64_PLT16_LO_DS
2984 BFD_RELOC_PPC64_SECTOFF_DS
2986 BFD_RELOC_PPC64_SECTOFF_LO_DS
2988 BFD_RELOC_PPC64_TOC16_DS
2990 BFD_RELOC_PPC64_TOC16_LO_DS
2992 BFD_RELOC_PPC64_PLTGOT16_DS
2994 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2996 BFD_RELOC_PPC64_ADDR16_HIGH
2998 BFD_RELOC_PPC64_ADDR16_HIGHA
3000 BFD_RELOC_PPC64_ADDR64_LOCAL
3002 BFD_RELOC_PPC64_ENTRY
3004 Power(rs6000) and PowerPC relocations.
3013 BFD_RELOC_PPC_DTPMOD
3015 BFD_RELOC_PPC_TPREL16
3017 BFD_RELOC_PPC_TPREL16_LO
3019 BFD_RELOC_PPC_TPREL16_HI
3021 BFD_RELOC_PPC_TPREL16_HA
3025 BFD_RELOC_PPC_DTPREL16
3027 BFD_RELOC_PPC_DTPREL16_LO
3029 BFD_RELOC_PPC_DTPREL16_HI
3031 BFD_RELOC_PPC_DTPREL16_HA
3033 BFD_RELOC_PPC_DTPREL
3035 BFD_RELOC_PPC_GOT_TLSGD16
3037 BFD_RELOC_PPC_GOT_TLSGD16_LO
3039 BFD_RELOC_PPC_GOT_TLSGD16_HI
3041 BFD_RELOC_PPC_GOT_TLSGD16_HA
3043 BFD_RELOC_PPC_GOT_TLSLD16
3045 BFD_RELOC_PPC_GOT_TLSLD16_LO
3047 BFD_RELOC_PPC_GOT_TLSLD16_HI
3049 BFD_RELOC_PPC_GOT_TLSLD16_HA
3051 BFD_RELOC_PPC_GOT_TPREL16
3053 BFD_RELOC_PPC_GOT_TPREL16_LO
3055 BFD_RELOC_PPC_GOT_TPREL16_HI
3057 BFD_RELOC_PPC_GOT_TPREL16_HA
3059 BFD_RELOC_PPC_GOT_DTPREL16
3061 BFD_RELOC_PPC_GOT_DTPREL16_LO
3063 BFD_RELOC_PPC_GOT_DTPREL16_HI
3065 BFD_RELOC_PPC_GOT_DTPREL16_HA
3067 BFD_RELOC_PPC64_TPREL16_DS
3069 BFD_RELOC_PPC64_TPREL16_LO_DS
3071 BFD_RELOC_PPC64_TPREL16_HIGHER
3073 BFD_RELOC_PPC64_TPREL16_HIGHERA
3075 BFD_RELOC_PPC64_TPREL16_HIGHEST
3077 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3079 BFD_RELOC_PPC64_DTPREL16_DS
3081 BFD_RELOC_PPC64_DTPREL16_LO_DS
3083 BFD_RELOC_PPC64_DTPREL16_HIGHER
3085 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3087 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3089 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3091 BFD_RELOC_PPC64_TPREL16_HIGH
3093 BFD_RELOC_PPC64_TPREL16_HIGHA
3095 BFD_RELOC_PPC64_DTPREL16_HIGH
3097 BFD_RELOC_PPC64_DTPREL16_HIGHA
3099 PowerPC and PowerPC64 thread-local storage relocations.
3104 IBM 370/390 relocations
3109 The type of reloc used to build a constructor table - at the moment
3110 probably a 32 bit wide absolute relocation, but the target can choose.
3111 It generally does map to one of the other relocation types.
3114 BFD_RELOC_ARM_PCREL_BRANCH
3116 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3117 not stored in the instruction.
3119 BFD_RELOC_ARM_PCREL_BLX
3121 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3122 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3123 field in the instruction.
3125 BFD_RELOC_THUMB_PCREL_BLX
3127 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3128 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3129 field in the instruction.
3131 BFD_RELOC_ARM_PCREL_CALL
3133 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3135 BFD_RELOC_ARM_PCREL_JUMP
3137 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3140 BFD_RELOC_THUMB_PCREL_BRANCH7
3142 BFD_RELOC_THUMB_PCREL_BRANCH9
3144 BFD_RELOC_THUMB_PCREL_BRANCH12
3146 BFD_RELOC_THUMB_PCREL_BRANCH20
3148 BFD_RELOC_THUMB_PCREL_BRANCH23
3150 BFD_RELOC_THUMB_PCREL_BRANCH25
3152 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3153 The lowest bit must be zero and is not stored in the instruction.
3154 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3155 "nn" one smaller in all cases. Note further that BRANCH23
3156 corresponds to R_ARM_THM_CALL.
3159 BFD_RELOC_ARM_OFFSET_IMM
3161 12-bit immediate offset, used in ARM-format ldr and str instructions.
3164 BFD_RELOC_ARM_THUMB_OFFSET
3166 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3169 BFD_RELOC_ARM_TARGET1
3171 Pc-relative or absolute relocation depending on target. Used for
3172 entries in .init_array sections.
3174 BFD_RELOC_ARM_ROSEGREL32
3176 Read-only segment base relative address.
3178 BFD_RELOC_ARM_SBREL32
3180 Data segment base relative address.
3182 BFD_RELOC_ARM_TARGET2
3184 This reloc is used for references to RTTI data from exception handling
3185 tables. The actual definition depends on the target. It may be a
3186 pc-relative or some form of GOT-indirect relocation.
3188 BFD_RELOC_ARM_PREL31
3190 31-bit PC relative address.
3196 BFD_RELOC_ARM_MOVW_PCREL
3198 BFD_RELOC_ARM_MOVT_PCREL
3200 BFD_RELOC_ARM_THUMB_MOVW
3202 BFD_RELOC_ARM_THUMB_MOVT
3204 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3206 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3208 Low and High halfword relocations for MOVW and MOVT instructions.
3211 BFD_RELOC_ARM_GOTFUNCDESC
3213 BFD_RELOC_ARM_GOTOFFFUNCDESC
3215 BFD_RELOC_ARM_FUNCDESC
3217 BFD_RELOC_ARM_FUNCDESC_VALUE
3219 ARM FDPIC specific relocations.
3222 BFD_RELOC_ARM_JUMP_SLOT
3224 BFD_RELOC_ARM_GLOB_DAT
3230 BFD_RELOC_ARM_RELATIVE
3232 BFD_RELOC_ARM_GOTOFF
3236 BFD_RELOC_ARM_GOT_PREL
3238 Relocations for setting up GOTs and PLTs for shared libraries.
3241 BFD_RELOC_ARM_TLS_GD32
3243 BFD_RELOC_ARM_TLS_LDO32
3245 BFD_RELOC_ARM_TLS_LDM32
3247 BFD_RELOC_ARM_TLS_DTPOFF32
3249 BFD_RELOC_ARM_TLS_DTPMOD32
3251 BFD_RELOC_ARM_TLS_TPOFF32
3253 BFD_RELOC_ARM_TLS_IE32
3255 BFD_RELOC_ARM_TLS_LE32
3257 BFD_RELOC_ARM_TLS_GOTDESC
3259 BFD_RELOC_ARM_TLS_CALL
3261 BFD_RELOC_ARM_THM_TLS_CALL
3263 BFD_RELOC_ARM_TLS_DESCSEQ
3265 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3267 BFD_RELOC_ARM_TLS_DESC
3269 ARM thread-local storage relocations.
3272 BFD_RELOC_ARM_ALU_PC_G0_NC
3274 BFD_RELOC_ARM_ALU_PC_G0
3276 BFD_RELOC_ARM_ALU_PC_G1_NC
3278 BFD_RELOC_ARM_ALU_PC_G1
3280 BFD_RELOC_ARM_ALU_PC_G2
3282 BFD_RELOC_ARM_LDR_PC_G0
3284 BFD_RELOC_ARM_LDR_PC_G1
3286 BFD_RELOC_ARM_LDR_PC_G2
3288 BFD_RELOC_ARM_LDRS_PC_G0
3290 BFD_RELOC_ARM_LDRS_PC_G1
3292 BFD_RELOC_ARM_LDRS_PC_G2
3294 BFD_RELOC_ARM_LDC_PC_G0
3296 BFD_RELOC_ARM_LDC_PC_G1
3298 BFD_RELOC_ARM_LDC_PC_G2
3300 BFD_RELOC_ARM_ALU_SB_G0_NC
3302 BFD_RELOC_ARM_ALU_SB_G0
3304 BFD_RELOC_ARM_ALU_SB_G1_NC
3306 BFD_RELOC_ARM_ALU_SB_G1
3308 BFD_RELOC_ARM_ALU_SB_G2
3310 BFD_RELOC_ARM_LDR_SB_G0
3312 BFD_RELOC_ARM_LDR_SB_G1
3314 BFD_RELOC_ARM_LDR_SB_G2
3316 BFD_RELOC_ARM_LDRS_SB_G0
3318 BFD_RELOC_ARM_LDRS_SB_G1
3320 BFD_RELOC_ARM_LDRS_SB_G2
3322 BFD_RELOC_ARM_LDC_SB_G0
3324 BFD_RELOC_ARM_LDC_SB_G1
3326 BFD_RELOC_ARM_LDC_SB_G2
3328 ARM group relocations.
3333 Annotation of BX instructions.
3336 BFD_RELOC_ARM_IRELATIVE
3338 ARM support for STT_GNU_IFUNC.
3341 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3343 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3345 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3347 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3349 Thumb1 relocations to support execute-only code.
3352 BFD_RELOC_ARM_IMMEDIATE
3354 BFD_RELOC_ARM_ADRL_IMMEDIATE
3356 BFD_RELOC_ARM_T32_IMMEDIATE
3358 BFD_RELOC_ARM_T32_ADD_IMM
3360 BFD_RELOC_ARM_T32_IMM12
3362 BFD_RELOC_ARM_T32_ADD_PC12
3364 BFD_RELOC_ARM_SHIFT_IMM
3374 BFD_RELOC_ARM_CP_OFF_IMM
3376 BFD_RELOC_ARM_CP_OFF_IMM_S2
3378 BFD_RELOC_ARM_T32_CP_OFF_IMM
3380 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3382 BFD_RELOC_ARM_ADR_IMM
3384 BFD_RELOC_ARM_LDR_IMM
3386 BFD_RELOC_ARM_LITERAL
3388 BFD_RELOC_ARM_IN_POOL
3390 BFD_RELOC_ARM_OFFSET_IMM8
3392 BFD_RELOC_ARM_T32_OFFSET_U8
3394 BFD_RELOC_ARM_T32_OFFSET_IMM
3396 BFD_RELOC_ARM_HWLITERAL
3398 BFD_RELOC_ARM_THUMB_ADD
3400 BFD_RELOC_ARM_THUMB_IMM
3402 BFD_RELOC_ARM_THUMB_SHIFT
3404 These relocs are only used within the ARM assembler. They are not
3405 (at present) written to any object files.
3408 BFD_RELOC_SH_PCDISP8BY2
3410 BFD_RELOC_SH_PCDISP12BY2
3418 BFD_RELOC_SH_DISP12BY2
3420 BFD_RELOC_SH_DISP12BY4
3422 BFD_RELOC_SH_DISP12BY8
3426 BFD_RELOC_SH_DISP20BY8
3430 BFD_RELOC_SH_IMM4BY2
3432 BFD_RELOC_SH_IMM4BY4
3436 BFD_RELOC_SH_IMM8BY2
3438 BFD_RELOC_SH_IMM8BY4
3440 BFD_RELOC_SH_PCRELIMM8BY2
3442 BFD_RELOC_SH_PCRELIMM8BY4
3444 BFD_RELOC_SH_SWITCH16
3446 BFD_RELOC_SH_SWITCH32
3460 BFD_RELOC_SH_LOOP_START
3462 BFD_RELOC_SH_LOOP_END
3466 BFD_RELOC_SH_GLOB_DAT
3468 BFD_RELOC_SH_JMP_SLOT
3470 BFD_RELOC_SH_RELATIVE
3474 BFD_RELOC_SH_GOT_LOW16
3476 BFD_RELOC_SH_GOT_MEDLOW16
3478 BFD_RELOC_SH_GOT_MEDHI16
3480 BFD_RELOC_SH_GOT_HI16
3482 BFD_RELOC_SH_GOTPLT_LOW16
3484 BFD_RELOC_SH_GOTPLT_MEDLOW16
3486 BFD_RELOC_SH_GOTPLT_MEDHI16
3488 BFD_RELOC_SH_GOTPLT_HI16
3490 BFD_RELOC_SH_PLT_LOW16
3492 BFD_RELOC_SH_PLT_MEDLOW16
3494 BFD_RELOC_SH_PLT_MEDHI16
3496 BFD_RELOC_SH_PLT_HI16
3498 BFD_RELOC_SH_GOTOFF_LOW16
3500 BFD_RELOC_SH_GOTOFF_MEDLOW16
3502 BFD_RELOC_SH_GOTOFF_MEDHI16
3504 BFD_RELOC_SH_GOTOFF_HI16
3506 BFD_RELOC_SH_GOTPC_LOW16
3508 BFD_RELOC_SH_GOTPC_MEDLOW16
3510 BFD_RELOC_SH_GOTPC_MEDHI16
3512 BFD_RELOC_SH_GOTPC_HI16
3516 BFD_RELOC_SH_GLOB_DAT64
3518 BFD_RELOC_SH_JMP_SLOT64
3520 BFD_RELOC_SH_RELATIVE64
3522 BFD_RELOC_SH_GOT10BY4
3524 BFD_RELOC_SH_GOT10BY8
3526 BFD_RELOC_SH_GOTPLT10BY4
3528 BFD_RELOC_SH_GOTPLT10BY8
3530 BFD_RELOC_SH_GOTPLT32
3532 BFD_RELOC_SH_SHMEDIA_CODE
3538 BFD_RELOC_SH_IMMS6BY32
3544 BFD_RELOC_SH_IMMS10BY2
3546 BFD_RELOC_SH_IMMS10BY4
3548 BFD_RELOC_SH_IMMS10BY8
3554 BFD_RELOC_SH_IMM_LOW16
3556 BFD_RELOC_SH_IMM_LOW16_PCREL
3558 BFD_RELOC_SH_IMM_MEDLOW16
3560 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3562 BFD_RELOC_SH_IMM_MEDHI16
3564 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3566 BFD_RELOC_SH_IMM_HI16
3568 BFD_RELOC_SH_IMM_HI16_PCREL
3572 BFD_RELOC_SH_TLS_GD_32
3574 BFD_RELOC_SH_TLS_LD_32
3576 BFD_RELOC_SH_TLS_LDO_32
3578 BFD_RELOC_SH_TLS_IE_32
3580 BFD_RELOC_SH_TLS_LE_32
3582 BFD_RELOC_SH_TLS_DTPMOD32
3584 BFD_RELOC_SH_TLS_DTPOFF32
3586 BFD_RELOC_SH_TLS_TPOFF32
3590 BFD_RELOC_SH_GOTOFF20
3592 BFD_RELOC_SH_GOTFUNCDESC
3594 BFD_RELOC_SH_GOTFUNCDESC20
3596 BFD_RELOC_SH_GOTOFFFUNCDESC
3598 BFD_RELOC_SH_GOTOFFFUNCDESC20
3600 BFD_RELOC_SH_FUNCDESC
3602 Renesas / SuperH SH relocs. Not all of these appear in object files.
3625 BFD_RELOC_ARC_SECTOFF
3627 BFD_RELOC_ARC_S21H_PCREL
3629 BFD_RELOC_ARC_S21W_PCREL
3631 BFD_RELOC_ARC_S25H_PCREL
3633 BFD_RELOC_ARC_S25W_PCREL
3637 BFD_RELOC_ARC_SDA_LDST
3639 BFD_RELOC_ARC_SDA_LDST1
3641 BFD_RELOC_ARC_SDA_LDST2
3643 BFD_RELOC_ARC_SDA16_LD
3645 BFD_RELOC_ARC_SDA16_LD1
3647 BFD_RELOC_ARC_SDA16_LD2
3649 BFD_RELOC_ARC_S13_PCREL
3655 BFD_RELOC_ARC_32_ME_S
3657 BFD_RELOC_ARC_N32_ME
3659 BFD_RELOC_ARC_SECTOFF_ME
3661 BFD_RELOC_ARC_SDA32_ME
3665 BFD_RELOC_AC_SECTOFF_U8
3667 BFD_RELOC_AC_SECTOFF_U8_1
3669 BFD_RELOC_AC_SECTOFF_U8_2
3671 BFD_RELOC_AC_SECTOFF_S9
3673 BFD_RELOC_AC_SECTOFF_S9_1
3675 BFD_RELOC_AC_SECTOFF_S9_2
3677 BFD_RELOC_ARC_SECTOFF_ME_1
3679 BFD_RELOC_ARC_SECTOFF_ME_2
3681 BFD_RELOC_ARC_SECTOFF_1
3683 BFD_RELOC_ARC_SECTOFF_2
3685 BFD_RELOC_ARC_SDA_12
3687 BFD_RELOC_ARC_SDA16_ST2
3689 BFD_RELOC_ARC_32_PCREL
3695 BFD_RELOC_ARC_GOTPC32
3701 BFD_RELOC_ARC_GLOB_DAT
3703 BFD_RELOC_ARC_JMP_SLOT
3705 BFD_RELOC_ARC_RELATIVE
3707 BFD_RELOC_ARC_GOTOFF
3711 BFD_RELOC_ARC_S21W_PCREL_PLT
3713 BFD_RELOC_ARC_S25H_PCREL_PLT
3715 BFD_RELOC_ARC_TLS_DTPMOD
3717 BFD_RELOC_ARC_TLS_TPOFF
3719 BFD_RELOC_ARC_TLS_GD_GOT
3721 BFD_RELOC_ARC_TLS_GD_LD
3723 BFD_RELOC_ARC_TLS_GD_CALL
3725 BFD_RELOC_ARC_TLS_IE_GOT
3727 BFD_RELOC_ARC_TLS_DTPOFF
3729 BFD_RELOC_ARC_TLS_DTPOFF_S9
3731 BFD_RELOC_ARC_TLS_LE_S9
3733 BFD_RELOC_ARC_TLS_LE_32
3735 BFD_RELOC_ARC_S25W_PCREL_PLT
3737 BFD_RELOC_ARC_S21H_PCREL_PLT
3739 BFD_RELOC_ARC_NPS_CMEM16
3741 BFD_RELOC_ARC_JLI_SECTOFF
3746 BFD_RELOC_BFIN_16_IMM
3748 ADI Blackfin 16 bit immediate absolute reloc.
3750 BFD_RELOC_BFIN_16_HIGH
3752 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3754 BFD_RELOC_BFIN_4_PCREL
3756 ADI Blackfin 'a' part of LSETUP.
3758 BFD_RELOC_BFIN_5_PCREL
3762 BFD_RELOC_BFIN_16_LOW
3764 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3766 BFD_RELOC_BFIN_10_PCREL
3770 BFD_RELOC_BFIN_11_PCREL
3772 ADI Blackfin 'b' part of LSETUP.
3774 BFD_RELOC_BFIN_12_PCREL_JUMP
3778 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3780 ADI Blackfin Short jump, pcrel.
3782 BFD_RELOC_BFIN_24_PCREL_CALL_X
3784 ADI Blackfin Call.x not implemented.
3786 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3788 ADI Blackfin Long Jump pcrel.
3790 BFD_RELOC_BFIN_GOT17M4
3792 BFD_RELOC_BFIN_GOTHI
3794 BFD_RELOC_BFIN_GOTLO
3796 BFD_RELOC_BFIN_FUNCDESC
3798 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3800 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3802 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3804 BFD_RELOC_BFIN_FUNCDESC_VALUE
3806 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3808 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3810 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3812 BFD_RELOC_BFIN_GOTOFF17M4
3814 BFD_RELOC_BFIN_GOTOFFHI
3816 BFD_RELOC_BFIN_GOTOFFLO
3818 ADI Blackfin FD-PIC relocations.
3822 ADI Blackfin GOT relocation.
3824 BFD_RELOC_BFIN_PLTPC
3826 ADI Blackfin PLTPC relocation.
3828 BFD_ARELOC_BFIN_PUSH
3830 ADI Blackfin arithmetic relocation.
3832 BFD_ARELOC_BFIN_CONST
3834 ADI Blackfin arithmetic relocation.
3838 ADI Blackfin arithmetic relocation.
3842 ADI Blackfin arithmetic relocation.
3844 BFD_ARELOC_BFIN_MULT
3846 ADI Blackfin arithmetic relocation.
3850 ADI Blackfin arithmetic relocation.
3854 ADI Blackfin arithmetic relocation.
3856 BFD_ARELOC_BFIN_LSHIFT
3858 ADI Blackfin arithmetic relocation.
3860 BFD_ARELOC_BFIN_RSHIFT
3862 ADI Blackfin arithmetic relocation.
3866 ADI Blackfin arithmetic relocation.
3870 ADI Blackfin arithmetic relocation.
3874 ADI Blackfin arithmetic relocation.
3876 BFD_ARELOC_BFIN_LAND
3878 ADI Blackfin arithmetic relocation.
3882 ADI Blackfin arithmetic relocation.
3886 ADI Blackfin arithmetic relocation.
3890 ADI Blackfin arithmetic relocation.
3892 BFD_ARELOC_BFIN_COMP
3894 ADI Blackfin arithmetic relocation.
3896 BFD_ARELOC_BFIN_PAGE
3898 ADI Blackfin arithmetic relocation.
3900 BFD_ARELOC_BFIN_HWPAGE
3902 ADI Blackfin arithmetic relocation.
3904 BFD_ARELOC_BFIN_ADDR
3906 ADI Blackfin arithmetic relocation.
3909 BFD_RELOC_D10V_10_PCREL_R
3911 Mitsubishi D10V relocs.
3912 This is a 10-bit reloc with the right 2 bits
3915 BFD_RELOC_D10V_10_PCREL_L
3917 Mitsubishi D10V relocs.
3918 This is a 10-bit reloc with the right 2 bits
3919 assumed to be 0. This is the same as the previous reloc
3920 except it is in the left container, i.e.,
3921 shifted left 15 bits.
3925 This is an 18-bit reloc with the right 2 bits
3928 BFD_RELOC_D10V_18_PCREL
3930 This is an 18-bit reloc with the right 2 bits
3936 Mitsubishi D30V relocs.
3937 This is a 6-bit absolute reloc.
3939 BFD_RELOC_D30V_9_PCREL
3941 This is a 6-bit pc-relative reloc with
3942 the right 3 bits assumed to be 0.
3944 BFD_RELOC_D30V_9_PCREL_R
3946 This is a 6-bit pc-relative reloc with
3947 the right 3 bits assumed to be 0. Same
3948 as the previous reloc but on the right side
3953 This is a 12-bit absolute reloc with the
3954 right 3 bitsassumed to be 0.
3956 BFD_RELOC_D30V_15_PCREL
3958 This is a 12-bit pc-relative reloc with
3959 the right 3 bits assumed to be 0.
3961 BFD_RELOC_D30V_15_PCREL_R
3963 This is a 12-bit pc-relative reloc with
3964 the right 3 bits assumed to be 0. Same
3965 as the previous reloc but on the right side
3970 This is an 18-bit absolute reloc with
3971 the right 3 bits assumed to be 0.
3973 BFD_RELOC_D30V_21_PCREL
3975 This is an 18-bit pc-relative reloc with
3976 the right 3 bits assumed to be 0.
3978 BFD_RELOC_D30V_21_PCREL_R
3980 This is an 18-bit pc-relative reloc with
3981 the right 3 bits assumed to be 0. Same
3982 as the previous reloc but on the right side
3987 This is a 32-bit absolute reloc.
3989 BFD_RELOC_D30V_32_PCREL
3991 This is a 32-bit pc-relative reloc.
3994 BFD_RELOC_DLX_HI16_S
4009 BFD_RELOC_M32C_RL_JUMP
4011 BFD_RELOC_M32C_RL_1ADDR
4013 BFD_RELOC_M32C_RL_2ADDR
4015 Renesas M16C/M32C Relocations.
4020 Renesas M32R (formerly Mitsubishi M32R) relocs.
4021 This is a 24 bit absolute address.
4023 BFD_RELOC_M32R_10_PCREL
4025 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4027 BFD_RELOC_M32R_18_PCREL
4029 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4031 BFD_RELOC_M32R_26_PCREL
4033 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4035 BFD_RELOC_M32R_HI16_ULO
4037 This is a 16-bit reloc containing the high 16 bits of an address
4038 used when the lower 16 bits are treated as unsigned.
4040 BFD_RELOC_M32R_HI16_SLO
4042 This is a 16-bit reloc containing the high 16 bits of an address
4043 used when the lower 16 bits are treated as signed.
4047 This is a 16-bit reloc containing the lower 16 bits of an address.
4049 BFD_RELOC_M32R_SDA16
4051 This is a 16-bit reloc containing the small data area offset for use in
4052 add3, load, and store instructions.
4054 BFD_RELOC_M32R_GOT24
4056 BFD_RELOC_M32R_26_PLTREL
4060 BFD_RELOC_M32R_GLOB_DAT
4062 BFD_RELOC_M32R_JMP_SLOT
4064 BFD_RELOC_M32R_RELATIVE
4066 BFD_RELOC_M32R_GOTOFF
4068 BFD_RELOC_M32R_GOTOFF_HI_ULO
4070 BFD_RELOC_M32R_GOTOFF_HI_SLO
4072 BFD_RELOC_M32R_GOTOFF_LO
4074 BFD_RELOC_M32R_GOTPC24
4076 BFD_RELOC_M32R_GOT16_HI_ULO
4078 BFD_RELOC_M32R_GOT16_HI_SLO
4080 BFD_RELOC_M32R_GOT16_LO
4082 BFD_RELOC_M32R_GOTPC_HI_ULO
4084 BFD_RELOC_M32R_GOTPC_HI_SLO
4086 BFD_RELOC_M32R_GOTPC_LO
4095 This is a 20 bit absolute address.
4097 BFD_RELOC_NDS32_9_PCREL
4099 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4101 BFD_RELOC_NDS32_WORD_9_PCREL
4103 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4105 BFD_RELOC_NDS32_15_PCREL
4107 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4109 BFD_RELOC_NDS32_17_PCREL
4111 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4113 BFD_RELOC_NDS32_25_PCREL
4115 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4117 BFD_RELOC_NDS32_HI20
4119 This is a 20-bit reloc containing the high 20 bits of an address
4120 used with the lower 12 bits
4122 BFD_RELOC_NDS32_LO12S3
4124 This is a 12-bit reloc containing the lower 12 bits of an address
4125 then shift right by 3. This is used with ldi,sdi...
4127 BFD_RELOC_NDS32_LO12S2
4129 This is a 12-bit reloc containing the lower 12 bits of an address
4130 then shift left by 2. This is used with lwi,swi...
4132 BFD_RELOC_NDS32_LO12S1
4134 This is a 12-bit reloc containing the lower 12 bits of an address
4135 then shift left by 1. This is used with lhi,shi...
4137 BFD_RELOC_NDS32_LO12S0
4139 This is a 12-bit reloc containing the lower 12 bits of an address
4140 then shift left by 0. This is used with lbisbi...
4142 BFD_RELOC_NDS32_LO12S0_ORI
4144 This is a 12-bit reloc containing the lower 12 bits of an address
4145 then shift left by 0. This is only used with branch relaxations
4147 BFD_RELOC_NDS32_SDA15S3
4149 This is a 15-bit reloc containing the small data area 18-bit signed offset
4150 and shift left by 3 for use in ldi, sdi...
4152 BFD_RELOC_NDS32_SDA15S2
4154 This is a 15-bit reloc containing the small data area 17-bit signed offset
4155 and shift left by 2 for use in lwi, swi...
4157 BFD_RELOC_NDS32_SDA15S1
4159 This is a 15-bit reloc containing the small data area 16-bit signed offset
4160 and shift left by 1 for use in lhi, shi...
4162 BFD_RELOC_NDS32_SDA15S0
4164 This is a 15-bit reloc containing the small data area 15-bit signed offset
4165 and shift left by 0 for use in lbi, sbi...
4167 BFD_RELOC_NDS32_SDA16S3
4169 This is a 16-bit reloc containing the small data area 16-bit signed offset
4172 BFD_RELOC_NDS32_SDA17S2
4174 This is a 17-bit reloc containing the small data area 17-bit signed offset
4175 and shift left by 2 for use in lwi.gp, swi.gp...
4177 BFD_RELOC_NDS32_SDA18S1
4179 This is a 18-bit reloc containing the small data area 18-bit signed offset
4180 and shift left by 1 for use in lhi.gp, shi.gp...
4182 BFD_RELOC_NDS32_SDA19S0
4184 This is a 19-bit reloc containing the small data area 19-bit signed offset
4185 and shift left by 0 for use in lbi.gp, sbi.gp...
4187 BFD_RELOC_NDS32_GOT20
4189 BFD_RELOC_NDS32_9_PLTREL
4191 BFD_RELOC_NDS32_25_PLTREL
4193 BFD_RELOC_NDS32_COPY
4195 BFD_RELOC_NDS32_GLOB_DAT
4197 BFD_RELOC_NDS32_JMP_SLOT
4199 BFD_RELOC_NDS32_RELATIVE
4201 BFD_RELOC_NDS32_GOTOFF
4203 BFD_RELOC_NDS32_GOTOFF_HI20
4205 BFD_RELOC_NDS32_GOTOFF_LO12
4207 BFD_RELOC_NDS32_GOTPC20
4209 BFD_RELOC_NDS32_GOT_HI20
4211 BFD_RELOC_NDS32_GOT_LO12
4213 BFD_RELOC_NDS32_GOTPC_HI20
4215 BFD_RELOC_NDS32_GOTPC_LO12
4219 BFD_RELOC_NDS32_INSN16
4221 BFD_RELOC_NDS32_LABEL
4223 BFD_RELOC_NDS32_LONGCALL1
4225 BFD_RELOC_NDS32_LONGCALL2
4227 BFD_RELOC_NDS32_LONGCALL3
4229 BFD_RELOC_NDS32_LONGJUMP1
4231 BFD_RELOC_NDS32_LONGJUMP2
4233 BFD_RELOC_NDS32_LONGJUMP3
4235 BFD_RELOC_NDS32_LOADSTORE
4237 BFD_RELOC_NDS32_9_FIXED
4239 BFD_RELOC_NDS32_15_FIXED
4241 BFD_RELOC_NDS32_17_FIXED
4243 BFD_RELOC_NDS32_25_FIXED
4245 BFD_RELOC_NDS32_LONGCALL4
4247 BFD_RELOC_NDS32_LONGCALL5
4249 BFD_RELOC_NDS32_LONGCALL6
4251 BFD_RELOC_NDS32_LONGJUMP4
4253 BFD_RELOC_NDS32_LONGJUMP5
4255 BFD_RELOC_NDS32_LONGJUMP6
4257 BFD_RELOC_NDS32_LONGJUMP7
4261 BFD_RELOC_NDS32_PLTREL_HI20
4263 BFD_RELOC_NDS32_PLTREL_LO12
4265 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4267 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4271 BFD_RELOC_NDS32_SDA12S2_DP
4273 BFD_RELOC_NDS32_SDA12S2_SP
4275 BFD_RELOC_NDS32_LO12S2_DP
4277 BFD_RELOC_NDS32_LO12S2_SP
4281 BFD_RELOC_NDS32_DWARF2_OP1
4283 BFD_RELOC_NDS32_DWARF2_OP2
4285 BFD_RELOC_NDS32_DWARF2_LEB
4287 for dwarf2 debug_line.
4289 BFD_RELOC_NDS32_UPDATE_TA
4291 for eliminate 16-bit instructions
4293 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4295 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4297 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4299 BFD_RELOC_NDS32_GOT_LO15
4301 BFD_RELOC_NDS32_GOT_LO19
4303 BFD_RELOC_NDS32_GOTOFF_LO15
4305 BFD_RELOC_NDS32_GOTOFF_LO19
4307 BFD_RELOC_NDS32_GOT15S2
4309 BFD_RELOC_NDS32_GOT17S2
4311 for PIC object relaxation
4316 This is a 5 bit absolute address.
4318 BFD_RELOC_NDS32_10_UPCREL
4320 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4322 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4324 If fp were omitted, fp can used as another gp.
4326 BFD_RELOC_NDS32_RELAX_ENTRY
4328 BFD_RELOC_NDS32_GOT_SUFF
4330 BFD_RELOC_NDS32_GOTOFF_SUFF
4332 BFD_RELOC_NDS32_PLT_GOT_SUFF
4334 BFD_RELOC_NDS32_MULCALL_SUFF
4338 BFD_RELOC_NDS32_PTR_COUNT
4340 BFD_RELOC_NDS32_PTR_RESOLVED
4342 BFD_RELOC_NDS32_PLTBLOCK
4344 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4346 BFD_RELOC_NDS32_RELAX_REGION_END
4348 BFD_RELOC_NDS32_MINUEND
4350 BFD_RELOC_NDS32_SUBTRAHEND
4352 BFD_RELOC_NDS32_DIFF8
4354 BFD_RELOC_NDS32_DIFF16
4356 BFD_RELOC_NDS32_DIFF32
4358 BFD_RELOC_NDS32_DIFF_ULEB128
4360 BFD_RELOC_NDS32_EMPTY
4362 relaxation relative relocation types
4364 BFD_RELOC_NDS32_25_ABS
4366 This is a 25 bit absolute address.
4368 BFD_RELOC_NDS32_DATA
4370 BFD_RELOC_NDS32_TRAN
4372 BFD_RELOC_NDS32_17IFC_PCREL
4374 BFD_RELOC_NDS32_10IFCU_PCREL
4376 For ex9 and ifc using.
4378 BFD_RELOC_NDS32_TPOFF
4380 BFD_RELOC_NDS32_TLS_LE_HI20
4382 BFD_RELOC_NDS32_TLS_LE_LO12
4384 BFD_RELOC_NDS32_TLS_LE_ADD
4386 BFD_RELOC_NDS32_TLS_LE_LS
4388 BFD_RELOC_NDS32_GOTTPOFF
4390 BFD_RELOC_NDS32_TLS_IE_HI20
4392 BFD_RELOC_NDS32_TLS_IE_LO12S2
4394 BFD_RELOC_NDS32_TLS_TPOFF
4396 BFD_RELOC_NDS32_TLS_LE_20
4398 BFD_RELOC_NDS32_TLS_LE_15S0
4400 BFD_RELOC_NDS32_TLS_LE_15S1
4402 BFD_RELOC_NDS32_TLS_LE_15S2
4408 BFD_RELOC_V850_9_PCREL
4410 This is a 9-bit reloc
4412 BFD_RELOC_V850_22_PCREL
4414 This is a 22-bit reloc
4417 BFD_RELOC_V850_SDA_16_16_OFFSET
4419 This is a 16 bit offset from the short data area pointer.
4421 BFD_RELOC_V850_SDA_15_16_OFFSET
4423 This is a 16 bit offset (of which only 15 bits are used) from the
4424 short data area pointer.
4426 BFD_RELOC_V850_ZDA_16_16_OFFSET
4428 This is a 16 bit offset from the zero data area pointer.
4430 BFD_RELOC_V850_ZDA_15_16_OFFSET
4432 This is a 16 bit offset (of which only 15 bits are used) from the
4433 zero data area pointer.
4435 BFD_RELOC_V850_TDA_6_8_OFFSET
4437 This is an 8 bit offset (of which only 6 bits are used) from the
4438 tiny data area pointer.
4440 BFD_RELOC_V850_TDA_7_8_OFFSET
4442 This is an 8bit offset (of which only 7 bits are used) from the tiny
4445 BFD_RELOC_V850_TDA_7_7_OFFSET
4447 This is a 7 bit offset from the tiny data area pointer.
4449 BFD_RELOC_V850_TDA_16_16_OFFSET
4451 This is a 16 bit offset from the tiny data area pointer.
4454 BFD_RELOC_V850_TDA_4_5_OFFSET
4456 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4459 BFD_RELOC_V850_TDA_4_4_OFFSET
4461 This is a 4 bit offset from the tiny data area pointer.
4463 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4465 This is a 16 bit offset from the short data area pointer, with the
4466 bits placed non-contiguously in the instruction.
4468 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4470 This is a 16 bit offset from the zero data area pointer, with the
4471 bits placed non-contiguously in the instruction.
4473 BFD_RELOC_V850_CALLT_6_7_OFFSET
4475 This is a 6 bit offset from the call table base pointer.
4477 BFD_RELOC_V850_CALLT_16_16_OFFSET
4479 This is a 16 bit offset from the call table base pointer.
4481 BFD_RELOC_V850_LONGCALL
4483 Used for relaxing indirect function calls.
4485 BFD_RELOC_V850_LONGJUMP
4487 Used for relaxing indirect jumps.
4489 BFD_RELOC_V850_ALIGN
4491 Used to maintain alignment whilst relaxing.
4493 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4495 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4498 BFD_RELOC_V850_16_PCREL
4500 This is a 16-bit reloc.
4502 BFD_RELOC_V850_17_PCREL
4504 This is a 17-bit reloc.
4508 This is a 23-bit reloc.
4510 BFD_RELOC_V850_32_PCREL
4512 This is a 32-bit reloc.
4514 BFD_RELOC_V850_32_ABS
4516 This is a 32-bit reloc.
4518 BFD_RELOC_V850_16_SPLIT_OFFSET
4520 This is a 16-bit reloc.
4522 BFD_RELOC_V850_16_S1
4524 This is a 16-bit reloc.
4526 BFD_RELOC_V850_LO16_S1
4528 Low 16 bits. 16 bit shifted by 1.
4530 BFD_RELOC_V850_CALLT_15_16_OFFSET
4532 This is a 16 bit offset from the call table base pointer.
4534 BFD_RELOC_V850_32_GOTPCREL
4538 BFD_RELOC_V850_16_GOT
4542 BFD_RELOC_V850_32_GOT
4546 BFD_RELOC_V850_22_PLT_PCREL
4550 BFD_RELOC_V850_32_PLT_PCREL
4558 BFD_RELOC_V850_GLOB_DAT
4562 BFD_RELOC_V850_JMP_SLOT
4566 BFD_RELOC_V850_RELATIVE
4570 BFD_RELOC_V850_16_GOTOFF
4574 BFD_RELOC_V850_32_GOTOFF
4589 This is a 8bit DP reloc for the tms320c30, where the most
4590 significant 8 bits of a 24 bit word are placed into the least
4591 significant 8 bits of the opcode.
4594 BFD_RELOC_TIC54X_PARTLS7
4596 This is a 7bit reloc for the tms320c54x, where the least
4597 significant 7 bits of a 16 bit word are placed into the least
4598 significant 7 bits of the opcode.
4601 BFD_RELOC_TIC54X_PARTMS9
4603 This is a 9bit DP reloc for the tms320c54x, where the most
4604 significant 9 bits of a 16 bit word are placed into the least
4605 significant 9 bits of the opcode.
4610 This is an extended address 23-bit reloc for the tms320c54x.
4613 BFD_RELOC_TIC54X_16_OF_23
4615 This is a 16-bit reloc for the tms320c54x, where the least
4616 significant 16 bits of a 23-bit extended address are placed into
4620 BFD_RELOC_TIC54X_MS7_OF_23
4622 This is a reloc for the tms320c54x, where the most
4623 significant 7 bits of a 23-bit extended address are placed into
4627 BFD_RELOC_C6000_PCR_S21
4629 BFD_RELOC_C6000_PCR_S12
4631 BFD_RELOC_C6000_PCR_S10
4633 BFD_RELOC_C6000_PCR_S7
4635 BFD_RELOC_C6000_ABS_S16
4637 BFD_RELOC_C6000_ABS_L16
4639 BFD_RELOC_C6000_ABS_H16
4641 BFD_RELOC_C6000_SBR_U15_B
4643 BFD_RELOC_C6000_SBR_U15_H
4645 BFD_RELOC_C6000_SBR_U15_W
4647 BFD_RELOC_C6000_SBR_S16
4649 BFD_RELOC_C6000_SBR_L16_B
4651 BFD_RELOC_C6000_SBR_L16_H
4653 BFD_RELOC_C6000_SBR_L16_W
4655 BFD_RELOC_C6000_SBR_H16_B
4657 BFD_RELOC_C6000_SBR_H16_H
4659 BFD_RELOC_C6000_SBR_H16_W
4661 BFD_RELOC_C6000_SBR_GOT_U15_W
4663 BFD_RELOC_C6000_SBR_GOT_L16_W
4665 BFD_RELOC_C6000_SBR_GOT_H16_W
4667 BFD_RELOC_C6000_DSBT_INDEX
4669 BFD_RELOC_C6000_PREL31
4671 BFD_RELOC_C6000_COPY
4673 BFD_RELOC_C6000_JUMP_SLOT
4675 BFD_RELOC_C6000_EHTYPE
4677 BFD_RELOC_C6000_PCR_H16
4679 BFD_RELOC_C6000_PCR_L16
4681 BFD_RELOC_C6000_ALIGN
4683 BFD_RELOC_C6000_FPHEAD
4685 BFD_RELOC_C6000_NOCMP
4687 TMS320C6000 relocations.
4692 This is a 48 bit reloc for the FR30 that stores 32 bits.
4696 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4699 BFD_RELOC_FR30_6_IN_4
4701 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4704 BFD_RELOC_FR30_8_IN_8
4706 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4709 BFD_RELOC_FR30_9_IN_8
4711 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4714 BFD_RELOC_FR30_10_IN_8
4716 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4719 BFD_RELOC_FR30_9_PCREL
4721 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4722 short offset into 8 bits.
4724 BFD_RELOC_FR30_12_PCREL
4726 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4727 short offset into 11 bits.
4730 BFD_RELOC_MCORE_PCREL_IMM8BY4
4732 BFD_RELOC_MCORE_PCREL_IMM11BY2
4734 BFD_RELOC_MCORE_PCREL_IMM4BY2
4736 BFD_RELOC_MCORE_PCREL_32
4738 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4742 Motorola Mcore relocations.
4751 BFD_RELOC_MEP_PCREL8A2
4753 BFD_RELOC_MEP_PCREL12A2
4755 BFD_RELOC_MEP_PCREL17A2
4757 BFD_RELOC_MEP_PCREL24A2
4759 BFD_RELOC_MEP_PCABS24A2
4771 BFD_RELOC_MEP_TPREL7
4773 BFD_RELOC_MEP_TPREL7A2
4775 BFD_RELOC_MEP_TPREL7A4
4777 BFD_RELOC_MEP_UIMM24
4779 BFD_RELOC_MEP_ADDR24A4
4781 BFD_RELOC_MEP_GNU_VTINHERIT
4783 BFD_RELOC_MEP_GNU_VTENTRY
4785 Toshiba Media Processor Relocations.
4789 BFD_RELOC_METAG_HIADDR16
4791 BFD_RELOC_METAG_LOADDR16
4793 BFD_RELOC_METAG_RELBRANCH
4795 BFD_RELOC_METAG_GETSETOFF
4797 BFD_RELOC_METAG_HIOG
4799 BFD_RELOC_METAG_LOOG
4801 BFD_RELOC_METAG_REL8
4803 BFD_RELOC_METAG_REL16
4805 BFD_RELOC_METAG_HI16_GOTOFF
4807 BFD_RELOC_METAG_LO16_GOTOFF
4809 BFD_RELOC_METAG_GETSET_GOTOFF
4811 BFD_RELOC_METAG_GETSET_GOT
4813 BFD_RELOC_METAG_HI16_GOTPC
4815 BFD_RELOC_METAG_LO16_GOTPC
4817 BFD_RELOC_METAG_HI16_PLT
4819 BFD_RELOC_METAG_LO16_PLT
4821 BFD_RELOC_METAG_RELBRANCH_PLT
4823 BFD_RELOC_METAG_GOTOFF
4827 BFD_RELOC_METAG_COPY
4829 BFD_RELOC_METAG_JMP_SLOT
4831 BFD_RELOC_METAG_RELATIVE
4833 BFD_RELOC_METAG_GLOB_DAT
4835 BFD_RELOC_METAG_TLS_GD
4837 BFD_RELOC_METAG_TLS_LDM
4839 BFD_RELOC_METAG_TLS_LDO_HI16
4841 BFD_RELOC_METAG_TLS_LDO_LO16
4843 BFD_RELOC_METAG_TLS_LDO
4845 BFD_RELOC_METAG_TLS_IE
4847 BFD_RELOC_METAG_TLS_IENONPIC
4849 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4851 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4853 BFD_RELOC_METAG_TLS_TPOFF
4855 BFD_RELOC_METAG_TLS_DTPMOD
4857 BFD_RELOC_METAG_TLS_DTPOFF
4859 BFD_RELOC_METAG_TLS_LE
4861 BFD_RELOC_METAG_TLS_LE_HI16
4863 BFD_RELOC_METAG_TLS_LE_LO16
4865 Imagination Technologies Meta relocations.
4870 BFD_RELOC_MMIX_GETA_1
4872 BFD_RELOC_MMIX_GETA_2
4874 BFD_RELOC_MMIX_GETA_3
4876 These are relocations for the GETA instruction.
4878 BFD_RELOC_MMIX_CBRANCH
4880 BFD_RELOC_MMIX_CBRANCH_J
4882 BFD_RELOC_MMIX_CBRANCH_1
4884 BFD_RELOC_MMIX_CBRANCH_2
4886 BFD_RELOC_MMIX_CBRANCH_3
4888 These are relocations for a conditional branch instruction.
4890 BFD_RELOC_MMIX_PUSHJ
4892 BFD_RELOC_MMIX_PUSHJ_1
4894 BFD_RELOC_MMIX_PUSHJ_2
4896 BFD_RELOC_MMIX_PUSHJ_3
4898 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4900 These are relocations for the PUSHJ instruction.
4904 BFD_RELOC_MMIX_JMP_1
4906 BFD_RELOC_MMIX_JMP_2
4908 BFD_RELOC_MMIX_JMP_3
4910 These are relocations for the JMP instruction.
4912 BFD_RELOC_MMIX_ADDR19
4914 This is a relocation for a relative address as in a GETA instruction or
4917 BFD_RELOC_MMIX_ADDR27
4919 This is a relocation for a relative address as in a JMP instruction.
4921 BFD_RELOC_MMIX_REG_OR_BYTE
4923 This is a relocation for an instruction field that may be a general
4924 register or a value 0..255.
4928 This is a relocation for an instruction field that may be a general
4931 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4933 This is a relocation for two instruction fields holding a register and
4934 an offset, the equivalent of the relocation.
4936 BFD_RELOC_MMIX_LOCAL
4938 This relocation is an assertion that the expression is not allocated as
4939 a global register. It does not modify contents.
4942 BFD_RELOC_AVR_7_PCREL
4944 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4945 short offset into 7 bits.
4947 BFD_RELOC_AVR_13_PCREL
4949 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4950 short offset into 12 bits.
4954 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4955 program memory address) into 16 bits.
4957 BFD_RELOC_AVR_LO8_LDI
4959 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4960 data memory address) into 8 bit immediate value of LDI insn.
4962 BFD_RELOC_AVR_HI8_LDI
4964 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4965 of data memory address) into 8 bit immediate value of LDI insn.
4967 BFD_RELOC_AVR_HH8_LDI
4969 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4970 of program memory address) into 8 bit immediate value of LDI insn.
4972 BFD_RELOC_AVR_MS8_LDI
4974 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4975 of 32 bit value) into 8 bit immediate value of LDI insn.
4977 BFD_RELOC_AVR_LO8_LDI_NEG
4979 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4980 (usually data memory address) into 8 bit immediate value of SUBI insn.
4982 BFD_RELOC_AVR_HI8_LDI_NEG
4984 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4985 (high 8 bit of data memory address) into 8 bit immediate value of
4988 BFD_RELOC_AVR_HH8_LDI_NEG
4990 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4991 (most high 8 bit of program memory address) into 8 bit immediate value
4992 of LDI or SUBI insn.
4994 BFD_RELOC_AVR_MS8_LDI_NEG
4996 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4997 of 32 bit value) into 8 bit immediate value of LDI insn.
4999 BFD_RELOC_AVR_LO8_LDI_PM
5001 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5002 command address) into 8 bit immediate value of LDI insn.
5004 BFD_RELOC_AVR_LO8_LDI_GS
5006 This is a 16 bit reloc for the AVR that stores 8 bit value
5007 (command address) into 8 bit immediate value of LDI insn. If the address
5008 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5011 BFD_RELOC_AVR_HI8_LDI_PM
5013 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5014 of command address) into 8 bit immediate value of LDI insn.
5016 BFD_RELOC_AVR_HI8_LDI_GS
5018 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5019 of command address) into 8 bit immediate value of LDI insn. If the address
5020 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5023 BFD_RELOC_AVR_HH8_LDI_PM
5025 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5026 of command address) into 8 bit immediate value of LDI insn.
5028 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5030 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5031 (usually command address) into 8 bit immediate value of SUBI insn.
5033 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5035 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5036 (high 8 bit of 16 bit command address) into 8 bit immediate value
5039 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5041 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5042 (high 6 bit of 22 bit command address) into 8 bit immediate
5047 This is a 32 bit reloc for the AVR that stores 23 bit value
5052 This is a 16 bit reloc for the AVR that stores all needed bits
5053 for absolute addressing with ldi with overflow check to linktime
5057 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5060 BFD_RELOC_AVR_6_ADIW
5062 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5067 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5068 in .byte lo8(symbol)
5072 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5073 in .byte hi8(symbol)
5077 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5078 in .byte hlo8(symbol)
5082 BFD_RELOC_AVR_DIFF16
5084 BFD_RELOC_AVR_DIFF32
5086 AVR relocations to mark the difference of two local symbols.
5087 These are only needed to support linker relaxation and can be ignored
5088 when not relaxing. The field is set to the value of the difference
5089 assuming no relaxation. The relocation encodes the position of the
5090 second symbol so the linker can determine whether to adjust the field
5093 BFD_RELOC_AVR_LDS_STS_16
5095 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5096 lds and sts instructions supported only tiny core.
5100 This is a 6 bit reloc for the AVR that stores an I/O register
5101 number for the IN and OUT instructions
5105 This is a 5 bit reloc for the AVR that stores an I/O register
5106 number for the SBIC, SBIS, SBI and CBI instructions
5109 BFD_RELOC_RISCV_HI20
5111 BFD_RELOC_RISCV_PCREL_HI20
5113 BFD_RELOC_RISCV_PCREL_LO12_I
5115 BFD_RELOC_RISCV_PCREL_LO12_S
5117 BFD_RELOC_RISCV_LO12_I
5119 BFD_RELOC_RISCV_LO12_S
5121 BFD_RELOC_RISCV_GPREL12_I
5123 BFD_RELOC_RISCV_GPREL12_S
5125 BFD_RELOC_RISCV_TPREL_HI20
5127 BFD_RELOC_RISCV_TPREL_LO12_I
5129 BFD_RELOC_RISCV_TPREL_LO12_S
5131 BFD_RELOC_RISCV_TPREL_ADD
5133 BFD_RELOC_RISCV_CALL
5135 BFD_RELOC_RISCV_CALL_PLT
5137 BFD_RELOC_RISCV_ADD8
5139 BFD_RELOC_RISCV_ADD16
5141 BFD_RELOC_RISCV_ADD32
5143 BFD_RELOC_RISCV_ADD64
5145 BFD_RELOC_RISCV_SUB8
5147 BFD_RELOC_RISCV_SUB16
5149 BFD_RELOC_RISCV_SUB32
5151 BFD_RELOC_RISCV_SUB64
5153 BFD_RELOC_RISCV_GOT_HI20
5155 BFD_RELOC_RISCV_TLS_GOT_HI20
5157 BFD_RELOC_RISCV_TLS_GD_HI20
5161 BFD_RELOC_RISCV_TLS_DTPMOD32
5163 BFD_RELOC_RISCV_TLS_DTPREL32
5165 BFD_RELOC_RISCV_TLS_DTPMOD64
5167 BFD_RELOC_RISCV_TLS_DTPREL64
5169 BFD_RELOC_RISCV_TLS_TPREL32
5171 BFD_RELOC_RISCV_TLS_TPREL64
5173 BFD_RELOC_RISCV_ALIGN
5175 BFD_RELOC_RISCV_RVC_BRANCH
5177 BFD_RELOC_RISCV_RVC_JUMP
5179 BFD_RELOC_RISCV_RVC_LUI
5181 BFD_RELOC_RISCV_GPREL_I
5183 BFD_RELOC_RISCV_GPREL_S
5185 BFD_RELOC_RISCV_TPREL_I
5187 BFD_RELOC_RISCV_TPREL_S
5189 BFD_RELOC_RISCV_RELAX
5193 BFD_RELOC_RISCV_SUB6
5195 BFD_RELOC_RISCV_SET6
5197 BFD_RELOC_RISCV_SET8
5199 BFD_RELOC_RISCV_SET16
5201 BFD_RELOC_RISCV_SET32
5203 BFD_RELOC_RISCV_32_PCREL
5210 BFD_RELOC_RL78_NEG16
5212 BFD_RELOC_RL78_NEG24
5214 BFD_RELOC_RL78_NEG32
5216 BFD_RELOC_RL78_16_OP
5218 BFD_RELOC_RL78_24_OP
5220 BFD_RELOC_RL78_32_OP
5228 BFD_RELOC_RL78_DIR3U_PCREL
5232 BFD_RELOC_RL78_GPRELB
5234 BFD_RELOC_RL78_GPRELW
5236 BFD_RELOC_RL78_GPRELL
5240 BFD_RELOC_RL78_OP_SUBTRACT
5242 BFD_RELOC_RL78_OP_NEG
5244 BFD_RELOC_RL78_OP_AND
5246 BFD_RELOC_RL78_OP_SHRA
5250 BFD_RELOC_RL78_ABS16
5252 BFD_RELOC_RL78_ABS16_REV
5254 BFD_RELOC_RL78_ABS32
5256 BFD_RELOC_RL78_ABS32_REV
5258 BFD_RELOC_RL78_ABS16U
5260 BFD_RELOC_RL78_ABS16UW
5262 BFD_RELOC_RL78_ABS16UL
5264 BFD_RELOC_RL78_RELAX
5274 BFD_RELOC_RL78_SADDR
5276 Renesas RL78 Relocations.
5299 BFD_RELOC_RX_DIR3U_PCREL
5311 BFD_RELOC_RX_OP_SUBTRACT
5319 BFD_RELOC_RX_ABS16_REV
5323 BFD_RELOC_RX_ABS32_REV
5327 BFD_RELOC_RX_ABS16UW
5329 BFD_RELOC_RX_ABS16UL
5333 Renesas RX Relocations.
5346 32 bit PC relative PLT address.
5350 Copy symbol at runtime.
5352 BFD_RELOC_390_GLOB_DAT
5356 BFD_RELOC_390_JMP_SLOT
5360 BFD_RELOC_390_RELATIVE
5362 Adjust by program base.
5366 32 bit PC relative offset to GOT.
5372 BFD_RELOC_390_PC12DBL
5374 PC relative 12 bit shifted by 1.
5376 BFD_RELOC_390_PLT12DBL
5378 12 bit PC rel. PLT shifted by 1.
5380 BFD_RELOC_390_PC16DBL
5382 PC relative 16 bit shifted by 1.
5384 BFD_RELOC_390_PLT16DBL
5386 16 bit PC rel. PLT shifted by 1.
5388 BFD_RELOC_390_PC24DBL
5390 PC relative 24 bit shifted by 1.
5392 BFD_RELOC_390_PLT24DBL
5394 24 bit PC rel. PLT shifted by 1.
5396 BFD_RELOC_390_PC32DBL
5398 PC relative 32 bit shifted by 1.
5400 BFD_RELOC_390_PLT32DBL
5402 32 bit PC rel. PLT shifted by 1.
5404 BFD_RELOC_390_GOTPCDBL
5406 32 bit PC rel. GOT shifted by 1.
5414 64 bit PC relative PLT address.
5416 BFD_RELOC_390_GOTENT
5418 32 bit rel. offset to GOT entry.
5420 BFD_RELOC_390_GOTOFF64
5422 64 bit offset to GOT.
5424 BFD_RELOC_390_GOTPLT12
5426 12-bit offset to symbol-entry within GOT, with PLT handling.
5428 BFD_RELOC_390_GOTPLT16
5430 16-bit offset to symbol-entry within GOT, with PLT handling.
5432 BFD_RELOC_390_GOTPLT32
5434 32-bit offset to symbol-entry within GOT, with PLT handling.
5436 BFD_RELOC_390_GOTPLT64
5438 64-bit offset to symbol-entry within GOT, with PLT handling.
5440 BFD_RELOC_390_GOTPLTENT
5442 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5444 BFD_RELOC_390_PLTOFF16
5446 16-bit rel. offset from the GOT to a PLT entry.
5448 BFD_RELOC_390_PLTOFF32
5450 32-bit rel. offset from the GOT to a PLT entry.
5452 BFD_RELOC_390_PLTOFF64
5454 64-bit rel. offset from the GOT to a PLT entry.
5457 BFD_RELOC_390_TLS_LOAD
5459 BFD_RELOC_390_TLS_GDCALL
5461 BFD_RELOC_390_TLS_LDCALL
5463 BFD_RELOC_390_TLS_GD32
5465 BFD_RELOC_390_TLS_GD64
5467 BFD_RELOC_390_TLS_GOTIE12
5469 BFD_RELOC_390_TLS_GOTIE32
5471 BFD_RELOC_390_TLS_GOTIE64
5473 BFD_RELOC_390_TLS_LDM32
5475 BFD_RELOC_390_TLS_LDM64
5477 BFD_RELOC_390_TLS_IE32
5479 BFD_RELOC_390_TLS_IE64
5481 BFD_RELOC_390_TLS_IEENT
5483 BFD_RELOC_390_TLS_LE32
5485 BFD_RELOC_390_TLS_LE64
5487 BFD_RELOC_390_TLS_LDO32
5489 BFD_RELOC_390_TLS_LDO64
5491 BFD_RELOC_390_TLS_DTPMOD
5493 BFD_RELOC_390_TLS_DTPOFF
5495 BFD_RELOC_390_TLS_TPOFF
5497 s390 tls relocations.
5504 BFD_RELOC_390_GOTPLT20
5506 BFD_RELOC_390_TLS_GOTIE20
5508 Long displacement extension.
5511 BFD_RELOC_390_IRELATIVE
5513 STT_GNU_IFUNC relocation.
5516 BFD_RELOC_SCORE_GPREL15
5519 Low 16 bit for load/store
5521 BFD_RELOC_SCORE_DUMMY2
5525 This is a 24-bit reloc with the right 1 bit assumed to be 0
5527 BFD_RELOC_SCORE_BRANCH
5529 This is a 19-bit reloc with the right 1 bit assumed to be 0
5531 BFD_RELOC_SCORE_IMM30
5533 This is a 32-bit reloc for 48-bit instructions.
5535 BFD_RELOC_SCORE_IMM32
5537 This is a 32-bit reloc for 48-bit instructions.
5539 BFD_RELOC_SCORE16_JMP
5541 This is a 11-bit reloc with the right 1 bit assumed to be 0
5543 BFD_RELOC_SCORE16_BRANCH
5545 This is a 8-bit reloc with the right 1 bit assumed to be 0
5547 BFD_RELOC_SCORE_BCMP
5549 This is a 9-bit reloc with the right 1 bit assumed to be 0
5551 BFD_RELOC_SCORE_GOT15
5553 BFD_RELOC_SCORE_GOT_LO16
5555 BFD_RELOC_SCORE_CALL15
5557 BFD_RELOC_SCORE_DUMMY_HI16
5559 Undocumented Score relocs
5564 Scenix IP2K - 9-bit register number / data address
5568 Scenix IP2K - 4-bit register/data bank number
5570 BFD_RELOC_IP2K_ADDR16CJP
5572 Scenix IP2K - low 13 bits of instruction word address
5574 BFD_RELOC_IP2K_PAGE3
5576 Scenix IP2K - high 3 bits of instruction word address
5578 BFD_RELOC_IP2K_LO8DATA
5580 BFD_RELOC_IP2K_HI8DATA
5582 BFD_RELOC_IP2K_EX8DATA
5584 Scenix IP2K - ext/low/high 8 bits of data address
5586 BFD_RELOC_IP2K_LO8INSN
5588 BFD_RELOC_IP2K_HI8INSN
5590 Scenix IP2K - low/high 8 bits of instruction word address
5592 BFD_RELOC_IP2K_PC_SKIP
5594 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5598 Scenix IP2K - 16 bit word address in text section.
5600 BFD_RELOC_IP2K_FR_OFFSET
5602 Scenix IP2K - 7-bit sp or dp offset
5604 BFD_RELOC_VPE4KMATH_DATA
5606 BFD_RELOC_VPE4KMATH_INSN
5608 Scenix VPE4K coprocessor - data/insn-space addressing
5611 BFD_RELOC_VTABLE_INHERIT
5613 BFD_RELOC_VTABLE_ENTRY
5615 These two relocations are used by the linker to determine which of
5616 the entries in a C++ virtual function table are actually used. When
5617 the --gc-sections option is given, the linker will zero out the entries
5618 that are not used, so that the code for those functions need not be
5619 included in the output.
5621 VTABLE_INHERIT is a zero-space relocation used to describe to the
5622 linker the inheritance tree of a C++ virtual function table. The
5623 relocation's symbol should be the parent class' vtable, and the
5624 relocation should be located at the child vtable.
5626 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5627 virtual function table entry. The reloc's symbol should refer to the
5628 table of the class mentioned in the code. Off of that base, an offset
5629 describes the entry that is being used. For Rela hosts, this offset
5630 is stored in the reloc's addend. For Rel hosts, we are forced to put
5631 this offset in the reloc's section offset.
5634 BFD_RELOC_IA64_IMM14
5636 BFD_RELOC_IA64_IMM22
5638 BFD_RELOC_IA64_IMM64
5640 BFD_RELOC_IA64_DIR32MSB
5642 BFD_RELOC_IA64_DIR32LSB
5644 BFD_RELOC_IA64_DIR64MSB
5646 BFD_RELOC_IA64_DIR64LSB
5648 BFD_RELOC_IA64_GPREL22
5650 BFD_RELOC_IA64_GPREL64I
5652 BFD_RELOC_IA64_GPREL32MSB
5654 BFD_RELOC_IA64_GPREL32LSB
5656 BFD_RELOC_IA64_GPREL64MSB
5658 BFD_RELOC_IA64_GPREL64LSB
5660 BFD_RELOC_IA64_LTOFF22
5662 BFD_RELOC_IA64_LTOFF64I
5664 BFD_RELOC_IA64_PLTOFF22
5666 BFD_RELOC_IA64_PLTOFF64I
5668 BFD_RELOC_IA64_PLTOFF64MSB
5670 BFD_RELOC_IA64_PLTOFF64LSB
5672 BFD_RELOC_IA64_FPTR64I
5674 BFD_RELOC_IA64_FPTR32MSB
5676 BFD_RELOC_IA64_FPTR32LSB
5678 BFD_RELOC_IA64_FPTR64MSB
5680 BFD_RELOC_IA64_FPTR64LSB
5682 BFD_RELOC_IA64_PCREL21B
5684 BFD_RELOC_IA64_PCREL21BI
5686 BFD_RELOC_IA64_PCREL21M
5688 BFD_RELOC_IA64_PCREL21F
5690 BFD_RELOC_IA64_PCREL22
5692 BFD_RELOC_IA64_PCREL60B
5694 BFD_RELOC_IA64_PCREL64I
5696 BFD_RELOC_IA64_PCREL32MSB
5698 BFD_RELOC_IA64_PCREL32LSB
5700 BFD_RELOC_IA64_PCREL64MSB
5702 BFD_RELOC_IA64_PCREL64LSB
5704 BFD_RELOC_IA64_LTOFF_FPTR22
5706 BFD_RELOC_IA64_LTOFF_FPTR64I
5708 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5710 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5712 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5714 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5716 BFD_RELOC_IA64_SEGREL32MSB
5718 BFD_RELOC_IA64_SEGREL32LSB
5720 BFD_RELOC_IA64_SEGREL64MSB
5722 BFD_RELOC_IA64_SEGREL64LSB
5724 BFD_RELOC_IA64_SECREL32MSB
5726 BFD_RELOC_IA64_SECREL32LSB
5728 BFD_RELOC_IA64_SECREL64MSB
5730 BFD_RELOC_IA64_SECREL64LSB
5732 BFD_RELOC_IA64_REL32MSB
5734 BFD_RELOC_IA64_REL32LSB
5736 BFD_RELOC_IA64_REL64MSB
5738 BFD_RELOC_IA64_REL64LSB
5740 BFD_RELOC_IA64_LTV32MSB
5742 BFD_RELOC_IA64_LTV32LSB
5744 BFD_RELOC_IA64_LTV64MSB
5746 BFD_RELOC_IA64_LTV64LSB
5748 BFD_RELOC_IA64_IPLTMSB
5750 BFD_RELOC_IA64_IPLTLSB
5754 BFD_RELOC_IA64_LTOFF22X
5756 BFD_RELOC_IA64_LDXMOV
5758 BFD_RELOC_IA64_TPREL14
5760 BFD_RELOC_IA64_TPREL22
5762 BFD_RELOC_IA64_TPREL64I
5764 BFD_RELOC_IA64_TPREL64MSB
5766 BFD_RELOC_IA64_TPREL64LSB
5768 BFD_RELOC_IA64_LTOFF_TPREL22
5770 BFD_RELOC_IA64_DTPMOD64MSB
5772 BFD_RELOC_IA64_DTPMOD64LSB
5774 BFD_RELOC_IA64_LTOFF_DTPMOD22
5776 BFD_RELOC_IA64_DTPREL14
5778 BFD_RELOC_IA64_DTPREL22
5780 BFD_RELOC_IA64_DTPREL64I
5782 BFD_RELOC_IA64_DTPREL32MSB
5784 BFD_RELOC_IA64_DTPREL32LSB
5786 BFD_RELOC_IA64_DTPREL64MSB
5788 BFD_RELOC_IA64_DTPREL64LSB
5790 BFD_RELOC_IA64_LTOFF_DTPREL22
5792 Intel IA64 Relocations.
5795 BFD_RELOC_M68HC11_HI8
5797 Motorola 68HC11 reloc.
5798 This is the 8 bit high part of an absolute address.
5800 BFD_RELOC_M68HC11_LO8
5802 Motorola 68HC11 reloc.
5803 This is the 8 bit low part of an absolute address.
5805 BFD_RELOC_M68HC11_3B
5807 Motorola 68HC11 reloc.
5808 This is the 3 bit of a value.
5810 BFD_RELOC_M68HC11_RL_JUMP
5812 Motorola 68HC11 reloc.
5813 This reloc marks the beginning of a jump/call instruction.
5814 It is used for linker relaxation to correctly identify beginning
5815 of instruction and change some branches to use PC-relative
5818 BFD_RELOC_M68HC11_RL_GROUP
5820 Motorola 68HC11 reloc.
5821 This reloc marks a group of several instructions that gcc generates
5822 and for which the linker relaxation pass can modify and/or remove
5825 BFD_RELOC_M68HC11_LO16
5827 Motorola 68HC11 reloc.
5828 This is the 16-bit lower part of an address. It is used for 'call'
5829 instruction to specify the symbol address without any special
5830 transformation (due to memory bank window).
5832 BFD_RELOC_M68HC11_PAGE
5834 Motorola 68HC11 reloc.
5835 This is a 8-bit reloc that specifies the page number of an address.
5836 It is used by 'call' instruction to specify the page number of
5839 BFD_RELOC_M68HC11_24
5841 Motorola 68HC11 reloc.
5842 This is a 24-bit reloc that represents the address with a 16-bit
5843 value and a 8-bit page number. The symbol address is transformed
5844 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5846 BFD_RELOC_M68HC12_5B
5848 Motorola 68HC12 reloc.
5849 This is the 5 bits of a value.
5851 BFD_RELOC_XGATE_RL_JUMP
5853 Freescale XGATE reloc.
5854 This reloc marks the beginning of a bra/jal instruction.
5856 BFD_RELOC_XGATE_RL_GROUP
5858 Freescale XGATE reloc.
5859 This reloc marks a group of several instructions that gcc generates
5860 and for which the linker relaxation pass can modify and/or remove
5863 BFD_RELOC_XGATE_LO16
5865 Freescale XGATE reloc.
5866 This is the 16-bit lower part of an address. It is used for the '16-bit'
5869 BFD_RELOC_XGATE_GPAGE
5871 Freescale XGATE reloc.
5875 Freescale XGATE reloc.
5877 BFD_RELOC_XGATE_PCREL_9
5879 Freescale XGATE reloc.
5880 This is a 9-bit pc-relative reloc.
5882 BFD_RELOC_XGATE_PCREL_10
5884 Freescale XGATE reloc.
5885 This is a 10-bit pc-relative reloc.
5887 BFD_RELOC_XGATE_IMM8_LO
5889 Freescale XGATE reloc.
5890 This is the 16-bit lower part of an address. It is used for the '16-bit'
5893 BFD_RELOC_XGATE_IMM8_HI
5895 Freescale XGATE reloc.
5896 This is the 16-bit higher part of an address. It is used for the '16-bit'
5899 BFD_RELOC_XGATE_IMM3
5901 Freescale XGATE reloc.
5902 This is a 3-bit pc-relative reloc.
5904 BFD_RELOC_XGATE_IMM4
5906 Freescale XGATE reloc.
5907 This is a 4-bit pc-relative reloc.
5909 BFD_RELOC_XGATE_IMM5
5911 Freescale XGATE reloc.
5912 This is a 5-bit pc-relative reloc.
5914 BFD_RELOC_M68HC12_9B
5916 Motorola 68HC12 reloc.
5917 This is the 9 bits of a value.
5919 BFD_RELOC_M68HC12_16B
5921 Motorola 68HC12 reloc.
5922 This is the 16 bits of a value.
5924 BFD_RELOC_M68HC12_9_PCREL
5926 Motorola 68HC12/XGATE reloc.
5927 This is a PCREL9 branch.
5929 BFD_RELOC_M68HC12_10_PCREL
5931 Motorola 68HC12/XGATE reloc.
5932 This is a PCREL10 branch.
5934 BFD_RELOC_M68HC12_LO8XG
5936 Motorola 68HC12/XGATE reloc.
5937 This is the 8 bit low part of an absolute address and immediately precedes
5938 a matching HI8XG part.
5940 BFD_RELOC_M68HC12_HI8XG
5942 Motorola 68HC12/XGATE reloc.
5943 This is the 8 bit high part of an absolute address and immediately follows
5944 a matching LO8XG part.
5948 BFD_RELOC_16C_NUM08_C
5952 BFD_RELOC_16C_NUM16_C
5956 BFD_RELOC_16C_NUM32_C
5958 BFD_RELOC_16C_DISP04
5960 BFD_RELOC_16C_DISP04_C
5962 BFD_RELOC_16C_DISP08
5964 BFD_RELOC_16C_DISP08_C
5966 BFD_RELOC_16C_DISP16
5968 BFD_RELOC_16C_DISP16_C
5970 BFD_RELOC_16C_DISP24
5972 BFD_RELOC_16C_DISP24_C
5974 BFD_RELOC_16C_DISP24a
5976 BFD_RELOC_16C_DISP24a_C
5980 BFD_RELOC_16C_REG04_C
5982 BFD_RELOC_16C_REG04a
5984 BFD_RELOC_16C_REG04a_C
5988 BFD_RELOC_16C_REG14_C
5992 BFD_RELOC_16C_REG16_C
5996 BFD_RELOC_16C_REG20_C
6000 BFD_RELOC_16C_ABS20_C
6004 BFD_RELOC_16C_ABS24_C
6008 BFD_RELOC_16C_IMM04_C
6012 BFD_RELOC_16C_IMM16_C
6016 BFD_RELOC_16C_IMM20_C
6020 BFD_RELOC_16C_IMM24_C
6024 BFD_RELOC_16C_IMM32_C
6026 NS CR16C Relocations.
6031 BFD_RELOC_CR16_NUM16
6033 BFD_RELOC_CR16_NUM32
6035 BFD_RELOC_CR16_NUM32a
6037 BFD_RELOC_CR16_REGREL0
6039 BFD_RELOC_CR16_REGREL4
6041 BFD_RELOC_CR16_REGREL4a
6043 BFD_RELOC_CR16_REGREL14
6045 BFD_RELOC_CR16_REGREL14a
6047 BFD_RELOC_CR16_REGREL16
6049 BFD_RELOC_CR16_REGREL20
6051 BFD_RELOC_CR16_REGREL20a
6053 BFD_RELOC_CR16_ABS20
6055 BFD_RELOC_CR16_ABS24
6061 BFD_RELOC_CR16_IMM16
6063 BFD_RELOC_CR16_IMM20
6065 BFD_RELOC_CR16_IMM24
6067 BFD_RELOC_CR16_IMM32
6069 BFD_RELOC_CR16_IMM32a
6071 BFD_RELOC_CR16_DISP4
6073 BFD_RELOC_CR16_DISP8
6075 BFD_RELOC_CR16_DISP16
6077 BFD_RELOC_CR16_DISP20
6079 BFD_RELOC_CR16_DISP24
6081 BFD_RELOC_CR16_DISP24a
6083 BFD_RELOC_CR16_SWITCH8
6085 BFD_RELOC_CR16_SWITCH16
6087 BFD_RELOC_CR16_SWITCH32
6089 BFD_RELOC_CR16_GOT_REGREL20
6091 BFD_RELOC_CR16_GOTC_REGREL20
6093 BFD_RELOC_CR16_GLOB_DAT
6095 NS CR16 Relocations.
6102 BFD_RELOC_CRX_REL8_CMP
6110 BFD_RELOC_CRX_REGREL12
6112 BFD_RELOC_CRX_REGREL22
6114 BFD_RELOC_CRX_REGREL28
6116 BFD_RELOC_CRX_REGREL32
6132 BFD_RELOC_CRX_SWITCH8
6134 BFD_RELOC_CRX_SWITCH16
6136 BFD_RELOC_CRX_SWITCH32
6141 BFD_RELOC_CRIS_BDISP8
6143 BFD_RELOC_CRIS_UNSIGNED_5
6145 BFD_RELOC_CRIS_SIGNED_6
6147 BFD_RELOC_CRIS_UNSIGNED_6
6149 BFD_RELOC_CRIS_SIGNED_8
6151 BFD_RELOC_CRIS_UNSIGNED_8
6153 BFD_RELOC_CRIS_SIGNED_16
6155 BFD_RELOC_CRIS_UNSIGNED_16
6157 BFD_RELOC_CRIS_LAPCQ_OFFSET
6159 BFD_RELOC_CRIS_UNSIGNED_4
6161 These relocs are only used within the CRIS assembler. They are not
6162 (at present) written to any object files.
6166 BFD_RELOC_CRIS_GLOB_DAT
6168 BFD_RELOC_CRIS_JUMP_SLOT
6170 BFD_RELOC_CRIS_RELATIVE
6172 Relocs used in ELF shared libraries for CRIS.
6174 BFD_RELOC_CRIS_32_GOT
6176 32-bit offset to symbol-entry within GOT.
6178 BFD_RELOC_CRIS_16_GOT
6180 16-bit offset to symbol-entry within GOT.
6182 BFD_RELOC_CRIS_32_GOTPLT
6184 32-bit offset to symbol-entry within GOT, with PLT handling.
6186 BFD_RELOC_CRIS_16_GOTPLT
6188 16-bit offset to symbol-entry within GOT, with PLT handling.
6190 BFD_RELOC_CRIS_32_GOTREL
6192 32-bit offset to symbol, relative to GOT.
6194 BFD_RELOC_CRIS_32_PLT_GOTREL
6196 32-bit offset to symbol with PLT entry, relative to GOT.
6198 BFD_RELOC_CRIS_32_PLT_PCREL
6200 32-bit offset to symbol with PLT entry, relative to this relocation.
6203 BFD_RELOC_CRIS_32_GOT_GD
6205 BFD_RELOC_CRIS_16_GOT_GD
6207 BFD_RELOC_CRIS_32_GD
6211 BFD_RELOC_CRIS_32_DTPREL
6213 BFD_RELOC_CRIS_16_DTPREL
6215 BFD_RELOC_CRIS_32_GOT_TPREL
6217 BFD_RELOC_CRIS_16_GOT_TPREL
6219 BFD_RELOC_CRIS_32_TPREL
6221 BFD_RELOC_CRIS_16_TPREL
6223 BFD_RELOC_CRIS_DTPMOD
6225 BFD_RELOC_CRIS_32_IE
6227 Relocs used in TLS code for CRIS.
6230 BFD_RELOC_OR1K_REL_26
6232 BFD_RELOC_OR1K_GOTPC_HI16
6234 BFD_RELOC_OR1K_GOTPC_LO16
6236 BFD_RELOC_OR1K_GOT16
6238 BFD_RELOC_OR1K_PLT26
6240 BFD_RELOC_OR1K_GOTOFF_HI16
6242 BFD_RELOC_OR1K_GOTOFF_LO16
6246 BFD_RELOC_OR1K_GLOB_DAT
6248 BFD_RELOC_OR1K_JMP_SLOT
6250 BFD_RELOC_OR1K_RELATIVE
6252 BFD_RELOC_OR1K_TLS_GD_HI16
6254 BFD_RELOC_OR1K_TLS_GD_LO16
6256 BFD_RELOC_OR1K_TLS_LDM_HI16
6258 BFD_RELOC_OR1K_TLS_LDM_LO16
6260 BFD_RELOC_OR1K_TLS_LDO_HI16
6262 BFD_RELOC_OR1K_TLS_LDO_LO16
6264 BFD_RELOC_OR1K_TLS_IE_HI16
6266 BFD_RELOC_OR1K_TLS_IE_LO16
6268 BFD_RELOC_OR1K_TLS_LE_HI16
6270 BFD_RELOC_OR1K_TLS_LE_LO16
6272 BFD_RELOC_OR1K_TLS_TPOFF
6274 BFD_RELOC_OR1K_TLS_DTPOFF
6276 BFD_RELOC_OR1K_TLS_DTPMOD
6278 OpenRISC 1000 Relocations.
6281 BFD_RELOC_H8_DIR16A8
6283 BFD_RELOC_H8_DIR16R8
6285 BFD_RELOC_H8_DIR24A8
6287 BFD_RELOC_H8_DIR24R8
6289 BFD_RELOC_H8_DIR32A16
6291 BFD_RELOC_H8_DISP32A16
6296 BFD_RELOC_XSTORMY16_REL_12
6298 BFD_RELOC_XSTORMY16_12
6300 BFD_RELOC_XSTORMY16_24
6302 BFD_RELOC_XSTORMY16_FPTR16
6304 Sony Xstormy16 Relocations.
6309 Self-describing complex relocations.
6321 Infineon Relocations.
6324 BFD_RELOC_VAX_GLOB_DAT
6326 BFD_RELOC_VAX_JMP_SLOT
6328 BFD_RELOC_VAX_RELATIVE
6330 Relocations used by VAX ELF.
6335 Morpho MT - 16 bit immediate relocation.
6339 Morpho MT - Hi 16 bits of an address.
6343 Morpho MT - Low 16 bits of an address.
6345 BFD_RELOC_MT_GNU_VTINHERIT
6347 Morpho MT - Used to tell the linker which vtable entries are used.
6349 BFD_RELOC_MT_GNU_VTENTRY
6351 Morpho MT - Used to tell the linker which vtable entries are used.
6353 BFD_RELOC_MT_PCINSN8
6355 Morpho MT - 8 bit immediate relocation.
6358 BFD_RELOC_MSP430_10_PCREL
6360 BFD_RELOC_MSP430_16_PCREL
6364 BFD_RELOC_MSP430_16_PCREL_BYTE
6366 BFD_RELOC_MSP430_16_BYTE
6368 BFD_RELOC_MSP430_2X_PCREL
6370 BFD_RELOC_MSP430_RL_PCREL
6372 BFD_RELOC_MSP430_ABS8
6374 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6376 BFD_RELOC_MSP430X_PCR20_EXT_DST
6378 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6380 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6382 BFD_RELOC_MSP430X_ABS20_EXT_DST
6384 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6386 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6388 BFD_RELOC_MSP430X_ABS20_ADR_DST
6390 BFD_RELOC_MSP430X_PCR16
6392 BFD_RELOC_MSP430X_PCR20_CALL
6394 BFD_RELOC_MSP430X_ABS16
6396 BFD_RELOC_MSP430_ABS_HI16
6398 BFD_RELOC_MSP430_PREL31
6400 BFD_RELOC_MSP430_SYM_DIFF
6402 msp430 specific relocation codes
6409 BFD_RELOC_NIOS2_CALL26
6411 BFD_RELOC_NIOS2_IMM5
6413 BFD_RELOC_NIOS2_CACHE_OPX
6415 BFD_RELOC_NIOS2_IMM6
6417 BFD_RELOC_NIOS2_IMM8
6419 BFD_RELOC_NIOS2_HI16
6421 BFD_RELOC_NIOS2_LO16
6423 BFD_RELOC_NIOS2_HIADJ16
6425 BFD_RELOC_NIOS2_GPREL
6427 BFD_RELOC_NIOS2_UJMP
6429 BFD_RELOC_NIOS2_CJMP
6431 BFD_RELOC_NIOS2_CALLR
6433 BFD_RELOC_NIOS2_ALIGN
6435 BFD_RELOC_NIOS2_GOT16
6437 BFD_RELOC_NIOS2_CALL16
6439 BFD_RELOC_NIOS2_GOTOFF_LO
6441 BFD_RELOC_NIOS2_GOTOFF_HA
6443 BFD_RELOC_NIOS2_PCREL_LO
6445 BFD_RELOC_NIOS2_PCREL_HA
6447 BFD_RELOC_NIOS2_TLS_GD16
6449 BFD_RELOC_NIOS2_TLS_LDM16
6451 BFD_RELOC_NIOS2_TLS_LDO16
6453 BFD_RELOC_NIOS2_TLS_IE16
6455 BFD_RELOC_NIOS2_TLS_LE16
6457 BFD_RELOC_NIOS2_TLS_DTPMOD
6459 BFD_RELOC_NIOS2_TLS_DTPREL
6461 BFD_RELOC_NIOS2_TLS_TPREL
6463 BFD_RELOC_NIOS2_COPY
6465 BFD_RELOC_NIOS2_GLOB_DAT
6467 BFD_RELOC_NIOS2_JUMP_SLOT
6469 BFD_RELOC_NIOS2_RELATIVE
6471 BFD_RELOC_NIOS2_GOTOFF
6473 BFD_RELOC_NIOS2_CALL26_NOAT
6475 BFD_RELOC_NIOS2_GOT_LO
6477 BFD_RELOC_NIOS2_GOT_HA
6479 BFD_RELOC_NIOS2_CALL_LO
6481 BFD_RELOC_NIOS2_CALL_HA
6483 BFD_RELOC_NIOS2_R2_S12
6485 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6487 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6489 BFD_RELOC_NIOS2_R2_T1I7_2
6491 BFD_RELOC_NIOS2_R2_T2I4
6493 BFD_RELOC_NIOS2_R2_T2I4_1
6495 BFD_RELOC_NIOS2_R2_T2I4_2
6497 BFD_RELOC_NIOS2_R2_X1I7_2
6499 BFD_RELOC_NIOS2_R2_X2L5
6501 BFD_RELOC_NIOS2_R2_F1I5_2
6503 BFD_RELOC_NIOS2_R2_L5I4X1
6505 BFD_RELOC_NIOS2_R2_T1X1I6
6507 BFD_RELOC_NIOS2_R2_T1X1I6_2
6509 Relocations used by the Altera Nios II core.
6514 PRU LDI 16-bit unsigned data-memory relocation.
6516 BFD_RELOC_PRU_U16_PMEMIMM
6518 PRU LDI 16-bit unsigned instruction-memory relocation.
6522 PRU relocation for two consecutive LDI load instructions that load a
6523 32 bit value into a register. If the higher bits are all zero, then
6524 the second instruction may be relaxed.
6526 BFD_RELOC_PRU_S10_PCREL
6528 PRU QBBx 10-bit signed PC-relative relocation.
6530 BFD_RELOC_PRU_U8_PCREL
6532 PRU 8-bit unsigned relocation used for the LOOP instruction.
6534 BFD_RELOC_PRU_32_PMEM
6536 BFD_RELOC_PRU_16_PMEM
6538 PRU Program Memory relocations. Used to convert from byte addressing to
6539 32-bit word addressing.
6541 BFD_RELOC_PRU_GNU_DIFF8
6543 BFD_RELOC_PRU_GNU_DIFF16
6545 BFD_RELOC_PRU_GNU_DIFF32
6547 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6549 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6551 PRU relocations to mark the difference of two local symbols.
6552 These are only needed to support linker relaxation and can be ignored
6553 when not relaxing. The field is set to the value of the difference
6554 assuming no relaxation. The relocation encodes the position of the
6555 second symbol so the linker can determine whether to adjust the field
6556 value. The PMEM variants encode the word difference, instead of byte
6557 difference between symbols.
6560 BFD_RELOC_IQ2000_OFFSET_16
6562 BFD_RELOC_IQ2000_OFFSET_21
6564 BFD_RELOC_IQ2000_UHI16
6569 BFD_RELOC_XTENSA_RTLD
6571 Special Xtensa relocation used only by PLT entries in ELF shared
6572 objects to indicate that the runtime linker should set the value
6573 to one of its own internal functions or data structures.
6575 BFD_RELOC_XTENSA_GLOB_DAT
6577 BFD_RELOC_XTENSA_JMP_SLOT
6579 BFD_RELOC_XTENSA_RELATIVE
6581 Xtensa relocations for ELF shared objects.
6583 BFD_RELOC_XTENSA_PLT
6585 Xtensa relocation used in ELF object files for symbols that may require
6586 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6588 BFD_RELOC_XTENSA_DIFF8
6590 BFD_RELOC_XTENSA_DIFF16
6592 BFD_RELOC_XTENSA_DIFF32
6594 Xtensa relocations to mark the difference of two local symbols.
6595 These are only needed to support linker relaxation and can be ignored
6596 when not relaxing. The field is set to the value of the difference
6597 assuming no relaxation. The relocation encodes the position of the
6598 first symbol so the linker can determine whether to adjust the field
6601 BFD_RELOC_XTENSA_SLOT0_OP
6603 BFD_RELOC_XTENSA_SLOT1_OP
6605 BFD_RELOC_XTENSA_SLOT2_OP
6607 BFD_RELOC_XTENSA_SLOT3_OP
6609 BFD_RELOC_XTENSA_SLOT4_OP
6611 BFD_RELOC_XTENSA_SLOT5_OP
6613 BFD_RELOC_XTENSA_SLOT6_OP
6615 BFD_RELOC_XTENSA_SLOT7_OP
6617 BFD_RELOC_XTENSA_SLOT8_OP
6619 BFD_RELOC_XTENSA_SLOT9_OP
6621 BFD_RELOC_XTENSA_SLOT10_OP
6623 BFD_RELOC_XTENSA_SLOT11_OP
6625 BFD_RELOC_XTENSA_SLOT12_OP
6627 BFD_RELOC_XTENSA_SLOT13_OP
6629 BFD_RELOC_XTENSA_SLOT14_OP
6631 Generic Xtensa relocations for instruction operands. Only the slot
6632 number is encoded in the relocation. The relocation applies to the
6633 last PC-relative immediate operand, or if there are no PC-relative
6634 immediates, to the last immediate operand.
6636 BFD_RELOC_XTENSA_SLOT0_ALT
6638 BFD_RELOC_XTENSA_SLOT1_ALT
6640 BFD_RELOC_XTENSA_SLOT2_ALT
6642 BFD_RELOC_XTENSA_SLOT3_ALT
6644 BFD_RELOC_XTENSA_SLOT4_ALT
6646 BFD_RELOC_XTENSA_SLOT5_ALT
6648 BFD_RELOC_XTENSA_SLOT6_ALT
6650 BFD_RELOC_XTENSA_SLOT7_ALT
6652 BFD_RELOC_XTENSA_SLOT8_ALT
6654 BFD_RELOC_XTENSA_SLOT9_ALT
6656 BFD_RELOC_XTENSA_SLOT10_ALT
6658 BFD_RELOC_XTENSA_SLOT11_ALT
6660 BFD_RELOC_XTENSA_SLOT12_ALT
6662 BFD_RELOC_XTENSA_SLOT13_ALT
6664 BFD_RELOC_XTENSA_SLOT14_ALT
6666 Alternate Xtensa relocations. Only the slot is encoded in the
6667 relocation. The meaning of these relocations is opcode-specific.
6669 BFD_RELOC_XTENSA_OP0
6671 BFD_RELOC_XTENSA_OP1
6673 BFD_RELOC_XTENSA_OP2
6675 Xtensa relocations for backward compatibility. These have all been
6676 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6678 BFD_RELOC_XTENSA_ASM_EXPAND
6680 Xtensa relocation to mark that the assembler expanded the
6681 instructions from an original target. The expansion size is
6682 encoded in the reloc size.
6684 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6686 Xtensa relocation to mark that the linker should simplify
6687 assembler-expanded instructions. This is commonly used
6688 internally by the linker after analysis of a
6689 BFD_RELOC_XTENSA_ASM_EXPAND.
6691 BFD_RELOC_XTENSA_TLSDESC_FN
6693 BFD_RELOC_XTENSA_TLSDESC_ARG
6695 BFD_RELOC_XTENSA_TLS_DTPOFF
6697 BFD_RELOC_XTENSA_TLS_TPOFF
6699 BFD_RELOC_XTENSA_TLS_FUNC
6701 BFD_RELOC_XTENSA_TLS_ARG
6703 BFD_RELOC_XTENSA_TLS_CALL
6705 Xtensa TLS relocations.
6710 8 bit signed offset in (ix+d) or (iy+d).
6728 BFD_RELOC_LM32_BRANCH
6730 BFD_RELOC_LM32_16_GOT
6732 BFD_RELOC_LM32_GOTOFF_HI16
6734 BFD_RELOC_LM32_GOTOFF_LO16
6738 BFD_RELOC_LM32_GLOB_DAT
6740 BFD_RELOC_LM32_JMP_SLOT
6742 BFD_RELOC_LM32_RELATIVE
6744 Lattice Mico32 relocations.
6747 BFD_RELOC_MACH_O_SECTDIFF
6749 Difference between two section addreses. Must be followed by a
6750 BFD_RELOC_MACH_O_PAIR.
6752 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6754 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6756 BFD_RELOC_MACH_O_PAIR
6758 Pair of relocation. Contains the first symbol.
6760 BFD_RELOC_MACH_O_SUBTRACTOR32
6762 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6764 BFD_RELOC_MACH_O_SUBTRACTOR64
6766 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6769 BFD_RELOC_MACH_O_X86_64_BRANCH32
6771 BFD_RELOC_MACH_O_X86_64_BRANCH8
6773 PCREL relocations. They are marked as branch to create PLT entry if
6776 BFD_RELOC_MACH_O_X86_64_GOT
6778 Used when referencing a GOT entry.
6780 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6782 Used when loading a GOT entry with movq. It is specially marked so that
6783 the linker could optimize the movq to a leaq if possible.
6785 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6787 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6789 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6791 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6793 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6795 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6799 BFD_RELOC_MACH_O_ARM64_ADDEND
6801 Addend for PAGE or PAGEOFF.
6803 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6805 Relative offset to page of GOT slot.
6807 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6809 Relative offset within page of GOT slot.
6811 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6813 Address of a GOT entry.
6816 BFD_RELOC_MICROBLAZE_32_LO
6818 This is a 32 bit reloc for the microblaze that stores the
6819 low 16 bits of a value
6821 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6823 This is a 32 bit pc-relative reloc for the microblaze that
6824 stores the low 16 bits of a value
6826 BFD_RELOC_MICROBLAZE_32_ROSDA
6828 This is a 32 bit reloc for the microblaze that stores a
6829 value relative to the read-only small data area anchor
6831 BFD_RELOC_MICROBLAZE_32_RWSDA
6833 This is a 32 bit reloc for the microblaze that stores a
6834 value relative to the read-write small data area anchor
6836 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6838 This is a 32 bit reloc for the microblaze to handle
6839 expressions of the form "Symbol Op Symbol"
6841 BFD_RELOC_MICROBLAZE_64_NONE
6843 This is a 64 bit reloc that stores the 32 bit pc relative
6844 value in two words (with an imm instruction). No relocation is
6845 done here - only used for relaxing
6847 BFD_RELOC_MICROBLAZE_64_GOTPC
6849 This is a 64 bit reloc that stores the 32 bit pc relative
6850 value in two words (with an imm instruction). The relocation is
6851 PC-relative GOT offset
6853 BFD_RELOC_MICROBLAZE_64_GOT
6855 This is a 64 bit reloc that stores the 32 bit pc relative
6856 value in two words (with an imm instruction). The relocation is
6859 BFD_RELOC_MICROBLAZE_64_PLT
6861 This is a 64 bit reloc that stores the 32 bit pc relative
6862 value in two words (with an imm instruction). The relocation is
6863 PC-relative offset into PLT
6865 BFD_RELOC_MICROBLAZE_64_GOTOFF
6867 This is a 64 bit reloc that stores the 32 bit GOT relative
6868 value in two words (with an imm instruction). The relocation is
6869 relative offset from _GLOBAL_OFFSET_TABLE_
6871 BFD_RELOC_MICROBLAZE_32_GOTOFF
6873 This is a 32 bit reloc that stores the 32 bit GOT relative
6874 value in a word. The relocation is relative offset from
6875 _GLOBAL_OFFSET_TABLE_
6877 BFD_RELOC_MICROBLAZE_COPY
6879 This is used to tell the dynamic linker to copy the value out of
6880 the dynamic object into the runtime process image.
6882 BFD_RELOC_MICROBLAZE_64_TLS
6886 BFD_RELOC_MICROBLAZE_64_TLSGD
6888 This is a 64 bit reloc that stores the 32 bit GOT relative value
6889 of the GOT TLS GD info entry in two words (with an imm instruction). The
6890 relocation is GOT offset.
6892 BFD_RELOC_MICROBLAZE_64_TLSLD
6894 This is a 64 bit reloc that stores the 32 bit GOT relative value
6895 of the GOT TLS LD info entry in two words (with an imm instruction). The
6896 relocation is GOT offset.
6898 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6900 This is a 32 bit reloc that stores the Module ID to GOT(n).
6902 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6904 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6906 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6908 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6911 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6913 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6914 to two words (uses imm instruction).
6916 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6918 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6919 to two words (uses imm instruction).
6921 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6923 This is a 64 bit reloc that stores the 32 bit pc relative
6924 value in two words (with an imm instruction). The relocation is
6925 PC-relative offset from start of TEXT.
6927 BFD_RELOC_MICROBLAZE_64_TEXTREL
6929 This is a 64 bit reloc that stores the 32 bit offset
6930 value in two words (with an imm instruction). The relocation is
6931 relative offset from start of TEXT.
6934 BFD_RELOC_AARCH64_RELOC_START
6936 AArch64 pseudo relocation code to mark the start of the AArch64
6937 relocation enumerators. N.B. the order of the enumerators is
6938 important as several tables in the AArch64 bfd backend are indexed
6939 by these enumerators; make sure they are all synced.
6941 BFD_RELOC_AARCH64_NULL
6943 Deprecated AArch64 null relocation code.
6945 BFD_RELOC_AARCH64_NONE
6947 AArch64 null relocation code.
6949 BFD_RELOC_AARCH64_64
6951 BFD_RELOC_AARCH64_32
6953 BFD_RELOC_AARCH64_16
6955 Basic absolute relocations of N bits. These are equivalent to
6956 BFD_RELOC_N and they were added to assist the indexing of the howto
6959 BFD_RELOC_AARCH64_64_PCREL
6961 BFD_RELOC_AARCH64_32_PCREL
6963 BFD_RELOC_AARCH64_16_PCREL
6965 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6966 and they were added to assist the indexing of the howto table.
6968 BFD_RELOC_AARCH64_MOVW_G0
6970 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6971 of an unsigned address/value.
6973 BFD_RELOC_AARCH64_MOVW_G0_NC
6975 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6976 an address/value. No overflow checking.
6978 BFD_RELOC_AARCH64_MOVW_G1
6980 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6981 of an unsigned address/value.
6983 BFD_RELOC_AARCH64_MOVW_G1_NC
6985 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6986 of an address/value. No overflow checking.
6988 BFD_RELOC_AARCH64_MOVW_G2
6990 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6991 of an unsigned address/value.
6993 BFD_RELOC_AARCH64_MOVW_G2_NC
6995 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6996 of an address/value. No overflow checking.
6998 BFD_RELOC_AARCH64_MOVW_G3
7000 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7001 of a signed or unsigned address/value.
7003 BFD_RELOC_AARCH64_MOVW_G0_S
7005 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7006 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7009 BFD_RELOC_AARCH64_MOVW_G1_S
7011 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7012 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7015 BFD_RELOC_AARCH64_MOVW_G2_S
7017 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7018 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7021 BFD_RELOC_AARCH64_MOVW_PREL_G0
7023 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7024 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7027 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7029 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7030 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7033 BFD_RELOC_AARCH64_MOVW_PREL_G1
7035 AArch64 MOVK instruction with most significant bits 16 to 31
7038 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7040 AArch64 MOVK instruction with most significant bits 16 to 31
7043 BFD_RELOC_AARCH64_MOVW_PREL_G2
7045 AArch64 MOVK instruction with most significant bits 32 to 47
7048 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7050 AArch64 MOVK instruction with most significant bits 32 to 47
7053 BFD_RELOC_AARCH64_MOVW_PREL_G3
7055 AArch64 MOVK instruction with most significant bits 47 to 63
7058 BFD_RELOC_AARCH64_LD_LO19_PCREL
7060 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7061 offset. The lowest two bits must be zero and are not stored in the
7062 instruction, giving a 21 bit signed byte offset.
7064 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7066 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7068 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7070 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7071 offset, giving a 4KB aligned page base address.
7073 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7075 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7076 offset, giving a 4KB aligned page base address, but with no overflow
7079 BFD_RELOC_AARCH64_ADD_LO12
7081 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7082 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7084 BFD_RELOC_AARCH64_LDST8_LO12
7086 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7087 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7089 BFD_RELOC_AARCH64_TSTBR14
7091 AArch64 14 bit pc-relative test bit and branch.
7092 The lowest two bits must be zero and are not stored in the instruction,
7093 giving a 16 bit signed byte offset.
7095 BFD_RELOC_AARCH64_BRANCH19
7097 AArch64 19 bit pc-relative conditional branch and compare & branch.
7098 The lowest two bits must be zero and are not stored in the instruction,
7099 giving a 21 bit signed byte offset.
7101 BFD_RELOC_AARCH64_JUMP26
7103 AArch64 26 bit pc-relative unconditional branch.
7104 The lowest two bits must be zero and are not stored in the instruction,
7105 giving a 28 bit signed byte offset.
7107 BFD_RELOC_AARCH64_CALL26
7109 AArch64 26 bit pc-relative unconditional branch and link.
7110 The lowest two bits must be zero and are not stored in the instruction,
7111 giving a 28 bit signed byte offset.
7113 BFD_RELOC_AARCH64_LDST16_LO12
7115 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7116 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7118 BFD_RELOC_AARCH64_LDST32_LO12
7120 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7121 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7123 BFD_RELOC_AARCH64_LDST64_LO12
7125 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7126 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7128 BFD_RELOC_AARCH64_LDST128_LO12
7130 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7131 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7133 BFD_RELOC_AARCH64_GOT_LD_PREL19
7135 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7136 offset of the global offset table entry for a symbol. The lowest two
7137 bits must be zero and are not stored in the instruction, giving a 21
7138 bit signed byte offset. This relocation type requires signed overflow
7141 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7143 Get to the page base of the global offset table entry for a symbol as
7144 part of an ADRP instruction using a 21 bit PC relative value.Used in
7145 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7147 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7149 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7150 the GOT entry for this symbol. Used in conjunction with
7151 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7153 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7155 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7156 the GOT entry for this symbol. Used in conjunction with
7157 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7159 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7161 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7162 for this symbol. Valid in LP64 ABI only.
7164 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7166 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7167 for this symbol. Valid in LP64 ABI only.
7169 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7171 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7172 the GOT entry for this symbol. Valid in LP64 ABI only.
7174 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7176 Scaled 14 bit byte offset to the page base of the global offset table.
7178 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7180 Scaled 15 bit byte offset to the page base of the global offset table.
7182 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7184 Get to the page base of the global offset table entry for a symbols
7185 tls_index structure as part of an adrp instruction using a 21 bit PC
7186 relative value. Used in conjunction with
7187 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7189 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7191 AArch64 TLS General Dynamic
7193 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7195 Unsigned 12 bit byte offset to global offset table entry for a symbols
7196 tls_index structure. Used in conjunction with
7197 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7199 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7201 AArch64 TLS General Dynamic relocation.
7203 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7205 AArch64 TLS General Dynamic relocation.
7207 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7209 AArch64 TLS INITIAL EXEC relocation.
7211 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7213 AArch64 TLS INITIAL EXEC relocation.
7215 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7217 AArch64 TLS INITIAL EXEC relocation.
7219 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7221 AArch64 TLS INITIAL EXEC relocation.
7223 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7225 AArch64 TLS INITIAL EXEC relocation.
7227 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7229 AArch64 TLS INITIAL EXEC relocation.
7231 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7233 bit[23:12] of byte offset to module TLS base address.
7235 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7237 Unsigned 12 bit byte offset to module TLS base address.
7239 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7241 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7243 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7245 Unsigned 12 bit byte offset to global offset table entry for a symbols
7246 tls_index structure. Used in conjunction with
7247 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7249 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7251 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7254 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7256 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7258 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7260 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7263 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7265 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7267 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7269 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7272 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7274 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7276 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7278 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7281 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7283 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7285 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7287 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7290 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7292 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7294 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7296 bit[15:0] of byte offset to module TLS base address.
7298 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7300 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7302 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7304 bit[31:16] of byte offset to module TLS base address.
7306 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7308 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7310 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7312 bit[47:32] of byte offset to module TLS base address.
7314 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7316 AArch64 TLS LOCAL EXEC relocation.
7318 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7320 AArch64 TLS LOCAL EXEC relocation.
7322 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7324 AArch64 TLS LOCAL EXEC relocation.
7326 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7328 AArch64 TLS LOCAL EXEC relocation.
7330 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7332 AArch64 TLS LOCAL EXEC relocation.
7334 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7336 AArch64 TLS LOCAL EXEC relocation.
7338 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7340 AArch64 TLS LOCAL EXEC relocation.
7342 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7344 AArch64 TLS LOCAL EXEC relocation.
7346 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7348 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7351 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7353 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7355 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7357 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7360 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7362 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7364 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7366 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7369 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7371 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7373 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7375 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7378 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7380 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7382 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7384 AArch64 TLS DESC relocation.
7386 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7388 AArch64 TLS DESC relocation.
7390 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7392 AArch64 TLS DESC relocation.
7394 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7396 AArch64 TLS DESC relocation.
7398 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7400 AArch64 TLS DESC relocation.
7402 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7404 AArch64 TLS DESC relocation.
7406 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7408 AArch64 TLS DESC relocation.
7410 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7412 AArch64 TLS DESC relocation.
7414 BFD_RELOC_AARCH64_TLSDESC_LDR
7416 AArch64 TLS DESC relocation.
7418 BFD_RELOC_AARCH64_TLSDESC_ADD
7420 AArch64 TLS DESC relocation.
7422 BFD_RELOC_AARCH64_TLSDESC_CALL
7424 AArch64 TLS DESC relocation.
7426 BFD_RELOC_AARCH64_COPY
7428 AArch64 TLS relocation.
7430 BFD_RELOC_AARCH64_GLOB_DAT
7432 AArch64 TLS relocation.
7434 BFD_RELOC_AARCH64_JUMP_SLOT
7436 AArch64 TLS relocation.
7438 BFD_RELOC_AARCH64_RELATIVE
7440 AArch64 TLS relocation.
7442 BFD_RELOC_AARCH64_TLS_DTPMOD
7444 AArch64 TLS relocation.
7446 BFD_RELOC_AARCH64_TLS_DTPREL
7448 AArch64 TLS relocation.
7450 BFD_RELOC_AARCH64_TLS_TPREL
7452 AArch64 TLS relocation.
7454 BFD_RELOC_AARCH64_TLSDESC
7456 AArch64 TLS relocation.
7458 BFD_RELOC_AARCH64_IRELATIVE
7460 AArch64 support for STT_GNU_IFUNC.
7462 BFD_RELOC_AARCH64_RELOC_END
7464 AArch64 pseudo relocation code to mark the end of the AArch64
7465 relocation enumerators that have direct mapping to ELF reloc codes.
7466 There are a few more enumerators after this one; those are mainly
7467 used by the AArch64 assembler for the internal fixup or to select
7468 one of the above enumerators.
7470 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7472 AArch64 pseudo relocation code to be used internally by the AArch64
7473 assembler and not (currently) written to any object files.
7475 BFD_RELOC_AARCH64_LDST_LO12
7477 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7478 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7480 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7482 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7483 used internally by the AArch64 assembler and not (currently) written to
7486 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7488 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7490 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7492 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7493 used internally by the AArch64 assembler and not (currently) written to
7496 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7498 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7500 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7502 AArch64 pseudo relocation code to be used internally by the AArch64
7503 assembler and not (currently) written to any object files.
7505 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7507 AArch64 pseudo relocation code to be used internally by the AArch64
7508 assembler and not (currently) written to any object files.
7510 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7512 AArch64 pseudo relocation code to be used internally by the AArch64
7513 assembler and not (currently) written to any object files.
7515 BFD_RELOC_TILEPRO_COPY
7517 BFD_RELOC_TILEPRO_GLOB_DAT
7519 BFD_RELOC_TILEPRO_JMP_SLOT
7521 BFD_RELOC_TILEPRO_RELATIVE
7523 BFD_RELOC_TILEPRO_BROFF_X1
7525 BFD_RELOC_TILEPRO_JOFFLONG_X1
7527 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7529 BFD_RELOC_TILEPRO_IMM8_X0
7531 BFD_RELOC_TILEPRO_IMM8_Y0
7533 BFD_RELOC_TILEPRO_IMM8_X1
7535 BFD_RELOC_TILEPRO_IMM8_Y1
7537 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7539 BFD_RELOC_TILEPRO_MT_IMM15_X1
7541 BFD_RELOC_TILEPRO_MF_IMM15_X1
7543 BFD_RELOC_TILEPRO_IMM16_X0
7545 BFD_RELOC_TILEPRO_IMM16_X1
7547 BFD_RELOC_TILEPRO_IMM16_X0_LO
7549 BFD_RELOC_TILEPRO_IMM16_X1_LO
7551 BFD_RELOC_TILEPRO_IMM16_X0_HI
7553 BFD_RELOC_TILEPRO_IMM16_X1_HI
7555 BFD_RELOC_TILEPRO_IMM16_X0_HA
7557 BFD_RELOC_TILEPRO_IMM16_X1_HA
7559 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7561 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7563 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7565 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7567 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7569 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7571 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7573 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7575 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7577 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7579 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7581 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7583 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7585 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7587 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7589 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7591 BFD_RELOC_TILEPRO_MMSTART_X0
7593 BFD_RELOC_TILEPRO_MMEND_X0
7595 BFD_RELOC_TILEPRO_MMSTART_X1
7597 BFD_RELOC_TILEPRO_MMEND_X1
7599 BFD_RELOC_TILEPRO_SHAMT_X0
7601 BFD_RELOC_TILEPRO_SHAMT_X1
7603 BFD_RELOC_TILEPRO_SHAMT_Y0
7605 BFD_RELOC_TILEPRO_SHAMT_Y1
7607 BFD_RELOC_TILEPRO_TLS_GD_CALL
7609 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7611 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7613 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7615 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7617 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7619 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7621 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7623 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7625 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7627 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7629 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7631 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7633 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7635 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7637 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7639 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7641 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7643 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7645 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7647 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7649 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7651 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7653 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7655 BFD_RELOC_TILEPRO_TLS_TPOFF32
7657 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7659 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7661 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7663 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7665 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7667 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7669 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7671 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7673 Tilera TILEPro Relocations.
7675 BFD_RELOC_TILEGX_HW0
7677 BFD_RELOC_TILEGX_HW1
7679 BFD_RELOC_TILEGX_HW2
7681 BFD_RELOC_TILEGX_HW3
7683 BFD_RELOC_TILEGX_HW0_LAST
7685 BFD_RELOC_TILEGX_HW1_LAST
7687 BFD_RELOC_TILEGX_HW2_LAST
7689 BFD_RELOC_TILEGX_COPY
7691 BFD_RELOC_TILEGX_GLOB_DAT
7693 BFD_RELOC_TILEGX_JMP_SLOT
7695 BFD_RELOC_TILEGX_RELATIVE
7697 BFD_RELOC_TILEGX_BROFF_X1
7699 BFD_RELOC_TILEGX_JUMPOFF_X1
7701 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7703 BFD_RELOC_TILEGX_IMM8_X0
7705 BFD_RELOC_TILEGX_IMM8_Y0
7707 BFD_RELOC_TILEGX_IMM8_X1
7709 BFD_RELOC_TILEGX_IMM8_Y1
7711 BFD_RELOC_TILEGX_DEST_IMM8_X1
7713 BFD_RELOC_TILEGX_MT_IMM14_X1
7715 BFD_RELOC_TILEGX_MF_IMM14_X1
7717 BFD_RELOC_TILEGX_MMSTART_X0
7719 BFD_RELOC_TILEGX_MMEND_X0
7721 BFD_RELOC_TILEGX_SHAMT_X0
7723 BFD_RELOC_TILEGX_SHAMT_X1
7725 BFD_RELOC_TILEGX_SHAMT_Y0
7727 BFD_RELOC_TILEGX_SHAMT_Y1
7729 BFD_RELOC_TILEGX_IMM16_X0_HW0
7731 BFD_RELOC_TILEGX_IMM16_X1_HW0
7733 BFD_RELOC_TILEGX_IMM16_X0_HW1
7735 BFD_RELOC_TILEGX_IMM16_X1_HW1
7737 BFD_RELOC_TILEGX_IMM16_X0_HW2
7739 BFD_RELOC_TILEGX_IMM16_X1_HW2
7741 BFD_RELOC_TILEGX_IMM16_X0_HW3
7743 BFD_RELOC_TILEGX_IMM16_X1_HW3
7745 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7747 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7749 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7751 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7753 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7755 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7757 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7759 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7761 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7763 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7765 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7767 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7769 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7771 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7773 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7775 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7777 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7779 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7781 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7783 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7785 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7787 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7789 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7791 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7793 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7795 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7797 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7799 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7801 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7803 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7805 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7807 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7809 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7811 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7813 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7815 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7817 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7819 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7821 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7823 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7825 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7827 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7829 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7831 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7833 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7835 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7837 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7839 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7841 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7843 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7845 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7847 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7849 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7851 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7853 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7855 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7857 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7859 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7861 BFD_RELOC_TILEGX_TLS_DTPMOD64
7863 BFD_RELOC_TILEGX_TLS_DTPOFF64
7865 BFD_RELOC_TILEGX_TLS_TPOFF64
7867 BFD_RELOC_TILEGX_TLS_DTPMOD32
7869 BFD_RELOC_TILEGX_TLS_DTPOFF32
7871 BFD_RELOC_TILEGX_TLS_TPOFF32
7873 BFD_RELOC_TILEGX_TLS_GD_CALL
7875 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7877 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7879 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7881 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7883 BFD_RELOC_TILEGX_TLS_IE_LOAD
7885 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7887 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7889 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7891 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7893 Tilera TILE-Gx Relocations.
7896 BFD_RELOC_EPIPHANY_SIMM8
7898 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7900 BFD_RELOC_EPIPHANY_SIMM24
7902 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7904 BFD_RELOC_EPIPHANY_HIGH
7906 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7908 BFD_RELOC_EPIPHANY_LOW
7910 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7912 BFD_RELOC_EPIPHANY_SIMM11
7914 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7916 BFD_RELOC_EPIPHANY_IMM11
7918 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7920 BFD_RELOC_EPIPHANY_IMM8
7922 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7925 BFD_RELOC_VISIUM_HI16
7927 BFD_RELOC_VISIUM_LO16
7929 BFD_RELOC_VISIUM_IM16
7931 BFD_RELOC_VISIUM_REL16
7933 BFD_RELOC_VISIUM_HI16_PCREL
7935 BFD_RELOC_VISIUM_LO16_PCREL
7937 BFD_RELOC_VISIUM_IM16_PCREL
7942 BFD_RELOC_WASM32_LEB128
7944 BFD_RELOC_WASM32_LEB128_GOT
7946 BFD_RELOC_WASM32_LEB128_GOT_CODE
7948 BFD_RELOC_WASM32_LEB128_PLT
7950 BFD_RELOC_WASM32_PLT_INDEX
7952 BFD_RELOC_WASM32_ABS32_CODE
7954 BFD_RELOC_WASM32_COPY
7956 BFD_RELOC_WASM32_CODE_POINTER
7958 BFD_RELOC_WASM32_INDEX
7960 BFD_RELOC_WASM32_PLT_SIG
7962 WebAssembly relocations.
7968 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7973 bfd_reloc_type_lookup
7974 bfd_reloc_name_lookup
7977 reloc_howto_type *bfd_reloc_type_lookup
7978 (bfd *abfd, bfd_reloc_code_real_type code);
7979 reloc_howto_type *bfd_reloc_name_lookup
7980 (bfd *abfd, const char *reloc_name);
7983 Return a pointer to a howto structure which, when
7984 invoked, will perform the relocation @var{code} on data from the
7990 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
7992 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
7996 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
7998 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
8001 static reloc_howto_type bfd_howto_32 =
8002 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
8006 bfd_default_reloc_type_lookup
8009 reloc_howto_type *bfd_default_reloc_type_lookup
8010 (bfd *abfd, bfd_reloc_code_real_type code);
8013 Provides a default relocation lookup routine for any architecture.
8018 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8022 case BFD_RELOC_CTOR:
8023 /* The type of reloc used in a ctor, which will be as wide as the
8024 address - so either a 64, 32, or 16 bitter. */
8025 switch (bfd_arch_bits_per_address (abfd))
8031 return &bfd_howto_32;
8047 bfd_get_reloc_code_name
8050 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8053 Provides a printable name for the supplied relocation code.
8054 Useful mainly for printing error messages.
8058 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
8060 if (code > BFD_RELOC_UNUSED)
8062 return bfd_reloc_code_real_names[code];
8067 bfd_generic_relax_section
8070 bfd_boolean bfd_generic_relax_section
8073 struct bfd_link_info *,
8077 Provides default handling for relaxing for back ends which
8082 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
8083 asection *section ATTRIBUTE_UNUSED,
8084 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
8087 if (bfd_link_relocatable (link_info))
8088 (*link_info->callbacks->einfo)
8089 (_("%P%F: --relax and -r may not be used together\n"));
8097 bfd_generic_gc_sections
8100 bfd_boolean bfd_generic_gc_sections
8101 (bfd *, struct bfd_link_info *);
8104 Provides default handling for relaxing for back ends which
8105 don't do section gc -- i.e., does nothing.
8109 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
8110 struct bfd_link_info *info ATTRIBUTE_UNUSED)
8117 bfd_generic_lookup_section_flags
8120 bfd_boolean bfd_generic_lookup_section_flags
8121 (struct bfd_link_info *, struct flag_info *, asection *);
8124 Provides default handling for section flags lookup
8125 -- i.e., does nothing.
8126 Returns FALSE if the section should be omitted, otherwise TRUE.
8130 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
8131 struct flag_info *flaginfo,
8132 asection *section ATTRIBUTE_UNUSED)
8134 if (flaginfo != NULL)
8136 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8144 bfd_generic_merge_sections
8147 bfd_boolean bfd_generic_merge_sections
8148 (bfd *, struct bfd_link_info *);
8151 Provides default handling for SEC_MERGE section merging for back ends
8152 which don't have SEC_MERGE support -- i.e., does nothing.
8156 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
8157 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
8164 bfd_generic_get_relocated_section_contents
8167 bfd_byte *bfd_generic_get_relocated_section_contents
8169 struct bfd_link_info *link_info,
8170 struct bfd_link_order *link_order,
8172 bfd_boolean relocatable,
8176 Provides default handling of relocation effort for back ends
8177 which can't be bothered to do it efficiently.
8182 bfd_generic_get_relocated_section_contents (bfd *abfd,
8183 struct bfd_link_info *link_info,
8184 struct bfd_link_order *link_order,
8186 bfd_boolean relocatable,
8189 bfd *input_bfd = link_order->u.indirect.section->owner;
8190 asection *input_section = link_order->u.indirect.section;
8192 arelent **reloc_vector;
8195 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
8199 /* Read in the section. */
8200 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
8206 if (reloc_size == 0)
8209 reloc_vector = (arelent **) bfd_malloc (reloc_size);
8210 if (reloc_vector == NULL)
8213 reloc_count = bfd_canonicalize_reloc (input_bfd,
8217 if (reloc_count < 0)
8220 if (reloc_count > 0)
8224 for (parent = reloc_vector; *parent != NULL; parent++)
8226 char *error_message = NULL;
8228 bfd_reloc_status_type r;
8230 symbol = *(*parent)->sym_ptr_ptr;
8231 /* PR ld/19628: A specially crafted input file
8232 can result in a NULL symbol pointer here. */
8235 link_info->callbacks->einfo
8236 /* xgettext:c-format */
8237 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8238 abfd, input_section, (* parent)->address);
8242 if (symbol->section && discarded_section (symbol->section))
8245 static reloc_howto_type none_howto
8246 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
8247 "unused", FALSE, 0, 0, FALSE);
8249 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
8250 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
8252 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
8253 (*parent)->addend = 0;
8254 (*parent)->howto = &none_howto;
8258 r = bfd_perform_relocation (input_bfd,
8262 relocatable ? abfd : NULL,
8267 asection *os = input_section->output_section;
8269 /* A partial link, so keep the relocs. */
8270 os->orelocation[os->reloc_count] = *parent;
8274 if (r != bfd_reloc_ok)
8278 case bfd_reloc_undefined:
8279 (*link_info->callbacks->undefined_symbol)
8280 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8281 input_bfd, input_section, (*parent)->address, TRUE);
8283 case bfd_reloc_dangerous:
8284 BFD_ASSERT (error_message != NULL);
8285 (*link_info->callbacks->reloc_dangerous)
8286 (link_info, error_message,
8287 input_bfd, input_section, (*parent)->address);
8289 case bfd_reloc_overflow:
8290 (*link_info->callbacks->reloc_overflow)
8292 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8293 (*parent)->howto->name, (*parent)->addend,
8294 input_bfd, input_section, (*parent)->address);
8296 case bfd_reloc_outofrange:
8298 This error can result when processing some partially
8299 complete binaries. Do not abort, but issue an error
8301 link_info->callbacks->einfo
8302 /* xgettext:c-format */
8303 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8304 abfd, input_section, * parent);
8307 case bfd_reloc_notsupported:
8309 This error can result when processing a corrupt binary.
8310 Do not abort. Issue an error message instead. */
8311 link_info->callbacks->einfo
8312 /* xgettext:c-format */
8313 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8314 abfd, input_section, * parent);
8318 /* PR 17512; file: 90c2a92e.
8319 Report unexpected results, without aborting. */
8320 link_info->callbacks->einfo
8321 /* xgettext:c-format */
8322 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8323 abfd, input_section, * parent, r);
8331 free (reloc_vector);
8335 free (reloc_vector);
8341 _bfd_generic_set_reloc
8344 void _bfd_generic_set_reloc
8348 unsigned int count);
8351 Installs a new set of internal relocations in SECTION.
8355 _bfd_generic_set_reloc (bfd *abfd ATTRIBUTE_UNUSED,
8360 section->orelocation = relptr;
8361 section->reloc_count = count;
8366 _bfd_unrecognized_reloc
8369 bfd_boolean _bfd_unrecognized_reloc
8372 unsigned int r_type);
8375 Reports an unrecognized reloc.
8376 Written as a function in order to reduce code duplication.
8377 Returns FALSE so that it can be called from a return statement.
8381 _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type)
8383 /* xgettext:c-format */
8384 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8385 abfd, r_type, section);
8387 /* PR 21803: Suggest the most likely cause of this error. */
8388 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8389 BFD_VERSION_STRING);
8391 bfd_set_error (bfd_error_bad_value);
8396 _bfd_norelocs_bfd_reloc_type_lookup
8398 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED)
8400 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8404 _bfd_norelocs_bfd_reloc_name_lookup (bfd *abfd,
8405 const char *reloc_name ATTRIBUTE_UNUSED)
8407 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8411 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd *abfd,
8412 arelent **relp ATTRIBUTE_UNUSED,
8413 asymbol **symp ATTRIBUTE_UNUSED)
8415 return _bfd_long_bfd_n1_error (abfd);