1 /* BFD support for handling relocation entries.
2 Copyright 1990-2013 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type *howto)
451 How relocs are tied together in an <<asection>>:
453 .typedef struct relent_chain
456 . struct relent_chain *next;
462 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
463 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
470 bfd_reloc_status_type bfd_check_overflow
471 (enum complain_overflow how,
472 unsigned int bitsize,
473 unsigned int rightshift,
474 unsigned int addrsize,
478 Perform overflow checking on @var{relocation} which has
479 @var{bitsize} significant bits and will be shifted right by
480 @var{rightshift} bits, on a machine with addresses containing
481 @var{addrsize} significant bits. The result is either of
482 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
486 bfd_reloc_status_type
487 bfd_check_overflow (enum complain_overflow how,
488 unsigned int bitsize,
489 unsigned int rightshift,
490 unsigned int addrsize,
493 bfd_vma fieldmask, addrmask, signmask, ss, a;
494 bfd_reloc_status_type flag = bfd_reloc_ok;
496 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
497 we'll be permissive: extra bits in the field mask will
498 automatically extend the address mask for purposes of the
500 fieldmask = N_ONES (bitsize);
501 signmask = ~fieldmask;
502 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
503 a = (relocation & addrmask) >> rightshift;
507 case complain_overflow_dont:
510 case complain_overflow_signed:
511 /* If any sign bits are set, all sign bits must be set. That
512 is, A must be a valid negative address after shifting. */
513 signmask = ~ (fieldmask >> 1);
516 case complain_overflow_bitfield:
517 /* Bitfields are sometimes signed, sometimes unsigned. We
518 explicitly allow an address wrap too, which means a bitfield
519 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
520 if the value has some, but not all, bits set outside the
523 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
524 flag = bfd_reloc_overflow;
527 case complain_overflow_unsigned:
528 /* We have an overflow if the address does not fit in the field. */
529 if ((a & signmask) != 0)
530 flag = bfd_reloc_overflow;
542 bfd_perform_relocation
545 bfd_reloc_status_type bfd_perform_relocation
547 arelent *reloc_entry,
549 asection *input_section,
551 char **error_message);
554 If @var{output_bfd} is supplied to this function, the
555 generated image will be relocatable; the relocations are
556 copied to the output file after they have been changed to
557 reflect the new state of the world. There are two ways of
558 reflecting the results of partial linkage in an output file:
559 by modifying the output data in place, and by modifying the
560 relocation record. Some native formats (e.g., basic a.out and
561 basic coff) have no way of specifying an addend in the
562 relocation type, so the addend has to go in the output data.
563 This is no big deal since in these formats the output data
564 slot will always be big enough for the addend. Complex reloc
565 types with addends were invented to solve just this problem.
566 The @var{error_message} argument is set to an error message if
567 this return @code{bfd_reloc_dangerous}.
571 bfd_reloc_status_type
572 bfd_perform_relocation (bfd *abfd,
573 arelent *reloc_entry,
575 asection *input_section,
577 char **error_message)
580 bfd_reloc_status_type flag = bfd_reloc_ok;
581 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
582 bfd_vma output_base = 0;
583 reloc_howto_type *howto = reloc_entry->howto;
584 asection *reloc_target_output_section;
587 symbol = *(reloc_entry->sym_ptr_ptr);
588 if (bfd_is_abs_section (symbol->section)
589 && output_bfd != NULL)
591 reloc_entry->address += input_section->output_offset;
595 /* If we are not producing relocatable output, return an error if
596 the symbol is not defined. An undefined weak symbol is
597 considered to have a value of zero (SVR4 ABI, p. 4-27). */
598 if (bfd_is_und_section (symbol->section)
599 && (symbol->flags & BSF_WEAK) == 0
600 && output_bfd == NULL)
601 flag = bfd_reloc_undefined;
603 /* If there is a function supplied to handle this relocation type,
604 call it. It'll return `bfd_reloc_continue' if further processing
606 if (howto->special_function)
608 bfd_reloc_status_type cont;
609 cont = howto->special_function (abfd, reloc_entry, symbol, data,
610 input_section, output_bfd,
612 if (cont != bfd_reloc_continue)
616 /* Is the address of the relocation really within the section? */
617 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
618 return bfd_reloc_outofrange;
620 /* Work out which section the relocation is targeted at and the
621 initial relocation command value. */
623 /* Get symbol value. (Common symbols are special.) */
624 if (bfd_is_com_section (symbol->section))
627 relocation = symbol->value;
629 reloc_target_output_section = symbol->section->output_section;
631 /* Convert input-section-relative symbol value to absolute. */
632 if ((output_bfd && ! howto->partial_inplace)
633 || reloc_target_output_section == NULL)
636 output_base = reloc_target_output_section->vma;
638 relocation += output_base + symbol->section->output_offset;
640 /* Add in supplied addend. */
641 relocation += reloc_entry->addend;
643 /* Here the variable relocation holds the final address of the
644 symbol we are relocating against, plus any addend. */
646 if (howto->pc_relative)
648 /* This is a PC relative relocation. We want to set RELOCATION
649 to the distance between the address of the symbol and the
650 location. RELOCATION is already the address of the symbol.
652 We start by subtracting the address of the section containing
655 If pcrel_offset is set, we must further subtract the position
656 of the location within the section. Some targets arrange for
657 the addend to be the negative of the position of the location
658 within the section; for example, i386-aout does this. For
659 i386-aout, pcrel_offset is FALSE. Some other targets do not
660 include the position of the location; for example, m88kbcs,
661 or ELF. For those targets, pcrel_offset is TRUE.
663 If we are producing relocatable output, then we must ensure
664 that this reloc will be correctly computed when the final
665 relocation is done. If pcrel_offset is FALSE we want to wind
666 up with the negative of the location within the section,
667 which means we must adjust the existing addend by the change
668 in the location within the section. If pcrel_offset is TRUE
669 we do not want to adjust the existing addend at all.
671 FIXME: This seems logical to me, but for the case of
672 producing relocatable output it is not what the code
673 actually does. I don't want to change it, because it seems
674 far too likely that something will break. */
677 input_section->output_section->vma + input_section->output_offset;
679 if (howto->pcrel_offset)
680 relocation -= reloc_entry->address;
683 if (output_bfd != NULL)
685 if (! howto->partial_inplace)
687 /* This is a partial relocation, and we want to apply the relocation
688 to the reloc entry rather than the raw data. Modify the reloc
689 inplace to reflect what we now know. */
690 reloc_entry->addend = relocation;
691 reloc_entry->address += input_section->output_offset;
696 /* This is a partial relocation, but inplace, so modify the
699 If we've relocated with a symbol with a section, change
700 into a ref to the section belonging to the symbol. */
702 reloc_entry->address += input_section->output_offset;
705 if (abfd->xvec->flavour == bfd_target_coff_flavour
706 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
707 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
709 /* For m68k-coff, the addend was being subtracted twice during
710 relocation with -r. Removing the line below this comment
711 fixes that problem; see PR 2953.
713 However, Ian wrote the following, regarding removing the line below,
714 which explains why it is still enabled: --djm
716 If you put a patch like that into BFD you need to check all the COFF
717 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
718 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
719 problem in a different way. There may very well be a reason that the
720 code works as it does.
722 Hmmm. The first obvious point is that bfd_perform_relocation should
723 not have any tests that depend upon the flavour. It's seem like
724 entirely the wrong place for such a thing. The second obvious point
725 is that the current code ignores the reloc addend when producing
726 relocatable output for COFF. That's peculiar. In fact, I really
727 have no idea what the point of the line you want to remove is.
729 A typical COFF reloc subtracts the old value of the symbol and adds in
730 the new value to the location in the object file (if it's a pc
731 relative reloc it adds the difference between the symbol value and the
732 location). When relocating we need to preserve that property.
734 BFD handles this by setting the addend to the negative of the old
735 value of the symbol. Unfortunately it handles common symbols in a
736 non-standard way (it doesn't subtract the old value) but that's a
737 different story (we can't change it without losing backward
738 compatibility with old object files) (coff-i386 does subtract the old
739 value, to be compatible with existing coff-i386 targets, like SCO).
741 So everything works fine when not producing relocatable output. When
742 we are producing relocatable output, logically we should do exactly
743 what we do when not producing relocatable output. Therefore, your
744 patch is correct. In fact, it should probably always just set
745 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
746 add the value into the object file. This won't hurt the COFF code,
747 which doesn't use the addend; I'm not sure what it will do to other
748 formats (the thing to check for would be whether any formats both use
749 the addend and set partial_inplace).
751 When I wanted to make coff-i386 produce relocatable output, I ran
752 into the problem that you are running into: I wanted to remove that
753 line. Rather than risk it, I made the coff-i386 relocs use a special
754 function; it's coff_i386_reloc in coff-i386.c. The function
755 specifically adds the addend field into the object file, knowing that
756 bfd_perform_relocation is not going to. If you remove that line, then
757 coff-i386.c will wind up adding the addend field in twice. It's
758 trivial to fix; it just needs to be done.
760 The problem with removing the line is just that it may break some
761 working code. With BFD it's hard to be sure of anything. The right
762 way to deal with this is simply to build and test at least all the
763 supported COFF targets. It should be straightforward if time and disk
764 space consuming. For each target:
766 2) generate some executable, and link it using -r (I would
767 probably use paranoia.o and link against newlib/libc.a, which
768 for all the supported targets would be available in
769 /usr/cygnus/progressive/H-host/target/lib/libc.a).
770 3) make the change to reloc.c
771 4) rebuild the linker
773 6) if the resulting object files are the same, you have at least
775 7) if they are different you have to figure out which version is
778 relocation -= reloc_entry->addend;
779 reloc_entry->addend = 0;
783 reloc_entry->addend = relocation;
789 reloc_entry->addend = 0;
792 /* FIXME: This overflow checking is incomplete, because the value
793 might have overflowed before we get here. For a correct check we
794 need to compute the value in a size larger than bitsize, but we
795 can't reasonably do that for a reloc the same size as a host
797 FIXME: We should also do overflow checking on the result after
798 adding in the value contained in the object file. */
799 if (howto->complain_on_overflow != complain_overflow_dont
800 && flag == bfd_reloc_ok)
801 flag = bfd_check_overflow (howto->complain_on_overflow,
804 bfd_arch_bits_per_address (abfd),
807 /* Either we are relocating all the way, or we don't want to apply
808 the relocation to the reloc entry (probably because there isn't
809 any room in the output format to describe addends to relocs). */
811 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
812 (OSF version 1.3, compiler version 3.11). It miscompiles the
826 x <<= (unsigned long) s.i0;
830 printf ("succeeded (%lx)\n", x);
834 relocation >>= (bfd_vma) howto->rightshift;
836 /* Shift everything up to where it's going to be used. */
837 relocation <<= (bfd_vma) howto->bitpos;
839 /* Wait for the day when all have the mask in them. */
842 i instruction to be left alone
843 o offset within instruction
844 r relocation offset to apply
853 (( i i i i i o o o o o from bfd_get<size>
854 and S S S S S) to get the size offset we want
855 + r r r r r r r r r r) to get the final value to place
856 and D D D D D to chop to right size
857 -----------------------
860 ( i i i i i o o o o o from bfd_get<size>
861 and N N N N N ) get instruction
862 -----------------------
868 -----------------------
869 = R R R R R R R R R R put into bfd_put<size>
873 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
879 char x = bfd_get_8 (abfd, (char *) data + octets);
881 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
887 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
889 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
894 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
896 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
901 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
902 relocation = -relocation;
904 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
910 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
911 relocation = -relocation;
913 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
924 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
926 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
933 return bfd_reloc_other;
941 bfd_install_relocation
944 bfd_reloc_status_type bfd_install_relocation
946 arelent *reloc_entry,
947 void *data, bfd_vma data_start,
948 asection *input_section,
949 char **error_message);
952 This looks remarkably like <<bfd_perform_relocation>>, except it
953 does not expect that the section contents have been filled in.
954 I.e., it's suitable for use when creating, rather than applying
957 For now, this function should be considered reserved for the
961 bfd_reloc_status_type
962 bfd_install_relocation (bfd *abfd,
963 arelent *reloc_entry,
965 bfd_vma data_start_offset,
966 asection *input_section,
967 char **error_message)
970 bfd_reloc_status_type flag = bfd_reloc_ok;
971 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
972 bfd_vma output_base = 0;
973 reloc_howto_type *howto = reloc_entry->howto;
974 asection *reloc_target_output_section;
978 symbol = *(reloc_entry->sym_ptr_ptr);
979 if (bfd_is_abs_section (symbol->section))
981 reloc_entry->address += input_section->output_offset;
985 /* If there is a function supplied to handle this relocation type,
986 call it. It'll return `bfd_reloc_continue' if further processing
988 if (howto->special_function)
990 bfd_reloc_status_type cont;
992 /* XXX - The special_function calls haven't been fixed up to deal
993 with creating new relocations and section contents. */
994 cont = howto->special_function (abfd, reloc_entry, symbol,
995 /* XXX - Non-portable! */
996 ((bfd_byte *) data_start
997 - data_start_offset),
998 input_section, abfd, error_message);
999 if (cont != bfd_reloc_continue)
1003 /* Is the address of the relocation really within the section? */
1004 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
1005 return bfd_reloc_outofrange;
1007 /* Work out which section the relocation is targeted at and the
1008 initial relocation command value. */
1010 /* Get symbol value. (Common symbols are special.) */
1011 if (bfd_is_com_section (symbol->section))
1014 relocation = symbol->value;
1016 reloc_target_output_section = symbol->section->output_section;
1018 /* Convert input-section-relative symbol value to absolute. */
1019 if (! howto->partial_inplace)
1022 output_base = reloc_target_output_section->vma;
1024 relocation += output_base + symbol->section->output_offset;
1026 /* Add in supplied addend. */
1027 relocation += reloc_entry->addend;
1029 /* Here the variable relocation holds the final address of the
1030 symbol we are relocating against, plus any addend. */
1032 if (howto->pc_relative)
1034 /* This is a PC relative relocation. We want to set RELOCATION
1035 to the distance between the address of the symbol and the
1036 location. RELOCATION is already the address of the symbol.
1038 We start by subtracting the address of the section containing
1041 If pcrel_offset is set, we must further subtract the position
1042 of the location within the section. Some targets arrange for
1043 the addend to be the negative of the position of the location
1044 within the section; for example, i386-aout does this. For
1045 i386-aout, pcrel_offset is FALSE. Some other targets do not
1046 include the position of the location; for example, m88kbcs,
1047 or ELF. For those targets, pcrel_offset is TRUE.
1049 If we are producing relocatable output, then we must ensure
1050 that this reloc will be correctly computed when the final
1051 relocation is done. If pcrel_offset is FALSE we want to wind
1052 up with the negative of the location within the section,
1053 which means we must adjust the existing addend by the change
1054 in the location within the section. If pcrel_offset is TRUE
1055 we do not want to adjust the existing addend at all.
1057 FIXME: This seems logical to me, but for the case of
1058 producing relocatable output it is not what the code
1059 actually does. I don't want to change it, because it seems
1060 far too likely that something will break. */
1063 input_section->output_section->vma + input_section->output_offset;
1065 if (howto->pcrel_offset && howto->partial_inplace)
1066 relocation -= reloc_entry->address;
1069 if (! howto->partial_inplace)
1071 /* This is a partial relocation, and we want to apply the relocation
1072 to the reloc entry rather than the raw data. Modify the reloc
1073 inplace to reflect what we now know. */
1074 reloc_entry->addend = relocation;
1075 reloc_entry->address += input_section->output_offset;
1080 /* This is a partial relocation, but inplace, so modify the
1083 If we've relocated with a symbol with a section, change
1084 into a ref to the section belonging to the symbol. */
1085 reloc_entry->address += input_section->output_offset;
1088 if (abfd->xvec->flavour == bfd_target_coff_flavour
1089 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1090 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1093 /* For m68k-coff, the addend was being subtracted twice during
1094 relocation with -r. Removing the line below this comment
1095 fixes that problem; see PR 2953.
1097 However, Ian wrote the following, regarding removing the line below,
1098 which explains why it is still enabled: --djm
1100 If you put a patch like that into BFD you need to check all the COFF
1101 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1102 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1103 problem in a different way. There may very well be a reason that the
1104 code works as it does.
1106 Hmmm. The first obvious point is that bfd_install_relocation should
1107 not have any tests that depend upon the flavour. It's seem like
1108 entirely the wrong place for such a thing. The second obvious point
1109 is that the current code ignores the reloc addend when producing
1110 relocatable output for COFF. That's peculiar. In fact, I really
1111 have no idea what the point of the line you want to remove is.
1113 A typical COFF reloc subtracts the old value of the symbol and adds in
1114 the new value to the location in the object file (if it's a pc
1115 relative reloc it adds the difference between the symbol value and the
1116 location). When relocating we need to preserve that property.
1118 BFD handles this by setting the addend to the negative of the old
1119 value of the symbol. Unfortunately it handles common symbols in a
1120 non-standard way (it doesn't subtract the old value) but that's a
1121 different story (we can't change it without losing backward
1122 compatibility with old object files) (coff-i386 does subtract the old
1123 value, to be compatible with existing coff-i386 targets, like SCO).
1125 So everything works fine when not producing relocatable output. When
1126 we are producing relocatable output, logically we should do exactly
1127 what we do when not producing relocatable output. Therefore, your
1128 patch is correct. In fact, it should probably always just set
1129 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1130 add the value into the object file. This won't hurt the COFF code,
1131 which doesn't use the addend; I'm not sure what it will do to other
1132 formats (the thing to check for would be whether any formats both use
1133 the addend and set partial_inplace).
1135 When I wanted to make coff-i386 produce relocatable output, I ran
1136 into the problem that you are running into: I wanted to remove that
1137 line. Rather than risk it, I made the coff-i386 relocs use a special
1138 function; it's coff_i386_reloc in coff-i386.c. The function
1139 specifically adds the addend field into the object file, knowing that
1140 bfd_install_relocation is not going to. If you remove that line, then
1141 coff-i386.c will wind up adding the addend field in twice. It's
1142 trivial to fix; it just needs to be done.
1144 The problem with removing the line is just that it may break some
1145 working code. With BFD it's hard to be sure of anything. The right
1146 way to deal with this is simply to build and test at least all the
1147 supported COFF targets. It should be straightforward if time and disk
1148 space consuming. For each target:
1150 2) generate some executable, and link it using -r (I would
1151 probably use paranoia.o and link against newlib/libc.a, which
1152 for all the supported targets would be available in
1153 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1154 3) make the change to reloc.c
1155 4) rebuild the linker
1157 6) if the resulting object files are the same, you have at least
1159 7) if they are different you have to figure out which version is
1161 relocation -= reloc_entry->addend;
1162 /* FIXME: There should be no target specific code here... */
1163 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1164 reloc_entry->addend = 0;
1168 reloc_entry->addend = relocation;
1172 /* FIXME: This overflow checking is incomplete, because the value
1173 might have overflowed before we get here. For a correct check we
1174 need to compute the value in a size larger than bitsize, but we
1175 can't reasonably do that for a reloc the same size as a host
1177 FIXME: We should also do overflow checking on the result after
1178 adding in the value contained in the object file. */
1179 if (howto->complain_on_overflow != complain_overflow_dont)
1180 flag = bfd_check_overflow (howto->complain_on_overflow,
1183 bfd_arch_bits_per_address (abfd),
1186 /* Either we are relocating all the way, or we don't want to apply
1187 the relocation to the reloc entry (probably because there isn't
1188 any room in the output format to describe addends to relocs). */
1190 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1191 (OSF version 1.3, compiler version 3.11). It miscompiles the
1205 x <<= (unsigned long) s.i0;
1207 printf ("failed\n");
1209 printf ("succeeded (%lx)\n", x);
1213 relocation >>= (bfd_vma) howto->rightshift;
1215 /* Shift everything up to where it's going to be used. */
1216 relocation <<= (bfd_vma) howto->bitpos;
1218 /* Wait for the day when all have the mask in them. */
1221 i instruction to be left alone
1222 o offset within instruction
1223 r relocation offset to apply
1232 (( i i i i i o o o o o from bfd_get<size>
1233 and S S S S S) to get the size offset we want
1234 + r r r r r r r r r r) to get the final value to place
1235 and D D D D D to chop to right size
1236 -----------------------
1239 ( i i i i i o o o o o from bfd_get<size>
1240 and N N N N N ) get instruction
1241 -----------------------
1247 -----------------------
1248 = R R R R R R R R R R put into bfd_put<size>
1252 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1254 data = (bfd_byte *) data_start + (octets - data_start_offset);
1256 switch (howto->size)
1260 char x = bfd_get_8 (abfd, data);
1262 bfd_put_8 (abfd, x, data);
1268 short x = bfd_get_16 (abfd, data);
1270 bfd_put_16 (abfd, (bfd_vma) x, data);
1275 long x = bfd_get_32 (abfd, data);
1277 bfd_put_32 (abfd, (bfd_vma) x, data);
1282 long x = bfd_get_32 (abfd, data);
1283 relocation = -relocation;
1285 bfd_put_32 (abfd, (bfd_vma) x, data);
1295 bfd_vma x = bfd_get_64 (abfd, data);
1297 bfd_put_64 (abfd, x, data);
1301 return bfd_reloc_other;
1307 /* This relocation routine is used by some of the backend linkers.
1308 They do not construct asymbol or arelent structures, so there is no
1309 reason for them to use bfd_perform_relocation. Also,
1310 bfd_perform_relocation is so hacked up it is easier to write a new
1311 function than to try to deal with it.
1313 This routine does a final relocation. Whether it is useful for a
1314 relocatable link depends upon how the object format defines
1317 FIXME: This routine ignores any special_function in the HOWTO,
1318 since the existing special_function values have been written for
1319 bfd_perform_relocation.
1321 HOWTO is the reloc howto information.
1322 INPUT_BFD is the BFD which the reloc applies to.
1323 INPUT_SECTION is the section which the reloc applies to.
1324 CONTENTS is the contents of the section.
1325 ADDRESS is the address of the reloc within INPUT_SECTION.
1326 VALUE is the value of the symbol the reloc refers to.
1327 ADDEND is the addend of the reloc. */
1329 bfd_reloc_status_type
1330 _bfd_final_link_relocate (reloc_howto_type *howto,
1332 asection *input_section,
1340 /* Sanity check the address. */
1341 if (address > bfd_get_section_limit (input_bfd, input_section))
1342 return bfd_reloc_outofrange;
1344 /* This function assumes that we are dealing with a basic relocation
1345 against a symbol. We want to compute the value of the symbol to
1346 relocate to. This is just VALUE, the value of the symbol, plus
1347 ADDEND, any addend associated with the reloc. */
1348 relocation = value + addend;
1350 /* If the relocation is PC relative, we want to set RELOCATION to
1351 the distance between the symbol (currently in RELOCATION) and the
1352 location we are relocating. Some targets (e.g., i386-aout)
1353 arrange for the contents of the section to be the negative of the
1354 offset of the location within the section; for such targets
1355 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1356 simply leave the contents of the section as zero; for such
1357 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1358 need to subtract out the offset of the location within the
1359 section (which is just ADDRESS). */
1360 if (howto->pc_relative)
1362 relocation -= (input_section->output_section->vma
1363 + input_section->output_offset);
1364 if (howto->pcrel_offset)
1365 relocation -= address;
1368 return _bfd_relocate_contents (howto, input_bfd, relocation,
1369 contents + address);
1372 /* Relocate a given location using a given value and howto. */
1374 bfd_reloc_status_type
1375 _bfd_relocate_contents (reloc_howto_type *howto,
1382 bfd_reloc_status_type flag;
1383 unsigned int rightshift = howto->rightshift;
1384 unsigned int bitpos = howto->bitpos;
1386 /* If the size is negative, negate RELOCATION. This isn't very
1388 if (howto->size < 0)
1389 relocation = -relocation;
1391 /* Get the value we are going to relocate. */
1392 size = bfd_get_reloc_size (howto);
1399 x = bfd_get_8 (input_bfd, location);
1402 x = bfd_get_16 (input_bfd, location);
1405 x = bfd_get_32 (input_bfd, location);
1409 x = bfd_get_64 (input_bfd, location);
1416 /* Check for overflow. FIXME: We may drop bits during the addition
1417 which we don't check for. We must either check at every single
1418 operation, which would be tedious, or we must do the computations
1419 in a type larger than bfd_vma, which would be inefficient. */
1420 flag = bfd_reloc_ok;
1421 if (howto->complain_on_overflow != complain_overflow_dont)
1423 bfd_vma addrmask, fieldmask, signmask, ss;
1426 /* Get the values to be added together. For signed and unsigned
1427 relocations, we assume that all values should be truncated to
1428 the size of an address. For bitfields, all the bits matter.
1429 See also bfd_check_overflow. */
1430 fieldmask = N_ONES (howto->bitsize);
1431 signmask = ~fieldmask;
1432 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1433 | (fieldmask << rightshift));
1434 a = (relocation & addrmask) >> rightshift;
1435 b = (x & howto->src_mask & addrmask) >> bitpos;
1436 addrmask >>= rightshift;
1438 switch (howto->complain_on_overflow)
1440 case complain_overflow_signed:
1441 /* If any sign bits are set, all sign bits must be set.
1442 That is, A must be a valid negative address after
1444 signmask = ~(fieldmask >> 1);
1447 case complain_overflow_bitfield:
1448 /* Much like the signed check, but for a field one bit
1449 wider. We allow a bitfield to represent numbers in the
1450 range -2**n to 2**n-1, where n is the number of bits in the
1451 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1452 can't overflow, which is exactly what we want. */
1454 if (ss != 0 && ss != (addrmask & signmask))
1455 flag = bfd_reloc_overflow;
1457 /* We only need this next bit of code if the sign bit of B
1458 is below the sign bit of A. This would only happen if
1459 SRC_MASK had fewer bits than BITSIZE. Note that if
1460 SRC_MASK has more bits than BITSIZE, we can get into
1461 trouble; we would need to verify that B is in range, as
1462 we do for A above. */
1463 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1466 /* Set all the bits above the sign bit. */
1469 /* Now we can do the addition. */
1472 /* See if the result has the correct sign. Bits above the
1473 sign bit are junk now; ignore them. If the sum is
1474 positive, make sure we did not have all negative inputs;
1475 if the sum is negative, make sure we did not have all
1476 positive inputs. The test below looks only at the sign
1477 bits, and it really just
1478 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1480 We mask with addrmask here to explicitly allow an address
1481 wrap-around. The Linux kernel relies on it, and it is
1482 the only way to write assembler code which can run when
1483 loaded at a location 0x80000000 away from the location at
1484 which it is linked. */
1485 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1486 flag = bfd_reloc_overflow;
1489 case complain_overflow_unsigned:
1490 /* Checking for an unsigned overflow is relatively easy:
1491 trim the addresses and add, and trim the result as well.
1492 Overflow is normally indicated when the result does not
1493 fit in the field. However, we also need to consider the
1494 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1495 input is 0x80000000, and bfd_vma is only 32 bits; then we
1496 will get sum == 0, but there is an overflow, since the
1497 inputs did not fit in the field. Instead of doing a
1498 separate test, we can check for this by or-ing in the
1499 operands when testing for the sum overflowing its final
1501 sum = (a + b) & addrmask;
1502 if ((a | b | sum) & signmask)
1503 flag = bfd_reloc_overflow;
1511 /* Put RELOCATION in the right bits. */
1512 relocation >>= (bfd_vma) rightshift;
1513 relocation <<= (bfd_vma) bitpos;
1515 /* Add RELOCATION to the right bits of X. */
1516 x = ((x & ~howto->dst_mask)
1517 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1519 /* Put the relocated value back in the object file. */
1525 bfd_put_8 (input_bfd, x, location);
1528 bfd_put_16 (input_bfd, x, location);
1531 bfd_put_32 (input_bfd, x, location);
1535 bfd_put_64 (input_bfd, x, location);
1545 /* Clear a given location using a given howto, by applying a fixed relocation
1546 value and discarding any in-place addend. This is used for fixed-up
1547 relocations against discarded symbols, to make ignorable debug or unwind
1548 information more obvious. */
1551 _bfd_clear_contents (reloc_howto_type *howto,
1553 asection *input_section,
1559 /* Get the value we are going to relocate. */
1560 size = bfd_get_reloc_size (howto);
1567 x = bfd_get_8 (input_bfd, location);
1570 x = bfd_get_16 (input_bfd, location);
1573 x = bfd_get_32 (input_bfd, location);
1577 x = bfd_get_64 (input_bfd, location);
1584 /* Zero out the unwanted bits of X. */
1585 x &= ~howto->dst_mask;
1587 /* For a range list, use 1 instead of 0 as placeholder. 0
1588 would terminate the list, hiding any later entries. */
1589 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1590 ".debug_ranges") == 0
1591 && (howto->dst_mask & 1) != 0)
1594 /* Put the relocated value back in the object file. */
1601 bfd_put_8 (input_bfd, x, location);
1604 bfd_put_16 (input_bfd, x, location);
1607 bfd_put_32 (input_bfd, x, location);
1611 bfd_put_64 (input_bfd, x, location);
1622 howto manager, , typedef arelent, Relocations
1627 When an application wants to create a relocation, but doesn't
1628 know what the target machine might call it, it can find out by
1629 using this bit of code.
1638 The insides of a reloc code. The idea is that, eventually, there
1639 will be one enumerator for every type of relocation we ever do.
1640 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1641 return a howto pointer.
1643 This does mean that the application must determine the correct
1644 enumerator value; you can't get a howto pointer from a random set
1665 Basic absolute relocations of N bits.
1680 PC-relative relocations. Sometimes these are relative to the address
1681 of the relocation itself; sometimes they are relative to the start of
1682 the section containing the relocation. It depends on the specific target.
1684 The 24-bit relocation is used in some Intel 960 configurations.
1689 Section relative relocations. Some targets need this for DWARF2.
1692 BFD_RELOC_32_GOT_PCREL
1694 BFD_RELOC_16_GOT_PCREL
1696 BFD_RELOC_8_GOT_PCREL
1702 BFD_RELOC_LO16_GOTOFF
1704 BFD_RELOC_HI16_GOTOFF
1706 BFD_RELOC_HI16_S_GOTOFF
1710 BFD_RELOC_64_PLT_PCREL
1712 BFD_RELOC_32_PLT_PCREL
1714 BFD_RELOC_24_PLT_PCREL
1716 BFD_RELOC_16_PLT_PCREL
1718 BFD_RELOC_8_PLT_PCREL
1726 BFD_RELOC_LO16_PLTOFF
1728 BFD_RELOC_HI16_PLTOFF
1730 BFD_RELOC_HI16_S_PLTOFF
1744 BFD_RELOC_68K_GLOB_DAT
1746 BFD_RELOC_68K_JMP_SLOT
1748 BFD_RELOC_68K_RELATIVE
1750 BFD_RELOC_68K_TLS_GD32
1752 BFD_RELOC_68K_TLS_GD16
1754 BFD_RELOC_68K_TLS_GD8
1756 BFD_RELOC_68K_TLS_LDM32
1758 BFD_RELOC_68K_TLS_LDM16
1760 BFD_RELOC_68K_TLS_LDM8
1762 BFD_RELOC_68K_TLS_LDO32
1764 BFD_RELOC_68K_TLS_LDO16
1766 BFD_RELOC_68K_TLS_LDO8
1768 BFD_RELOC_68K_TLS_IE32
1770 BFD_RELOC_68K_TLS_IE16
1772 BFD_RELOC_68K_TLS_IE8
1774 BFD_RELOC_68K_TLS_LE32
1776 BFD_RELOC_68K_TLS_LE16
1778 BFD_RELOC_68K_TLS_LE8
1780 Relocations used by 68K ELF.
1783 BFD_RELOC_32_BASEREL
1785 BFD_RELOC_16_BASEREL
1787 BFD_RELOC_LO16_BASEREL
1789 BFD_RELOC_HI16_BASEREL
1791 BFD_RELOC_HI16_S_BASEREL
1797 Linkage-table relative.
1802 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1805 BFD_RELOC_32_PCREL_S2
1807 BFD_RELOC_16_PCREL_S2
1809 BFD_RELOC_23_PCREL_S2
1811 These PC-relative relocations are stored as word displacements --
1812 i.e., byte displacements shifted right two bits. The 30-bit word
1813 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1814 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1815 signed 16-bit displacement is used on the MIPS, and the 23-bit
1816 displacement is used on the Alpha.
1823 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1824 the target word. These are used on the SPARC.
1831 For systems that allocate a Global Pointer register, these are
1832 displacements off that register. These relocation types are
1833 handled specially, because the value the register will have is
1834 decided relatively late.
1837 BFD_RELOC_I960_CALLJ
1839 Reloc types used for i960/b.out.
1844 BFD_RELOC_SPARC_WDISP22
1850 BFD_RELOC_SPARC_GOT10
1852 BFD_RELOC_SPARC_GOT13
1854 BFD_RELOC_SPARC_GOT22
1856 BFD_RELOC_SPARC_PC10
1858 BFD_RELOC_SPARC_PC22
1860 BFD_RELOC_SPARC_WPLT30
1862 BFD_RELOC_SPARC_COPY
1864 BFD_RELOC_SPARC_GLOB_DAT
1866 BFD_RELOC_SPARC_JMP_SLOT
1868 BFD_RELOC_SPARC_RELATIVE
1870 BFD_RELOC_SPARC_UA16
1872 BFD_RELOC_SPARC_UA32
1874 BFD_RELOC_SPARC_UA64
1876 BFD_RELOC_SPARC_GOTDATA_HIX22
1878 BFD_RELOC_SPARC_GOTDATA_LOX10
1880 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1882 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1884 BFD_RELOC_SPARC_GOTDATA_OP
1886 BFD_RELOC_SPARC_JMP_IREL
1888 BFD_RELOC_SPARC_IRELATIVE
1890 SPARC ELF relocations. There is probably some overlap with other
1891 relocation types already defined.
1894 BFD_RELOC_SPARC_BASE13
1896 BFD_RELOC_SPARC_BASE22
1898 I think these are specific to SPARC a.out (e.g., Sun 4).
1908 BFD_RELOC_SPARC_OLO10
1910 BFD_RELOC_SPARC_HH22
1912 BFD_RELOC_SPARC_HM10
1914 BFD_RELOC_SPARC_LM22
1916 BFD_RELOC_SPARC_PC_HH22
1918 BFD_RELOC_SPARC_PC_HM10
1920 BFD_RELOC_SPARC_PC_LM22
1922 BFD_RELOC_SPARC_WDISP16
1924 BFD_RELOC_SPARC_WDISP19
1932 BFD_RELOC_SPARC_DISP64
1935 BFD_RELOC_SPARC_PLT32
1937 BFD_RELOC_SPARC_PLT64
1939 BFD_RELOC_SPARC_HIX22
1941 BFD_RELOC_SPARC_LOX10
1949 BFD_RELOC_SPARC_REGISTER
1953 BFD_RELOC_SPARC_SIZE32
1955 BFD_RELOC_SPARC_SIZE64
1957 BFD_RELOC_SPARC_WDISP10
1962 BFD_RELOC_SPARC_REV32
1964 SPARC little endian relocation
1966 BFD_RELOC_SPARC_TLS_GD_HI22
1968 BFD_RELOC_SPARC_TLS_GD_LO10
1970 BFD_RELOC_SPARC_TLS_GD_ADD
1972 BFD_RELOC_SPARC_TLS_GD_CALL
1974 BFD_RELOC_SPARC_TLS_LDM_HI22
1976 BFD_RELOC_SPARC_TLS_LDM_LO10
1978 BFD_RELOC_SPARC_TLS_LDM_ADD
1980 BFD_RELOC_SPARC_TLS_LDM_CALL
1982 BFD_RELOC_SPARC_TLS_LDO_HIX22
1984 BFD_RELOC_SPARC_TLS_LDO_LOX10
1986 BFD_RELOC_SPARC_TLS_LDO_ADD
1988 BFD_RELOC_SPARC_TLS_IE_HI22
1990 BFD_RELOC_SPARC_TLS_IE_LO10
1992 BFD_RELOC_SPARC_TLS_IE_LD
1994 BFD_RELOC_SPARC_TLS_IE_LDX
1996 BFD_RELOC_SPARC_TLS_IE_ADD
1998 BFD_RELOC_SPARC_TLS_LE_HIX22
2000 BFD_RELOC_SPARC_TLS_LE_LOX10
2002 BFD_RELOC_SPARC_TLS_DTPMOD32
2004 BFD_RELOC_SPARC_TLS_DTPMOD64
2006 BFD_RELOC_SPARC_TLS_DTPOFF32
2008 BFD_RELOC_SPARC_TLS_DTPOFF64
2010 BFD_RELOC_SPARC_TLS_TPOFF32
2012 BFD_RELOC_SPARC_TLS_TPOFF64
2014 SPARC TLS relocations
2023 BFD_RELOC_SPU_IMM10W
2027 BFD_RELOC_SPU_IMM16W
2031 BFD_RELOC_SPU_PCREL9a
2033 BFD_RELOC_SPU_PCREL9b
2035 BFD_RELOC_SPU_PCREL16
2045 BFD_RELOC_SPU_ADD_PIC
2050 BFD_RELOC_ALPHA_GPDISP_HI16
2052 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2053 "addend" in some special way.
2054 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2055 writing; when reading, it will be the absolute section symbol. The
2056 addend is the displacement in bytes of the "lda" instruction from
2057 the "ldah" instruction (which is at the address of this reloc).
2059 BFD_RELOC_ALPHA_GPDISP_LO16
2061 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2062 with GPDISP_HI16 relocs. The addend is ignored when writing the
2063 relocations out, and is filled in with the file's GP value on
2064 reading, for convenience.
2067 BFD_RELOC_ALPHA_GPDISP
2069 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2070 relocation except that there is no accompanying GPDISP_LO16
2074 BFD_RELOC_ALPHA_LITERAL
2076 BFD_RELOC_ALPHA_ELF_LITERAL
2078 BFD_RELOC_ALPHA_LITUSE
2080 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2081 the assembler turns it into a LDQ instruction to load the address of
2082 the symbol, and then fills in a register in the real instruction.
2084 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2085 section symbol. The addend is ignored when writing, but is filled
2086 in with the file's GP value on reading, for convenience, as with the
2089 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2090 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2091 but it generates output not based on the position within the .got
2092 section, but relative to the GP value chosen for the file during the
2095 The LITUSE reloc, on the instruction using the loaded address, gives
2096 information to the linker that it might be able to use to optimize
2097 away some literal section references. The symbol is ignored (read
2098 as the absolute section symbol), and the "addend" indicates the type
2099 of instruction using the register:
2100 1 - "memory" fmt insn
2101 2 - byte-manipulation (byte offset reg)
2102 3 - jsr (target of branch)
2105 BFD_RELOC_ALPHA_HINT
2107 The HINT relocation indicates a value that should be filled into the
2108 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2109 prediction logic which may be provided on some processors.
2112 BFD_RELOC_ALPHA_LINKAGE
2114 The LINKAGE relocation outputs a linkage pair in the object file,
2115 which is filled by the linker.
2118 BFD_RELOC_ALPHA_CODEADDR
2120 The CODEADDR relocation outputs a STO_CA in the object file,
2121 which is filled by the linker.
2124 BFD_RELOC_ALPHA_GPREL_HI16
2126 BFD_RELOC_ALPHA_GPREL_LO16
2128 The GPREL_HI/LO relocations together form a 32-bit offset from the
2132 BFD_RELOC_ALPHA_BRSGP
2134 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2135 share a common GP, and the target address is adjusted for
2136 STO_ALPHA_STD_GPLOAD.
2141 The NOP relocation outputs a NOP if the longword displacement
2142 between two procedure entry points is < 2^21.
2147 The BSR relocation outputs a BSR if the longword displacement
2148 between two procedure entry points is < 2^21.
2153 The LDA relocation outputs a LDA if the longword displacement
2154 between two procedure entry points is < 2^16.
2159 The BOH relocation outputs a BSR if the longword displacement
2160 between two procedure entry points is < 2^21, or else a hint.
2163 BFD_RELOC_ALPHA_TLSGD
2165 BFD_RELOC_ALPHA_TLSLDM
2167 BFD_RELOC_ALPHA_DTPMOD64
2169 BFD_RELOC_ALPHA_GOTDTPREL16
2171 BFD_RELOC_ALPHA_DTPREL64
2173 BFD_RELOC_ALPHA_DTPREL_HI16
2175 BFD_RELOC_ALPHA_DTPREL_LO16
2177 BFD_RELOC_ALPHA_DTPREL16
2179 BFD_RELOC_ALPHA_GOTTPREL16
2181 BFD_RELOC_ALPHA_TPREL64
2183 BFD_RELOC_ALPHA_TPREL_HI16
2185 BFD_RELOC_ALPHA_TPREL_LO16
2187 BFD_RELOC_ALPHA_TPREL16
2189 Alpha thread-local storage relocations.
2194 BFD_RELOC_MICROMIPS_JMP
2196 The MIPS jump instruction.
2199 BFD_RELOC_MIPS16_JMP
2201 The MIPS16 jump instruction.
2204 BFD_RELOC_MIPS16_GPREL
2206 MIPS16 GP relative reloc.
2211 High 16 bits of 32-bit value; simple reloc.
2216 High 16 bits of 32-bit value but the low 16 bits will be sign
2217 extended and added to form the final result. If the low 16
2218 bits form a negative number, we need to add one to the high value
2219 to compensate for the borrow when the low bits are added.
2227 BFD_RELOC_HI16_PCREL
2229 High 16 bits of 32-bit pc-relative value
2231 BFD_RELOC_HI16_S_PCREL
2233 High 16 bits of 32-bit pc-relative value, adjusted
2235 BFD_RELOC_LO16_PCREL
2237 Low 16 bits of pc-relative value
2240 BFD_RELOC_MIPS16_GOT16
2242 BFD_RELOC_MIPS16_CALL16
2244 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2245 16-bit immediate fields
2247 BFD_RELOC_MIPS16_HI16
2249 MIPS16 high 16 bits of 32-bit value.
2251 BFD_RELOC_MIPS16_HI16_S
2253 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2254 extended and added to form the final result. If the low 16
2255 bits form a negative number, we need to add one to the high value
2256 to compensate for the borrow when the low bits are added.
2258 BFD_RELOC_MIPS16_LO16
2263 BFD_RELOC_MIPS16_TLS_GD
2265 BFD_RELOC_MIPS16_TLS_LDM
2267 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2269 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2271 BFD_RELOC_MIPS16_TLS_GOTTPREL
2273 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2275 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2277 MIPS16 TLS relocations
2280 BFD_RELOC_MIPS_LITERAL
2282 BFD_RELOC_MICROMIPS_LITERAL
2284 Relocation against a MIPS literal section.
2287 BFD_RELOC_MICROMIPS_7_PCREL_S1
2289 BFD_RELOC_MICROMIPS_10_PCREL_S1
2291 BFD_RELOC_MICROMIPS_16_PCREL_S1
2293 microMIPS PC-relative relocations.
2296 BFD_RELOC_MICROMIPS_GPREL16
2298 BFD_RELOC_MICROMIPS_HI16
2300 BFD_RELOC_MICROMIPS_HI16_S
2302 BFD_RELOC_MICROMIPS_LO16
2304 microMIPS versions of generic BFD relocs.
2307 BFD_RELOC_MIPS_GOT16
2309 BFD_RELOC_MICROMIPS_GOT16
2311 BFD_RELOC_MIPS_CALL16
2313 BFD_RELOC_MICROMIPS_CALL16
2315 BFD_RELOC_MIPS_GOT_HI16
2317 BFD_RELOC_MICROMIPS_GOT_HI16
2319 BFD_RELOC_MIPS_GOT_LO16
2321 BFD_RELOC_MICROMIPS_GOT_LO16
2323 BFD_RELOC_MIPS_CALL_HI16
2325 BFD_RELOC_MICROMIPS_CALL_HI16
2327 BFD_RELOC_MIPS_CALL_LO16
2329 BFD_RELOC_MICROMIPS_CALL_LO16
2333 BFD_RELOC_MICROMIPS_SUB
2335 BFD_RELOC_MIPS_GOT_PAGE
2337 BFD_RELOC_MICROMIPS_GOT_PAGE
2339 BFD_RELOC_MIPS_GOT_OFST
2341 BFD_RELOC_MICROMIPS_GOT_OFST
2343 BFD_RELOC_MIPS_GOT_DISP
2345 BFD_RELOC_MICROMIPS_GOT_DISP
2347 BFD_RELOC_MIPS_SHIFT5
2349 BFD_RELOC_MIPS_SHIFT6
2351 BFD_RELOC_MIPS_INSERT_A
2353 BFD_RELOC_MIPS_INSERT_B
2355 BFD_RELOC_MIPS_DELETE
2357 BFD_RELOC_MIPS_HIGHEST
2359 BFD_RELOC_MICROMIPS_HIGHEST
2361 BFD_RELOC_MIPS_HIGHER
2363 BFD_RELOC_MICROMIPS_HIGHER
2365 BFD_RELOC_MIPS_SCN_DISP
2367 BFD_RELOC_MICROMIPS_SCN_DISP
2369 BFD_RELOC_MIPS_REL16
2371 BFD_RELOC_MIPS_RELGOT
2375 BFD_RELOC_MICROMIPS_JALR
2377 BFD_RELOC_MIPS_TLS_DTPMOD32
2379 BFD_RELOC_MIPS_TLS_DTPREL32
2381 BFD_RELOC_MIPS_TLS_DTPMOD64
2383 BFD_RELOC_MIPS_TLS_DTPREL64
2385 BFD_RELOC_MIPS_TLS_GD
2387 BFD_RELOC_MICROMIPS_TLS_GD
2389 BFD_RELOC_MIPS_TLS_LDM
2391 BFD_RELOC_MICROMIPS_TLS_LDM
2393 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2395 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2397 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2399 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2401 BFD_RELOC_MIPS_TLS_GOTTPREL
2403 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2405 BFD_RELOC_MIPS_TLS_TPREL32
2407 BFD_RELOC_MIPS_TLS_TPREL64
2409 BFD_RELOC_MIPS_TLS_TPREL_HI16
2411 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2413 BFD_RELOC_MIPS_TLS_TPREL_LO16
2415 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2419 MIPS ELF relocations.
2425 BFD_RELOC_MIPS_JUMP_SLOT
2427 MIPS ELF relocations (VxWorks and PLT extensions).
2431 BFD_RELOC_MOXIE_10_PCREL
2433 Moxie ELF relocations.
2437 BFD_RELOC_FRV_LABEL16
2439 BFD_RELOC_FRV_LABEL24
2445 BFD_RELOC_FRV_GPREL12
2447 BFD_RELOC_FRV_GPRELU12
2449 BFD_RELOC_FRV_GPREL32
2451 BFD_RELOC_FRV_GPRELHI
2453 BFD_RELOC_FRV_GPRELLO
2461 BFD_RELOC_FRV_FUNCDESC
2463 BFD_RELOC_FRV_FUNCDESC_GOT12
2465 BFD_RELOC_FRV_FUNCDESC_GOTHI
2467 BFD_RELOC_FRV_FUNCDESC_GOTLO
2469 BFD_RELOC_FRV_FUNCDESC_VALUE
2471 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2473 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2475 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2477 BFD_RELOC_FRV_GOTOFF12
2479 BFD_RELOC_FRV_GOTOFFHI
2481 BFD_RELOC_FRV_GOTOFFLO
2483 BFD_RELOC_FRV_GETTLSOFF
2485 BFD_RELOC_FRV_TLSDESC_VALUE
2487 BFD_RELOC_FRV_GOTTLSDESC12
2489 BFD_RELOC_FRV_GOTTLSDESCHI
2491 BFD_RELOC_FRV_GOTTLSDESCLO
2493 BFD_RELOC_FRV_TLSMOFF12
2495 BFD_RELOC_FRV_TLSMOFFHI
2497 BFD_RELOC_FRV_TLSMOFFLO
2499 BFD_RELOC_FRV_GOTTLSOFF12
2501 BFD_RELOC_FRV_GOTTLSOFFHI
2503 BFD_RELOC_FRV_GOTTLSOFFLO
2505 BFD_RELOC_FRV_TLSOFF
2507 BFD_RELOC_FRV_TLSDESC_RELAX
2509 BFD_RELOC_FRV_GETTLSOFF_RELAX
2511 BFD_RELOC_FRV_TLSOFF_RELAX
2513 BFD_RELOC_FRV_TLSMOFF
2515 Fujitsu Frv Relocations.
2519 BFD_RELOC_MN10300_GOTOFF24
2521 This is a 24bit GOT-relative reloc for the mn10300.
2523 BFD_RELOC_MN10300_GOT32
2525 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2528 BFD_RELOC_MN10300_GOT24
2530 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2533 BFD_RELOC_MN10300_GOT16
2535 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2538 BFD_RELOC_MN10300_COPY
2540 Copy symbol at runtime.
2542 BFD_RELOC_MN10300_GLOB_DAT
2546 BFD_RELOC_MN10300_JMP_SLOT
2550 BFD_RELOC_MN10300_RELATIVE
2552 Adjust by program base.
2554 BFD_RELOC_MN10300_SYM_DIFF
2556 Together with another reloc targeted at the same location,
2557 allows for a value that is the difference of two symbols
2558 in the same section.
2560 BFD_RELOC_MN10300_ALIGN
2562 The addend of this reloc is an alignment power that must
2563 be honoured at the offset's location, regardless of linker
2566 BFD_RELOC_MN10300_TLS_GD
2568 BFD_RELOC_MN10300_TLS_LD
2570 BFD_RELOC_MN10300_TLS_LDO
2572 BFD_RELOC_MN10300_TLS_GOTIE
2574 BFD_RELOC_MN10300_TLS_IE
2576 BFD_RELOC_MN10300_TLS_LE
2578 BFD_RELOC_MN10300_TLS_DTPMOD
2580 BFD_RELOC_MN10300_TLS_DTPOFF
2582 BFD_RELOC_MN10300_TLS_TPOFF
2584 Various TLS-related relocations.
2586 BFD_RELOC_MN10300_32_PCREL
2588 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2591 BFD_RELOC_MN10300_16_PCREL
2593 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2604 BFD_RELOC_386_GLOB_DAT
2606 BFD_RELOC_386_JUMP_SLOT
2608 BFD_RELOC_386_RELATIVE
2610 BFD_RELOC_386_GOTOFF
2614 BFD_RELOC_386_TLS_TPOFF
2616 BFD_RELOC_386_TLS_IE
2618 BFD_RELOC_386_TLS_GOTIE
2620 BFD_RELOC_386_TLS_LE
2622 BFD_RELOC_386_TLS_GD
2624 BFD_RELOC_386_TLS_LDM
2626 BFD_RELOC_386_TLS_LDO_32
2628 BFD_RELOC_386_TLS_IE_32
2630 BFD_RELOC_386_TLS_LE_32
2632 BFD_RELOC_386_TLS_DTPMOD32
2634 BFD_RELOC_386_TLS_DTPOFF32
2636 BFD_RELOC_386_TLS_TPOFF32
2638 BFD_RELOC_386_TLS_GOTDESC
2640 BFD_RELOC_386_TLS_DESC_CALL
2642 BFD_RELOC_386_TLS_DESC
2644 BFD_RELOC_386_IRELATIVE
2646 i386/elf relocations
2649 BFD_RELOC_X86_64_GOT32
2651 BFD_RELOC_X86_64_PLT32
2653 BFD_RELOC_X86_64_COPY
2655 BFD_RELOC_X86_64_GLOB_DAT
2657 BFD_RELOC_X86_64_JUMP_SLOT
2659 BFD_RELOC_X86_64_RELATIVE
2661 BFD_RELOC_X86_64_GOTPCREL
2663 BFD_RELOC_X86_64_32S
2665 BFD_RELOC_X86_64_DTPMOD64
2667 BFD_RELOC_X86_64_DTPOFF64
2669 BFD_RELOC_X86_64_TPOFF64
2671 BFD_RELOC_X86_64_TLSGD
2673 BFD_RELOC_X86_64_TLSLD
2675 BFD_RELOC_X86_64_DTPOFF32
2677 BFD_RELOC_X86_64_GOTTPOFF
2679 BFD_RELOC_X86_64_TPOFF32
2681 BFD_RELOC_X86_64_GOTOFF64
2683 BFD_RELOC_X86_64_GOTPC32
2685 BFD_RELOC_X86_64_GOT64
2687 BFD_RELOC_X86_64_GOTPCREL64
2689 BFD_RELOC_X86_64_GOTPC64
2691 BFD_RELOC_X86_64_GOTPLT64
2693 BFD_RELOC_X86_64_PLTOFF64
2695 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2697 BFD_RELOC_X86_64_TLSDESC_CALL
2699 BFD_RELOC_X86_64_TLSDESC
2701 BFD_RELOC_X86_64_IRELATIVE
2703 x86-64/elf relocations
2706 BFD_RELOC_NS32K_IMM_8
2708 BFD_RELOC_NS32K_IMM_16
2710 BFD_RELOC_NS32K_IMM_32
2712 BFD_RELOC_NS32K_IMM_8_PCREL
2714 BFD_RELOC_NS32K_IMM_16_PCREL
2716 BFD_RELOC_NS32K_IMM_32_PCREL
2718 BFD_RELOC_NS32K_DISP_8
2720 BFD_RELOC_NS32K_DISP_16
2722 BFD_RELOC_NS32K_DISP_32
2724 BFD_RELOC_NS32K_DISP_8_PCREL
2726 BFD_RELOC_NS32K_DISP_16_PCREL
2728 BFD_RELOC_NS32K_DISP_32_PCREL
2733 BFD_RELOC_PDP11_DISP_8_PCREL
2735 BFD_RELOC_PDP11_DISP_6_PCREL
2740 BFD_RELOC_PJ_CODE_HI16
2742 BFD_RELOC_PJ_CODE_LO16
2744 BFD_RELOC_PJ_CODE_DIR16
2746 BFD_RELOC_PJ_CODE_DIR32
2748 BFD_RELOC_PJ_CODE_REL16
2750 BFD_RELOC_PJ_CODE_REL32
2752 Picojava relocs. Not all of these appear in object files.
2763 BFD_RELOC_PPC_B16_BRTAKEN
2765 BFD_RELOC_PPC_B16_BRNTAKEN
2769 BFD_RELOC_PPC_BA16_BRTAKEN
2771 BFD_RELOC_PPC_BA16_BRNTAKEN
2775 BFD_RELOC_PPC_GLOB_DAT
2777 BFD_RELOC_PPC_JMP_SLOT
2779 BFD_RELOC_PPC_RELATIVE
2781 BFD_RELOC_PPC_LOCAL24PC
2783 BFD_RELOC_PPC_EMB_NADDR32
2785 BFD_RELOC_PPC_EMB_NADDR16
2787 BFD_RELOC_PPC_EMB_NADDR16_LO
2789 BFD_RELOC_PPC_EMB_NADDR16_HI
2791 BFD_RELOC_PPC_EMB_NADDR16_HA
2793 BFD_RELOC_PPC_EMB_SDAI16
2795 BFD_RELOC_PPC_EMB_SDA2I16
2797 BFD_RELOC_PPC_EMB_SDA2REL
2799 BFD_RELOC_PPC_EMB_SDA21
2801 BFD_RELOC_PPC_EMB_MRKREF
2803 BFD_RELOC_PPC_EMB_RELSEC16
2805 BFD_RELOC_PPC_EMB_RELST_LO
2807 BFD_RELOC_PPC_EMB_RELST_HI
2809 BFD_RELOC_PPC_EMB_RELST_HA
2811 BFD_RELOC_PPC_EMB_BIT_FLD
2813 BFD_RELOC_PPC_EMB_RELSDA
2815 BFD_RELOC_PPC_VLE_REL8
2817 BFD_RELOC_PPC_VLE_REL15
2819 BFD_RELOC_PPC_VLE_REL24
2821 BFD_RELOC_PPC_VLE_LO16A
2823 BFD_RELOC_PPC_VLE_LO16D
2825 BFD_RELOC_PPC_VLE_HI16A
2827 BFD_RELOC_PPC_VLE_HI16D
2829 BFD_RELOC_PPC_VLE_HA16A
2831 BFD_RELOC_PPC_VLE_HA16D
2833 BFD_RELOC_PPC_VLE_SDA21
2835 BFD_RELOC_PPC_VLE_SDA21_LO
2837 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2839 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2841 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2843 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2845 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2847 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2849 BFD_RELOC_PPC64_HIGHER
2851 BFD_RELOC_PPC64_HIGHER_S
2853 BFD_RELOC_PPC64_HIGHEST
2855 BFD_RELOC_PPC64_HIGHEST_S
2857 BFD_RELOC_PPC64_TOC16_LO
2859 BFD_RELOC_PPC64_TOC16_HI
2861 BFD_RELOC_PPC64_TOC16_HA
2865 BFD_RELOC_PPC64_PLTGOT16
2867 BFD_RELOC_PPC64_PLTGOT16_LO
2869 BFD_RELOC_PPC64_PLTGOT16_HI
2871 BFD_RELOC_PPC64_PLTGOT16_HA
2873 BFD_RELOC_PPC64_ADDR16_DS
2875 BFD_RELOC_PPC64_ADDR16_LO_DS
2877 BFD_RELOC_PPC64_GOT16_DS
2879 BFD_RELOC_PPC64_GOT16_LO_DS
2881 BFD_RELOC_PPC64_PLT16_LO_DS
2883 BFD_RELOC_PPC64_SECTOFF_DS
2885 BFD_RELOC_PPC64_SECTOFF_LO_DS
2887 BFD_RELOC_PPC64_TOC16_DS
2889 BFD_RELOC_PPC64_TOC16_LO_DS
2891 BFD_RELOC_PPC64_PLTGOT16_DS
2893 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2895 Power(rs6000) and PowerPC relocations.
2904 BFD_RELOC_PPC_DTPMOD
2906 BFD_RELOC_PPC_TPREL16
2908 BFD_RELOC_PPC_TPREL16_LO
2910 BFD_RELOC_PPC_TPREL16_HI
2912 BFD_RELOC_PPC_TPREL16_HA
2916 BFD_RELOC_PPC_DTPREL16
2918 BFD_RELOC_PPC_DTPREL16_LO
2920 BFD_RELOC_PPC_DTPREL16_HI
2922 BFD_RELOC_PPC_DTPREL16_HA
2924 BFD_RELOC_PPC_DTPREL
2926 BFD_RELOC_PPC_GOT_TLSGD16
2928 BFD_RELOC_PPC_GOT_TLSGD16_LO
2930 BFD_RELOC_PPC_GOT_TLSGD16_HI
2932 BFD_RELOC_PPC_GOT_TLSGD16_HA
2934 BFD_RELOC_PPC_GOT_TLSLD16
2936 BFD_RELOC_PPC_GOT_TLSLD16_LO
2938 BFD_RELOC_PPC_GOT_TLSLD16_HI
2940 BFD_RELOC_PPC_GOT_TLSLD16_HA
2942 BFD_RELOC_PPC_GOT_TPREL16
2944 BFD_RELOC_PPC_GOT_TPREL16_LO
2946 BFD_RELOC_PPC_GOT_TPREL16_HI
2948 BFD_RELOC_PPC_GOT_TPREL16_HA
2950 BFD_RELOC_PPC_GOT_DTPREL16
2952 BFD_RELOC_PPC_GOT_DTPREL16_LO
2954 BFD_RELOC_PPC_GOT_DTPREL16_HI
2956 BFD_RELOC_PPC_GOT_DTPREL16_HA
2958 BFD_RELOC_PPC64_TPREL16_DS
2960 BFD_RELOC_PPC64_TPREL16_LO_DS
2962 BFD_RELOC_PPC64_TPREL16_HIGHER
2964 BFD_RELOC_PPC64_TPREL16_HIGHERA
2966 BFD_RELOC_PPC64_TPREL16_HIGHEST
2968 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2970 BFD_RELOC_PPC64_DTPREL16_DS
2972 BFD_RELOC_PPC64_DTPREL16_LO_DS
2974 BFD_RELOC_PPC64_DTPREL16_HIGHER
2976 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2978 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2980 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2982 PowerPC and PowerPC64 thread-local storage relocations.
2987 IBM 370/390 relocations
2992 The type of reloc used to build a constructor table - at the moment
2993 probably a 32 bit wide absolute relocation, but the target can choose.
2994 It generally does map to one of the other relocation types.
2997 BFD_RELOC_ARM_PCREL_BRANCH
2999 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3000 not stored in the instruction.
3002 BFD_RELOC_ARM_PCREL_BLX
3004 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3005 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3006 field in the instruction.
3008 BFD_RELOC_THUMB_PCREL_BLX
3010 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3011 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3012 field in the instruction.
3014 BFD_RELOC_ARM_PCREL_CALL
3016 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3018 BFD_RELOC_ARM_PCREL_JUMP
3020 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3023 BFD_RELOC_THUMB_PCREL_BRANCH7
3025 BFD_RELOC_THUMB_PCREL_BRANCH9
3027 BFD_RELOC_THUMB_PCREL_BRANCH12
3029 BFD_RELOC_THUMB_PCREL_BRANCH20
3031 BFD_RELOC_THUMB_PCREL_BRANCH23
3033 BFD_RELOC_THUMB_PCREL_BRANCH25
3035 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3036 The lowest bit must be zero and is not stored in the instruction.
3037 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3038 "nn" one smaller in all cases. Note further that BRANCH23
3039 corresponds to R_ARM_THM_CALL.
3042 BFD_RELOC_ARM_OFFSET_IMM
3044 12-bit immediate offset, used in ARM-format ldr and str instructions.
3047 BFD_RELOC_ARM_THUMB_OFFSET
3049 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3052 BFD_RELOC_ARM_TARGET1
3054 Pc-relative or absolute relocation depending on target. Used for
3055 entries in .init_array sections.
3057 BFD_RELOC_ARM_ROSEGREL32
3059 Read-only segment base relative address.
3061 BFD_RELOC_ARM_SBREL32
3063 Data segment base relative address.
3065 BFD_RELOC_ARM_TARGET2
3067 This reloc is used for references to RTTI data from exception handling
3068 tables. The actual definition depends on the target. It may be a
3069 pc-relative or some form of GOT-indirect relocation.
3071 BFD_RELOC_ARM_PREL31
3073 31-bit PC relative address.
3079 BFD_RELOC_ARM_MOVW_PCREL
3081 BFD_RELOC_ARM_MOVT_PCREL
3083 BFD_RELOC_ARM_THUMB_MOVW
3085 BFD_RELOC_ARM_THUMB_MOVT
3087 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3089 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3091 Low and High halfword relocations for MOVW and MOVT instructions.
3094 BFD_RELOC_ARM_JUMP_SLOT
3096 BFD_RELOC_ARM_GLOB_DAT
3102 BFD_RELOC_ARM_RELATIVE
3104 BFD_RELOC_ARM_GOTOFF
3108 BFD_RELOC_ARM_GOT_PREL
3110 Relocations for setting up GOTs and PLTs for shared libraries.
3113 BFD_RELOC_ARM_TLS_GD32
3115 BFD_RELOC_ARM_TLS_LDO32
3117 BFD_RELOC_ARM_TLS_LDM32
3119 BFD_RELOC_ARM_TLS_DTPOFF32
3121 BFD_RELOC_ARM_TLS_DTPMOD32
3123 BFD_RELOC_ARM_TLS_TPOFF32
3125 BFD_RELOC_ARM_TLS_IE32
3127 BFD_RELOC_ARM_TLS_LE32
3129 BFD_RELOC_ARM_TLS_GOTDESC
3131 BFD_RELOC_ARM_TLS_CALL
3133 BFD_RELOC_ARM_THM_TLS_CALL
3135 BFD_RELOC_ARM_TLS_DESCSEQ
3137 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3139 BFD_RELOC_ARM_TLS_DESC
3141 ARM thread-local storage relocations.
3144 BFD_RELOC_ARM_ALU_PC_G0_NC
3146 BFD_RELOC_ARM_ALU_PC_G0
3148 BFD_RELOC_ARM_ALU_PC_G1_NC
3150 BFD_RELOC_ARM_ALU_PC_G1
3152 BFD_RELOC_ARM_ALU_PC_G2
3154 BFD_RELOC_ARM_LDR_PC_G0
3156 BFD_RELOC_ARM_LDR_PC_G1
3158 BFD_RELOC_ARM_LDR_PC_G2
3160 BFD_RELOC_ARM_LDRS_PC_G0
3162 BFD_RELOC_ARM_LDRS_PC_G1
3164 BFD_RELOC_ARM_LDRS_PC_G2
3166 BFD_RELOC_ARM_LDC_PC_G0
3168 BFD_RELOC_ARM_LDC_PC_G1
3170 BFD_RELOC_ARM_LDC_PC_G2
3172 BFD_RELOC_ARM_ALU_SB_G0_NC
3174 BFD_RELOC_ARM_ALU_SB_G0
3176 BFD_RELOC_ARM_ALU_SB_G1_NC
3178 BFD_RELOC_ARM_ALU_SB_G1
3180 BFD_RELOC_ARM_ALU_SB_G2
3182 BFD_RELOC_ARM_LDR_SB_G0
3184 BFD_RELOC_ARM_LDR_SB_G1
3186 BFD_RELOC_ARM_LDR_SB_G2
3188 BFD_RELOC_ARM_LDRS_SB_G0
3190 BFD_RELOC_ARM_LDRS_SB_G1
3192 BFD_RELOC_ARM_LDRS_SB_G2
3194 BFD_RELOC_ARM_LDC_SB_G0
3196 BFD_RELOC_ARM_LDC_SB_G1
3198 BFD_RELOC_ARM_LDC_SB_G2
3200 ARM group relocations.
3205 Annotation of BX instructions.
3208 BFD_RELOC_ARM_IRELATIVE
3210 ARM support for STT_GNU_IFUNC.
3213 BFD_RELOC_ARM_IMMEDIATE
3215 BFD_RELOC_ARM_ADRL_IMMEDIATE
3217 BFD_RELOC_ARM_T32_IMMEDIATE
3219 BFD_RELOC_ARM_T32_ADD_IMM
3221 BFD_RELOC_ARM_T32_IMM12
3223 BFD_RELOC_ARM_T32_ADD_PC12
3225 BFD_RELOC_ARM_SHIFT_IMM
3235 BFD_RELOC_ARM_CP_OFF_IMM
3237 BFD_RELOC_ARM_CP_OFF_IMM_S2
3239 BFD_RELOC_ARM_T32_CP_OFF_IMM
3241 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3243 BFD_RELOC_ARM_ADR_IMM
3245 BFD_RELOC_ARM_LDR_IMM
3247 BFD_RELOC_ARM_LITERAL
3249 BFD_RELOC_ARM_IN_POOL
3251 BFD_RELOC_ARM_OFFSET_IMM8
3253 BFD_RELOC_ARM_T32_OFFSET_U8
3255 BFD_RELOC_ARM_T32_OFFSET_IMM
3257 BFD_RELOC_ARM_HWLITERAL
3259 BFD_RELOC_ARM_THUMB_ADD
3261 BFD_RELOC_ARM_THUMB_IMM
3263 BFD_RELOC_ARM_THUMB_SHIFT
3265 These relocs are only used within the ARM assembler. They are not
3266 (at present) written to any object files.
3269 BFD_RELOC_SH_PCDISP8BY2
3271 BFD_RELOC_SH_PCDISP12BY2
3279 BFD_RELOC_SH_DISP12BY2
3281 BFD_RELOC_SH_DISP12BY4
3283 BFD_RELOC_SH_DISP12BY8
3287 BFD_RELOC_SH_DISP20BY8
3291 BFD_RELOC_SH_IMM4BY2
3293 BFD_RELOC_SH_IMM4BY4
3297 BFD_RELOC_SH_IMM8BY2
3299 BFD_RELOC_SH_IMM8BY4
3301 BFD_RELOC_SH_PCRELIMM8BY2
3303 BFD_RELOC_SH_PCRELIMM8BY4
3305 BFD_RELOC_SH_SWITCH16
3307 BFD_RELOC_SH_SWITCH32
3321 BFD_RELOC_SH_LOOP_START
3323 BFD_RELOC_SH_LOOP_END
3327 BFD_RELOC_SH_GLOB_DAT
3329 BFD_RELOC_SH_JMP_SLOT
3331 BFD_RELOC_SH_RELATIVE
3335 BFD_RELOC_SH_GOT_LOW16
3337 BFD_RELOC_SH_GOT_MEDLOW16
3339 BFD_RELOC_SH_GOT_MEDHI16
3341 BFD_RELOC_SH_GOT_HI16
3343 BFD_RELOC_SH_GOTPLT_LOW16
3345 BFD_RELOC_SH_GOTPLT_MEDLOW16
3347 BFD_RELOC_SH_GOTPLT_MEDHI16
3349 BFD_RELOC_SH_GOTPLT_HI16
3351 BFD_RELOC_SH_PLT_LOW16
3353 BFD_RELOC_SH_PLT_MEDLOW16
3355 BFD_RELOC_SH_PLT_MEDHI16
3357 BFD_RELOC_SH_PLT_HI16
3359 BFD_RELOC_SH_GOTOFF_LOW16
3361 BFD_RELOC_SH_GOTOFF_MEDLOW16
3363 BFD_RELOC_SH_GOTOFF_MEDHI16
3365 BFD_RELOC_SH_GOTOFF_HI16
3367 BFD_RELOC_SH_GOTPC_LOW16
3369 BFD_RELOC_SH_GOTPC_MEDLOW16
3371 BFD_RELOC_SH_GOTPC_MEDHI16
3373 BFD_RELOC_SH_GOTPC_HI16
3377 BFD_RELOC_SH_GLOB_DAT64
3379 BFD_RELOC_SH_JMP_SLOT64
3381 BFD_RELOC_SH_RELATIVE64
3383 BFD_RELOC_SH_GOT10BY4
3385 BFD_RELOC_SH_GOT10BY8
3387 BFD_RELOC_SH_GOTPLT10BY4
3389 BFD_RELOC_SH_GOTPLT10BY8
3391 BFD_RELOC_SH_GOTPLT32
3393 BFD_RELOC_SH_SHMEDIA_CODE
3399 BFD_RELOC_SH_IMMS6BY32
3405 BFD_RELOC_SH_IMMS10BY2
3407 BFD_RELOC_SH_IMMS10BY4
3409 BFD_RELOC_SH_IMMS10BY8
3415 BFD_RELOC_SH_IMM_LOW16
3417 BFD_RELOC_SH_IMM_LOW16_PCREL
3419 BFD_RELOC_SH_IMM_MEDLOW16
3421 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3423 BFD_RELOC_SH_IMM_MEDHI16
3425 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3427 BFD_RELOC_SH_IMM_HI16
3429 BFD_RELOC_SH_IMM_HI16_PCREL
3433 BFD_RELOC_SH_TLS_GD_32
3435 BFD_RELOC_SH_TLS_LD_32
3437 BFD_RELOC_SH_TLS_LDO_32
3439 BFD_RELOC_SH_TLS_IE_32
3441 BFD_RELOC_SH_TLS_LE_32
3443 BFD_RELOC_SH_TLS_DTPMOD32
3445 BFD_RELOC_SH_TLS_DTPOFF32
3447 BFD_RELOC_SH_TLS_TPOFF32
3451 BFD_RELOC_SH_GOTOFF20
3453 BFD_RELOC_SH_GOTFUNCDESC
3455 BFD_RELOC_SH_GOTFUNCDESC20
3457 BFD_RELOC_SH_GOTOFFFUNCDESC
3459 BFD_RELOC_SH_GOTOFFFUNCDESC20
3461 BFD_RELOC_SH_FUNCDESC
3463 Renesas / SuperH SH relocs. Not all of these appear in object files.
3466 BFD_RELOC_ARC_B22_PCREL
3469 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
3470 not stored in the instruction. The high 20 bits are installed in bits 26
3471 through 7 of the instruction.
3475 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
3476 stored in the instruction. The high 24 bits are installed in bits 23
3480 BFD_RELOC_BFIN_16_IMM
3482 ADI Blackfin 16 bit immediate absolute reloc.
3484 BFD_RELOC_BFIN_16_HIGH
3486 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3488 BFD_RELOC_BFIN_4_PCREL
3490 ADI Blackfin 'a' part of LSETUP.
3492 BFD_RELOC_BFIN_5_PCREL
3496 BFD_RELOC_BFIN_16_LOW
3498 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3500 BFD_RELOC_BFIN_10_PCREL
3504 BFD_RELOC_BFIN_11_PCREL
3506 ADI Blackfin 'b' part of LSETUP.
3508 BFD_RELOC_BFIN_12_PCREL_JUMP
3512 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3514 ADI Blackfin Short jump, pcrel.
3516 BFD_RELOC_BFIN_24_PCREL_CALL_X
3518 ADI Blackfin Call.x not implemented.
3520 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3522 ADI Blackfin Long Jump pcrel.
3524 BFD_RELOC_BFIN_GOT17M4
3526 BFD_RELOC_BFIN_GOTHI
3528 BFD_RELOC_BFIN_GOTLO
3530 BFD_RELOC_BFIN_FUNCDESC
3532 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3534 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3536 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3538 BFD_RELOC_BFIN_FUNCDESC_VALUE
3540 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3542 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3544 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3546 BFD_RELOC_BFIN_GOTOFF17M4
3548 BFD_RELOC_BFIN_GOTOFFHI
3550 BFD_RELOC_BFIN_GOTOFFLO
3552 ADI Blackfin FD-PIC relocations.
3556 ADI Blackfin GOT relocation.
3558 BFD_RELOC_BFIN_PLTPC
3560 ADI Blackfin PLTPC relocation.
3562 BFD_ARELOC_BFIN_PUSH
3564 ADI Blackfin arithmetic relocation.
3566 BFD_ARELOC_BFIN_CONST
3568 ADI Blackfin arithmetic relocation.
3572 ADI Blackfin arithmetic relocation.
3576 ADI Blackfin arithmetic relocation.
3578 BFD_ARELOC_BFIN_MULT
3580 ADI Blackfin arithmetic relocation.
3584 ADI Blackfin arithmetic relocation.
3588 ADI Blackfin arithmetic relocation.
3590 BFD_ARELOC_BFIN_LSHIFT
3592 ADI Blackfin arithmetic relocation.
3594 BFD_ARELOC_BFIN_RSHIFT
3596 ADI Blackfin arithmetic relocation.
3600 ADI Blackfin arithmetic relocation.
3604 ADI Blackfin arithmetic relocation.
3608 ADI Blackfin arithmetic relocation.
3610 BFD_ARELOC_BFIN_LAND
3612 ADI Blackfin arithmetic relocation.
3616 ADI Blackfin arithmetic relocation.
3620 ADI Blackfin arithmetic relocation.
3624 ADI Blackfin arithmetic relocation.
3626 BFD_ARELOC_BFIN_COMP
3628 ADI Blackfin arithmetic relocation.
3630 BFD_ARELOC_BFIN_PAGE
3632 ADI Blackfin arithmetic relocation.
3634 BFD_ARELOC_BFIN_HWPAGE
3636 ADI Blackfin arithmetic relocation.
3638 BFD_ARELOC_BFIN_ADDR
3640 ADI Blackfin arithmetic relocation.
3643 BFD_RELOC_D10V_10_PCREL_R
3645 Mitsubishi D10V relocs.
3646 This is a 10-bit reloc with the right 2 bits
3649 BFD_RELOC_D10V_10_PCREL_L
3651 Mitsubishi D10V relocs.
3652 This is a 10-bit reloc with the right 2 bits
3653 assumed to be 0. This is the same as the previous reloc
3654 except it is in the left container, i.e.,
3655 shifted left 15 bits.
3659 This is an 18-bit reloc with the right 2 bits
3662 BFD_RELOC_D10V_18_PCREL
3664 This is an 18-bit reloc with the right 2 bits
3670 Mitsubishi D30V relocs.
3671 This is a 6-bit absolute reloc.
3673 BFD_RELOC_D30V_9_PCREL
3675 This is a 6-bit pc-relative reloc with
3676 the right 3 bits assumed to be 0.
3678 BFD_RELOC_D30V_9_PCREL_R
3680 This is a 6-bit pc-relative reloc with
3681 the right 3 bits assumed to be 0. Same
3682 as the previous reloc but on the right side
3687 This is a 12-bit absolute reloc with the
3688 right 3 bitsassumed to be 0.
3690 BFD_RELOC_D30V_15_PCREL
3692 This is a 12-bit pc-relative reloc with
3693 the right 3 bits assumed to be 0.
3695 BFD_RELOC_D30V_15_PCREL_R
3697 This is a 12-bit pc-relative reloc with
3698 the right 3 bits assumed to be 0. Same
3699 as the previous reloc but on the right side
3704 This is an 18-bit absolute reloc with
3705 the right 3 bits assumed to be 0.
3707 BFD_RELOC_D30V_21_PCREL
3709 This is an 18-bit pc-relative reloc with
3710 the right 3 bits assumed to be 0.
3712 BFD_RELOC_D30V_21_PCREL_R
3714 This is an 18-bit pc-relative reloc with
3715 the right 3 bits assumed to be 0. Same
3716 as the previous reloc but on the right side
3721 This is a 32-bit absolute reloc.
3723 BFD_RELOC_D30V_32_PCREL
3725 This is a 32-bit pc-relative reloc.
3728 BFD_RELOC_DLX_HI16_S
3743 BFD_RELOC_M32C_RL_JUMP
3745 BFD_RELOC_M32C_RL_1ADDR
3747 BFD_RELOC_M32C_RL_2ADDR
3749 Renesas M16C/M32C Relocations.
3754 Renesas M32R (formerly Mitsubishi M32R) relocs.
3755 This is a 24 bit absolute address.
3757 BFD_RELOC_M32R_10_PCREL
3759 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3761 BFD_RELOC_M32R_18_PCREL
3763 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3765 BFD_RELOC_M32R_26_PCREL
3767 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3769 BFD_RELOC_M32R_HI16_ULO
3771 This is a 16-bit reloc containing the high 16 bits of an address
3772 used when the lower 16 bits are treated as unsigned.
3774 BFD_RELOC_M32R_HI16_SLO
3776 This is a 16-bit reloc containing the high 16 bits of an address
3777 used when the lower 16 bits are treated as signed.
3781 This is a 16-bit reloc containing the lower 16 bits of an address.
3783 BFD_RELOC_M32R_SDA16
3785 This is a 16-bit reloc containing the small data area offset for use in
3786 add3, load, and store instructions.
3788 BFD_RELOC_M32R_GOT24
3790 BFD_RELOC_M32R_26_PLTREL
3794 BFD_RELOC_M32R_GLOB_DAT
3796 BFD_RELOC_M32R_JMP_SLOT
3798 BFD_RELOC_M32R_RELATIVE
3800 BFD_RELOC_M32R_GOTOFF
3802 BFD_RELOC_M32R_GOTOFF_HI_ULO
3804 BFD_RELOC_M32R_GOTOFF_HI_SLO
3806 BFD_RELOC_M32R_GOTOFF_LO
3808 BFD_RELOC_M32R_GOTPC24
3810 BFD_RELOC_M32R_GOT16_HI_ULO
3812 BFD_RELOC_M32R_GOT16_HI_SLO
3814 BFD_RELOC_M32R_GOT16_LO
3816 BFD_RELOC_M32R_GOTPC_HI_ULO
3818 BFD_RELOC_M32R_GOTPC_HI_SLO
3820 BFD_RELOC_M32R_GOTPC_LO
3826 BFD_RELOC_V850_9_PCREL
3828 This is a 9-bit reloc
3830 BFD_RELOC_V850_22_PCREL
3832 This is a 22-bit reloc
3835 BFD_RELOC_V850_SDA_16_16_OFFSET
3837 This is a 16 bit offset from the short data area pointer.
3839 BFD_RELOC_V850_SDA_15_16_OFFSET
3841 This is a 16 bit offset (of which only 15 bits are used) from the
3842 short data area pointer.
3844 BFD_RELOC_V850_ZDA_16_16_OFFSET
3846 This is a 16 bit offset from the zero data area pointer.
3848 BFD_RELOC_V850_ZDA_15_16_OFFSET
3850 This is a 16 bit offset (of which only 15 bits are used) from the
3851 zero data area pointer.
3853 BFD_RELOC_V850_TDA_6_8_OFFSET
3855 This is an 8 bit offset (of which only 6 bits are used) from the
3856 tiny data area pointer.
3858 BFD_RELOC_V850_TDA_7_8_OFFSET
3860 This is an 8bit offset (of which only 7 bits are used) from the tiny
3863 BFD_RELOC_V850_TDA_7_7_OFFSET
3865 This is a 7 bit offset from the tiny data area pointer.
3867 BFD_RELOC_V850_TDA_16_16_OFFSET
3869 This is a 16 bit offset from the tiny data area pointer.
3872 BFD_RELOC_V850_TDA_4_5_OFFSET
3874 This is a 5 bit offset (of which only 4 bits are used) from the tiny
3877 BFD_RELOC_V850_TDA_4_4_OFFSET
3879 This is a 4 bit offset from the tiny data area pointer.
3881 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
3883 This is a 16 bit offset from the short data area pointer, with the
3884 bits placed non-contiguously in the instruction.
3886 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
3888 This is a 16 bit offset from the zero data area pointer, with the
3889 bits placed non-contiguously in the instruction.
3891 BFD_RELOC_V850_CALLT_6_7_OFFSET
3893 This is a 6 bit offset from the call table base pointer.
3895 BFD_RELOC_V850_CALLT_16_16_OFFSET
3897 This is a 16 bit offset from the call table base pointer.
3899 BFD_RELOC_V850_LONGCALL
3901 Used for relaxing indirect function calls.
3903 BFD_RELOC_V850_LONGJUMP
3905 Used for relaxing indirect jumps.
3907 BFD_RELOC_V850_ALIGN
3909 Used to maintain alignment whilst relaxing.
3911 BFD_RELOC_V850_LO16_SPLIT_OFFSET
3913 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
3916 BFD_RELOC_V850_16_PCREL
3918 This is a 16-bit reloc.
3920 BFD_RELOC_V850_17_PCREL
3922 This is a 17-bit reloc.
3926 This is a 23-bit reloc.
3928 BFD_RELOC_V850_32_PCREL
3930 This is a 32-bit reloc.
3932 BFD_RELOC_V850_32_ABS
3934 This is a 32-bit reloc.
3936 BFD_RELOC_V850_16_SPLIT_OFFSET
3938 This is a 16-bit reloc.
3940 BFD_RELOC_V850_16_S1
3942 This is a 16-bit reloc.
3944 BFD_RELOC_V850_LO16_S1
3946 Low 16 bits. 16 bit shifted by 1.
3948 BFD_RELOC_V850_CALLT_15_16_OFFSET
3950 This is a 16 bit offset from the call table base pointer.
3952 BFD_RELOC_V850_32_GOTPCREL
3956 BFD_RELOC_V850_16_GOT
3960 BFD_RELOC_V850_32_GOT
3964 BFD_RELOC_V850_22_PLT_PCREL
3968 BFD_RELOC_V850_32_PLT_PCREL
3976 BFD_RELOC_V850_GLOB_DAT
3980 BFD_RELOC_V850_JMP_SLOT
3984 BFD_RELOC_V850_RELATIVE
3988 BFD_RELOC_V850_16_GOTOFF
3992 BFD_RELOC_V850_32_GOTOFF
4007 This is a 8bit DP reloc for the tms320c30, where the most
4008 significant 8 bits of a 24 bit word are placed into the least
4009 significant 8 bits of the opcode.
4012 BFD_RELOC_TIC54X_PARTLS7
4014 This is a 7bit reloc for the tms320c54x, where the least
4015 significant 7 bits of a 16 bit word are placed into the least
4016 significant 7 bits of the opcode.
4019 BFD_RELOC_TIC54X_PARTMS9
4021 This is a 9bit DP reloc for the tms320c54x, where the most
4022 significant 9 bits of a 16 bit word are placed into the least
4023 significant 9 bits of the opcode.
4028 This is an extended address 23-bit reloc for the tms320c54x.
4031 BFD_RELOC_TIC54X_16_OF_23
4033 This is a 16-bit reloc for the tms320c54x, where the least
4034 significant 16 bits of a 23-bit extended address are placed into
4038 BFD_RELOC_TIC54X_MS7_OF_23
4040 This is a reloc for the tms320c54x, where the most
4041 significant 7 bits of a 23-bit extended address are placed into
4045 BFD_RELOC_C6000_PCR_S21
4047 BFD_RELOC_C6000_PCR_S12
4049 BFD_RELOC_C6000_PCR_S10
4051 BFD_RELOC_C6000_PCR_S7
4053 BFD_RELOC_C6000_ABS_S16
4055 BFD_RELOC_C6000_ABS_L16
4057 BFD_RELOC_C6000_ABS_H16
4059 BFD_RELOC_C6000_SBR_U15_B
4061 BFD_RELOC_C6000_SBR_U15_H
4063 BFD_RELOC_C6000_SBR_U15_W
4065 BFD_RELOC_C6000_SBR_S16
4067 BFD_RELOC_C6000_SBR_L16_B
4069 BFD_RELOC_C6000_SBR_L16_H
4071 BFD_RELOC_C6000_SBR_L16_W
4073 BFD_RELOC_C6000_SBR_H16_B
4075 BFD_RELOC_C6000_SBR_H16_H
4077 BFD_RELOC_C6000_SBR_H16_W
4079 BFD_RELOC_C6000_SBR_GOT_U15_W
4081 BFD_RELOC_C6000_SBR_GOT_L16_W
4083 BFD_RELOC_C6000_SBR_GOT_H16_W
4085 BFD_RELOC_C6000_DSBT_INDEX
4087 BFD_RELOC_C6000_PREL31
4089 BFD_RELOC_C6000_COPY
4091 BFD_RELOC_C6000_JUMP_SLOT
4093 BFD_RELOC_C6000_EHTYPE
4095 BFD_RELOC_C6000_PCR_H16
4097 BFD_RELOC_C6000_PCR_L16
4099 BFD_RELOC_C6000_ALIGN
4101 BFD_RELOC_C6000_FPHEAD
4103 BFD_RELOC_C6000_NOCMP
4105 TMS320C6000 relocations.
4110 This is a 48 bit reloc for the FR30 that stores 32 bits.
4114 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4117 BFD_RELOC_FR30_6_IN_4
4119 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4122 BFD_RELOC_FR30_8_IN_8
4124 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4127 BFD_RELOC_FR30_9_IN_8
4129 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4132 BFD_RELOC_FR30_10_IN_8
4134 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4137 BFD_RELOC_FR30_9_PCREL
4139 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4140 short offset into 8 bits.
4142 BFD_RELOC_FR30_12_PCREL
4144 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4145 short offset into 11 bits.
4148 BFD_RELOC_MCORE_PCREL_IMM8BY4
4150 BFD_RELOC_MCORE_PCREL_IMM11BY2
4152 BFD_RELOC_MCORE_PCREL_IMM4BY2
4154 BFD_RELOC_MCORE_PCREL_32
4156 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4160 Motorola Mcore relocations.
4169 BFD_RELOC_MEP_PCREL8A2
4171 BFD_RELOC_MEP_PCREL12A2
4173 BFD_RELOC_MEP_PCREL17A2
4175 BFD_RELOC_MEP_PCREL24A2
4177 BFD_RELOC_MEP_PCABS24A2
4189 BFD_RELOC_MEP_TPREL7
4191 BFD_RELOC_MEP_TPREL7A2
4193 BFD_RELOC_MEP_TPREL7A4
4195 BFD_RELOC_MEP_UIMM24
4197 BFD_RELOC_MEP_ADDR24A4
4199 BFD_RELOC_MEP_GNU_VTINHERIT
4201 BFD_RELOC_MEP_GNU_VTENTRY
4203 Toshiba Media Processor Relocations.
4207 BFD_RELOC_METAG_HIADDR16
4209 BFD_RELOC_METAG_LOADDR16
4211 BFD_RELOC_METAG_RELBRANCH
4213 BFD_RELOC_METAG_GETSETOFF
4215 BFD_RELOC_METAG_HIOG
4217 BFD_RELOC_METAG_LOOG
4219 BFD_RELOC_METAG_REL8
4221 BFD_RELOC_METAG_REL16
4223 BFD_RELOC_METAG_HI16_GOTOFF
4225 BFD_RELOC_METAG_LO16_GOTOFF
4227 BFD_RELOC_METAG_GETSET_GOTOFF
4229 BFD_RELOC_METAG_GETSET_GOT
4231 BFD_RELOC_METAG_HI16_GOTPC
4233 BFD_RELOC_METAG_LO16_GOTPC
4235 BFD_RELOC_METAG_HI16_PLT
4237 BFD_RELOC_METAG_LO16_PLT
4239 BFD_RELOC_METAG_RELBRANCH_PLT
4241 BFD_RELOC_METAG_GOTOFF
4245 BFD_RELOC_METAG_COPY
4247 BFD_RELOC_METAG_JMP_SLOT
4249 BFD_RELOC_METAG_RELATIVE
4251 BFD_RELOC_METAG_GLOB_DAT
4253 BFD_RELOC_METAG_TLS_GD
4255 BFD_RELOC_METAG_TLS_LDM
4257 BFD_RELOC_METAG_TLS_LDO_HI16
4259 BFD_RELOC_METAG_TLS_LDO_LO16
4261 BFD_RELOC_METAG_TLS_LDO
4263 BFD_RELOC_METAG_TLS_IE
4265 BFD_RELOC_METAG_TLS_IENONPIC
4267 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4269 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4271 BFD_RELOC_METAG_TLS_TPOFF
4273 BFD_RELOC_METAG_TLS_DTPMOD
4275 BFD_RELOC_METAG_TLS_DTPOFF
4277 BFD_RELOC_METAG_TLS_LE
4279 BFD_RELOC_METAG_TLS_LE_HI16
4281 BFD_RELOC_METAG_TLS_LE_LO16
4283 Imagination Technologies Meta relocations.
4288 BFD_RELOC_MMIX_GETA_1
4290 BFD_RELOC_MMIX_GETA_2
4292 BFD_RELOC_MMIX_GETA_3
4294 These are relocations for the GETA instruction.
4296 BFD_RELOC_MMIX_CBRANCH
4298 BFD_RELOC_MMIX_CBRANCH_J
4300 BFD_RELOC_MMIX_CBRANCH_1
4302 BFD_RELOC_MMIX_CBRANCH_2
4304 BFD_RELOC_MMIX_CBRANCH_3
4306 These are relocations for a conditional branch instruction.
4308 BFD_RELOC_MMIX_PUSHJ
4310 BFD_RELOC_MMIX_PUSHJ_1
4312 BFD_RELOC_MMIX_PUSHJ_2
4314 BFD_RELOC_MMIX_PUSHJ_3
4316 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4318 These are relocations for the PUSHJ instruction.
4322 BFD_RELOC_MMIX_JMP_1
4324 BFD_RELOC_MMIX_JMP_2
4326 BFD_RELOC_MMIX_JMP_3
4328 These are relocations for the JMP instruction.
4330 BFD_RELOC_MMIX_ADDR19
4332 This is a relocation for a relative address as in a GETA instruction or
4335 BFD_RELOC_MMIX_ADDR27
4337 This is a relocation for a relative address as in a JMP instruction.
4339 BFD_RELOC_MMIX_REG_OR_BYTE
4341 This is a relocation for an instruction field that may be a general
4342 register or a value 0..255.
4346 This is a relocation for an instruction field that may be a general
4349 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4351 This is a relocation for two instruction fields holding a register and
4352 an offset, the equivalent of the relocation.
4354 BFD_RELOC_MMIX_LOCAL
4356 This relocation is an assertion that the expression is not allocated as
4357 a global register. It does not modify contents.
4360 BFD_RELOC_AVR_7_PCREL
4362 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4363 short offset into 7 bits.
4365 BFD_RELOC_AVR_13_PCREL
4367 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4368 short offset into 12 bits.
4372 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4373 program memory address) into 16 bits.
4375 BFD_RELOC_AVR_LO8_LDI
4377 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4378 data memory address) into 8 bit immediate value of LDI insn.
4380 BFD_RELOC_AVR_HI8_LDI
4382 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4383 of data memory address) into 8 bit immediate value of LDI insn.
4385 BFD_RELOC_AVR_HH8_LDI
4387 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4388 of program memory address) into 8 bit immediate value of LDI insn.
4390 BFD_RELOC_AVR_MS8_LDI
4392 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4393 of 32 bit value) into 8 bit immediate value of LDI insn.
4395 BFD_RELOC_AVR_LO8_LDI_NEG
4397 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4398 (usually data memory address) into 8 bit immediate value of SUBI insn.
4400 BFD_RELOC_AVR_HI8_LDI_NEG
4402 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4403 (high 8 bit of data memory address) into 8 bit immediate value of
4406 BFD_RELOC_AVR_HH8_LDI_NEG
4408 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4409 (most high 8 bit of program memory address) into 8 bit immediate value
4410 of LDI or SUBI insn.
4412 BFD_RELOC_AVR_MS8_LDI_NEG
4414 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4415 of 32 bit value) into 8 bit immediate value of LDI insn.
4417 BFD_RELOC_AVR_LO8_LDI_PM
4419 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4420 command address) into 8 bit immediate value of LDI insn.
4422 BFD_RELOC_AVR_LO8_LDI_GS
4424 This is a 16 bit reloc for the AVR that stores 8 bit value
4425 (command address) into 8 bit immediate value of LDI insn. If the address
4426 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4429 BFD_RELOC_AVR_HI8_LDI_PM
4431 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4432 of command address) into 8 bit immediate value of LDI insn.
4434 BFD_RELOC_AVR_HI8_LDI_GS
4436 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4437 of command address) into 8 bit immediate value of LDI insn. If the address
4438 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4441 BFD_RELOC_AVR_HH8_LDI_PM
4443 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4444 of command address) into 8 bit immediate value of LDI insn.
4446 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4448 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4449 (usually command address) into 8 bit immediate value of SUBI insn.
4451 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4453 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4454 (high 8 bit of 16 bit command address) into 8 bit immediate value
4457 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4459 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4460 (high 6 bit of 22 bit command address) into 8 bit immediate
4465 This is a 32 bit reloc for the AVR that stores 23 bit value
4470 This is a 16 bit reloc for the AVR that stores all needed bits
4471 for absolute addressing with ldi with overflow check to linktime
4475 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4478 BFD_RELOC_AVR_6_ADIW
4480 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4485 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4486 in .byte lo8(symbol)
4490 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4491 in .byte hi8(symbol)
4495 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4496 in .byte hlo8(symbol)
4501 BFD_RELOC_RL78_NEG16
4503 BFD_RELOC_RL78_NEG24
4505 BFD_RELOC_RL78_NEG32
4507 BFD_RELOC_RL78_16_OP
4509 BFD_RELOC_RL78_24_OP
4511 BFD_RELOC_RL78_32_OP
4519 BFD_RELOC_RL78_DIR3U_PCREL
4523 BFD_RELOC_RL78_GPRELB
4525 BFD_RELOC_RL78_GPRELW
4527 BFD_RELOC_RL78_GPRELL
4531 BFD_RELOC_RL78_OP_SUBTRACT
4533 BFD_RELOC_RL78_OP_NEG
4535 BFD_RELOC_RL78_OP_AND
4537 BFD_RELOC_RL78_OP_SHRA
4541 BFD_RELOC_RL78_ABS16
4543 BFD_RELOC_RL78_ABS16_REV
4545 BFD_RELOC_RL78_ABS32
4547 BFD_RELOC_RL78_ABS32_REV
4549 BFD_RELOC_RL78_ABS16U
4551 BFD_RELOC_RL78_ABS16UW
4553 BFD_RELOC_RL78_ABS16UL
4555 BFD_RELOC_RL78_RELAX
4565 Renesas RL78 Relocations.
4588 BFD_RELOC_RX_DIR3U_PCREL
4600 BFD_RELOC_RX_OP_SUBTRACT
4608 BFD_RELOC_RX_ABS16_REV
4612 BFD_RELOC_RX_ABS32_REV
4616 BFD_RELOC_RX_ABS16UW
4618 BFD_RELOC_RX_ABS16UL
4622 Renesas RX Relocations.
4635 32 bit PC relative PLT address.
4639 Copy symbol at runtime.
4641 BFD_RELOC_390_GLOB_DAT
4645 BFD_RELOC_390_JMP_SLOT
4649 BFD_RELOC_390_RELATIVE
4651 Adjust by program base.
4655 32 bit PC relative offset to GOT.
4661 BFD_RELOC_390_PC16DBL
4663 PC relative 16 bit shifted by 1.
4665 BFD_RELOC_390_PLT16DBL
4667 16 bit PC rel. PLT shifted by 1.
4669 BFD_RELOC_390_PC32DBL
4671 PC relative 32 bit shifted by 1.
4673 BFD_RELOC_390_PLT32DBL
4675 32 bit PC rel. PLT shifted by 1.
4677 BFD_RELOC_390_GOTPCDBL
4679 32 bit PC rel. GOT shifted by 1.
4687 64 bit PC relative PLT address.
4689 BFD_RELOC_390_GOTENT
4691 32 bit rel. offset to GOT entry.
4693 BFD_RELOC_390_GOTOFF64
4695 64 bit offset to GOT.
4697 BFD_RELOC_390_GOTPLT12
4699 12-bit offset to symbol-entry within GOT, with PLT handling.
4701 BFD_RELOC_390_GOTPLT16
4703 16-bit offset to symbol-entry within GOT, with PLT handling.
4705 BFD_RELOC_390_GOTPLT32
4707 32-bit offset to symbol-entry within GOT, with PLT handling.
4709 BFD_RELOC_390_GOTPLT64
4711 64-bit offset to symbol-entry within GOT, with PLT handling.
4713 BFD_RELOC_390_GOTPLTENT
4715 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
4717 BFD_RELOC_390_PLTOFF16
4719 16-bit rel. offset from the GOT to a PLT entry.
4721 BFD_RELOC_390_PLTOFF32
4723 32-bit rel. offset from the GOT to a PLT entry.
4725 BFD_RELOC_390_PLTOFF64
4727 64-bit rel. offset from the GOT to a PLT entry.
4730 BFD_RELOC_390_TLS_LOAD
4732 BFD_RELOC_390_TLS_GDCALL
4734 BFD_RELOC_390_TLS_LDCALL
4736 BFD_RELOC_390_TLS_GD32
4738 BFD_RELOC_390_TLS_GD64
4740 BFD_RELOC_390_TLS_GOTIE12
4742 BFD_RELOC_390_TLS_GOTIE32
4744 BFD_RELOC_390_TLS_GOTIE64
4746 BFD_RELOC_390_TLS_LDM32
4748 BFD_RELOC_390_TLS_LDM64
4750 BFD_RELOC_390_TLS_IE32
4752 BFD_RELOC_390_TLS_IE64
4754 BFD_RELOC_390_TLS_IEENT
4756 BFD_RELOC_390_TLS_LE32
4758 BFD_RELOC_390_TLS_LE64
4760 BFD_RELOC_390_TLS_LDO32
4762 BFD_RELOC_390_TLS_LDO64
4764 BFD_RELOC_390_TLS_DTPMOD
4766 BFD_RELOC_390_TLS_DTPOFF
4768 BFD_RELOC_390_TLS_TPOFF
4770 s390 tls relocations.
4777 BFD_RELOC_390_GOTPLT20
4779 BFD_RELOC_390_TLS_GOTIE20
4781 Long displacement extension.
4784 BFD_RELOC_390_IRELATIVE
4786 STT_GNU_IFUNC relocation.
4789 BFD_RELOC_SCORE_GPREL15
4792 Low 16 bit for load/store
4794 BFD_RELOC_SCORE_DUMMY2
4798 This is a 24-bit reloc with the right 1 bit assumed to be 0
4800 BFD_RELOC_SCORE_BRANCH
4802 This is a 19-bit reloc with the right 1 bit assumed to be 0
4804 BFD_RELOC_SCORE_IMM30
4806 This is a 32-bit reloc for 48-bit instructions.
4808 BFD_RELOC_SCORE_IMM32
4810 This is a 32-bit reloc for 48-bit instructions.
4812 BFD_RELOC_SCORE16_JMP
4814 This is a 11-bit reloc with the right 1 bit assumed to be 0
4816 BFD_RELOC_SCORE16_BRANCH
4818 This is a 8-bit reloc with the right 1 bit assumed to be 0
4820 BFD_RELOC_SCORE_BCMP
4822 This is a 9-bit reloc with the right 1 bit assumed to be 0
4824 BFD_RELOC_SCORE_GOT15
4826 BFD_RELOC_SCORE_GOT_LO16
4828 BFD_RELOC_SCORE_CALL15
4830 BFD_RELOC_SCORE_DUMMY_HI16
4832 Undocumented Score relocs
4837 Scenix IP2K - 9-bit register number / data address
4841 Scenix IP2K - 4-bit register/data bank number
4843 BFD_RELOC_IP2K_ADDR16CJP
4845 Scenix IP2K - low 13 bits of instruction word address
4847 BFD_RELOC_IP2K_PAGE3
4849 Scenix IP2K - high 3 bits of instruction word address
4851 BFD_RELOC_IP2K_LO8DATA
4853 BFD_RELOC_IP2K_HI8DATA
4855 BFD_RELOC_IP2K_EX8DATA
4857 Scenix IP2K - ext/low/high 8 bits of data address
4859 BFD_RELOC_IP2K_LO8INSN
4861 BFD_RELOC_IP2K_HI8INSN
4863 Scenix IP2K - low/high 8 bits of instruction word address
4865 BFD_RELOC_IP2K_PC_SKIP
4867 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
4871 Scenix IP2K - 16 bit word address in text section.
4873 BFD_RELOC_IP2K_FR_OFFSET
4875 Scenix IP2K - 7-bit sp or dp offset
4877 BFD_RELOC_VPE4KMATH_DATA
4879 BFD_RELOC_VPE4KMATH_INSN
4881 Scenix VPE4K coprocessor - data/insn-space addressing
4884 BFD_RELOC_VTABLE_INHERIT
4886 BFD_RELOC_VTABLE_ENTRY
4888 These two relocations are used by the linker to determine which of
4889 the entries in a C++ virtual function table are actually used. When
4890 the --gc-sections option is given, the linker will zero out the entries
4891 that are not used, so that the code for those functions need not be
4892 included in the output.
4894 VTABLE_INHERIT is a zero-space relocation used to describe to the
4895 linker the inheritance tree of a C++ virtual function table. The
4896 relocation's symbol should be the parent class' vtable, and the
4897 relocation should be located at the child vtable.
4899 VTABLE_ENTRY is a zero-space relocation that describes the use of a
4900 virtual function table entry. The reloc's symbol should refer to the
4901 table of the class mentioned in the code. Off of that base, an offset
4902 describes the entry that is being used. For Rela hosts, this offset
4903 is stored in the reloc's addend. For Rel hosts, we are forced to put
4904 this offset in the reloc's section offset.
4907 BFD_RELOC_IA64_IMM14
4909 BFD_RELOC_IA64_IMM22
4911 BFD_RELOC_IA64_IMM64
4913 BFD_RELOC_IA64_DIR32MSB
4915 BFD_RELOC_IA64_DIR32LSB
4917 BFD_RELOC_IA64_DIR64MSB
4919 BFD_RELOC_IA64_DIR64LSB
4921 BFD_RELOC_IA64_GPREL22
4923 BFD_RELOC_IA64_GPREL64I
4925 BFD_RELOC_IA64_GPREL32MSB
4927 BFD_RELOC_IA64_GPREL32LSB
4929 BFD_RELOC_IA64_GPREL64MSB
4931 BFD_RELOC_IA64_GPREL64LSB
4933 BFD_RELOC_IA64_LTOFF22
4935 BFD_RELOC_IA64_LTOFF64I
4937 BFD_RELOC_IA64_PLTOFF22
4939 BFD_RELOC_IA64_PLTOFF64I
4941 BFD_RELOC_IA64_PLTOFF64MSB
4943 BFD_RELOC_IA64_PLTOFF64LSB
4945 BFD_RELOC_IA64_FPTR64I
4947 BFD_RELOC_IA64_FPTR32MSB
4949 BFD_RELOC_IA64_FPTR32LSB
4951 BFD_RELOC_IA64_FPTR64MSB
4953 BFD_RELOC_IA64_FPTR64LSB
4955 BFD_RELOC_IA64_PCREL21B
4957 BFD_RELOC_IA64_PCREL21BI
4959 BFD_RELOC_IA64_PCREL21M
4961 BFD_RELOC_IA64_PCREL21F
4963 BFD_RELOC_IA64_PCREL22
4965 BFD_RELOC_IA64_PCREL60B
4967 BFD_RELOC_IA64_PCREL64I
4969 BFD_RELOC_IA64_PCREL32MSB
4971 BFD_RELOC_IA64_PCREL32LSB
4973 BFD_RELOC_IA64_PCREL64MSB
4975 BFD_RELOC_IA64_PCREL64LSB
4977 BFD_RELOC_IA64_LTOFF_FPTR22
4979 BFD_RELOC_IA64_LTOFF_FPTR64I
4981 BFD_RELOC_IA64_LTOFF_FPTR32MSB
4983 BFD_RELOC_IA64_LTOFF_FPTR32LSB
4985 BFD_RELOC_IA64_LTOFF_FPTR64MSB
4987 BFD_RELOC_IA64_LTOFF_FPTR64LSB
4989 BFD_RELOC_IA64_SEGREL32MSB
4991 BFD_RELOC_IA64_SEGREL32LSB
4993 BFD_RELOC_IA64_SEGREL64MSB
4995 BFD_RELOC_IA64_SEGREL64LSB
4997 BFD_RELOC_IA64_SECREL32MSB
4999 BFD_RELOC_IA64_SECREL32LSB
5001 BFD_RELOC_IA64_SECREL64MSB
5003 BFD_RELOC_IA64_SECREL64LSB
5005 BFD_RELOC_IA64_REL32MSB
5007 BFD_RELOC_IA64_REL32LSB
5009 BFD_RELOC_IA64_REL64MSB
5011 BFD_RELOC_IA64_REL64LSB
5013 BFD_RELOC_IA64_LTV32MSB
5015 BFD_RELOC_IA64_LTV32LSB
5017 BFD_RELOC_IA64_LTV64MSB
5019 BFD_RELOC_IA64_LTV64LSB
5021 BFD_RELOC_IA64_IPLTMSB
5023 BFD_RELOC_IA64_IPLTLSB
5027 BFD_RELOC_IA64_LTOFF22X
5029 BFD_RELOC_IA64_LDXMOV
5031 BFD_RELOC_IA64_TPREL14
5033 BFD_RELOC_IA64_TPREL22
5035 BFD_RELOC_IA64_TPREL64I
5037 BFD_RELOC_IA64_TPREL64MSB
5039 BFD_RELOC_IA64_TPREL64LSB
5041 BFD_RELOC_IA64_LTOFF_TPREL22
5043 BFD_RELOC_IA64_DTPMOD64MSB
5045 BFD_RELOC_IA64_DTPMOD64LSB
5047 BFD_RELOC_IA64_LTOFF_DTPMOD22
5049 BFD_RELOC_IA64_DTPREL14
5051 BFD_RELOC_IA64_DTPREL22
5053 BFD_RELOC_IA64_DTPREL64I
5055 BFD_RELOC_IA64_DTPREL32MSB
5057 BFD_RELOC_IA64_DTPREL32LSB
5059 BFD_RELOC_IA64_DTPREL64MSB
5061 BFD_RELOC_IA64_DTPREL64LSB
5063 BFD_RELOC_IA64_LTOFF_DTPREL22
5065 Intel IA64 Relocations.
5068 BFD_RELOC_M68HC11_HI8
5070 Motorola 68HC11 reloc.
5071 This is the 8 bit high part of an absolute address.
5073 BFD_RELOC_M68HC11_LO8
5075 Motorola 68HC11 reloc.
5076 This is the 8 bit low part of an absolute address.
5078 BFD_RELOC_M68HC11_3B
5080 Motorola 68HC11 reloc.
5081 This is the 3 bit of a value.
5083 BFD_RELOC_M68HC11_RL_JUMP
5085 Motorola 68HC11 reloc.
5086 This reloc marks the beginning of a jump/call instruction.
5087 It is used for linker relaxation to correctly identify beginning
5088 of instruction and change some branches to use PC-relative
5091 BFD_RELOC_M68HC11_RL_GROUP
5093 Motorola 68HC11 reloc.
5094 This reloc marks a group of several instructions that gcc generates
5095 and for which the linker relaxation pass can modify and/or remove
5098 BFD_RELOC_M68HC11_LO16
5100 Motorola 68HC11 reloc.
5101 This is the 16-bit lower part of an address. It is used for 'call'
5102 instruction to specify the symbol address without any special
5103 transformation (due to memory bank window).
5105 BFD_RELOC_M68HC11_PAGE
5107 Motorola 68HC11 reloc.
5108 This is a 8-bit reloc that specifies the page number of an address.
5109 It is used by 'call' instruction to specify the page number of
5112 BFD_RELOC_M68HC11_24
5114 Motorola 68HC11 reloc.
5115 This is a 24-bit reloc that represents the address with a 16-bit
5116 value and a 8-bit page number. The symbol address is transformed
5117 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5119 BFD_RELOC_M68HC12_5B
5121 Motorola 68HC12 reloc.
5122 This is the 5 bits of a value.
5124 BFD_RELOC_XGATE_RL_JUMP
5126 Freescale XGATE reloc.
5127 This reloc marks the beginning of a bra/jal instruction.
5129 BFD_RELOC_XGATE_RL_GROUP
5131 Freescale XGATE reloc.
5132 This reloc marks a group of several instructions that gcc generates
5133 and for which the linker relaxation pass can modify and/or remove
5136 BFD_RELOC_XGATE_LO16
5138 Freescale XGATE reloc.
5139 This is the 16-bit lower part of an address. It is used for the '16-bit'
5142 BFD_RELOC_XGATE_GPAGE
5144 Freescale XGATE reloc.
5148 Freescale XGATE reloc.
5150 BFD_RELOC_XGATE_PCREL_9
5152 Freescale XGATE reloc.
5153 This is a 9-bit pc-relative reloc.
5155 BFD_RELOC_XGATE_PCREL_10
5157 Freescale XGATE reloc.
5158 This is a 10-bit pc-relative reloc.
5160 BFD_RELOC_XGATE_IMM8_LO
5162 Freescale XGATE reloc.
5163 This is the 16-bit lower part of an address. It is used for the '16-bit'
5166 BFD_RELOC_XGATE_IMM8_HI
5168 Freescale XGATE reloc.
5169 This is the 16-bit higher part of an address. It is used for the '16-bit'
5172 BFD_RELOC_XGATE_IMM3
5174 Freescale XGATE reloc.
5175 This is a 3-bit pc-relative reloc.
5177 BFD_RELOC_XGATE_IMM4
5179 Freescale XGATE reloc.
5180 This is a 4-bit pc-relative reloc.
5182 BFD_RELOC_XGATE_IMM5
5184 Freescale XGATE reloc.
5185 This is a 5-bit pc-relative reloc.
5187 BFD_RELOC_M68HC12_9B
5189 Motorola 68HC12 reloc.
5190 This is the 9 bits of a value.
5192 BFD_RELOC_M68HC12_16B
5194 Motorola 68HC12 reloc.
5195 This is the 16 bits of a value.
5197 BFD_RELOC_M68HC12_9_PCREL
5199 Motorola 68HC12/XGATE reloc.
5200 This is a PCREL9 branch.
5202 BFD_RELOC_M68HC12_10_PCREL
5204 Motorola 68HC12/XGATE reloc.
5205 This is a PCREL10 branch.
5207 BFD_RELOC_M68HC12_LO8XG
5209 Motorola 68HC12/XGATE reloc.
5210 This is the 8 bit low part of an absolute address and immediately precedes
5211 a matching HI8XG part.
5213 BFD_RELOC_M68HC12_HI8XG
5215 Motorola 68HC12/XGATE reloc.
5216 This is the 8 bit high part of an absolute address and immediately follows
5217 a matching LO8XG part.
5221 BFD_RELOC_16C_NUM08_C
5225 BFD_RELOC_16C_NUM16_C
5229 BFD_RELOC_16C_NUM32_C
5231 BFD_RELOC_16C_DISP04
5233 BFD_RELOC_16C_DISP04_C
5235 BFD_RELOC_16C_DISP08
5237 BFD_RELOC_16C_DISP08_C
5239 BFD_RELOC_16C_DISP16
5241 BFD_RELOC_16C_DISP16_C
5243 BFD_RELOC_16C_DISP24
5245 BFD_RELOC_16C_DISP24_C
5247 BFD_RELOC_16C_DISP24a
5249 BFD_RELOC_16C_DISP24a_C
5253 BFD_RELOC_16C_REG04_C
5255 BFD_RELOC_16C_REG04a
5257 BFD_RELOC_16C_REG04a_C
5261 BFD_RELOC_16C_REG14_C
5265 BFD_RELOC_16C_REG16_C
5269 BFD_RELOC_16C_REG20_C
5273 BFD_RELOC_16C_ABS20_C
5277 BFD_RELOC_16C_ABS24_C
5281 BFD_RELOC_16C_IMM04_C
5285 BFD_RELOC_16C_IMM16_C
5289 BFD_RELOC_16C_IMM20_C
5293 BFD_RELOC_16C_IMM24_C
5297 BFD_RELOC_16C_IMM32_C
5299 NS CR16C Relocations.
5304 BFD_RELOC_CR16_NUM16
5306 BFD_RELOC_CR16_NUM32
5308 BFD_RELOC_CR16_NUM32a
5310 BFD_RELOC_CR16_REGREL0
5312 BFD_RELOC_CR16_REGREL4
5314 BFD_RELOC_CR16_REGREL4a
5316 BFD_RELOC_CR16_REGREL14
5318 BFD_RELOC_CR16_REGREL14a
5320 BFD_RELOC_CR16_REGREL16
5322 BFD_RELOC_CR16_REGREL20
5324 BFD_RELOC_CR16_REGREL20a
5326 BFD_RELOC_CR16_ABS20
5328 BFD_RELOC_CR16_ABS24
5334 BFD_RELOC_CR16_IMM16
5336 BFD_RELOC_CR16_IMM20
5338 BFD_RELOC_CR16_IMM24
5340 BFD_RELOC_CR16_IMM32
5342 BFD_RELOC_CR16_IMM32a
5344 BFD_RELOC_CR16_DISP4
5346 BFD_RELOC_CR16_DISP8
5348 BFD_RELOC_CR16_DISP16
5350 BFD_RELOC_CR16_DISP20
5352 BFD_RELOC_CR16_DISP24
5354 BFD_RELOC_CR16_DISP24a
5356 BFD_RELOC_CR16_SWITCH8
5358 BFD_RELOC_CR16_SWITCH16
5360 BFD_RELOC_CR16_SWITCH32
5362 BFD_RELOC_CR16_GOT_REGREL20
5364 BFD_RELOC_CR16_GOTC_REGREL20
5366 BFD_RELOC_CR16_GLOB_DAT
5368 NS CR16 Relocations.
5375 BFD_RELOC_CRX_REL8_CMP
5383 BFD_RELOC_CRX_REGREL12
5385 BFD_RELOC_CRX_REGREL22
5387 BFD_RELOC_CRX_REGREL28
5389 BFD_RELOC_CRX_REGREL32
5405 BFD_RELOC_CRX_SWITCH8
5407 BFD_RELOC_CRX_SWITCH16
5409 BFD_RELOC_CRX_SWITCH32
5414 BFD_RELOC_CRIS_BDISP8
5416 BFD_RELOC_CRIS_UNSIGNED_5
5418 BFD_RELOC_CRIS_SIGNED_6
5420 BFD_RELOC_CRIS_UNSIGNED_6
5422 BFD_RELOC_CRIS_SIGNED_8
5424 BFD_RELOC_CRIS_UNSIGNED_8
5426 BFD_RELOC_CRIS_SIGNED_16
5428 BFD_RELOC_CRIS_UNSIGNED_16
5430 BFD_RELOC_CRIS_LAPCQ_OFFSET
5432 BFD_RELOC_CRIS_UNSIGNED_4
5434 These relocs are only used within the CRIS assembler. They are not
5435 (at present) written to any object files.
5439 BFD_RELOC_CRIS_GLOB_DAT
5441 BFD_RELOC_CRIS_JUMP_SLOT
5443 BFD_RELOC_CRIS_RELATIVE
5445 Relocs used in ELF shared libraries for CRIS.
5447 BFD_RELOC_CRIS_32_GOT
5449 32-bit offset to symbol-entry within GOT.
5451 BFD_RELOC_CRIS_16_GOT
5453 16-bit offset to symbol-entry within GOT.
5455 BFD_RELOC_CRIS_32_GOTPLT
5457 32-bit offset to symbol-entry within GOT, with PLT handling.
5459 BFD_RELOC_CRIS_16_GOTPLT
5461 16-bit offset to symbol-entry within GOT, with PLT handling.
5463 BFD_RELOC_CRIS_32_GOTREL
5465 32-bit offset to symbol, relative to GOT.
5467 BFD_RELOC_CRIS_32_PLT_GOTREL
5469 32-bit offset to symbol with PLT entry, relative to GOT.
5471 BFD_RELOC_CRIS_32_PLT_PCREL
5473 32-bit offset to symbol with PLT entry, relative to this relocation.
5476 BFD_RELOC_CRIS_32_GOT_GD
5478 BFD_RELOC_CRIS_16_GOT_GD
5480 BFD_RELOC_CRIS_32_GD
5484 BFD_RELOC_CRIS_32_DTPREL
5486 BFD_RELOC_CRIS_16_DTPREL
5488 BFD_RELOC_CRIS_32_GOT_TPREL
5490 BFD_RELOC_CRIS_16_GOT_TPREL
5492 BFD_RELOC_CRIS_32_TPREL
5494 BFD_RELOC_CRIS_16_TPREL
5496 BFD_RELOC_CRIS_DTPMOD
5498 BFD_RELOC_CRIS_32_IE
5500 Relocs used in TLS code for CRIS.
5505 BFD_RELOC_860_GLOB_DAT
5507 BFD_RELOC_860_JUMP_SLOT
5509 BFD_RELOC_860_RELATIVE
5519 BFD_RELOC_860_SPLIT0
5523 BFD_RELOC_860_SPLIT1
5527 BFD_RELOC_860_SPLIT2
5531 BFD_RELOC_860_LOGOT0
5533 BFD_RELOC_860_SPGOT0
5535 BFD_RELOC_860_LOGOT1
5537 BFD_RELOC_860_SPGOT1
5539 BFD_RELOC_860_LOGOTOFF0
5541 BFD_RELOC_860_SPGOTOFF0
5543 BFD_RELOC_860_LOGOTOFF1
5545 BFD_RELOC_860_SPGOTOFF1
5547 BFD_RELOC_860_LOGOTOFF2
5549 BFD_RELOC_860_LOGOTOFF3
5553 BFD_RELOC_860_HIGHADJ
5557 BFD_RELOC_860_HAGOTOFF
5565 BFD_RELOC_860_HIGOTOFF
5567 Intel i860 Relocations.
5570 BFD_RELOC_OPENRISC_ABS_26
5572 BFD_RELOC_OPENRISC_REL_26
5574 OpenRISC Relocations.
5577 BFD_RELOC_H8_DIR16A8
5579 BFD_RELOC_H8_DIR16R8
5581 BFD_RELOC_H8_DIR24A8
5583 BFD_RELOC_H8_DIR24R8
5585 BFD_RELOC_H8_DIR32A16
5587 BFD_RELOC_H8_DISP32A16
5592 BFD_RELOC_XSTORMY16_REL_12
5594 BFD_RELOC_XSTORMY16_12
5596 BFD_RELOC_XSTORMY16_24
5598 BFD_RELOC_XSTORMY16_FPTR16
5600 Sony Xstormy16 Relocations.
5605 Self-describing complex relocations.
5617 Infineon Relocations.
5620 BFD_RELOC_VAX_GLOB_DAT
5622 BFD_RELOC_VAX_JMP_SLOT
5624 BFD_RELOC_VAX_RELATIVE
5626 Relocations used by VAX ELF.
5631 Morpho MT - 16 bit immediate relocation.
5635 Morpho MT - Hi 16 bits of an address.
5639 Morpho MT - Low 16 bits of an address.
5641 BFD_RELOC_MT_GNU_VTINHERIT
5643 Morpho MT - Used to tell the linker which vtable entries are used.
5645 BFD_RELOC_MT_GNU_VTENTRY
5647 Morpho MT - Used to tell the linker which vtable entries are used.
5649 BFD_RELOC_MT_PCINSN8
5651 Morpho MT - 8 bit immediate relocation.
5654 BFD_RELOC_MSP430_10_PCREL
5656 BFD_RELOC_MSP430_16_PCREL
5660 BFD_RELOC_MSP430_16_PCREL_BYTE
5662 BFD_RELOC_MSP430_16_BYTE
5664 BFD_RELOC_MSP430_2X_PCREL
5666 BFD_RELOC_MSP430_RL_PCREL
5668 BFD_RELOC_MSP430_ABS8
5670 BFD_RELOC_MSP430X_PCR20_EXT_SRC
5672 BFD_RELOC_MSP430X_PCR20_EXT_DST
5674 BFD_RELOC_MSP430X_PCR20_EXT_ODST
5676 BFD_RELOC_MSP430X_ABS20_EXT_SRC
5678 BFD_RELOC_MSP430X_ABS20_EXT_DST
5680 BFD_RELOC_MSP430X_ABS20_EXT_ODST
5682 BFD_RELOC_MSP430X_ABS20_ADR_SRC
5684 BFD_RELOC_MSP430X_ABS20_ADR_DST
5686 BFD_RELOC_MSP430X_PCR16
5688 BFD_RELOC_MSP430X_PCR20_CALL
5690 BFD_RELOC_MSP430X_ABS16
5692 BFD_RELOC_MSP430_ABS_HI16
5694 BFD_RELOC_MSP430_PREL31
5696 BFD_RELOC_MSP430_SYM_DIFF
5698 msp430 specific relocation codes
5705 BFD_RELOC_NIOS2_CALL26
5707 BFD_RELOC_NIOS2_IMM5
5709 BFD_RELOC_NIOS2_CACHE_OPX
5711 BFD_RELOC_NIOS2_IMM6
5713 BFD_RELOC_NIOS2_IMM8
5715 BFD_RELOC_NIOS2_HI16
5717 BFD_RELOC_NIOS2_LO16
5719 BFD_RELOC_NIOS2_HIADJ16
5721 BFD_RELOC_NIOS2_GPREL
5723 BFD_RELOC_NIOS2_UJMP
5725 BFD_RELOC_NIOS2_CJMP
5727 BFD_RELOC_NIOS2_CALLR
5729 BFD_RELOC_NIOS2_ALIGN
5731 BFD_RELOC_NIOS2_GOT16
5733 BFD_RELOC_NIOS2_CALL16
5735 BFD_RELOC_NIOS2_GOTOFF_LO
5737 BFD_RELOC_NIOS2_GOTOFF_HA
5739 BFD_RELOC_NIOS2_PCREL_LO
5741 BFD_RELOC_NIOS2_PCREL_HA
5743 BFD_RELOC_NIOS2_TLS_GD16
5745 BFD_RELOC_NIOS2_TLS_LDM16
5747 BFD_RELOC_NIOS2_TLS_LDO16
5749 BFD_RELOC_NIOS2_TLS_IE16
5751 BFD_RELOC_NIOS2_TLS_LE16
5753 BFD_RELOC_NIOS2_TLS_DTPMOD
5755 BFD_RELOC_NIOS2_TLS_DTPREL
5757 BFD_RELOC_NIOS2_TLS_TPREL
5759 BFD_RELOC_NIOS2_COPY
5761 BFD_RELOC_NIOS2_GLOB_DAT
5763 BFD_RELOC_NIOS2_JUMP_SLOT
5765 BFD_RELOC_NIOS2_RELATIVE
5767 BFD_RELOC_NIOS2_GOTOFF
5769 Relocations used by the Altera Nios II core.
5772 BFD_RELOC_IQ2000_OFFSET_16
5774 BFD_RELOC_IQ2000_OFFSET_21
5776 BFD_RELOC_IQ2000_UHI16
5781 BFD_RELOC_XTENSA_RTLD
5783 Special Xtensa relocation used only by PLT entries in ELF shared
5784 objects to indicate that the runtime linker should set the value
5785 to one of its own internal functions or data structures.
5787 BFD_RELOC_XTENSA_GLOB_DAT
5789 BFD_RELOC_XTENSA_JMP_SLOT
5791 BFD_RELOC_XTENSA_RELATIVE
5793 Xtensa relocations for ELF shared objects.
5795 BFD_RELOC_XTENSA_PLT
5797 Xtensa relocation used in ELF object files for symbols that may require
5798 PLT entries. Otherwise, this is just a generic 32-bit relocation.
5800 BFD_RELOC_XTENSA_DIFF8
5802 BFD_RELOC_XTENSA_DIFF16
5804 BFD_RELOC_XTENSA_DIFF32
5806 Xtensa relocations to mark the difference of two local symbols.
5807 These are only needed to support linker relaxation and can be ignored
5808 when not relaxing. The field is set to the value of the difference
5809 assuming no relaxation. The relocation encodes the position of the
5810 first symbol so the linker can determine whether to adjust the field
5813 BFD_RELOC_XTENSA_SLOT0_OP
5815 BFD_RELOC_XTENSA_SLOT1_OP
5817 BFD_RELOC_XTENSA_SLOT2_OP
5819 BFD_RELOC_XTENSA_SLOT3_OP
5821 BFD_RELOC_XTENSA_SLOT4_OP
5823 BFD_RELOC_XTENSA_SLOT5_OP
5825 BFD_RELOC_XTENSA_SLOT6_OP
5827 BFD_RELOC_XTENSA_SLOT7_OP
5829 BFD_RELOC_XTENSA_SLOT8_OP
5831 BFD_RELOC_XTENSA_SLOT9_OP
5833 BFD_RELOC_XTENSA_SLOT10_OP
5835 BFD_RELOC_XTENSA_SLOT11_OP
5837 BFD_RELOC_XTENSA_SLOT12_OP
5839 BFD_RELOC_XTENSA_SLOT13_OP
5841 BFD_RELOC_XTENSA_SLOT14_OP
5843 Generic Xtensa relocations for instruction operands. Only the slot
5844 number is encoded in the relocation. The relocation applies to the
5845 last PC-relative immediate operand, or if there are no PC-relative
5846 immediates, to the last immediate operand.
5848 BFD_RELOC_XTENSA_SLOT0_ALT
5850 BFD_RELOC_XTENSA_SLOT1_ALT
5852 BFD_RELOC_XTENSA_SLOT2_ALT
5854 BFD_RELOC_XTENSA_SLOT3_ALT
5856 BFD_RELOC_XTENSA_SLOT4_ALT
5858 BFD_RELOC_XTENSA_SLOT5_ALT
5860 BFD_RELOC_XTENSA_SLOT6_ALT
5862 BFD_RELOC_XTENSA_SLOT7_ALT
5864 BFD_RELOC_XTENSA_SLOT8_ALT
5866 BFD_RELOC_XTENSA_SLOT9_ALT
5868 BFD_RELOC_XTENSA_SLOT10_ALT
5870 BFD_RELOC_XTENSA_SLOT11_ALT
5872 BFD_RELOC_XTENSA_SLOT12_ALT
5874 BFD_RELOC_XTENSA_SLOT13_ALT
5876 BFD_RELOC_XTENSA_SLOT14_ALT
5878 Alternate Xtensa relocations. Only the slot is encoded in the
5879 relocation. The meaning of these relocations is opcode-specific.
5881 BFD_RELOC_XTENSA_OP0
5883 BFD_RELOC_XTENSA_OP1
5885 BFD_RELOC_XTENSA_OP2
5887 Xtensa relocations for backward compatibility. These have all been
5888 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
5890 BFD_RELOC_XTENSA_ASM_EXPAND
5892 Xtensa relocation to mark that the assembler expanded the
5893 instructions from an original target. The expansion size is
5894 encoded in the reloc size.
5896 BFD_RELOC_XTENSA_ASM_SIMPLIFY
5898 Xtensa relocation to mark that the linker should simplify
5899 assembler-expanded instructions. This is commonly used
5900 internally by the linker after analysis of a
5901 BFD_RELOC_XTENSA_ASM_EXPAND.
5903 BFD_RELOC_XTENSA_TLSDESC_FN
5905 BFD_RELOC_XTENSA_TLSDESC_ARG
5907 BFD_RELOC_XTENSA_TLS_DTPOFF
5909 BFD_RELOC_XTENSA_TLS_TPOFF
5911 BFD_RELOC_XTENSA_TLS_FUNC
5913 BFD_RELOC_XTENSA_TLS_ARG
5915 BFD_RELOC_XTENSA_TLS_CALL
5917 Xtensa TLS relocations.
5922 8 bit signed offset in (ix+d) or (iy+d).
5940 BFD_RELOC_LM32_BRANCH
5942 BFD_RELOC_LM32_16_GOT
5944 BFD_RELOC_LM32_GOTOFF_HI16
5946 BFD_RELOC_LM32_GOTOFF_LO16
5950 BFD_RELOC_LM32_GLOB_DAT
5952 BFD_RELOC_LM32_JMP_SLOT
5954 BFD_RELOC_LM32_RELATIVE
5956 Lattice Mico32 relocations.
5959 BFD_RELOC_MACH_O_SECTDIFF
5961 Difference between two section addreses. Must be followed by a
5962 BFD_RELOC_MACH_O_PAIR.
5964 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
5966 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
5968 BFD_RELOC_MACH_O_PAIR
5970 Pair of relocation. Contains the first symbol.
5973 BFD_RELOC_MACH_O_X86_64_BRANCH32
5975 BFD_RELOC_MACH_O_X86_64_BRANCH8
5977 PCREL relocations. They are marked as branch to create PLT entry if
5980 BFD_RELOC_MACH_O_X86_64_GOT
5982 Used when referencing a GOT entry.
5984 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
5986 Used when loading a GOT entry with movq. It is specially marked so that
5987 the linker could optimize the movq to a leaq if possible.
5989 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
5991 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
5993 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
5995 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
5997 BFD_RELOC_MACH_O_X86_64_PCREL32_1
5999 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6001 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6003 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6005 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6007 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6010 BFD_RELOC_MICROBLAZE_32_LO
6012 This is a 32 bit reloc for the microblaze that stores the
6013 low 16 bits of a value
6015 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6017 This is a 32 bit pc-relative reloc for the microblaze that
6018 stores the low 16 bits of a value
6020 BFD_RELOC_MICROBLAZE_32_ROSDA
6022 This is a 32 bit reloc for the microblaze that stores a
6023 value relative to the read-only small data area anchor
6025 BFD_RELOC_MICROBLAZE_32_RWSDA
6027 This is a 32 bit reloc for the microblaze that stores a
6028 value relative to the read-write small data area anchor
6030 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6032 This is a 32 bit reloc for the microblaze to handle
6033 expressions of the form "Symbol Op Symbol"
6035 BFD_RELOC_MICROBLAZE_64_NONE
6037 This is a 64 bit reloc that stores the 32 bit pc relative
6038 value in two words (with an imm instruction). No relocation is
6039 done here - only used for relaxing
6041 BFD_RELOC_MICROBLAZE_64_GOTPC
6043 This is a 64 bit reloc that stores the 32 bit pc relative
6044 value in two words (with an imm instruction). The relocation is
6045 PC-relative GOT offset
6047 BFD_RELOC_MICROBLAZE_64_GOT
6049 This is a 64 bit reloc that stores the 32 bit pc relative
6050 value in two words (with an imm instruction). The relocation is
6053 BFD_RELOC_MICROBLAZE_64_PLT
6055 This is a 64 bit reloc that stores the 32 bit pc relative
6056 value in two words (with an imm instruction). The relocation is
6057 PC-relative offset into PLT
6059 BFD_RELOC_MICROBLAZE_64_GOTOFF
6061 This is a 64 bit reloc that stores the 32 bit GOT relative
6062 value in two words (with an imm instruction). The relocation is
6063 relative offset from _GLOBAL_OFFSET_TABLE_
6065 BFD_RELOC_MICROBLAZE_32_GOTOFF
6067 This is a 32 bit reloc that stores the 32 bit GOT relative
6068 value in a word. The relocation is relative offset from
6069 _GLOBAL_OFFSET_TABLE_
6071 BFD_RELOC_MICROBLAZE_COPY
6073 This is used to tell the dynamic linker to copy the value out of
6074 the dynamic object into the runtime process image.
6076 BFD_RELOC_MICROBLAZE_64_TLS
6080 BFD_RELOC_MICROBLAZE_64_TLSGD
6082 This is a 64 bit reloc that stores the 32 bit GOT relative value
6083 of the GOT TLS GD info entry in two words (with an imm instruction). The
6084 relocation is GOT offset.
6086 BFD_RELOC_MICROBLAZE_64_TLSLD
6088 This is a 64 bit reloc that stores the 32 bit GOT relative value
6089 of the GOT TLS LD info entry in two words (with an imm instruction). The
6090 relocation is GOT offset.
6092 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6094 This is a 32 bit reloc that stores the Module ID to GOT(n).
6096 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6098 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6100 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6102 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6105 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6107 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6108 to two words (uses imm instruction).
6110 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6112 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6113 to two words (uses imm instruction).
6116 BFD_RELOC_AARCH64_ADD_LO12
6118 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6119 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6121 BFD_RELOC_AARCH64_GOT_LD_PREL19
6123 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6124 offset of the global offset table entry for a symbol. The lowest two
6125 bits must be zero and are not stored in the instruction, giving a 21
6126 bit signed byte offset. This relocation type requires signed overflow
6129 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6131 Get to the page base of the global offset table entry for a symbol as
6132 part of an ADRP instruction using a 21 bit PC relative value.Used in
6133 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6135 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6137 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6138 offset, giving a 4KB aligned page base address.
6140 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6142 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6143 offset, giving a 4KB aligned page base address, but with no overflow
6146 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6148 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6150 BFD_RELOC_AARCH64_BRANCH19
6152 AArch64 19 bit pc-relative conditional branch and compare & branch.
6153 The lowest two bits must be zero and are not stored in the instruction,
6154 giving a 21 bit signed byte offset.
6156 BFD_RELOC_AARCH64_CALL26
6158 AArch64 26 bit pc-relative unconditional branch and link.
6159 The lowest two bits must be zero and are not stored in the instruction,
6160 giving a 28 bit signed byte offset.
6162 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
6164 AArch64 pseudo relocation code to be used internally by the AArch64
6165 assembler and not (currently) written to any object files.
6167 BFD_RELOC_AARCH64_JUMP26
6169 AArch64 26 bit pc-relative unconditional branch.
6170 The lowest two bits must be zero and are not stored in the instruction,
6171 giving a 28 bit signed byte offset.
6173 BFD_RELOC_AARCH64_LD_LO19_PCREL
6175 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6176 offset. The lowest two bits must be zero and are not stored in the
6177 instruction, giving a 21 bit signed byte offset.
6179 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6181 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6182 the GOT entry for this symbol. Used in conjunction with
6183 BFD_RELOC_AARCH64_ADR_GOTPAGE.
6185 BFD_RELOC_AARCH64_LDST_LO12
6187 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
6188 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6190 BFD_RELOC_AARCH64_LDST8_LO12
6192 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6193 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6195 BFD_RELOC_AARCH64_LDST16_LO12
6197 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6198 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6200 BFD_RELOC_AARCH64_LDST32_LO12
6202 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6203 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6205 BFD_RELOC_AARCH64_LDST64_LO12
6207 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6208 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6210 BFD_RELOC_AARCH64_LDST128_LO12
6212 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6213 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6215 BFD_RELOC_AARCH64_MOVW_G0
6217 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6218 of an unsigned address/value.
6220 BFD_RELOC_AARCH64_MOVW_G0_S
6222 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6223 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6226 BFD_RELOC_AARCH64_MOVW_G0_NC
6228 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6229 an address/value. No overflow checking.
6231 BFD_RELOC_AARCH64_MOVW_G1
6233 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6234 of an unsigned address/value.
6236 BFD_RELOC_AARCH64_MOVW_G1_NC
6238 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6239 of an address/value. No overflow checking.
6241 BFD_RELOC_AARCH64_MOVW_G1_S
6243 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6244 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6247 BFD_RELOC_AARCH64_MOVW_G2
6249 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6250 of an unsigned address/value.
6252 BFD_RELOC_AARCH64_MOVW_G2_NC
6254 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6255 of an address/value. No overflow checking.
6257 BFD_RELOC_AARCH64_MOVW_G2_S
6259 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6260 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6263 BFD_RELOC_AARCH64_MOVW_G3
6265 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6266 of a signed or unsigned address/value.
6268 BFD_RELOC_AARCH64_TLSDESC
6270 AArch64 TLS relocation.
6272 BFD_RELOC_AARCH64_TLSDESC_ADD
6274 AArch64 TLS DESC relocation.
6276 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
6278 AArch64 TLS DESC relocation.
6280 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
6282 AArch64 TLS DESC relocation.
6284 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
6286 AArch64 TLS DESC relocation.
6288 BFD_RELOC_AARCH64_TLSDESC_CALL
6290 AArch64 TLS DESC relocation.
6292 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
6294 AArch64 TLS DESC relocation.
6296 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
6298 AArch64 TLS DESC relocation.
6300 BFD_RELOC_AARCH64_TLSDESC_LDR
6302 AArch64 TLS DESC relocation.
6304 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
6306 AArch64 TLS DESC relocation.
6308 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
6310 AArch64 TLS DESC relocation.
6312 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6314 Unsigned 12 bit byte offset to global offset table entry for a symbols
6315 tls_index structure. Used in conjunction with
6316 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
6318 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6320 Get to the page base of the global offset table entry for a symbols
6321 tls_index structure as part of an adrp instruction using a 21 bit PC
6322 relative value. Used in conjunction with
6323 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6325 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
6327 AArch64 TLS INITIAL EXEC relocation.
6329 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
6331 AArch64 TLS INITIAL EXEC relocation.
6333 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
6335 AArch64 TLS INITIAL EXEC relocation.
6337 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
6339 AArch64 TLS INITIAL EXEC relocation.
6341 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
6343 AArch64 TLS INITIAL EXEC relocation.
6345 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
6347 AArch64 TLS LOCAL EXEC relocation.
6349 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
6351 AArch64 TLS LOCAL EXEC relocation.
6353 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
6355 AArch64 TLS LOCAL EXEC relocation.
6357 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
6359 AArch64 TLS LOCAL EXEC relocation.
6361 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
6363 AArch64 TLS LOCAL EXEC relocation.
6365 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
6367 AArch64 TLS LOCAL EXEC relocation.
6369 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
6371 AArch64 TLS LOCAL EXEC relocation.
6373 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
6375 AArch64 TLS LOCAL EXEC relocation.
6377 BFD_RELOC_AARCH64_TLS_DTPMOD64
6379 AArch64 TLS relocation.
6381 BFD_RELOC_AARCH64_TLS_DTPREL64
6383 AArch64 TLS relocation.
6385 BFD_RELOC_AARCH64_TLS_TPREL64
6387 AArch64 TLS relocation.
6389 BFD_RELOC_AARCH64_TSTBR14
6391 AArch64 14 bit pc-relative test bit and branch.
6392 The lowest two bits must be zero and are not stored in the instruction,
6393 giving a 16 bit signed byte offset.
6396 BFD_RELOC_TILEPRO_COPY
6398 BFD_RELOC_TILEPRO_GLOB_DAT
6400 BFD_RELOC_TILEPRO_JMP_SLOT
6402 BFD_RELOC_TILEPRO_RELATIVE
6404 BFD_RELOC_TILEPRO_BROFF_X1
6406 BFD_RELOC_TILEPRO_JOFFLONG_X1
6408 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
6410 BFD_RELOC_TILEPRO_IMM8_X0
6412 BFD_RELOC_TILEPRO_IMM8_Y0
6414 BFD_RELOC_TILEPRO_IMM8_X1
6416 BFD_RELOC_TILEPRO_IMM8_Y1
6418 BFD_RELOC_TILEPRO_DEST_IMM8_X1
6420 BFD_RELOC_TILEPRO_MT_IMM15_X1
6422 BFD_RELOC_TILEPRO_MF_IMM15_X1
6424 BFD_RELOC_TILEPRO_IMM16_X0
6426 BFD_RELOC_TILEPRO_IMM16_X1
6428 BFD_RELOC_TILEPRO_IMM16_X0_LO
6430 BFD_RELOC_TILEPRO_IMM16_X1_LO
6432 BFD_RELOC_TILEPRO_IMM16_X0_HI
6434 BFD_RELOC_TILEPRO_IMM16_X1_HI
6436 BFD_RELOC_TILEPRO_IMM16_X0_HA
6438 BFD_RELOC_TILEPRO_IMM16_X1_HA
6440 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
6442 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
6444 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
6446 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
6448 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
6450 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
6452 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
6454 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
6456 BFD_RELOC_TILEPRO_IMM16_X0_GOT
6458 BFD_RELOC_TILEPRO_IMM16_X1_GOT
6460 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
6462 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
6464 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
6466 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
6468 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
6470 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
6472 BFD_RELOC_TILEPRO_MMSTART_X0
6474 BFD_RELOC_TILEPRO_MMEND_X0
6476 BFD_RELOC_TILEPRO_MMSTART_X1
6478 BFD_RELOC_TILEPRO_MMEND_X1
6480 BFD_RELOC_TILEPRO_SHAMT_X0
6482 BFD_RELOC_TILEPRO_SHAMT_X1
6484 BFD_RELOC_TILEPRO_SHAMT_Y0
6486 BFD_RELOC_TILEPRO_SHAMT_Y1
6488 BFD_RELOC_TILEPRO_TLS_GD_CALL
6490 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
6492 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
6494 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
6496 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
6498 BFD_RELOC_TILEPRO_TLS_IE_LOAD
6500 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
6502 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
6504 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
6506 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
6508 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
6510 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
6512 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
6514 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
6516 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
6518 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
6520 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
6522 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
6524 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
6526 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
6528 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
6530 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
6532 BFD_RELOC_TILEPRO_TLS_DTPMOD32
6534 BFD_RELOC_TILEPRO_TLS_DTPOFF32
6536 BFD_RELOC_TILEPRO_TLS_TPOFF32
6538 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
6540 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
6542 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
6544 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
6546 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
6548 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
6550 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
6552 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
6554 Tilera TILEPro Relocations.
6556 BFD_RELOC_TILEGX_HW0
6558 BFD_RELOC_TILEGX_HW1
6560 BFD_RELOC_TILEGX_HW2
6562 BFD_RELOC_TILEGX_HW3
6564 BFD_RELOC_TILEGX_HW0_LAST
6566 BFD_RELOC_TILEGX_HW1_LAST
6568 BFD_RELOC_TILEGX_HW2_LAST
6570 BFD_RELOC_TILEGX_COPY
6572 BFD_RELOC_TILEGX_GLOB_DAT
6574 BFD_RELOC_TILEGX_JMP_SLOT
6576 BFD_RELOC_TILEGX_RELATIVE
6578 BFD_RELOC_TILEGX_BROFF_X1
6580 BFD_RELOC_TILEGX_JUMPOFF_X1
6582 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
6584 BFD_RELOC_TILEGX_IMM8_X0
6586 BFD_RELOC_TILEGX_IMM8_Y0
6588 BFD_RELOC_TILEGX_IMM8_X1
6590 BFD_RELOC_TILEGX_IMM8_Y1
6592 BFD_RELOC_TILEGX_DEST_IMM8_X1
6594 BFD_RELOC_TILEGX_MT_IMM14_X1
6596 BFD_RELOC_TILEGX_MF_IMM14_X1
6598 BFD_RELOC_TILEGX_MMSTART_X0
6600 BFD_RELOC_TILEGX_MMEND_X0
6602 BFD_RELOC_TILEGX_SHAMT_X0
6604 BFD_RELOC_TILEGX_SHAMT_X1
6606 BFD_RELOC_TILEGX_SHAMT_Y0
6608 BFD_RELOC_TILEGX_SHAMT_Y1
6610 BFD_RELOC_TILEGX_IMM16_X0_HW0
6612 BFD_RELOC_TILEGX_IMM16_X1_HW0
6614 BFD_RELOC_TILEGX_IMM16_X0_HW1
6616 BFD_RELOC_TILEGX_IMM16_X1_HW1
6618 BFD_RELOC_TILEGX_IMM16_X0_HW2
6620 BFD_RELOC_TILEGX_IMM16_X1_HW2
6622 BFD_RELOC_TILEGX_IMM16_X0_HW3
6624 BFD_RELOC_TILEGX_IMM16_X1_HW3
6626 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
6628 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
6630 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
6632 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
6634 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
6636 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
6638 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
6640 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
6642 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
6644 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
6646 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
6648 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
6650 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
6652 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
6654 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
6656 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
6658 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
6660 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
6662 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
6664 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
6666 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
6668 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
6670 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
6672 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
6674 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
6676 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
6678 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
6680 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
6682 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
6684 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
6686 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
6688 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
6690 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
6692 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
6694 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
6696 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
6698 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
6700 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
6702 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
6704 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
6706 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
6708 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
6710 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
6712 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
6714 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
6716 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
6718 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
6720 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
6722 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
6724 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
6726 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
6728 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
6730 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
6732 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
6734 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
6736 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
6738 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
6740 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
6742 BFD_RELOC_TILEGX_TLS_DTPMOD64
6744 BFD_RELOC_TILEGX_TLS_DTPOFF64
6746 BFD_RELOC_TILEGX_TLS_TPOFF64
6748 BFD_RELOC_TILEGX_TLS_DTPMOD32
6750 BFD_RELOC_TILEGX_TLS_DTPOFF32
6752 BFD_RELOC_TILEGX_TLS_TPOFF32
6754 BFD_RELOC_TILEGX_TLS_GD_CALL
6756 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
6758 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
6760 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
6762 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
6764 BFD_RELOC_TILEGX_TLS_IE_LOAD
6766 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
6768 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
6770 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
6772 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
6774 Tilera TILE-Gx Relocations.
6776 BFD_RELOC_EPIPHANY_SIMM8
6778 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
6780 BFD_RELOC_EPIPHANY_SIMM24
6782 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
6784 BFD_RELOC_EPIPHANY_HIGH
6786 Adapteva EPIPHANY - 16 most-significant bits of absolute address
6788 BFD_RELOC_EPIPHANY_LOW
6790 Adapteva EPIPHANY - 16 least-significant bits of absolute address
6792 BFD_RELOC_EPIPHANY_SIMM11
6794 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
6796 BFD_RELOC_EPIPHANY_IMM11
6798 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
6800 BFD_RELOC_EPIPHANY_IMM8
6802 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
6809 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
6814 bfd_reloc_type_lookup
6815 bfd_reloc_name_lookup
6818 reloc_howto_type *bfd_reloc_type_lookup
6819 (bfd *abfd, bfd_reloc_code_real_type code);
6820 reloc_howto_type *bfd_reloc_name_lookup
6821 (bfd *abfd, const char *reloc_name);
6824 Return a pointer to a howto structure which, when
6825 invoked, will perform the relocation @var{code} on data from the
6831 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
6833 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
6837 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
6839 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
6842 static reloc_howto_type bfd_howto_32 =
6843 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
6847 bfd_default_reloc_type_lookup
6850 reloc_howto_type *bfd_default_reloc_type_lookup
6851 (bfd *abfd, bfd_reloc_code_real_type code);
6854 Provides a default relocation lookup routine for any architecture.
6859 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
6863 case BFD_RELOC_CTOR:
6864 /* The type of reloc used in a ctor, which will be as wide as the
6865 address - so either a 64, 32, or 16 bitter. */
6866 switch (bfd_arch_bits_per_address (abfd))
6871 return &bfd_howto_32;
6885 bfd_get_reloc_code_name
6888 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
6891 Provides a printable name for the supplied relocation code.
6892 Useful mainly for printing error messages.
6896 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
6898 if (code > BFD_RELOC_UNUSED)
6900 return bfd_reloc_code_real_names[code];
6905 bfd_generic_relax_section
6908 bfd_boolean bfd_generic_relax_section
6911 struct bfd_link_info *,
6915 Provides default handling for relaxing for back ends which
6920 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
6921 asection *section ATTRIBUTE_UNUSED,
6922 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
6925 if (link_info->relocatable)
6926 (*link_info->callbacks->einfo)
6927 (_("%P%F: --relax and -r may not be used together\n"));
6935 bfd_generic_gc_sections
6938 bfd_boolean bfd_generic_gc_sections
6939 (bfd *, struct bfd_link_info *);
6942 Provides default handling for relaxing for back ends which
6943 don't do section gc -- i.e., does nothing.
6947 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
6948 struct bfd_link_info *info ATTRIBUTE_UNUSED)
6955 bfd_generic_lookup_section_flags
6958 bfd_boolean bfd_generic_lookup_section_flags
6959 (struct bfd_link_info *, struct flag_info *, asection *);
6962 Provides default handling for section flags lookup
6963 -- i.e., does nothing.
6964 Returns FALSE if the section should be omitted, otherwise TRUE.
6968 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
6969 struct flag_info *flaginfo,
6970 asection *section ATTRIBUTE_UNUSED)
6972 if (flaginfo != NULL)
6974 (*_bfd_error_handler) (_("INPUT_SECTION_FLAGS are not supported.\n"));
6982 bfd_generic_merge_sections
6985 bfd_boolean bfd_generic_merge_sections
6986 (bfd *, struct bfd_link_info *);
6989 Provides default handling for SEC_MERGE section merging for back ends
6990 which don't have SEC_MERGE support -- i.e., does nothing.
6994 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
6995 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
7002 bfd_generic_get_relocated_section_contents
7005 bfd_byte *bfd_generic_get_relocated_section_contents
7007 struct bfd_link_info *link_info,
7008 struct bfd_link_order *link_order,
7010 bfd_boolean relocatable,
7014 Provides default handling of relocation effort for back ends
7015 which can't be bothered to do it efficiently.
7020 bfd_generic_get_relocated_section_contents (bfd *abfd,
7021 struct bfd_link_info *link_info,
7022 struct bfd_link_order *link_order,
7024 bfd_boolean relocatable,
7027 bfd *input_bfd = link_order->u.indirect.section->owner;
7028 asection *input_section = link_order->u.indirect.section;
7030 arelent **reloc_vector;
7033 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
7037 /* Read in the section. */
7038 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
7041 if (reloc_size == 0)
7044 reloc_vector = (arelent **) bfd_malloc (reloc_size);
7045 if (reloc_vector == NULL)
7048 reloc_count = bfd_canonicalize_reloc (input_bfd,
7052 if (reloc_count < 0)
7055 if (reloc_count > 0)
7058 for (parent = reloc_vector; *parent != NULL; parent++)
7060 char *error_message = NULL;
7062 bfd_reloc_status_type r;
7064 symbol = *(*parent)->sym_ptr_ptr;
7065 if (symbol->section && discarded_section (symbol->section))
7068 static reloc_howto_type none_howto
7069 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
7070 "unused", FALSE, 0, 0, FALSE);
7072 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
7073 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
7075 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
7076 (*parent)->addend = 0;
7077 (*parent)->howto = &none_howto;
7081 r = bfd_perform_relocation (input_bfd,
7085 relocatable ? abfd : NULL,
7090 asection *os = input_section->output_section;
7092 /* A partial link, so keep the relocs. */
7093 os->orelocation[os->reloc_count] = *parent;
7097 if (r != bfd_reloc_ok)
7101 case bfd_reloc_undefined:
7102 if (!((*link_info->callbacks->undefined_symbol)
7103 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
7104 input_bfd, input_section, (*parent)->address,
7108 case bfd_reloc_dangerous:
7109 BFD_ASSERT (error_message != NULL);
7110 if (!((*link_info->callbacks->reloc_dangerous)
7111 (link_info, error_message, input_bfd, input_section,
7112 (*parent)->address)))
7115 case bfd_reloc_overflow:
7116 if (!((*link_info->callbacks->reloc_overflow)
7118 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
7119 (*parent)->howto->name, (*parent)->addend,
7120 input_bfd, input_section, (*parent)->address)))
7123 case bfd_reloc_outofrange:
7125 This error can result when processing some partially
7126 complete binaries. Do not abort, but issue an error
7128 link_info->callbacks->einfo
7129 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
7130 abfd, input_section, * parent);
7142 free (reloc_vector);
7146 free (reloc_vector);