1 /* BFD support for handling relocation entries.
2 Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
6 Written by Cygnus Support.
8 This file is part of BFD, the Binary File Descriptor library.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
29 BFD maintains relocations in much the same way it maintains
30 symbols: they are left alone until required, then read in
31 en-masse and translated into an internal form. A common
32 routine <<bfd_perform_relocation>> acts upon the
33 canonical form to do the fixup.
35 Relocations are maintained on a per section basis,
36 while symbols are maintained on a per BFD basis.
38 All that a back end has to do to fit the BFD interface is to create
39 a <<struct reloc_cache_entry>> for each relocation
40 in a particular section, and fill in the right bits of the structures.
49 /* DO compile in the reloc_code name table from libbfd.h. */
50 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
59 typedef arelent, howto manager, Relocations, Relocations
64 This is the structure of a relocation entry:
68 .typedef enum bfd_reloc_status
70 . {* No errors detected. *}
73 . {* The relocation was performed, but there was an overflow. *}
76 . {* The address to relocate was not within the section supplied. *}
77 . bfd_reloc_outofrange,
79 . {* Used by special functions. *}
82 . {* Unsupported relocation size requested. *}
83 . bfd_reloc_notsupported,
88 . {* The symbol to relocate against was undefined. *}
89 . bfd_reloc_undefined,
91 . {* The relocation was performed, but may not be ok - presently
92 . generated only when linking i960 coff files with i960 b.out
93 . symbols. If this type is returned, the error_message argument
94 . to bfd_perform_relocation will be set. *}
97 . bfd_reloc_status_type;
100 .typedef struct reloc_cache_entry
102 . {* A pointer into the canonical table of pointers. *}
103 . struct bfd_symbol **sym_ptr_ptr;
105 . {* offset in section. *}
106 . bfd_size_type address;
108 . {* addend for relocation value. *}
111 . {* Pointer to how to perform the required relocation. *}
112 . reloc_howto_type *howto;
122 Here is a description of each of the fields within an <<arelent>>:
126 The symbol table pointer points to a pointer to the symbol
127 associated with the relocation request. It is the pointer
128 into the table returned by the back end's
129 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
130 referenced through a pointer to a pointer so that tools like
131 the linker can fix up all the symbols of the same name by
132 modifying only one pointer. The relocation routine looks in
133 the symbol and uses the base of the section the symbol is
134 attached to and the value of the symbol as the initial
135 relocation offset. If the symbol pointer is zero, then the
136 section provided is looked up.
140 The <<address>> field gives the offset in bytes from the base of
141 the section data which owns the relocation record to the first
142 byte of relocatable information. The actual data relocated
143 will be relative to this point; for example, a relocation
144 type which modifies the bottom two bytes of a four byte word
145 would not touch the first byte pointed to in a big endian
150 The <<addend>> is a value provided by the back end to be added (!)
151 to the relocation offset. Its interpretation is dependent upon
152 the howto. For example, on the 68k the code:
157 | return foo[0x12345678];
160 Could be compiled into:
163 | moveb @@#12345678,d0
168 This could create a reloc pointing to <<foo>>, but leave the
169 offset in the data, something like:
171 |RELOCATION RECORDS FOR [.text]:
175 |00000000 4e56 fffc ; linkw fp,#-4
176 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
177 |0000000a 49c0 ; extbl d0
178 |0000000c 4e5e ; unlk fp
181 Using coff and an 88k, some instructions don't have enough
182 space in them to represent the full address range, and
183 pointers have to be loaded in two parts. So you'd get something like:
185 | or.u r13,r0,hi16(_foo+0x12345678)
186 | ld.b r2,r13,lo16(_foo+0x12345678)
189 This should create two relocs, both pointing to <<_foo>>, and with
190 0x12340000 in their addend field. The data would consist of:
192 |RELOCATION RECORDS FOR [.text]:
194 |00000002 HVRT16 _foo+0x12340000
195 |00000006 LVRT16 _foo+0x12340000
197 |00000000 5da05678 ; or.u r13,r0,0x5678
198 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
199 |00000008 f400c001 ; jmp r1
201 The relocation routine digs out the value from the data, adds
202 it to the addend to get the original offset, and then adds the
203 value of <<_foo>>. Note that all 32 bits have to be kept around
204 somewhere, to cope with carry from bit 15 to bit 16.
206 One further example is the sparc and the a.out format. The
207 sparc has a similar problem to the 88k, in that some
208 instructions don't have room for an entire offset, but on the
209 sparc the parts are created in odd sized lumps. The designers of
210 the a.out format chose to not use the data within the section
211 for storing part of the offset; all the offset is kept within
212 the reloc. Anything in the data should be ignored.
215 | sethi %hi(_foo+0x12345678),%g2
216 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
220 Both relocs contain a pointer to <<foo>>, and the offsets
223 |RELOCATION RECORDS FOR [.text]:
225 |00000004 HI22 _foo+0x12345678
226 |00000008 LO10 _foo+0x12345678
228 |00000000 9de3bf90 ; save %sp,-112,%sp
229 |00000004 05000000 ; sethi %hi(_foo+0),%g2
230 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
231 |0000000c 81c7e008 ; ret
232 |00000010 81e80000 ; restore
236 The <<howto>> field can be imagined as a
237 relocation instruction. It is a pointer to a structure which
238 contains information on what to do with all of the other
239 information in the reloc record and data section. A back end
240 would normally have a relocation instruction set and turn
241 relocations into pointers to the correct structure on input -
242 but it would be possible to create each howto field on demand.
248 <<enum complain_overflow>>
250 Indicates what sort of overflow checking should be done when
251 performing a relocation.
255 .enum complain_overflow
257 . {* Do not complain on overflow. *}
258 . complain_overflow_dont,
260 . {* Complain if the value overflows when considered as a signed
261 . number one bit larger than the field. ie. A bitfield of N bits
262 . is allowed to represent -2**n to 2**n-1. *}
263 . complain_overflow_bitfield,
265 . {* Complain if the value overflows when considered as a signed
267 . complain_overflow_signed,
269 . {* Complain if the value overflows when considered as an
270 . unsigned number. *}
271 . complain_overflow_unsigned
280 The <<reloc_howto_type>> is a structure which contains all the
281 information that libbfd needs to know to tie up a back end's data.
284 .struct bfd_symbol; {* Forward declaration. *}
286 .struct reloc_howto_struct
288 . {* The type field has mainly a documentary use - the back end can
289 . do what it wants with it, though normally the back end's
290 . external idea of what a reloc number is stored
291 . in this field. For example, a PC relative word relocation
292 . in a coff environment has the type 023 - because that's
293 . what the outside world calls a R_PCRWORD reloc. *}
296 . {* The value the final relocation is shifted right by. This drops
297 . unwanted data from the relocation. *}
298 . unsigned int rightshift;
300 . {* The size of the item to be relocated. This is *not* a
301 . power-of-two measure. To get the number of bytes operated
302 . on by a type of relocation, use bfd_get_reloc_size. *}
305 . {* The number of bits in the item to be relocated. This is used
306 . when doing overflow checking. *}
307 . unsigned int bitsize;
309 . {* The relocation is relative to the field being relocated. *}
310 . bfd_boolean pc_relative;
312 . {* The bit position of the reloc value in the destination.
313 . The relocated value is left shifted by this amount. *}
314 . unsigned int bitpos;
316 . {* What type of overflow error should be checked for when
318 . enum complain_overflow complain_on_overflow;
320 . {* If this field is non null, then the supplied function is
321 . called rather than the normal function. This allows really
322 . strange relocation methods to be accommodated (e.g., i960 callj
324 . bfd_reloc_status_type (*special_function)
325 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
328 . {* The textual name of the relocation type. *}
331 . {* Some formats record a relocation addend in the section contents
332 . rather than with the relocation. For ELF formats this is the
333 . distinction between USE_REL and USE_RELA (though the code checks
334 . for USE_REL == 1/0). The value of this field is TRUE if the
335 . addend is recorded with the section contents; when performing a
336 . partial link (ld -r) the section contents (the data) will be
337 . modified. The value of this field is FALSE if addends are
338 . recorded with the relocation (in arelent.addend); when performing
339 . a partial link the relocation will be modified.
340 . All relocations for all ELF USE_RELA targets should set this field
341 . to FALSE (values of TRUE should be looked on with suspicion).
342 . However, the converse is not true: not all relocations of all ELF
343 . USE_REL targets set this field to TRUE. Why this is so is peculiar
344 . to each particular target. For relocs that aren't used in partial
345 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
346 . bfd_boolean partial_inplace;
348 . {* src_mask selects the part of the instruction (or data) to be used
349 . in the relocation sum. If the target relocations don't have an
350 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
351 . dst_mask to extract the addend from the section contents. If
352 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
353 . field should be zero. Non-zero values for ELF USE_RELA targets are
354 . bogus as in those cases the value in the dst_mask part of the
355 . section contents should be treated as garbage. *}
358 . {* dst_mask selects which parts of the instruction (or data) are
359 . replaced with a relocated value. *}
362 . {* When some formats create PC relative instructions, they leave
363 . the value of the pc of the place being relocated in the offset
364 . slot of the instruction, so that a PC relative relocation can
365 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
366 . Some formats leave the displacement part of an instruction
367 . empty (e.g., m88k bcs); this flag signals the fact. *}
368 . bfd_boolean pcrel_offset;
378 The HOWTO define is horrible and will go away.
380 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
381 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
384 And will be replaced with the totally magic way. But for the
385 moment, we are compatible, so do it this way.
387 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
388 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
389 . NAME, FALSE, 0, 0, IN)
393 This is used to fill in an empty howto entry in an array.
395 .#define EMPTY_HOWTO(C) \
396 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
397 . NULL, FALSE, 0, 0, FALSE)
401 Helper routine to turn a symbol into a relocation value.
403 .#define HOWTO_PREPARE(relocation, symbol) \
405 . if (symbol != NULL) \
407 . if (bfd_is_com_section (symbol->section)) \
413 . relocation = symbol->value; \
425 unsigned int bfd_get_reloc_size (reloc_howto_type *);
428 For a reloc_howto_type that operates on a fixed number of bytes,
429 this returns the number of bytes operated on.
433 bfd_get_reloc_size (reloc_howto_type *howto)
454 How relocs are tied together in an <<asection>>:
456 .typedef struct relent_chain
459 . struct relent_chain *next;
465 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
466 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
473 bfd_reloc_status_type bfd_check_overflow
474 (enum complain_overflow how,
475 unsigned int bitsize,
476 unsigned int rightshift,
477 unsigned int addrsize,
481 Perform overflow checking on @var{relocation} which has
482 @var{bitsize} significant bits and will be shifted right by
483 @var{rightshift} bits, on a machine with addresses containing
484 @var{addrsize} significant bits. The result is either of
485 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
489 bfd_reloc_status_type
490 bfd_check_overflow (enum complain_overflow how,
491 unsigned int bitsize,
492 unsigned int rightshift,
493 unsigned int addrsize,
496 bfd_vma fieldmask, addrmask, signmask, ss, a;
497 bfd_reloc_status_type flag = bfd_reloc_ok;
499 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
500 we'll be permissive: extra bits in the field mask will
501 automatically extend the address mask for purposes of the
503 fieldmask = N_ONES (bitsize);
504 signmask = ~fieldmask;
505 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
506 a = (relocation & addrmask) >> rightshift;;
510 case complain_overflow_dont:
513 case complain_overflow_signed:
514 /* If any sign bits are set, all sign bits must be set. That
515 is, A must be a valid negative address after shifting. */
516 signmask = ~ (fieldmask >> 1);
519 case complain_overflow_bitfield:
520 /* Bitfields are sometimes signed, sometimes unsigned. We
521 explicitly allow an address wrap too, which means a bitfield
522 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
523 if the value has some, but not all, bits set outside the
526 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
527 flag = bfd_reloc_overflow;
530 case complain_overflow_unsigned:
531 /* We have an overflow if the address does not fit in the field. */
532 if ((a & signmask) != 0)
533 flag = bfd_reloc_overflow;
545 bfd_perform_relocation
548 bfd_reloc_status_type bfd_perform_relocation
550 arelent *reloc_entry,
552 asection *input_section,
554 char **error_message);
557 If @var{output_bfd} is supplied to this function, the
558 generated image will be relocatable; the relocations are
559 copied to the output file after they have been changed to
560 reflect the new state of the world. There are two ways of
561 reflecting the results of partial linkage in an output file:
562 by modifying the output data in place, and by modifying the
563 relocation record. Some native formats (e.g., basic a.out and
564 basic coff) have no way of specifying an addend in the
565 relocation type, so the addend has to go in the output data.
566 This is no big deal since in these formats the output data
567 slot will always be big enough for the addend. Complex reloc
568 types with addends were invented to solve just this problem.
569 The @var{error_message} argument is set to an error message if
570 this return @code{bfd_reloc_dangerous}.
574 bfd_reloc_status_type
575 bfd_perform_relocation (bfd *abfd,
576 arelent *reloc_entry,
578 asection *input_section,
580 char **error_message)
583 bfd_reloc_status_type flag = bfd_reloc_ok;
584 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
585 bfd_vma output_base = 0;
586 reloc_howto_type *howto = reloc_entry->howto;
587 asection *reloc_target_output_section;
590 symbol = *(reloc_entry->sym_ptr_ptr);
591 if (bfd_is_abs_section (symbol->section)
592 && output_bfd != NULL)
594 reloc_entry->address += input_section->output_offset;
598 /* If we are not producing relocatable output, return an error if
599 the symbol is not defined. An undefined weak symbol is
600 considered to have a value of zero (SVR4 ABI, p. 4-27). */
601 if (bfd_is_und_section (symbol->section)
602 && (symbol->flags & BSF_WEAK) == 0
603 && output_bfd == NULL)
604 flag = bfd_reloc_undefined;
606 /* If there is a function supplied to handle this relocation type,
607 call it. It'll return `bfd_reloc_continue' if further processing
609 if (howto->special_function)
611 bfd_reloc_status_type cont;
612 cont = howto->special_function (abfd, reloc_entry, symbol, data,
613 input_section, output_bfd,
615 if (cont != bfd_reloc_continue)
619 /* Is the address of the relocation really within the section? */
620 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
621 return bfd_reloc_outofrange;
623 /* Work out which section the relocation is targeted at and the
624 initial relocation command value. */
626 /* Get symbol value. (Common symbols are special.) */
627 if (bfd_is_com_section (symbol->section))
630 relocation = symbol->value;
632 reloc_target_output_section = symbol->section->output_section;
634 /* Convert input-section-relative symbol value to absolute. */
635 if ((output_bfd && ! howto->partial_inplace)
636 || reloc_target_output_section == NULL)
639 output_base = reloc_target_output_section->vma;
641 relocation += output_base + symbol->section->output_offset;
643 /* Add in supplied addend. */
644 relocation += reloc_entry->addend;
646 /* Here the variable relocation holds the final address of the
647 symbol we are relocating against, plus any addend. */
649 if (howto->pc_relative)
651 /* This is a PC relative relocation. We want to set RELOCATION
652 to the distance between the address of the symbol and the
653 location. RELOCATION is already the address of the symbol.
655 We start by subtracting the address of the section containing
658 If pcrel_offset is set, we must further subtract the position
659 of the location within the section. Some targets arrange for
660 the addend to be the negative of the position of the location
661 within the section; for example, i386-aout does this. For
662 i386-aout, pcrel_offset is FALSE. Some other targets do not
663 include the position of the location; for example, m88kbcs,
664 or ELF. For those targets, pcrel_offset is TRUE.
666 If we are producing relocatable output, then we must ensure
667 that this reloc will be correctly computed when the final
668 relocation is done. If pcrel_offset is FALSE we want to wind
669 up with the negative of the location within the section,
670 which means we must adjust the existing addend by the change
671 in the location within the section. If pcrel_offset is TRUE
672 we do not want to adjust the existing addend at all.
674 FIXME: This seems logical to me, but for the case of
675 producing relocatable output it is not what the code
676 actually does. I don't want to change it, because it seems
677 far too likely that something will break. */
680 input_section->output_section->vma + input_section->output_offset;
682 if (howto->pcrel_offset)
683 relocation -= reloc_entry->address;
686 if (output_bfd != NULL)
688 if (! howto->partial_inplace)
690 /* This is a partial relocation, and we want to apply the relocation
691 to the reloc entry rather than the raw data. Modify the reloc
692 inplace to reflect what we now know. */
693 reloc_entry->addend = relocation;
694 reloc_entry->address += input_section->output_offset;
699 /* This is a partial relocation, but inplace, so modify the
702 If we've relocated with a symbol with a section, change
703 into a ref to the section belonging to the symbol. */
705 reloc_entry->address += input_section->output_offset;
708 if (abfd->xvec->flavour == bfd_target_coff_flavour
709 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
710 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
712 /* For m68k-coff, the addend was being subtracted twice during
713 relocation with -r. Removing the line below this comment
714 fixes that problem; see PR 2953.
716 However, Ian wrote the following, regarding removing the line below,
717 which explains why it is still enabled: --djm
719 If you put a patch like that into BFD you need to check all the COFF
720 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
721 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
722 problem in a different way. There may very well be a reason that the
723 code works as it does.
725 Hmmm. The first obvious point is that bfd_perform_relocation should
726 not have any tests that depend upon the flavour. It's seem like
727 entirely the wrong place for such a thing. The second obvious point
728 is that the current code ignores the reloc addend when producing
729 relocatable output for COFF. That's peculiar. In fact, I really
730 have no idea what the point of the line you want to remove is.
732 A typical COFF reloc subtracts the old value of the symbol and adds in
733 the new value to the location in the object file (if it's a pc
734 relative reloc it adds the difference between the symbol value and the
735 location). When relocating we need to preserve that property.
737 BFD handles this by setting the addend to the negative of the old
738 value of the symbol. Unfortunately it handles common symbols in a
739 non-standard way (it doesn't subtract the old value) but that's a
740 different story (we can't change it without losing backward
741 compatibility with old object files) (coff-i386 does subtract the old
742 value, to be compatible with existing coff-i386 targets, like SCO).
744 So everything works fine when not producing relocatable output. When
745 we are producing relocatable output, logically we should do exactly
746 what we do when not producing relocatable output. Therefore, your
747 patch is correct. In fact, it should probably always just set
748 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
749 add the value into the object file. This won't hurt the COFF code,
750 which doesn't use the addend; I'm not sure what it will do to other
751 formats (the thing to check for would be whether any formats both use
752 the addend and set partial_inplace).
754 When I wanted to make coff-i386 produce relocatable output, I ran
755 into the problem that you are running into: I wanted to remove that
756 line. Rather than risk it, I made the coff-i386 relocs use a special
757 function; it's coff_i386_reloc in coff-i386.c. The function
758 specifically adds the addend field into the object file, knowing that
759 bfd_perform_relocation is not going to. If you remove that line, then
760 coff-i386.c will wind up adding the addend field in twice. It's
761 trivial to fix; it just needs to be done.
763 The problem with removing the line is just that it may break some
764 working code. With BFD it's hard to be sure of anything. The right
765 way to deal with this is simply to build and test at least all the
766 supported COFF targets. It should be straightforward if time and disk
767 space consuming. For each target:
769 2) generate some executable, and link it using -r (I would
770 probably use paranoia.o and link against newlib/libc.a, which
771 for all the supported targets would be available in
772 /usr/cygnus/progressive/H-host/target/lib/libc.a).
773 3) make the change to reloc.c
774 4) rebuild the linker
776 6) if the resulting object files are the same, you have at least
778 7) if they are different you have to figure out which version is
781 relocation -= reloc_entry->addend;
782 reloc_entry->addend = 0;
786 reloc_entry->addend = relocation;
792 reloc_entry->addend = 0;
795 /* FIXME: This overflow checking is incomplete, because the value
796 might have overflowed before we get here. For a correct check we
797 need to compute the value in a size larger than bitsize, but we
798 can't reasonably do that for a reloc the same size as a host
800 FIXME: We should also do overflow checking on the result after
801 adding in the value contained in the object file. */
802 if (howto->complain_on_overflow != complain_overflow_dont
803 && flag == bfd_reloc_ok)
804 flag = bfd_check_overflow (howto->complain_on_overflow,
807 bfd_arch_bits_per_address (abfd),
810 /* Either we are relocating all the way, or we don't want to apply
811 the relocation to the reloc entry (probably because there isn't
812 any room in the output format to describe addends to relocs). */
814 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
815 (OSF version 1.3, compiler version 3.11). It miscompiles the
829 x <<= (unsigned long) s.i0;
833 printf ("succeeded (%lx)\n", x);
837 relocation >>= (bfd_vma) howto->rightshift;
839 /* Shift everything up to where it's going to be used. */
840 relocation <<= (bfd_vma) howto->bitpos;
842 /* Wait for the day when all have the mask in them. */
845 i instruction to be left alone
846 o offset within instruction
847 r relocation offset to apply
856 (( i i i i i o o o o o from bfd_get<size>
857 and S S S S S) to get the size offset we want
858 + r r r r r r r r r r) to get the final value to place
859 and D D D D D to chop to right size
860 -----------------------
863 ( i i i i i o o o o o from bfd_get<size>
864 and N N N N N ) get instruction
865 -----------------------
871 -----------------------
872 = R R R R R R R R R R put into bfd_put<size>
876 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
882 char x = bfd_get_8 (abfd, (char *) data + octets);
884 bfd_put_8 (abfd, x, (unsigned char *) data + octets);
890 short x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
892 bfd_put_16 (abfd, (bfd_vma) x, (unsigned char *) data + octets);
897 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
899 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
904 long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
905 relocation = -relocation;
907 bfd_put_32 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
913 long x = bfd_get_16 (abfd, (bfd_byte *) data + octets);
914 relocation = -relocation;
916 bfd_put_16 (abfd, (bfd_vma) x, (bfd_byte *) data + octets);
927 bfd_vma x = bfd_get_64 (abfd, (bfd_byte *) data + octets);
929 bfd_put_64 (abfd, x, (bfd_byte *) data + octets);
936 return bfd_reloc_other;
944 bfd_install_relocation
947 bfd_reloc_status_type bfd_install_relocation
949 arelent *reloc_entry,
950 void *data, bfd_vma data_start,
951 asection *input_section,
952 char **error_message);
955 This looks remarkably like <<bfd_perform_relocation>>, except it
956 does not expect that the section contents have been filled in.
957 I.e., it's suitable for use when creating, rather than applying
960 For now, this function should be considered reserved for the
964 bfd_reloc_status_type
965 bfd_install_relocation (bfd *abfd,
966 arelent *reloc_entry,
968 bfd_vma data_start_offset,
969 asection *input_section,
970 char **error_message)
973 bfd_reloc_status_type flag = bfd_reloc_ok;
974 bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte (abfd);
975 bfd_vma output_base = 0;
976 reloc_howto_type *howto = reloc_entry->howto;
977 asection *reloc_target_output_section;
981 symbol = *(reloc_entry->sym_ptr_ptr);
982 if (bfd_is_abs_section (symbol->section))
984 reloc_entry->address += input_section->output_offset;
988 /* If there is a function supplied to handle this relocation type,
989 call it. It'll return `bfd_reloc_continue' if further processing
991 if (howto->special_function)
993 bfd_reloc_status_type cont;
995 /* XXX - The special_function calls haven't been fixed up to deal
996 with creating new relocations and section contents. */
997 cont = howto->special_function (abfd, reloc_entry, symbol,
998 /* XXX - Non-portable! */
999 ((bfd_byte *) data_start
1000 - data_start_offset),
1001 input_section, abfd, error_message);
1002 if (cont != bfd_reloc_continue)
1006 /* Is the address of the relocation really within the section? */
1007 if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
1008 return bfd_reloc_outofrange;
1010 /* Work out which section the relocation is targeted at and the
1011 initial relocation command value. */
1013 /* Get symbol value. (Common symbols are special.) */
1014 if (bfd_is_com_section (symbol->section))
1017 relocation = symbol->value;
1019 reloc_target_output_section = symbol->section->output_section;
1021 /* Convert input-section-relative symbol value to absolute. */
1022 if (! howto->partial_inplace)
1025 output_base = reloc_target_output_section->vma;
1027 relocation += output_base + symbol->section->output_offset;
1029 /* Add in supplied addend. */
1030 relocation += reloc_entry->addend;
1032 /* Here the variable relocation holds the final address of the
1033 symbol we are relocating against, plus any addend. */
1035 if (howto->pc_relative)
1037 /* This is a PC relative relocation. We want to set RELOCATION
1038 to the distance between the address of the symbol and the
1039 location. RELOCATION is already the address of the symbol.
1041 We start by subtracting the address of the section containing
1044 If pcrel_offset is set, we must further subtract the position
1045 of the location within the section. Some targets arrange for
1046 the addend to be the negative of the position of the location
1047 within the section; for example, i386-aout does this. For
1048 i386-aout, pcrel_offset is FALSE. Some other targets do not
1049 include the position of the location; for example, m88kbcs,
1050 or ELF. For those targets, pcrel_offset is TRUE.
1052 If we are producing relocatable output, then we must ensure
1053 that this reloc will be correctly computed when the final
1054 relocation is done. If pcrel_offset is FALSE we want to wind
1055 up with the negative of the location within the section,
1056 which means we must adjust the existing addend by the change
1057 in the location within the section. If pcrel_offset is TRUE
1058 we do not want to adjust the existing addend at all.
1060 FIXME: This seems logical to me, but for the case of
1061 producing relocatable output it is not what the code
1062 actually does. I don't want to change it, because it seems
1063 far too likely that something will break. */
1066 input_section->output_section->vma + input_section->output_offset;
1068 if (howto->pcrel_offset && howto->partial_inplace)
1069 relocation -= reloc_entry->address;
1072 if (! howto->partial_inplace)
1074 /* This is a partial relocation, and we want to apply the relocation
1075 to the reloc entry rather than the raw data. Modify the reloc
1076 inplace to reflect what we now know. */
1077 reloc_entry->addend = relocation;
1078 reloc_entry->address += input_section->output_offset;
1083 /* This is a partial relocation, but inplace, so modify the
1086 If we've relocated with a symbol with a section, change
1087 into a ref to the section belonging to the symbol. */
1088 reloc_entry->address += input_section->output_offset;
1091 if (abfd->xvec->flavour == bfd_target_coff_flavour
1092 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1093 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1096 /* For m68k-coff, the addend was being subtracted twice during
1097 relocation with -r. Removing the line below this comment
1098 fixes that problem; see PR 2953.
1100 However, Ian wrote the following, regarding removing the line below,
1101 which explains why it is still enabled: --djm
1103 If you put a patch like that into BFD you need to check all the COFF
1104 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1105 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1106 problem in a different way. There may very well be a reason that the
1107 code works as it does.
1109 Hmmm. The first obvious point is that bfd_install_relocation should
1110 not have any tests that depend upon the flavour. It's seem like
1111 entirely the wrong place for such a thing. The second obvious point
1112 is that the current code ignores the reloc addend when producing
1113 relocatable output for COFF. That's peculiar. In fact, I really
1114 have no idea what the point of the line you want to remove is.
1116 A typical COFF reloc subtracts the old value of the symbol and adds in
1117 the new value to the location in the object file (if it's a pc
1118 relative reloc it adds the difference between the symbol value and the
1119 location). When relocating we need to preserve that property.
1121 BFD handles this by setting the addend to the negative of the old
1122 value of the symbol. Unfortunately it handles common symbols in a
1123 non-standard way (it doesn't subtract the old value) but that's a
1124 different story (we can't change it without losing backward
1125 compatibility with old object files) (coff-i386 does subtract the old
1126 value, to be compatible with existing coff-i386 targets, like SCO).
1128 So everything works fine when not producing relocatable output. When
1129 we are producing relocatable output, logically we should do exactly
1130 what we do when not producing relocatable output. Therefore, your
1131 patch is correct. In fact, it should probably always just set
1132 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1133 add the value into the object file. This won't hurt the COFF code,
1134 which doesn't use the addend; I'm not sure what it will do to other
1135 formats (the thing to check for would be whether any formats both use
1136 the addend and set partial_inplace).
1138 When I wanted to make coff-i386 produce relocatable output, I ran
1139 into the problem that you are running into: I wanted to remove that
1140 line. Rather than risk it, I made the coff-i386 relocs use a special
1141 function; it's coff_i386_reloc in coff-i386.c. The function
1142 specifically adds the addend field into the object file, knowing that
1143 bfd_install_relocation is not going to. If you remove that line, then
1144 coff-i386.c will wind up adding the addend field in twice. It's
1145 trivial to fix; it just needs to be done.
1147 The problem with removing the line is just that it may break some
1148 working code. With BFD it's hard to be sure of anything. The right
1149 way to deal with this is simply to build and test at least all the
1150 supported COFF targets. It should be straightforward if time and disk
1151 space consuming. For each target:
1153 2) generate some executable, and link it using -r (I would
1154 probably use paranoia.o and link against newlib/libc.a, which
1155 for all the supported targets would be available in
1156 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1157 3) make the change to reloc.c
1158 4) rebuild the linker
1160 6) if the resulting object files are the same, you have at least
1162 7) if they are different you have to figure out which version is
1164 relocation -= reloc_entry->addend;
1165 /* FIXME: There should be no target specific code here... */
1166 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1167 reloc_entry->addend = 0;
1171 reloc_entry->addend = relocation;
1175 /* FIXME: This overflow checking is incomplete, because the value
1176 might have overflowed before we get here. For a correct check we
1177 need to compute the value in a size larger than bitsize, but we
1178 can't reasonably do that for a reloc the same size as a host
1180 FIXME: We should also do overflow checking on the result after
1181 adding in the value contained in the object file. */
1182 if (howto->complain_on_overflow != complain_overflow_dont)
1183 flag = bfd_check_overflow (howto->complain_on_overflow,
1186 bfd_arch_bits_per_address (abfd),
1189 /* Either we are relocating all the way, or we don't want to apply
1190 the relocation to the reloc entry (probably because there isn't
1191 any room in the output format to describe addends to relocs). */
1193 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1194 (OSF version 1.3, compiler version 3.11). It miscompiles the
1208 x <<= (unsigned long) s.i0;
1210 printf ("failed\n");
1212 printf ("succeeded (%lx)\n", x);
1216 relocation >>= (bfd_vma) howto->rightshift;
1218 /* Shift everything up to where it's going to be used. */
1219 relocation <<= (bfd_vma) howto->bitpos;
1221 /* Wait for the day when all have the mask in them. */
1224 i instruction to be left alone
1225 o offset within instruction
1226 r relocation offset to apply
1235 (( i i i i i o o o o o from bfd_get<size>
1236 and S S S S S) to get the size offset we want
1237 + r r r r r r r r r r) to get the final value to place
1238 and D D D D D to chop to right size
1239 -----------------------
1242 ( i i i i i o o o o o from bfd_get<size>
1243 and N N N N N ) get instruction
1244 -----------------------
1250 -----------------------
1251 = R R R R R R R R R R put into bfd_put<size>
1255 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1257 data = (bfd_byte *) data_start + (octets - data_start_offset);
1259 switch (howto->size)
1263 char x = bfd_get_8 (abfd, data);
1265 bfd_put_8 (abfd, x, data);
1271 short x = bfd_get_16 (abfd, data);
1273 bfd_put_16 (abfd, (bfd_vma) x, data);
1278 long x = bfd_get_32 (abfd, data);
1280 bfd_put_32 (abfd, (bfd_vma) x, data);
1285 long x = bfd_get_32 (abfd, data);
1286 relocation = -relocation;
1288 bfd_put_32 (abfd, (bfd_vma) x, data);
1298 bfd_vma x = bfd_get_64 (abfd, data);
1300 bfd_put_64 (abfd, x, data);
1304 return bfd_reloc_other;
1310 /* This relocation routine is used by some of the backend linkers.
1311 They do not construct asymbol or arelent structures, so there is no
1312 reason for them to use bfd_perform_relocation. Also,
1313 bfd_perform_relocation is so hacked up it is easier to write a new
1314 function than to try to deal with it.
1316 This routine does a final relocation. Whether it is useful for a
1317 relocatable link depends upon how the object format defines
1320 FIXME: This routine ignores any special_function in the HOWTO,
1321 since the existing special_function values have been written for
1322 bfd_perform_relocation.
1324 HOWTO is the reloc howto information.
1325 INPUT_BFD is the BFD which the reloc applies to.
1326 INPUT_SECTION is the section which the reloc applies to.
1327 CONTENTS is the contents of the section.
1328 ADDRESS is the address of the reloc within INPUT_SECTION.
1329 VALUE is the value of the symbol the reloc refers to.
1330 ADDEND is the addend of the reloc. */
1332 bfd_reloc_status_type
1333 _bfd_final_link_relocate (reloc_howto_type *howto,
1335 asection *input_section,
1343 /* Sanity check the address. */
1344 if (address > bfd_get_section_limit (input_bfd, input_section))
1345 return bfd_reloc_outofrange;
1347 /* This function assumes that we are dealing with a basic relocation
1348 against a symbol. We want to compute the value of the symbol to
1349 relocate to. This is just VALUE, the value of the symbol, plus
1350 ADDEND, any addend associated with the reloc. */
1351 relocation = value + addend;
1353 /* If the relocation is PC relative, we want to set RELOCATION to
1354 the distance between the symbol (currently in RELOCATION) and the
1355 location we are relocating. Some targets (e.g., i386-aout)
1356 arrange for the contents of the section to be the negative of the
1357 offset of the location within the section; for such targets
1358 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1359 simply leave the contents of the section as zero; for such
1360 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1361 need to subtract out the offset of the location within the
1362 section (which is just ADDRESS). */
1363 if (howto->pc_relative)
1365 relocation -= (input_section->output_section->vma
1366 + input_section->output_offset);
1367 if (howto->pcrel_offset)
1368 relocation -= address;
1371 return _bfd_relocate_contents (howto, input_bfd, relocation,
1372 contents + address);
1375 /* Relocate a given location using a given value and howto. */
1377 bfd_reloc_status_type
1378 _bfd_relocate_contents (reloc_howto_type *howto,
1385 bfd_reloc_status_type flag;
1386 unsigned int rightshift = howto->rightshift;
1387 unsigned int bitpos = howto->bitpos;
1389 /* If the size is negative, negate RELOCATION. This isn't very
1391 if (howto->size < 0)
1392 relocation = -relocation;
1394 /* Get the value we are going to relocate. */
1395 size = bfd_get_reloc_size (howto);
1402 x = bfd_get_8 (input_bfd, location);
1405 x = bfd_get_16 (input_bfd, location);
1408 x = bfd_get_32 (input_bfd, location);
1412 x = bfd_get_64 (input_bfd, location);
1419 /* Check for overflow. FIXME: We may drop bits during the addition
1420 which we don't check for. We must either check at every single
1421 operation, which would be tedious, or we must do the computations
1422 in a type larger than bfd_vma, which would be inefficient. */
1423 flag = bfd_reloc_ok;
1424 if (howto->complain_on_overflow != complain_overflow_dont)
1426 bfd_vma addrmask, fieldmask, signmask, ss;
1429 /* Get the values to be added together. For signed and unsigned
1430 relocations, we assume that all values should be truncated to
1431 the size of an address. For bitfields, all the bits matter.
1432 See also bfd_check_overflow. */
1433 fieldmask = N_ONES (howto->bitsize);
1434 signmask = ~fieldmask;
1435 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1436 | (fieldmask << rightshift));
1437 a = (relocation & addrmask) >> rightshift;
1438 b = (x & howto->src_mask & addrmask) >> bitpos;
1439 addrmask >>= rightshift;
1441 switch (howto->complain_on_overflow)
1443 case complain_overflow_signed:
1444 /* If any sign bits are set, all sign bits must be set.
1445 That is, A must be a valid negative address after
1447 signmask = ~(fieldmask >> 1);
1450 case complain_overflow_bitfield:
1451 /* Much like the signed check, but for a field one bit
1452 wider. We allow a bitfield to represent numbers in the
1453 range -2**n to 2**n-1, where n is the number of bits in the
1454 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1455 can't overflow, which is exactly what we want. */
1457 if (ss != 0 && ss != (addrmask & signmask))
1458 flag = bfd_reloc_overflow;
1460 /* We only need this next bit of code if the sign bit of B
1461 is below the sign bit of A. This would only happen if
1462 SRC_MASK had fewer bits than BITSIZE. Note that if
1463 SRC_MASK has more bits than BITSIZE, we can get into
1464 trouble; we would need to verify that B is in range, as
1465 we do for A above. */
1466 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1469 /* Set all the bits above the sign bit. */
1472 /* Now we can do the addition. */
1475 /* See if the result has the correct sign. Bits above the
1476 sign bit are junk now; ignore them. If the sum is
1477 positive, make sure we did not have all negative inputs;
1478 if the sum is negative, make sure we did not have all
1479 positive inputs. The test below looks only at the sign
1480 bits, and it really just
1481 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1483 We mask with addrmask here to explicitly allow an address
1484 wrap-around. The Linux kernel relies on it, and it is
1485 the only way to write assembler code which can run when
1486 loaded at a location 0x80000000 away from the location at
1487 which it is linked. */
1488 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1489 flag = bfd_reloc_overflow;
1492 case complain_overflow_unsigned:
1493 /* Checking for an unsigned overflow is relatively easy:
1494 trim the addresses and add, and trim the result as well.
1495 Overflow is normally indicated when the result does not
1496 fit in the field. However, we also need to consider the
1497 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1498 input is 0x80000000, and bfd_vma is only 32 bits; then we
1499 will get sum == 0, but there is an overflow, since the
1500 inputs did not fit in the field. Instead of doing a
1501 separate test, we can check for this by or-ing in the
1502 operands when testing for the sum overflowing its final
1504 sum = (a + b) & addrmask;
1505 if ((a | b | sum) & signmask)
1506 flag = bfd_reloc_overflow;
1514 /* Put RELOCATION in the right bits. */
1515 relocation >>= (bfd_vma) rightshift;
1516 relocation <<= (bfd_vma) bitpos;
1518 /* Add RELOCATION to the right bits of X. */
1519 x = ((x & ~howto->dst_mask)
1520 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1522 /* Put the relocated value back in the object file. */
1528 bfd_put_8 (input_bfd, x, location);
1531 bfd_put_16 (input_bfd, x, location);
1534 bfd_put_32 (input_bfd, x, location);
1538 bfd_put_64 (input_bfd, x, location);
1548 /* Clear a given location using a given howto, by applying a fixed relocation
1549 value and discarding any in-place addend. This is used for fixed-up
1550 relocations against discarded symbols, to make ignorable debug or unwind
1551 information more obvious. */
1554 _bfd_clear_contents (reloc_howto_type *howto,
1556 asection *input_section,
1562 /* Get the value we are going to relocate. */
1563 size = bfd_get_reloc_size (howto);
1570 x = bfd_get_8 (input_bfd, location);
1573 x = bfd_get_16 (input_bfd, location);
1576 x = bfd_get_32 (input_bfd, location);
1580 x = bfd_get_64 (input_bfd, location);
1587 /* Zero out the unwanted bits of X. */
1588 x &= ~howto->dst_mask;
1590 /* For a range list, use 1 instead of 0 as placeholder. 0
1591 would terminate the list, hiding any later entries. */
1592 if (strcmp (bfd_get_section_name (input_bfd, input_section),
1593 ".debug_ranges") == 0
1594 && (howto->dst_mask & 1) != 0)
1597 /* Put the relocated value back in the object file. */
1604 bfd_put_8 (input_bfd, x, location);
1607 bfd_put_16 (input_bfd, x, location);
1610 bfd_put_32 (input_bfd, x, location);
1614 bfd_put_64 (input_bfd, x, location);
1625 howto manager, , typedef arelent, Relocations
1630 When an application wants to create a relocation, but doesn't
1631 know what the target machine might call it, it can find out by
1632 using this bit of code.
1641 The insides of a reloc code. The idea is that, eventually, there
1642 will be one enumerator for every type of relocation we ever do.
1643 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1644 return a howto pointer.
1646 This does mean that the application must determine the correct
1647 enumerator value; you can't get a howto pointer from a random set
1668 Basic absolute relocations of N bits.
1683 PC-relative relocations. Sometimes these are relative to the address
1684 of the relocation itself; sometimes they are relative to the start of
1685 the section containing the relocation. It depends on the specific target.
1687 The 24-bit relocation is used in some Intel 960 configurations.
1692 Section relative relocations. Some targets need this for DWARF2.
1695 BFD_RELOC_32_GOT_PCREL
1697 BFD_RELOC_16_GOT_PCREL
1699 BFD_RELOC_8_GOT_PCREL
1705 BFD_RELOC_LO16_GOTOFF
1707 BFD_RELOC_HI16_GOTOFF
1709 BFD_RELOC_HI16_S_GOTOFF
1713 BFD_RELOC_64_PLT_PCREL
1715 BFD_RELOC_32_PLT_PCREL
1717 BFD_RELOC_24_PLT_PCREL
1719 BFD_RELOC_16_PLT_PCREL
1721 BFD_RELOC_8_PLT_PCREL
1729 BFD_RELOC_LO16_PLTOFF
1731 BFD_RELOC_HI16_PLTOFF
1733 BFD_RELOC_HI16_S_PLTOFF
1740 BFD_RELOC_68K_GLOB_DAT
1742 BFD_RELOC_68K_JMP_SLOT
1744 BFD_RELOC_68K_RELATIVE
1746 BFD_RELOC_68K_TLS_GD32
1748 BFD_RELOC_68K_TLS_GD16
1750 BFD_RELOC_68K_TLS_GD8
1752 BFD_RELOC_68K_TLS_LDM32
1754 BFD_RELOC_68K_TLS_LDM16
1756 BFD_RELOC_68K_TLS_LDM8
1758 BFD_RELOC_68K_TLS_LDO32
1760 BFD_RELOC_68K_TLS_LDO16
1762 BFD_RELOC_68K_TLS_LDO8
1764 BFD_RELOC_68K_TLS_IE32
1766 BFD_RELOC_68K_TLS_IE16
1768 BFD_RELOC_68K_TLS_IE8
1770 BFD_RELOC_68K_TLS_LE32
1772 BFD_RELOC_68K_TLS_LE16
1774 BFD_RELOC_68K_TLS_LE8
1776 Relocations used by 68K ELF.
1779 BFD_RELOC_32_BASEREL
1781 BFD_RELOC_16_BASEREL
1783 BFD_RELOC_LO16_BASEREL
1785 BFD_RELOC_HI16_BASEREL
1787 BFD_RELOC_HI16_S_BASEREL
1793 Linkage-table relative.
1798 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1801 BFD_RELOC_32_PCREL_S2
1803 BFD_RELOC_16_PCREL_S2
1805 BFD_RELOC_23_PCREL_S2
1807 These PC-relative relocations are stored as word displacements --
1808 i.e., byte displacements shifted right two bits. The 30-bit word
1809 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1810 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1811 signed 16-bit displacement is used on the MIPS, and the 23-bit
1812 displacement is used on the Alpha.
1819 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1820 the target word. These are used on the SPARC.
1827 For systems that allocate a Global Pointer register, these are
1828 displacements off that register. These relocation types are
1829 handled specially, because the value the register will have is
1830 decided relatively late.
1833 BFD_RELOC_I960_CALLJ
1835 Reloc types used for i960/b.out.
1840 BFD_RELOC_SPARC_WDISP22
1846 BFD_RELOC_SPARC_GOT10
1848 BFD_RELOC_SPARC_GOT13
1850 BFD_RELOC_SPARC_GOT22
1852 BFD_RELOC_SPARC_PC10
1854 BFD_RELOC_SPARC_PC22
1856 BFD_RELOC_SPARC_WPLT30
1858 BFD_RELOC_SPARC_COPY
1860 BFD_RELOC_SPARC_GLOB_DAT
1862 BFD_RELOC_SPARC_JMP_SLOT
1864 BFD_RELOC_SPARC_RELATIVE
1866 BFD_RELOC_SPARC_UA16
1868 BFD_RELOC_SPARC_UA32
1870 BFD_RELOC_SPARC_UA64
1872 BFD_RELOC_SPARC_GOTDATA_HIX22
1874 BFD_RELOC_SPARC_GOTDATA_LOX10
1876 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1878 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1880 BFD_RELOC_SPARC_GOTDATA_OP
1882 BFD_RELOC_SPARC_JMP_IREL
1884 BFD_RELOC_SPARC_IRELATIVE
1886 SPARC ELF relocations. There is probably some overlap with other
1887 relocation types already defined.
1890 BFD_RELOC_SPARC_BASE13
1892 BFD_RELOC_SPARC_BASE22
1894 I think these are specific to SPARC a.out (e.g., Sun 4).
1904 BFD_RELOC_SPARC_OLO10
1906 BFD_RELOC_SPARC_HH22
1908 BFD_RELOC_SPARC_HM10
1910 BFD_RELOC_SPARC_LM22
1912 BFD_RELOC_SPARC_PC_HH22
1914 BFD_RELOC_SPARC_PC_HM10
1916 BFD_RELOC_SPARC_PC_LM22
1918 BFD_RELOC_SPARC_WDISP16
1920 BFD_RELOC_SPARC_WDISP19
1928 BFD_RELOC_SPARC_DISP64
1931 BFD_RELOC_SPARC_PLT32
1933 BFD_RELOC_SPARC_PLT64
1935 BFD_RELOC_SPARC_HIX22
1937 BFD_RELOC_SPARC_LOX10
1945 BFD_RELOC_SPARC_REGISTER
1949 BFD_RELOC_SPARC_SIZE32
1951 BFD_RELOC_SPARC_SIZE64
1953 BFD_RELOC_SPARC_WDISP10
1958 BFD_RELOC_SPARC_REV32
1960 SPARC little endian relocation
1962 BFD_RELOC_SPARC_TLS_GD_HI22
1964 BFD_RELOC_SPARC_TLS_GD_LO10
1966 BFD_RELOC_SPARC_TLS_GD_ADD
1968 BFD_RELOC_SPARC_TLS_GD_CALL
1970 BFD_RELOC_SPARC_TLS_LDM_HI22
1972 BFD_RELOC_SPARC_TLS_LDM_LO10
1974 BFD_RELOC_SPARC_TLS_LDM_ADD
1976 BFD_RELOC_SPARC_TLS_LDM_CALL
1978 BFD_RELOC_SPARC_TLS_LDO_HIX22
1980 BFD_RELOC_SPARC_TLS_LDO_LOX10
1982 BFD_RELOC_SPARC_TLS_LDO_ADD
1984 BFD_RELOC_SPARC_TLS_IE_HI22
1986 BFD_RELOC_SPARC_TLS_IE_LO10
1988 BFD_RELOC_SPARC_TLS_IE_LD
1990 BFD_RELOC_SPARC_TLS_IE_LDX
1992 BFD_RELOC_SPARC_TLS_IE_ADD
1994 BFD_RELOC_SPARC_TLS_LE_HIX22
1996 BFD_RELOC_SPARC_TLS_LE_LOX10
1998 BFD_RELOC_SPARC_TLS_DTPMOD32
2000 BFD_RELOC_SPARC_TLS_DTPMOD64
2002 BFD_RELOC_SPARC_TLS_DTPOFF32
2004 BFD_RELOC_SPARC_TLS_DTPOFF64
2006 BFD_RELOC_SPARC_TLS_TPOFF32
2008 BFD_RELOC_SPARC_TLS_TPOFF64
2010 SPARC TLS relocations
2019 BFD_RELOC_SPU_IMM10W
2023 BFD_RELOC_SPU_IMM16W
2027 BFD_RELOC_SPU_PCREL9a
2029 BFD_RELOC_SPU_PCREL9b
2031 BFD_RELOC_SPU_PCREL16
2041 BFD_RELOC_SPU_ADD_PIC
2046 BFD_RELOC_ALPHA_GPDISP_HI16
2048 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2049 "addend" in some special way.
2050 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2051 writing; when reading, it will be the absolute section symbol. The
2052 addend is the displacement in bytes of the "lda" instruction from
2053 the "ldah" instruction (which is at the address of this reloc).
2055 BFD_RELOC_ALPHA_GPDISP_LO16
2057 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2058 with GPDISP_HI16 relocs. The addend is ignored when writing the
2059 relocations out, and is filled in with the file's GP value on
2060 reading, for convenience.
2063 BFD_RELOC_ALPHA_GPDISP
2065 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2066 relocation except that there is no accompanying GPDISP_LO16
2070 BFD_RELOC_ALPHA_LITERAL
2072 BFD_RELOC_ALPHA_ELF_LITERAL
2074 BFD_RELOC_ALPHA_LITUSE
2076 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2077 the assembler turns it into a LDQ instruction to load the address of
2078 the symbol, and then fills in a register in the real instruction.
2080 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2081 section symbol. The addend is ignored when writing, but is filled
2082 in with the file's GP value on reading, for convenience, as with the
2085 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2086 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2087 but it generates output not based on the position within the .got
2088 section, but relative to the GP value chosen for the file during the
2091 The LITUSE reloc, on the instruction using the loaded address, gives
2092 information to the linker that it might be able to use to optimize
2093 away some literal section references. The symbol is ignored (read
2094 as the absolute section symbol), and the "addend" indicates the type
2095 of instruction using the register:
2096 1 - "memory" fmt insn
2097 2 - byte-manipulation (byte offset reg)
2098 3 - jsr (target of branch)
2101 BFD_RELOC_ALPHA_HINT
2103 The HINT relocation indicates a value that should be filled into the
2104 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2105 prediction logic which may be provided on some processors.
2108 BFD_RELOC_ALPHA_LINKAGE
2110 The LINKAGE relocation outputs a linkage pair in the object file,
2111 which is filled by the linker.
2114 BFD_RELOC_ALPHA_CODEADDR
2116 The CODEADDR relocation outputs a STO_CA in the object file,
2117 which is filled by the linker.
2120 BFD_RELOC_ALPHA_GPREL_HI16
2122 BFD_RELOC_ALPHA_GPREL_LO16
2124 The GPREL_HI/LO relocations together form a 32-bit offset from the
2128 BFD_RELOC_ALPHA_BRSGP
2130 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2131 share a common GP, and the target address is adjusted for
2132 STO_ALPHA_STD_GPLOAD.
2137 The NOP relocation outputs a NOP if the longword displacement
2138 between two procedure entry points is < 2^21.
2143 The BSR relocation outputs a BSR if the longword displacement
2144 between two procedure entry points is < 2^21.
2149 The LDA relocation outputs a LDA if the longword displacement
2150 between two procedure entry points is < 2^16.
2155 The BOH relocation outputs a BSR if the longword displacement
2156 between two procedure entry points is < 2^21, or else a hint.
2159 BFD_RELOC_ALPHA_TLSGD
2161 BFD_RELOC_ALPHA_TLSLDM
2163 BFD_RELOC_ALPHA_DTPMOD64
2165 BFD_RELOC_ALPHA_GOTDTPREL16
2167 BFD_RELOC_ALPHA_DTPREL64
2169 BFD_RELOC_ALPHA_DTPREL_HI16
2171 BFD_RELOC_ALPHA_DTPREL_LO16
2173 BFD_RELOC_ALPHA_DTPREL16
2175 BFD_RELOC_ALPHA_GOTTPREL16
2177 BFD_RELOC_ALPHA_TPREL64
2179 BFD_RELOC_ALPHA_TPREL_HI16
2181 BFD_RELOC_ALPHA_TPREL_LO16
2183 BFD_RELOC_ALPHA_TPREL16
2185 Alpha thread-local storage relocations.
2190 BFD_RELOC_MICROMIPS_JMP
2192 The MIPS jump instruction.
2195 BFD_RELOC_MIPS16_JMP
2197 The MIPS16 jump instruction.
2200 BFD_RELOC_MIPS16_GPREL
2202 MIPS16 GP relative reloc.
2207 High 16 bits of 32-bit value; simple reloc.
2212 High 16 bits of 32-bit value but the low 16 bits will be sign
2213 extended and added to form the final result. If the low 16
2214 bits form a negative number, we need to add one to the high value
2215 to compensate for the borrow when the low bits are added.
2223 BFD_RELOC_HI16_PCREL
2225 High 16 bits of 32-bit pc-relative value
2227 BFD_RELOC_HI16_S_PCREL
2229 High 16 bits of 32-bit pc-relative value, adjusted
2231 BFD_RELOC_LO16_PCREL
2233 Low 16 bits of pc-relative value
2236 BFD_RELOC_MIPS16_GOT16
2238 BFD_RELOC_MIPS16_CALL16
2240 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2241 16-bit immediate fields
2243 BFD_RELOC_MIPS16_HI16
2245 MIPS16 high 16 bits of 32-bit value.
2247 BFD_RELOC_MIPS16_HI16_S
2249 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2250 extended and added to form the final result. If the low 16
2251 bits form a negative number, we need to add one to the high value
2252 to compensate for the borrow when the low bits are added.
2254 BFD_RELOC_MIPS16_LO16
2259 BFD_RELOC_MIPS16_TLS_GD
2261 BFD_RELOC_MIPS16_TLS_LDM
2263 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2265 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2267 BFD_RELOC_MIPS16_TLS_GOTTPREL
2269 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2271 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2273 MIPS16 TLS relocations
2276 BFD_RELOC_MIPS_LITERAL
2278 BFD_RELOC_MICROMIPS_LITERAL
2280 Relocation against a MIPS literal section.
2283 BFD_RELOC_MICROMIPS_7_PCREL_S1
2285 BFD_RELOC_MICROMIPS_10_PCREL_S1
2287 BFD_RELOC_MICROMIPS_16_PCREL_S1
2289 microMIPS PC-relative relocations.
2292 BFD_RELOC_MICROMIPS_GPREL16
2294 BFD_RELOC_MICROMIPS_HI16
2296 BFD_RELOC_MICROMIPS_HI16_S
2298 BFD_RELOC_MICROMIPS_LO16
2300 microMIPS versions of generic BFD relocs.
2303 BFD_RELOC_MIPS_GOT16
2305 BFD_RELOC_MICROMIPS_GOT16
2307 BFD_RELOC_MIPS_CALL16
2309 BFD_RELOC_MICROMIPS_CALL16
2311 BFD_RELOC_MIPS_GOT_HI16
2313 BFD_RELOC_MICROMIPS_GOT_HI16
2315 BFD_RELOC_MIPS_GOT_LO16
2317 BFD_RELOC_MICROMIPS_GOT_LO16
2319 BFD_RELOC_MIPS_CALL_HI16
2321 BFD_RELOC_MICROMIPS_CALL_HI16
2323 BFD_RELOC_MIPS_CALL_LO16
2325 BFD_RELOC_MICROMIPS_CALL_LO16
2329 BFD_RELOC_MICROMIPS_SUB
2331 BFD_RELOC_MIPS_GOT_PAGE
2333 BFD_RELOC_MICROMIPS_GOT_PAGE
2335 BFD_RELOC_MIPS_GOT_OFST
2337 BFD_RELOC_MICROMIPS_GOT_OFST
2339 BFD_RELOC_MIPS_GOT_DISP
2341 BFD_RELOC_MICROMIPS_GOT_DISP
2343 BFD_RELOC_MIPS_SHIFT5
2345 BFD_RELOC_MIPS_SHIFT6
2347 BFD_RELOC_MIPS_INSERT_A
2349 BFD_RELOC_MIPS_INSERT_B
2351 BFD_RELOC_MIPS_DELETE
2353 BFD_RELOC_MIPS_HIGHEST
2355 BFD_RELOC_MICROMIPS_HIGHEST
2357 BFD_RELOC_MIPS_HIGHER
2359 BFD_RELOC_MICROMIPS_HIGHER
2361 BFD_RELOC_MIPS_SCN_DISP
2363 BFD_RELOC_MICROMIPS_SCN_DISP
2365 BFD_RELOC_MIPS_REL16
2367 BFD_RELOC_MIPS_RELGOT
2371 BFD_RELOC_MICROMIPS_JALR
2373 BFD_RELOC_MIPS_TLS_DTPMOD32
2375 BFD_RELOC_MIPS_TLS_DTPREL32
2377 BFD_RELOC_MIPS_TLS_DTPMOD64
2379 BFD_RELOC_MIPS_TLS_DTPREL64
2381 BFD_RELOC_MIPS_TLS_GD
2383 BFD_RELOC_MICROMIPS_TLS_GD
2385 BFD_RELOC_MIPS_TLS_LDM
2387 BFD_RELOC_MICROMIPS_TLS_LDM
2389 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2391 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2393 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2395 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2397 BFD_RELOC_MIPS_TLS_GOTTPREL
2399 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2401 BFD_RELOC_MIPS_TLS_TPREL32
2403 BFD_RELOC_MIPS_TLS_TPREL64
2405 BFD_RELOC_MIPS_TLS_TPREL_HI16
2407 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2409 BFD_RELOC_MIPS_TLS_TPREL_LO16
2411 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2413 MIPS ELF relocations.
2419 BFD_RELOC_MIPS_JUMP_SLOT
2421 MIPS ELF relocations (VxWorks and PLT extensions).
2425 BFD_RELOC_MOXIE_10_PCREL
2427 Moxie ELF relocations.
2431 BFD_RELOC_FRV_LABEL16
2433 BFD_RELOC_FRV_LABEL24
2439 BFD_RELOC_FRV_GPREL12
2441 BFD_RELOC_FRV_GPRELU12
2443 BFD_RELOC_FRV_GPREL32
2445 BFD_RELOC_FRV_GPRELHI
2447 BFD_RELOC_FRV_GPRELLO
2455 BFD_RELOC_FRV_FUNCDESC
2457 BFD_RELOC_FRV_FUNCDESC_GOT12
2459 BFD_RELOC_FRV_FUNCDESC_GOTHI
2461 BFD_RELOC_FRV_FUNCDESC_GOTLO
2463 BFD_RELOC_FRV_FUNCDESC_VALUE
2465 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2467 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2469 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2471 BFD_RELOC_FRV_GOTOFF12
2473 BFD_RELOC_FRV_GOTOFFHI
2475 BFD_RELOC_FRV_GOTOFFLO
2477 BFD_RELOC_FRV_GETTLSOFF
2479 BFD_RELOC_FRV_TLSDESC_VALUE
2481 BFD_RELOC_FRV_GOTTLSDESC12
2483 BFD_RELOC_FRV_GOTTLSDESCHI
2485 BFD_RELOC_FRV_GOTTLSDESCLO
2487 BFD_RELOC_FRV_TLSMOFF12
2489 BFD_RELOC_FRV_TLSMOFFHI
2491 BFD_RELOC_FRV_TLSMOFFLO
2493 BFD_RELOC_FRV_GOTTLSOFF12
2495 BFD_RELOC_FRV_GOTTLSOFFHI
2497 BFD_RELOC_FRV_GOTTLSOFFLO
2499 BFD_RELOC_FRV_TLSOFF
2501 BFD_RELOC_FRV_TLSDESC_RELAX
2503 BFD_RELOC_FRV_GETTLSOFF_RELAX
2505 BFD_RELOC_FRV_TLSOFF_RELAX
2507 BFD_RELOC_FRV_TLSMOFF
2509 Fujitsu Frv Relocations.
2513 BFD_RELOC_MN10300_GOTOFF24
2515 This is a 24bit GOT-relative reloc for the mn10300.
2517 BFD_RELOC_MN10300_GOT32
2519 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2522 BFD_RELOC_MN10300_GOT24
2524 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2527 BFD_RELOC_MN10300_GOT16
2529 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2532 BFD_RELOC_MN10300_COPY
2534 Copy symbol at runtime.
2536 BFD_RELOC_MN10300_GLOB_DAT
2540 BFD_RELOC_MN10300_JMP_SLOT
2544 BFD_RELOC_MN10300_RELATIVE
2546 Adjust by program base.
2548 BFD_RELOC_MN10300_SYM_DIFF
2550 Together with another reloc targeted at the same location,
2551 allows for a value that is the difference of two symbols
2552 in the same section.
2554 BFD_RELOC_MN10300_ALIGN
2556 The addend of this reloc is an alignment power that must
2557 be honoured at the offset's location, regardless of linker
2560 BFD_RELOC_MN10300_TLS_GD
2562 BFD_RELOC_MN10300_TLS_LD
2564 BFD_RELOC_MN10300_TLS_LDO
2566 BFD_RELOC_MN10300_TLS_GOTIE
2568 BFD_RELOC_MN10300_TLS_IE
2570 BFD_RELOC_MN10300_TLS_LE
2572 BFD_RELOC_MN10300_TLS_DTPMOD
2574 BFD_RELOC_MN10300_TLS_DTPOFF
2576 BFD_RELOC_MN10300_TLS_TPOFF
2578 Various TLS-related relocations.
2580 BFD_RELOC_MN10300_32_PCREL
2582 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2585 BFD_RELOC_MN10300_16_PCREL
2587 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2598 BFD_RELOC_386_GLOB_DAT
2600 BFD_RELOC_386_JUMP_SLOT
2602 BFD_RELOC_386_RELATIVE
2604 BFD_RELOC_386_GOTOFF
2608 BFD_RELOC_386_TLS_TPOFF
2610 BFD_RELOC_386_TLS_IE
2612 BFD_RELOC_386_TLS_GOTIE
2614 BFD_RELOC_386_TLS_LE
2616 BFD_RELOC_386_TLS_GD
2618 BFD_RELOC_386_TLS_LDM
2620 BFD_RELOC_386_TLS_LDO_32
2622 BFD_RELOC_386_TLS_IE_32
2624 BFD_RELOC_386_TLS_LE_32
2626 BFD_RELOC_386_TLS_DTPMOD32
2628 BFD_RELOC_386_TLS_DTPOFF32
2630 BFD_RELOC_386_TLS_TPOFF32
2632 BFD_RELOC_386_TLS_GOTDESC
2634 BFD_RELOC_386_TLS_DESC_CALL
2636 BFD_RELOC_386_TLS_DESC
2638 BFD_RELOC_386_IRELATIVE
2640 i386/elf relocations
2643 BFD_RELOC_X86_64_GOT32
2645 BFD_RELOC_X86_64_PLT32
2647 BFD_RELOC_X86_64_COPY
2649 BFD_RELOC_X86_64_GLOB_DAT
2651 BFD_RELOC_X86_64_JUMP_SLOT
2653 BFD_RELOC_X86_64_RELATIVE
2655 BFD_RELOC_X86_64_GOTPCREL
2657 BFD_RELOC_X86_64_32S
2659 BFD_RELOC_X86_64_DTPMOD64
2661 BFD_RELOC_X86_64_DTPOFF64
2663 BFD_RELOC_X86_64_TPOFF64
2665 BFD_RELOC_X86_64_TLSGD
2667 BFD_RELOC_X86_64_TLSLD
2669 BFD_RELOC_X86_64_DTPOFF32
2671 BFD_RELOC_X86_64_GOTTPOFF
2673 BFD_RELOC_X86_64_TPOFF32
2675 BFD_RELOC_X86_64_GOTOFF64
2677 BFD_RELOC_X86_64_GOTPC32
2679 BFD_RELOC_X86_64_GOT64
2681 BFD_RELOC_X86_64_GOTPCREL64
2683 BFD_RELOC_X86_64_GOTPC64
2685 BFD_RELOC_X86_64_GOTPLT64
2687 BFD_RELOC_X86_64_PLTOFF64
2689 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2691 BFD_RELOC_X86_64_TLSDESC_CALL
2693 BFD_RELOC_X86_64_TLSDESC
2695 BFD_RELOC_X86_64_IRELATIVE
2697 x86-64/elf relocations
2700 BFD_RELOC_NS32K_IMM_8
2702 BFD_RELOC_NS32K_IMM_16
2704 BFD_RELOC_NS32K_IMM_32
2706 BFD_RELOC_NS32K_IMM_8_PCREL
2708 BFD_RELOC_NS32K_IMM_16_PCREL
2710 BFD_RELOC_NS32K_IMM_32_PCREL
2712 BFD_RELOC_NS32K_DISP_8
2714 BFD_RELOC_NS32K_DISP_16
2716 BFD_RELOC_NS32K_DISP_32
2718 BFD_RELOC_NS32K_DISP_8_PCREL
2720 BFD_RELOC_NS32K_DISP_16_PCREL
2722 BFD_RELOC_NS32K_DISP_32_PCREL
2727 BFD_RELOC_PDP11_DISP_8_PCREL
2729 BFD_RELOC_PDP11_DISP_6_PCREL
2734 BFD_RELOC_PJ_CODE_HI16
2736 BFD_RELOC_PJ_CODE_LO16
2738 BFD_RELOC_PJ_CODE_DIR16
2740 BFD_RELOC_PJ_CODE_DIR32
2742 BFD_RELOC_PJ_CODE_REL16
2744 BFD_RELOC_PJ_CODE_REL32
2746 Picojava relocs. Not all of these appear in object files.
2757 BFD_RELOC_PPC_B16_BRTAKEN
2759 BFD_RELOC_PPC_B16_BRNTAKEN
2763 BFD_RELOC_PPC_BA16_BRTAKEN
2765 BFD_RELOC_PPC_BA16_BRNTAKEN
2769 BFD_RELOC_PPC_GLOB_DAT
2771 BFD_RELOC_PPC_JMP_SLOT
2773 BFD_RELOC_PPC_RELATIVE
2775 BFD_RELOC_PPC_LOCAL24PC
2777 BFD_RELOC_PPC_EMB_NADDR32
2779 BFD_RELOC_PPC_EMB_NADDR16
2781 BFD_RELOC_PPC_EMB_NADDR16_LO
2783 BFD_RELOC_PPC_EMB_NADDR16_HI
2785 BFD_RELOC_PPC_EMB_NADDR16_HA
2787 BFD_RELOC_PPC_EMB_SDAI16
2789 BFD_RELOC_PPC_EMB_SDA2I16
2791 BFD_RELOC_PPC_EMB_SDA2REL
2793 BFD_RELOC_PPC_EMB_SDA21
2795 BFD_RELOC_PPC_EMB_MRKREF
2797 BFD_RELOC_PPC_EMB_RELSEC16
2799 BFD_RELOC_PPC_EMB_RELST_LO
2801 BFD_RELOC_PPC_EMB_RELST_HI
2803 BFD_RELOC_PPC_EMB_RELST_HA
2805 BFD_RELOC_PPC_EMB_BIT_FLD
2807 BFD_RELOC_PPC_EMB_RELSDA
2809 BFD_RELOC_PPC64_HIGHER
2811 BFD_RELOC_PPC64_HIGHER_S
2813 BFD_RELOC_PPC64_HIGHEST
2815 BFD_RELOC_PPC64_HIGHEST_S
2817 BFD_RELOC_PPC64_TOC16_LO
2819 BFD_RELOC_PPC64_TOC16_HI
2821 BFD_RELOC_PPC64_TOC16_HA
2825 BFD_RELOC_PPC64_PLTGOT16
2827 BFD_RELOC_PPC64_PLTGOT16_LO
2829 BFD_RELOC_PPC64_PLTGOT16_HI
2831 BFD_RELOC_PPC64_PLTGOT16_HA
2833 BFD_RELOC_PPC64_ADDR16_DS
2835 BFD_RELOC_PPC64_ADDR16_LO_DS
2837 BFD_RELOC_PPC64_GOT16_DS
2839 BFD_RELOC_PPC64_GOT16_LO_DS
2841 BFD_RELOC_PPC64_PLT16_LO_DS
2843 BFD_RELOC_PPC64_SECTOFF_DS
2845 BFD_RELOC_PPC64_SECTOFF_LO_DS
2847 BFD_RELOC_PPC64_TOC16_DS
2849 BFD_RELOC_PPC64_TOC16_LO_DS
2851 BFD_RELOC_PPC64_PLTGOT16_DS
2853 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2855 Power(rs6000) and PowerPC relocations.
2864 BFD_RELOC_PPC_DTPMOD
2866 BFD_RELOC_PPC_TPREL16
2868 BFD_RELOC_PPC_TPREL16_LO
2870 BFD_RELOC_PPC_TPREL16_HI
2872 BFD_RELOC_PPC_TPREL16_HA
2876 BFD_RELOC_PPC_DTPREL16
2878 BFD_RELOC_PPC_DTPREL16_LO
2880 BFD_RELOC_PPC_DTPREL16_HI
2882 BFD_RELOC_PPC_DTPREL16_HA
2884 BFD_RELOC_PPC_DTPREL
2886 BFD_RELOC_PPC_GOT_TLSGD16
2888 BFD_RELOC_PPC_GOT_TLSGD16_LO
2890 BFD_RELOC_PPC_GOT_TLSGD16_HI
2892 BFD_RELOC_PPC_GOT_TLSGD16_HA
2894 BFD_RELOC_PPC_GOT_TLSLD16
2896 BFD_RELOC_PPC_GOT_TLSLD16_LO
2898 BFD_RELOC_PPC_GOT_TLSLD16_HI
2900 BFD_RELOC_PPC_GOT_TLSLD16_HA
2902 BFD_RELOC_PPC_GOT_TPREL16
2904 BFD_RELOC_PPC_GOT_TPREL16_LO
2906 BFD_RELOC_PPC_GOT_TPREL16_HI
2908 BFD_RELOC_PPC_GOT_TPREL16_HA
2910 BFD_RELOC_PPC_GOT_DTPREL16
2912 BFD_RELOC_PPC_GOT_DTPREL16_LO
2914 BFD_RELOC_PPC_GOT_DTPREL16_HI
2916 BFD_RELOC_PPC_GOT_DTPREL16_HA
2918 BFD_RELOC_PPC64_TPREL16_DS
2920 BFD_RELOC_PPC64_TPREL16_LO_DS
2922 BFD_RELOC_PPC64_TPREL16_HIGHER
2924 BFD_RELOC_PPC64_TPREL16_HIGHERA
2926 BFD_RELOC_PPC64_TPREL16_HIGHEST
2928 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2930 BFD_RELOC_PPC64_DTPREL16_DS
2932 BFD_RELOC_PPC64_DTPREL16_LO_DS
2934 BFD_RELOC_PPC64_DTPREL16_HIGHER
2936 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2938 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2940 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2942 PowerPC and PowerPC64 thread-local storage relocations.
2947 IBM 370/390 relocations
2952 The type of reloc used to build a constructor table - at the moment
2953 probably a 32 bit wide absolute relocation, but the target can choose.
2954 It generally does map to one of the other relocation types.
2957 BFD_RELOC_ARM_PCREL_BRANCH
2959 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
2960 not stored in the instruction.
2962 BFD_RELOC_ARM_PCREL_BLX
2964 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
2965 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
2966 field in the instruction.
2968 BFD_RELOC_THUMB_PCREL_BLX
2970 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
2971 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
2972 field in the instruction.
2974 BFD_RELOC_ARM_PCREL_CALL
2976 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
2978 BFD_RELOC_ARM_PCREL_JUMP
2980 ARM 26-bit pc-relative branch for B or conditional BL instruction.
2983 BFD_RELOC_THUMB_PCREL_BRANCH7
2985 BFD_RELOC_THUMB_PCREL_BRANCH9
2987 BFD_RELOC_THUMB_PCREL_BRANCH12
2989 BFD_RELOC_THUMB_PCREL_BRANCH20
2991 BFD_RELOC_THUMB_PCREL_BRANCH23
2993 BFD_RELOC_THUMB_PCREL_BRANCH25
2995 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
2996 The lowest bit must be zero and is not stored in the instruction.
2997 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
2998 "nn" one smaller in all cases. Note further that BRANCH23
2999 corresponds to R_ARM_THM_CALL.
3002 BFD_RELOC_ARM_OFFSET_IMM
3004 12-bit immediate offset, used in ARM-format ldr and str instructions.
3007 BFD_RELOC_ARM_THUMB_OFFSET
3009 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3012 BFD_RELOC_ARM_TARGET1
3014 Pc-relative or absolute relocation depending on target. Used for
3015 entries in .init_array sections.
3017 BFD_RELOC_ARM_ROSEGREL32
3019 Read-only segment base relative address.
3021 BFD_RELOC_ARM_SBREL32
3023 Data segment base relative address.
3025 BFD_RELOC_ARM_TARGET2
3027 This reloc is used for references to RTTI data from exception handling
3028 tables. The actual definition depends on the target. It may be a
3029 pc-relative or some form of GOT-indirect relocation.
3031 BFD_RELOC_ARM_PREL31
3033 31-bit PC relative address.
3039 BFD_RELOC_ARM_MOVW_PCREL
3041 BFD_RELOC_ARM_MOVT_PCREL
3043 BFD_RELOC_ARM_THUMB_MOVW
3045 BFD_RELOC_ARM_THUMB_MOVT
3047 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3049 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3051 Low and High halfword relocations for MOVW and MOVT instructions.
3054 BFD_RELOC_ARM_JUMP_SLOT
3056 BFD_RELOC_ARM_GLOB_DAT
3062 BFD_RELOC_ARM_RELATIVE
3064 BFD_RELOC_ARM_GOTOFF
3068 BFD_RELOC_ARM_GOT_PREL
3070 Relocations for setting up GOTs and PLTs for shared libraries.
3073 BFD_RELOC_ARM_TLS_GD32
3075 BFD_RELOC_ARM_TLS_LDO32
3077 BFD_RELOC_ARM_TLS_LDM32
3079 BFD_RELOC_ARM_TLS_DTPOFF32
3081 BFD_RELOC_ARM_TLS_DTPMOD32
3083 BFD_RELOC_ARM_TLS_TPOFF32
3085 BFD_RELOC_ARM_TLS_IE32
3087 BFD_RELOC_ARM_TLS_LE32
3089 BFD_RELOC_ARM_TLS_GOTDESC
3091 BFD_RELOC_ARM_TLS_CALL
3093 BFD_RELOC_ARM_THM_TLS_CALL
3095 BFD_RELOC_ARM_TLS_DESCSEQ
3097 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3099 BFD_RELOC_ARM_TLS_DESC
3101 ARM thread-local storage relocations.
3104 BFD_RELOC_ARM_ALU_PC_G0_NC
3106 BFD_RELOC_ARM_ALU_PC_G0
3108 BFD_RELOC_ARM_ALU_PC_G1_NC
3110 BFD_RELOC_ARM_ALU_PC_G1
3112 BFD_RELOC_ARM_ALU_PC_G2
3114 BFD_RELOC_ARM_LDR_PC_G0
3116 BFD_RELOC_ARM_LDR_PC_G1
3118 BFD_RELOC_ARM_LDR_PC_G2
3120 BFD_RELOC_ARM_LDRS_PC_G0
3122 BFD_RELOC_ARM_LDRS_PC_G1
3124 BFD_RELOC_ARM_LDRS_PC_G2
3126 BFD_RELOC_ARM_LDC_PC_G0
3128 BFD_RELOC_ARM_LDC_PC_G1
3130 BFD_RELOC_ARM_LDC_PC_G2
3132 BFD_RELOC_ARM_ALU_SB_G0_NC
3134 BFD_RELOC_ARM_ALU_SB_G0
3136 BFD_RELOC_ARM_ALU_SB_G1_NC
3138 BFD_RELOC_ARM_ALU_SB_G1
3140 BFD_RELOC_ARM_ALU_SB_G2
3142 BFD_RELOC_ARM_LDR_SB_G0
3144 BFD_RELOC_ARM_LDR_SB_G1
3146 BFD_RELOC_ARM_LDR_SB_G2
3148 BFD_RELOC_ARM_LDRS_SB_G0
3150 BFD_RELOC_ARM_LDRS_SB_G1
3152 BFD_RELOC_ARM_LDRS_SB_G2
3154 BFD_RELOC_ARM_LDC_SB_G0
3156 BFD_RELOC_ARM_LDC_SB_G1
3158 BFD_RELOC_ARM_LDC_SB_G2
3160 ARM group relocations.
3165 Annotation of BX instructions.
3168 BFD_RELOC_ARM_IRELATIVE
3170 ARM support for STT_GNU_IFUNC.
3173 BFD_RELOC_ARM_IMMEDIATE
3175 BFD_RELOC_ARM_ADRL_IMMEDIATE
3177 BFD_RELOC_ARM_T32_IMMEDIATE
3179 BFD_RELOC_ARM_T32_ADD_IMM
3181 BFD_RELOC_ARM_T32_IMM12
3183 BFD_RELOC_ARM_T32_ADD_PC12
3185 BFD_RELOC_ARM_SHIFT_IMM
3195 BFD_RELOC_ARM_CP_OFF_IMM
3197 BFD_RELOC_ARM_CP_OFF_IMM_S2
3199 BFD_RELOC_ARM_T32_CP_OFF_IMM
3201 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3203 BFD_RELOC_ARM_ADR_IMM
3205 BFD_RELOC_ARM_LDR_IMM
3207 BFD_RELOC_ARM_LITERAL
3209 BFD_RELOC_ARM_IN_POOL
3211 BFD_RELOC_ARM_OFFSET_IMM8
3213 BFD_RELOC_ARM_T32_OFFSET_U8
3215 BFD_RELOC_ARM_T32_OFFSET_IMM
3217 BFD_RELOC_ARM_HWLITERAL
3219 BFD_RELOC_ARM_THUMB_ADD
3221 BFD_RELOC_ARM_THUMB_IMM
3223 BFD_RELOC_ARM_THUMB_SHIFT
3225 These relocs are only used within the ARM assembler. They are not
3226 (at present) written to any object files.
3229 BFD_RELOC_SH_PCDISP8BY2
3231 BFD_RELOC_SH_PCDISP12BY2
3239 BFD_RELOC_SH_DISP12BY2
3241 BFD_RELOC_SH_DISP12BY4
3243 BFD_RELOC_SH_DISP12BY8
3247 BFD_RELOC_SH_DISP20BY8
3251 BFD_RELOC_SH_IMM4BY2
3253 BFD_RELOC_SH_IMM4BY4
3257 BFD_RELOC_SH_IMM8BY2
3259 BFD_RELOC_SH_IMM8BY4
3261 BFD_RELOC_SH_PCRELIMM8BY2
3263 BFD_RELOC_SH_PCRELIMM8BY4
3265 BFD_RELOC_SH_SWITCH16
3267 BFD_RELOC_SH_SWITCH32
3281 BFD_RELOC_SH_LOOP_START
3283 BFD_RELOC_SH_LOOP_END
3287 BFD_RELOC_SH_GLOB_DAT
3289 BFD_RELOC_SH_JMP_SLOT
3291 BFD_RELOC_SH_RELATIVE
3295 BFD_RELOC_SH_GOT_LOW16
3297 BFD_RELOC_SH_GOT_MEDLOW16
3299 BFD_RELOC_SH_GOT_MEDHI16
3301 BFD_RELOC_SH_GOT_HI16
3303 BFD_RELOC_SH_GOTPLT_LOW16
3305 BFD_RELOC_SH_GOTPLT_MEDLOW16
3307 BFD_RELOC_SH_GOTPLT_MEDHI16
3309 BFD_RELOC_SH_GOTPLT_HI16
3311 BFD_RELOC_SH_PLT_LOW16
3313 BFD_RELOC_SH_PLT_MEDLOW16
3315 BFD_RELOC_SH_PLT_MEDHI16
3317 BFD_RELOC_SH_PLT_HI16
3319 BFD_RELOC_SH_GOTOFF_LOW16
3321 BFD_RELOC_SH_GOTOFF_MEDLOW16
3323 BFD_RELOC_SH_GOTOFF_MEDHI16
3325 BFD_RELOC_SH_GOTOFF_HI16
3327 BFD_RELOC_SH_GOTPC_LOW16
3329 BFD_RELOC_SH_GOTPC_MEDLOW16
3331 BFD_RELOC_SH_GOTPC_MEDHI16
3333 BFD_RELOC_SH_GOTPC_HI16
3337 BFD_RELOC_SH_GLOB_DAT64
3339 BFD_RELOC_SH_JMP_SLOT64
3341 BFD_RELOC_SH_RELATIVE64
3343 BFD_RELOC_SH_GOT10BY4
3345 BFD_RELOC_SH_GOT10BY8
3347 BFD_RELOC_SH_GOTPLT10BY4
3349 BFD_RELOC_SH_GOTPLT10BY8
3351 BFD_RELOC_SH_GOTPLT32
3353 BFD_RELOC_SH_SHMEDIA_CODE
3359 BFD_RELOC_SH_IMMS6BY32
3365 BFD_RELOC_SH_IMMS10BY2
3367 BFD_RELOC_SH_IMMS10BY4
3369 BFD_RELOC_SH_IMMS10BY8
3375 BFD_RELOC_SH_IMM_LOW16
3377 BFD_RELOC_SH_IMM_LOW16_PCREL
3379 BFD_RELOC_SH_IMM_MEDLOW16
3381 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3383 BFD_RELOC_SH_IMM_MEDHI16
3385 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3387 BFD_RELOC_SH_IMM_HI16
3389 BFD_RELOC_SH_IMM_HI16_PCREL
3393 BFD_RELOC_SH_TLS_GD_32
3395 BFD_RELOC_SH_TLS_LD_32
3397 BFD_RELOC_SH_TLS_LDO_32
3399 BFD_RELOC_SH_TLS_IE_32
3401 BFD_RELOC_SH_TLS_LE_32
3403 BFD_RELOC_SH_TLS_DTPMOD32
3405 BFD_RELOC_SH_TLS_DTPOFF32
3407 BFD_RELOC_SH_TLS_TPOFF32
3411 BFD_RELOC_SH_GOTOFF20
3413 BFD_RELOC_SH_GOTFUNCDESC
3415 BFD_RELOC_SH_GOTFUNCDESC20
3417 BFD_RELOC_SH_GOTOFFFUNCDESC
3419 BFD_RELOC_SH_GOTOFFFUNCDESC20
3421 BFD_RELOC_SH_FUNCDESC
3423 Renesas / SuperH SH relocs. Not all of these appear in object files.
3426 BFD_RELOC_ARC_B22_PCREL
3429 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
3430 not stored in the instruction. The high 20 bits are installed in bits 26
3431 through 7 of the instruction.
3435 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
3436 stored in the instruction. The high 24 bits are installed in bits 23
3440 BFD_RELOC_BFIN_16_IMM
3442 ADI Blackfin 16 bit immediate absolute reloc.
3444 BFD_RELOC_BFIN_16_HIGH
3446 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3448 BFD_RELOC_BFIN_4_PCREL
3450 ADI Blackfin 'a' part of LSETUP.
3452 BFD_RELOC_BFIN_5_PCREL
3456 BFD_RELOC_BFIN_16_LOW
3458 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3460 BFD_RELOC_BFIN_10_PCREL
3464 BFD_RELOC_BFIN_11_PCREL
3466 ADI Blackfin 'b' part of LSETUP.
3468 BFD_RELOC_BFIN_12_PCREL_JUMP
3472 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3474 ADI Blackfin Short jump, pcrel.
3476 BFD_RELOC_BFIN_24_PCREL_CALL_X
3478 ADI Blackfin Call.x not implemented.
3480 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3482 ADI Blackfin Long Jump pcrel.
3484 BFD_RELOC_BFIN_GOT17M4
3486 BFD_RELOC_BFIN_GOTHI
3488 BFD_RELOC_BFIN_GOTLO
3490 BFD_RELOC_BFIN_FUNCDESC
3492 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3494 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3496 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3498 BFD_RELOC_BFIN_FUNCDESC_VALUE
3500 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3502 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3504 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3506 BFD_RELOC_BFIN_GOTOFF17M4
3508 BFD_RELOC_BFIN_GOTOFFHI
3510 BFD_RELOC_BFIN_GOTOFFLO
3512 ADI Blackfin FD-PIC relocations.
3516 ADI Blackfin GOT relocation.
3518 BFD_RELOC_BFIN_PLTPC
3520 ADI Blackfin PLTPC relocation.
3522 BFD_ARELOC_BFIN_PUSH
3524 ADI Blackfin arithmetic relocation.
3526 BFD_ARELOC_BFIN_CONST
3528 ADI Blackfin arithmetic relocation.
3532 ADI Blackfin arithmetic relocation.
3536 ADI Blackfin arithmetic relocation.
3538 BFD_ARELOC_BFIN_MULT
3540 ADI Blackfin arithmetic relocation.
3544 ADI Blackfin arithmetic relocation.
3548 ADI Blackfin arithmetic relocation.
3550 BFD_ARELOC_BFIN_LSHIFT
3552 ADI Blackfin arithmetic relocation.
3554 BFD_ARELOC_BFIN_RSHIFT
3556 ADI Blackfin arithmetic relocation.
3560 ADI Blackfin arithmetic relocation.
3564 ADI Blackfin arithmetic relocation.
3568 ADI Blackfin arithmetic relocation.
3570 BFD_ARELOC_BFIN_LAND
3572 ADI Blackfin arithmetic relocation.
3576 ADI Blackfin arithmetic relocation.
3580 ADI Blackfin arithmetic relocation.
3584 ADI Blackfin arithmetic relocation.
3586 BFD_ARELOC_BFIN_COMP
3588 ADI Blackfin arithmetic relocation.
3590 BFD_ARELOC_BFIN_PAGE
3592 ADI Blackfin arithmetic relocation.
3594 BFD_ARELOC_BFIN_HWPAGE
3596 ADI Blackfin arithmetic relocation.
3598 BFD_ARELOC_BFIN_ADDR
3600 ADI Blackfin arithmetic relocation.
3603 BFD_RELOC_D10V_10_PCREL_R
3605 Mitsubishi D10V relocs.
3606 This is a 10-bit reloc with the right 2 bits
3609 BFD_RELOC_D10V_10_PCREL_L
3611 Mitsubishi D10V relocs.
3612 This is a 10-bit reloc with the right 2 bits
3613 assumed to be 0. This is the same as the previous reloc
3614 except it is in the left container, i.e.,
3615 shifted left 15 bits.
3619 This is an 18-bit reloc with the right 2 bits
3622 BFD_RELOC_D10V_18_PCREL
3624 This is an 18-bit reloc with the right 2 bits
3630 Mitsubishi D30V relocs.
3631 This is a 6-bit absolute reloc.
3633 BFD_RELOC_D30V_9_PCREL
3635 This is a 6-bit pc-relative reloc with
3636 the right 3 bits assumed to be 0.
3638 BFD_RELOC_D30V_9_PCREL_R
3640 This is a 6-bit pc-relative reloc with
3641 the right 3 bits assumed to be 0. Same
3642 as the previous reloc but on the right side
3647 This is a 12-bit absolute reloc with the
3648 right 3 bitsassumed to be 0.
3650 BFD_RELOC_D30V_15_PCREL
3652 This is a 12-bit pc-relative reloc with
3653 the right 3 bits assumed to be 0.
3655 BFD_RELOC_D30V_15_PCREL_R
3657 This is a 12-bit pc-relative reloc with
3658 the right 3 bits assumed to be 0. Same
3659 as the previous reloc but on the right side
3664 This is an 18-bit absolute reloc with
3665 the right 3 bits assumed to be 0.
3667 BFD_RELOC_D30V_21_PCREL
3669 This is an 18-bit pc-relative reloc with
3670 the right 3 bits assumed to be 0.
3672 BFD_RELOC_D30V_21_PCREL_R
3674 This is an 18-bit pc-relative reloc with
3675 the right 3 bits assumed to be 0. Same
3676 as the previous reloc but on the right side
3681 This is a 32-bit absolute reloc.
3683 BFD_RELOC_D30V_32_PCREL
3685 This is a 32-bit pc-relative reloc.
3688 BFD_RELOC_DLX_HI16_S
3703 BFD_RELOC_M32C_RL_JUMP
3705 BFD_RELOC_M32C_RL_1ADDR
3707 BFD_RELOC_M32C_RL_2ADDR
3709 Renesas M16C/M32C Relocations.
3714 Renesas M32R (formerly Mitsubishi M32R) relocs.
3715 This is a 24 bit absolute address.
3717 BFD_RELOC_M32R_10_PCREL
3719 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3721 BFD_RELOC_M32R_18_PCREL
3723 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3725 BFD_RELOC_M32R_26_PCREL
3727 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3729 BFD_RELOC_M32R_HI16_ULO
3731 This is a 16-bit reloc containing the high 16 bits of an address
3732 used when the lower 16 bits are treated as unsigned.
3734 BFD_RELOC_M32R_HI16_SLO
3736 This is a 16-bit reloc containing the high 16 bits of an address
3737 used when the lower 16 bits are treated as signed.
3741 This is a 16-bit reloc containing the lower 16 bits of an address.
3743 BFD_RELOC_M32R_SDA16
3745 This is a 16-bit reloc containing the small data area offset for use in
3746 add3, load, and store instructions.
3748 BFD_RELOC_M32R_GOT24
3750 BFD_RELOC_M32R_26_PLTREL
3754 BFD_RELOC_M32R_GLOB_DAT
3756 BFD_RELOC_M32R_JMP_SLOT
3758 BFD_RELOC_M32R_RELATIVE
3760 BFD_RELOC_M32R_GOTOFF
3762 BFD_RELOC_M32R_GOTOFF_HI_ULO
3764 BFD_RELOC_M32R_GOTOFF_HI_SLO
3766 BFD_RELOC_M32R_GOTOFF_LO
3768 BFD_RELOC_M32R_GOTPC24
3770 BFD_RELOC_M32R_GOT16_HI_ULO
3772 BFD_RELOC_M32R_GOT16_HI_SLO
3774 BFD_RELOC_M32R_GOT16_LO
3776 BFD_RELOC_M32R_GOTPC_HI_ULO
3778 BFD_RELOC_M32R_GOTPC_HI_SLO
3780 BFD_RELOC_M32R_GOTPC_LO
3786 BFD_RELOC_V850_9_PCREL
3788 This is a 9-bit reloc
3790 BFD_RELOC_V850_22_PCREL
3792 This is a 22-bit reloc
3795 BFD_RELOC_V850_SDA_16_16_OFFSET
3797 This is a 16 bit offset from the short data area pointer.
3799 BFD_RELOC_V850_SDA_15_16_OFFSET
3801 This is a 16 bit offset (of which only 15 bits are used) from the
3802 short data area pointer.
3804 BFD_RELOC_V850_ZDA_16_16_OFFSET
3806 This is a 16 bit offset from the zero data area pointer.
3808 BFD_RELOC_V850_ZDA_15_16_OFFSET
3810 This is a 16 bit offset (of which only 15 bits are used) from the
3811 zero data area pointer.
3813 BFD_RELOC_V850_TDA_6_8_OFFSET
3815 This is an 8 bit offset (of which only 6 bits are used) from the
3816 tiny data area pointer.
3818 BFD_RELOC_V850_TDA_7_8_OFFSET
3820 This is an 8bit offset (of which only 7 bits are used) from the tiny
3823 BFD_RELOC_V850_TDA_7_7_OFFSET
3825 This is a 7 bit offset from the tiny data area pointer.
3827 BFD_RELOC_V850_TDA_16_16_OFFSET
3829 This is a 16 bit offset from the tiny data area pointer.
3832 BFD_RELOC_V850_TDA_4_5_OFFSET
3834 This is a 5 bit offset (of which only 4 bits are used) from the tiny
3837 BFD_RELOC_V850_TDA_4_4_OFFSET
3839 This is a 4 bit offset from the tiny data area pointer.
3841 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
3843 This is a 16 bit offset from the short data area pointer, with the
3844 bits placed non-contiguously in the instruction.
3846 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
3848 This is a 16 bit offset from the zero data area pointer, with the
3849 bits placed non-contiguously in the instruction.
3851 BFD_RELOC_V850_CALLT_6_7_OFFSET
3853 This is a 6 bit offset from the call table base pointer.
3855 BFD_RELOC_V850_CALLT_16_16_OFFSET
3857 This is a 16 bit offset from the call table base pointer.
3859 BFD_RELOC_V850_LONGCALL
3861 Used for relaxing indirect function calls.
3863 BFD_RELOC_V850_LONGJUMP
3865 Used for relaxing indirect jumps.
3867 BFD_RELOC_V850_ALIGN
3869 Used to maintain alignment whilst relaxing.
3871 BFD_RELOC_V850_LO16_SPLIT_OFFSET
3873 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
3876 BFD_RELOC_V850_16_PCREL
3878 This is a 16-bit reloc.
3880 BFD_RELOC_V850_17_PCREL
3882 This is a 17-bit reloc.
3886 This is a 23-bit reloc.
3888 BFD_RELOC_V850_32_PCREL
3890 This is a 32-bit reloc.
3892 BFD_RELOC_V850_32_ABS
3894 This is a 32-bit reloc.
3896 BFD_RELOC_V850_16_SPLIT_OFFSET
3898 This is a 16-bit reloc.
3900 BFD_RELOC_V850_16_S1
3902 This is a 16-bit reloc.
3904 BFD_RELOC_V850_LO16_S1
3906 Low 16 bits. 16 bit shifted by 1.
3908 BFD_RELOC_V850_CALLT_15_16_OFFSET
3910 This is a 16 bit offset from the call table base pointer.
3912 BFD_RELOC_V850_32_GOTPCREL
3916 BFD_RELOC_V850_16_GOT
3920 BFD_RELOC_V850_32_GOT
3924 BFD_RELOC_V850_22_PLT_PCREL
3928 BFD_RELOC_V850_32_PLT_PCREL
3936 BFD_RELOC_V850_GLOB_DAT
3940 BFD_RELOC_V850_JMP_SLOT
3944 BFD_RELOC_V850_RELATIVE
3948 BFD_RELOC_V850_16_GOTOFF
3952 BFD_RELOC_V850_32_GOTOFF
3967 This is a 8bit DP reloc for the tms320c30, where the most
3968 significant 8 bits of a 24 bit word are placed into the least
3969 significant 8 bits of the opcode.
3972 BFD_RELOC_TIC54X_PARTLS7
3974 This is a 7bit reloc for the tms320c54x, where the least
3975 significant 7 bits of a 16 bit word are placed into the least
3976 significant 7 bits of the opcode.
3979 BFD_RELOC_TIC54X_PARTMS9
3981 This is a 9bit DP reloc for the tms320c54x, where the most
3982 significant 9 bits of a 16 bit word are placed into the least
3983 significant 9 bits of the opcode.
3988 This is an extended address 23-bit reloc for the tms320c54x.
3991 BFD_RELOC_TIC54X_16_OF_23
3993 This is a 16-bit reloc for the tms320c54x, where the least
3994 significant 16 bits of a 23-bit extended address are placed into
3998 BFD_RELOC_TIC54X_MS7_OF_23
4000 This is a reloc for the tms320c54x, where the most
4001 significant 7 bits of a 23-bit extended address are placed into
4005 BFD_RELOC_C6000_PCR_S21
4007 BFD_RELOC_C6000_PCR_S12
4009 BFD_RELOC_C6000_PCR_S10
4011 BFD_RELOC_C6000_PCR_S7
4013 BFD_RELOC_C6000_ABS_S16
4015 BFD_RELOC_C6000_ABS_L16
4017 BFD_RELOC_C6000_ABS_H16
4019 BFD_RELOC_C6000_SBR_U15_B
4021 BFD_RELOC_C6000_SBR_U15_H
4023 BFD_RELOC_C6000_SBR_U15_W
4025 BFD_RELOC_C6000_SBR_S16
4027 BFD_RELOC_C6000_SBR_L16_B
4029 BFD_RELOC_C6000_SBR_L16_H
4031 BFD_RELOC_C6000_SBR_L16_W
4033 BFD_RELOC_C6000_SBR_H16_B
4035 BFD_RELOC_C6000_SBR_H16_H
4037 BFD_RELOC_C6000_SBR_H16_W
4039 BFD_RELOC_C6000_SBR_GOT_U15_W
4041 BFD_RELOC_C6000_SBR_GOT_L16_W
4043 BFD_RELOC_C6000_SBR_GOT_H16_W
4045 BFD_RELOC_C6000_DSBT_INDEX
4047 BFD_RELOC_C6000_PREL31
4049 BFD_RELOC_C6000_COPY
4051 BFD_RELOC_C6000_JUMP_SLOT
4053 BFD_RELOC_C6000_EHTYPE
4055 BFD_RELOC_C6000_PCR_H16
4057 BFD_RELOC_C6000_PCR_L16
4059 BFD_RELOC_C6000_ALIGN
4061 BFD_RELOC_C6000_FPHEAD
4063 BFD_RELOC_C6000_NOCMP
4065 TMS320C6000 relocations.
4070 This is a 48 bit reloc for the FR30 that stores 32 bits.
4074 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4077 BFD_RELOC_FR30_6_IN_4
4079 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4082 BFD_RELOC_FR30_8_IN_8
4084 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4087 BFD_RELOC_FR30_9_IN_8
4089 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4092 BFD_RELOC_FR30_10_IN_8
4094 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4097 BFD_RELOC_FR30_9_PCREL
4099 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4100 short offset into 8 bits.
4102 BFD_RELOC_FR30_12_PCREL
4104 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4105 short offset into 11 bits.
4108 BFD_RELOC_MCORE_PCREL_IMM8BY4
4110 BFD_RELOC_MCORE_PCREL_IMM11BY2
4112 BFD_RELOC_MCORE_PCREL_IMM4BY2
4114 BFD_RELOC_MCORE_PCREL_32
4116 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4120 Motorola Mcore relocations.
4129 BFD_RELOC_MEP_PCREL8A2
4131 BFD_RELOC_MEP_PCREL12A2
4133 BFD_RELOC_MEP_PCREL17A2
4135 BFD_RELOC_MEP_PCREL24A2
4137 BFD_RELOC_MEP_PCABS24A2
4149 BFD_RELOC_MEP_TPREL7
4151 BFD_RELOC_MEP_TPREL7A2
4153 BFD_RELOC_MEP_TPREL7A4
4155 BFD_RELOC_MEP_UIMM24
4157 BFD_RELOC_MEP_ADDR24A4
4159 BFD_RELOC_MEP_GNU_VTINHERIT
4161 BFD_RELOC_MEP_GNU_VTENTRY
4163 Toshiba Media Processor Relocations.
4169 BFD_RELOC_MMIX_GETA_1
4171 BFD_RELOC_MMIX_GETA_2
4173 BFD_RELOC_MMIX_GETA_3
4175 These are relocations for the GETA instruction.
4177 BFD_RELOC_MMIX_CBRANCH
4179 BFD_RELOC_MMIX_CBRANCH_J
4181 BFD_RELOC_MMIX_CBRANCH_1
4183 BFD_RELOC_MMIX_CBRANCH_2
4185 BFD_RELOC_MMIX_CBRANCH_3
4187 These are relocations for a conditional branch instruction.
4189 BFD_RELOC_MMIX_PUSHJ
4191 BFD_RELOC_MMIX_PUSHJ_1
4193 BFD_RELOC_MMIX_PUSHJ_2
4195 BFD_RELOC_MMIX_PUSHJ_3
4197 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4199 These are relocations for the PUSHJ instruction.
4203 BFD_RELOC_MMIX_JMP_1
4205 BFD_RELOC_MMIX_JMP_2
4207 BFD_RELOC_MMIX_JMP_3
4209 These are relocations for the JMP instruction.
4211 BFD_RELOC_MMIX_ADDR19
4213 This is a relocation for a relative address as in a GETA instruction or
4216 BFD_RELOC_MMIX_ADDR27
4218 This is a relocation for a relative address as in a JMP instruction.
4220 BFD_RELOC_MMIX_REG_OR_BYTE
4222 This is a relocation for an instruction field that may be a general
4223 register or a value 0..255.
4227 This is a relocation for an instruction field that may be a general
4230 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4232 This is a relocation for two instruction fields holding a register and
4233 an offset, the equivalent of the relocation.
4235 BFD_RELOC_MMIX_LOCAL
4237 This relocation is an assertion that the expression is not allocated as
4238 a global register. It does not modify contents.
4241 BFD_RELOC_AVR_7_PCREL
4243 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4244 short offset into 7 bits.
4246 BFD_RELOC_AVR_13_PCREL
4248 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4249 short offset into 12 bits.
4253 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4254 program memory address) into 16 bits.
4256 BFD_RELOC_AVR_LO8_LDI
4258 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4259 data memory address) into 8 bit immediate value of LDI insn.
4261 BFD_RELOC_AVR_HI8_LDI
4263 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4264 of data memory address) into 8 bit immediate value of LDI insn.
4266 BFD_RELOC_AVR_HH8_LDI
4268 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4269 of program memory address) into 8 bit immediate value of LDI insn.
4271 BFD_RELOC_AVR_MS8_LDI
4273 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4274 of 32 bit value) into 8 bit immediate value of LDI insn.
4276 BFD_RELOC_AVR_LO8_LDI_NEG
4278 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4279 (usually data memory address) into 8 bit immediate value of SUBI insn.
4281 BFD_RELOC_AVR_HI8_LDI_NEG
4283 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4284 (high 8 bit of data memory address) into 8 bit immediate value of
4287 BFD_RELOC_AVR_HH8_LDI_NEG
4289 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4290 (most high 8 bit of program memory address) into 8 bit immediate value
4291 of LDI or SUBI insn.
4293 BFD_RELOC_AVR_MS8_LDI_NEG
4295 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4296 of 32 bit value) into 8 bit immediate value of LDI insn.
4298 BFD_RELOC_AVR_LO8_LDI_PM
4300 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4301 command address) into 8 bit immediate value of LDI insn.
4303 BFD_RELOC_AVR_LO8_LDI_GS
4305 This is a 16 bit reloc for the AVR that stores 8 bit value
4306 (command address) into 8 bit immediate value of LDI insn. If the address
4307 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4310 BFD_RELOC_AVR_HI8_LDI_PM
4312 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4313 of command address) into 8 bit immediate value of LDI insn.
4315 BFD_RELOC_AVR_HI8_LDI_GS
4317 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4318 of command address) into 8 bit immediate value of LDI insn. If the address
4319 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4322 BFD_RELOC_AVR_HH8_LDI_PM
4324 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4325 of command address) into 8 bit immediate value of LDI insn.
4327 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4329 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4330 (usually command address) into 8 bit immediate value of SUBI insn.
4332 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4334 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4335 (high 8 bit of 16 bit command address) into 8 bit immediate value
4338 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4340 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4341 (high 6 bit of 22 bit command address) into 8 bit immediate
4346 This is a 32 bit reloc for the AVR that stores 23 bit value
4351 This is a 16 bit reloc for the AVR that stores all needed bits
4352 for absolute addressing with ldi with overflow check to linktime
4356 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4359 BFD_RELOC_AVR_6_ADIW
4361 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4366 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4367 in .byte lo8(symbol)
4371 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4372 in .byte hi8(symbol)
4376 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4377 in .byte hhi8(symbol)
4382 BFD_RELOC_RL78_NEG16
4384 BFD_RELOC_RL78_NEG24
4386 BFD_RELOC_RL78_NEG32
4388 BFD_RELOC_RL78_16_OP
4390 BFD_RELOC_RL78_24_OP
4392 BFD_RELOC_RL78_32_OP
4400 BFD_RELOC_RL78_DIR3U_PCREL
4404 BFD_RELOC_RL78_GPRELB
4406 BFD_RELOC_RL78_GPRELW
4408 BFD_RELOC_RL78_GPRELL
4412 BFD_RELOC_RL78_OP_SUBTRACT
4414 BFD_RELOC_RL78_OP_NEG
4416 BFD_RELOC_RL78_OP_AND
4418 BFD_RELOC_RL78_OP_SHRA
4422 BFD_RELOC_RL78_ABS16
4424 BFD_RELOC_RL78_ABS16_REV
4426 BFD_RELOC_RL78_ABS32
4428 BFD_RELOC_RL78_ABS32_REV
4430 BFD_RELOC_RL78_ABS16U
4432 BFD_RELOC_RL78_ABS16UW
4434 BFD_RELOC_RL78_ABS16UL
4436 BFD_RELOC_RL78_RELAX
4444 Renesas RL78 Relocations.
4467 BFD_RELOC_RX_DIR3U_PCREL
4479 BFD_RELOC_RX_OP_SUBTRACT
4487 BFD_RELOC_RX_ABS16_REV
4491 BFD_RELOC_RX_ABS32_REV
4495 BFD_RELOC_RX_ABS16UW
4497 BFD_RELOC_RX_ABS16UL
4501 Renesas RX Relocations.
4514 32 bit PC relative PLT address.
4518 Copy symbol at runtime.
4520 BFD_RELOC_390_GLOB_DAT
4524 BFD_RELOC_390_JMP_SLOT
4528 BFD_RELOC_390_RELATIVE
4530 Adjust by program base.
4534 32 bit PC relative offset to GOT.
4540 BFD_RELOC_390_PC16DBL
4542 PC relative 16 bit shifted by 1.
4544 BFD_RELOC_390_PLT16DBL
4546 16 bit PC rel. PLT shifted by 1.
4548 BFD_RELOC_390_PC32DBL
4550 PC relative 32 bit shifted by 1.
4552 BFD_RELOC_390_PLT32DBL
4554 32 bit PC rel. PLT shifted by 1.
4556 BFD_RELOC_390_GOTPCDBL
4558 32 bit PC rel. GOT shifted by 1.
4566 64 bit PC relative PLT address.
4568 BFD_RELOC_390_GOTENT
4570 32 bit rel. offset to GOT entry.
4572 BFD_RELOC_390_GOTOFF64
4574 64 bit offset to GOT.
4576 BFD_RELOC_390_GOTPLT12
4578 12-bit offset to symbol-entry within GOT, with PLT handling.
4580 BFD_RELOC_390_GOTPLT16
4582 16-bit offset to symbol-entry within GOT, with PLT handling.
4584 BFD_RELOC_390_GOTPLT32
4586 32-bit offset to symbol-entry within GOT, with PLT handling.
4588 BFD_RELOC_390_GOTPLT64
4590 64-bit offset to symbol-entry within GOT, with PLT handling.
4592 BFD_RELOC_390_GOTPLTENT
4594 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
4596 BFD_RELOC_390_PLTOFF16
4598 16-bit rel. offset from the GOT to a PLT entry.
4600 BFD_RELOC_390_PLTOFF32
4602 32-bit rel. offset from the GOT to a PLT entry.
4604 BFD_RELOC_390_PLTOFF64
4606 64-bit rel. offset from the GOT to a PLT entry.
4609 BFD_RELOC_390_TLS_LOAD
4611 BFD_RELOC_390_TLS_GDCALL
4613 BFD_RELOC_390_TLS_LDCALL
4615 BFD_RELOC_390_TLS_GD32
4617 BFD_RELOC_390_TLS_GD64
4619 BFD_RELOC_390_TLS_GOTIE12
4621 BFD_RELOC_390_TLS_GOTIE32
4623 BFD_RELOC_390_TLS_GOTIE64
4625 BFD_RELOC_390_TLS_LDM32
4627 BFD_RELOC_390_TLS_LDM64
4629 BFD_RELOC_390_TLS_IE32
4631 BFD_RELOC_390_TLS_IE64
4633 BFD_RELOC_390_TLS_IEENT
4635 BFD_RELOC_390_TLS_LE32
4637 BFD_RELOC_390_TLS_LE64
4639 BFD_RELOC_390_TLS_LDO32
4641 BFD_RELOC_390_TLS_LDO64
4643 BFD_RELOC_390_TLS_DTPMOD
4645 BFD_RELOC_390_TLS_DTPOFF
4647 BFD_RELOC_390_TLS_TPOFF
4649 s390 tls relocations.
4656 BFD_RELOC_390_GOTPLT20
4658 BFD_RELOC_390_TLS_GOTIE20
4660 Long displacement extension.
4663 BFD_RELOC_SCORE_GPREL15
4666 Low 16 bit for load/store
4668 BFD_RELOC_SCORE_DUMMY2
4672 This is a 24-bit reloc with the right 1 bit assumed to be 0
4674 BFD_RELOC_SCORE_BRANCH
4676 This is a 19-bit reloc with the right 1 bit assumed to be 0
4678 BFD_RELOC_SCORE_IMM30
4680 This is a 32-bit reloc for 48-bit instructions.
4682 BFD_RELOC_SCORE_IMM32
4684 This is a 32-bit reloc for 48-bit instructions.
4686 BFD_RELOC_SCORE16_JMP
4688 This is a 11-bit reloc with the right 1 bit assumed to be 0
4690 BFD_RELOC_SCORE16_BRANCH
4692 This is a 8-bit reloc with the right 1 bit assumed to be 0
4694 BFD_RELOC_SCORE_BCMP
4696 This is a 9-bit reloc with the right 1 bit assumed to be 0
4698 BFD_RELOC_SCORE_GOT15
4700 BFD_RELOC_SCORE_GOT_LO16
4702 BFD_RELOC_SCORE_CALL15
4704 BFD_RELOC_SCORE_DUMMY_HI16
4706 Undocumented Score relocs
4711 Scenix IP2K - 9-bit register number / data address
4715 Scenix IP2K - 4-bit register/data bank number
4717 BFD_RELOC_IP2K_ADDR16CJP
4719 Scenix IP2K - low 13 bits of instruction word address
4721 BFD_RELOC_IP2K_PAGE3
4723 Scenix IP2K - high 3 bits of instruction word address
4725 BFD_RELOC_IP2K_LO8DATA
4727 BFD_RELOC_IP2K_HI8DATA
4729 BFD_RELOC_IP2K_EX8DATA
4731 Scenix IP2K - ext/low/high 8 bits of data address
4733 BFD_RELOC_IP2K_LO8INSN
4735 BFD_RELOC_IP2K_HI8INSN
4737 Scenix IP2K - low/high 8 bits of instruction word address
4739 BFD_RELOC_IP2K_PC_SKIP
4741 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
4745 Scenix IP2K - 16 bit word address in text section.
4747 BFD_RELOC_IP2K_FR_OFFSET
4749 Scenix IP2K - 7-bit sp or dp offset
4751 BFD_RELOC_VPE4KMATH_DATA
4753 BFD_RELOC_VPE4KMATH_INSN
4755 Scenix VPE4K coprocessor - data/insn-space addressing
4758 BFD_RELOC_VTABLE_INHERIT
4760 BFD_RELOC_VTABLE_ENTRY
4762 These two relocations are used by the linker to determine which of
4763 the entries in a C++ virtual function table are actually used. When
4764 the --gc-sections option is given, the linker will zero out the entries
4765 that are not used, so that the code for those functions need not be
4766 included in the output.
4768 VTABLE_INHERIT is a zero-space relocation used to describe to the
4769 linker the inheritance tree of a C++ virtual function table. The
4770 relocation's symbol should be the parent class' vtable, and the
4771 relocation should be located at the child vtable.
4773 VTABLE_ENTRY is a zero-space relocation that describes the use of a
4774 virtual function table entry. The reloc's symbol should refer to the
4775 table of the class mentioned in the code. Off of that base, an offset
4776 describes the entry that is being used. For Rela hosts, this offset
4777 is stored in the reloc's addend. For Rel hosts, we are forced to put
4778 this offset in the reloc's section offset.
4781 BFD_RELOC_IA64_IMM14
4783 BFD_RELOC_IA64_IMM22
4785 BFD_RELOC_IA64_IMM64
4787 BFD_RELOC_IA64_DIR32MSB
4789 BFD_RELOC_IA64_DIR32LSB
4791 BFD_RELOC_IA64_DIR64MSB
4793 BFD_RELOC_IA64_DIR64LSB
4795 BFD_RELOC_IA64_GPREL22
4797 BFD_RELOC_IA64_GPREL64I
4799 BFD_RELOC_IA64_GPREL32MSB
4801 BFD_RELOC_IA64_GPREL32LSB
4803 BFD_RELOC_IA64_GPREL64MSB
4805 BFD_RELOC_IA64_GPREL64LSB
4807 BFD_RELOC_IA64_LTOFF22
4809 BFD_RELOC_IA64_LTOFF64I
4811 BFD_RELOC_IA64_PLTOFF22
4813 BFD_RELOC_IA64_PLTOFF64I
4815 BFD_RELOC_IA64_PLTOFF64MSB
4817 BFD_RELOC_IA64_PLTOFF64LSB
4819 BFD_RELOC_IA64_FPTR64I
4821 BFD_RELOC_IA64_FPTR32MSB
4823 BFD_RELOC_IA64_FPTR32LSB
4825 BFD_RELOC_IA64_FPTR64MSB
4827 BFD_RELOC_IA64_FPTR64LSB
4829 BFD_RELOC_IA64_PCREL21B
4831 BFD_RELOC_IA64_PCREL21BI
4833 BFD_RELOC_IA64_PCREL21M
4835 BFD_RELOC_IA64_PCREL21F
4837 BFD_RELOC_IA64_PCREL22
4839 BFD_RELOC_IA64_PCREL60B
4841 BFD_RELOC_IA64_PCREL64I
4843 BFD_RELOC_IA64_PCREL32MSB
4845 BFD_RELOC_IA64_PCREL32LSB
4847 BFD_RELOC_IA64_PCREL64MSB
4849 BFD_RELOC_IA64_PCREL64LSB
4851 BFD_RELOC_IA64_LTOFF_FPTR22
4853 BFD_RELOC_IA64_LTOFF_FPTR64I
4855 BFD_RELOC_IA64_LTOFF_FPTR32MSB
4857 BFD_RELOC_IA64_LTOFF_FPTR32LSB
4859 BFD_RELOC_IA64_LTOFF_FPTR64MSB
4861 BFD_RELOC_IA64_LTOFF_FPTR64LSB
4863 BFD_RELOC_IA64_SEGREL32MSB
4865 BFD_RELOC_IA64_SEGREL32LSB
4867 BFD_RELOC_IA64_SEGREL64MSB
4869 BFD_RELOC_IA64_SEGREL64LSB
4871 BFD_RELOC_IA64_SECREL32MSB
4873 BFD_RELOC_IA64_SECREL32LSB
4875 BFD_RELOC_IA64_SECREL64MSB
4877 BFD_RELOC_IA64_SECREL64LSB
4879 BFD_RELOC_IA64_REL32MSB
4881 BFD_RELOC_IA64_REL32LSB
4883 BFD_RELOC_IA64_REL64MSB
4885 BFD_RELOC_IA64_REL64LSB
4887 BFD_RELOC_IA64_LTV32MSB
4889 BFD_RELOC_IA64_LTV32LSB
4891 BFD_RELOC_IA64_LTV64MSB
4893 BFD_RELOC_IA64_LTV64LSB
4895 BFD_RELOC_IA64_IPLTMSB
4897 BFD_RELOC_IA64_IPLTLSB
4901 BFD_RELOC_IA64_LTOFF22X
4903 BFD_RELOC_IA64_LDXMOV
4905 BFD_RELOC_IA64_TPREL14
4907 BFD_RELOC_IA64_TPREL22
4909 BFD_RELOC_IA64_TPREL64I
4911 BFD_RELOC_IA64_TPREL64MSB
4913 BFD_RELOC_IA64_TPREL64LSB
4915 BFD_RELOC_IA64_LTOFF_TPREL22
4917 BFD_RELOC_IA64_DTPMOD64MSB
4919 BFD_RELOC_IA64_DTPMOD64LSB
4921 BFD_RELOC_IA64_LTOFF_DTPMOD22
4923 BFD_RELOC_IA64_DTPREL14
4925 BFD_RELOC_IA64_DTPREL22
4927 BFD_RELOC_IA64_DTPREL64I
4929 BFD_RELOC_IA64_DTPREL32MSB
4931 BFD_RELOC_IA64_DTPREL32LSB
4933 BFD_RELOC_IA64_DTPREL64MSB
4935 BFD_RELOC_IA64_DTPREL64LSB
4937 BFD_RELOC_IA64_LTOFF_DTPREL22
4939 Intel IA64 Relocations.
4942 BFD_RELOC_M68HC11_HI8
4944 Motorola 68HC11 reloc.
4945 This is the 8 bit high part of an absolute address.
4947 BFD_RELOC_M68HC11_LO8
4949 Motorola 68HC11 reloc.
4950 This is the 8 bit low part of an absolute address.
4952 BFD_RELOC_M68HC11_3B
4954 Motorola 68HC11 reloc.
4955 This is the 3 bit of a value.
4957 BFD_RELOC_M68HC11_RL_JUMP
4959 Motorola 68HC11 reloc.
4960 This reloc marks the beginning of a jump/call instruction.
4961 It is used for linker relaxation to correctly identify beginning
4962 of instruction and change some branches to use PC-relative
4965 BFD_RELOC_M68HC11_RL_GROUP
4967 Motorola 68HC11 reloc.
4968 This reloc marks a group of several instructions that gcc generates
4969 and for which the linker relaxation pass can modify and/or remove
4972 BFD_RELOC_M68HC11_LO16
4974 Motorola 68HC11 reloc.
4975 This is the 16-bit lower part of an address. It is used for 'call'
4976 instruction to specify the symbol address without any special
4977 transformation (due to memory bank window).
4979 BFD_RELOC_M68HC11_PAGE
4981 Motorola 68HC11 reloc.
4982 This is a 8-bit reloc that specifies the page number of an address.
4983 It is used by 'call' instruction to specify the page number of
4986 BFD_RELOC_M68HC11_24
4988 Motorola 68HC11 reloc.
4989 This is a 24-bit reloc that represents the address with a 16-bit
4990 value and a 8-bit page number. The symbol address is transformed
4991 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
4993 BFD_RELOC_M68HC12_5B
4995 Motorola 68HC12 reloc.
4996 This is the 5 bits of a value.
4998 BFD_RELOC_XGATE_RL_JUMP
5000 Freescale XGATE reloc.
5001 This reloc marks the beginning of a bra/jal instruction.
5003 BFD_RELOC_XGATE_RL_GROUP
5005 Freescale XGATE reloc.
5006 This reloc marks a group of several instructions that gcc generates
5007 and for which the linker relaxation pass can modify and/or remove
5010 BFD_RELOC_XGATE_LO16
5012 Freescale XGATE reloc.
5013 This is the 16-bit lower part of an address. It is used for the '16-bit'
5016 BFD_RELOC_XGATE_GPAGE
5018 Freescale XGATE reloc.
5022 Freescale XGATE reloc.
5024 BFD_RELOC_XGATE_PCREL_9
5026 Freescale XGATE reloc.
5027 This is a 9-bit pc-relative reloc.
5029 BFD_RELOC_XGATE_PCREL_10
5031 Freescale XGATE reloc.
5032 This is a 10-bit pc-relative reloc.
5034 BFD_RELOC_XGATE_IMM8_LO
5036 Freescale XGATE reloc.
5037 This is the 16-bit lower part of an address. It is used for the '16-bit'
5040 BFD_RELOC_XGATE_IMM8_HI
5042 Freescale XGATE reloc.
5043 This is the 16-bit higher part of an address. It is used for the '16-bit'
5046 BFD_RELOC_XGATE_IMM3
5048 Freescale XGATE reloc.
5049 This is a 3-bit pc-relative reloc.
5051 BFD_RELOC_XGATE_IMM4
5053 Freescale XGATE reloc.
5054 This is a 4-bit pc-relative reloc.
5056 BFD_RELOC_XGATE_IMM5
5058 Freescale XGATE reloc.
5059 This is a 5-bit pc-relative reloc.
5063 BFD_RELOC_16C_NUM08_C
5067 BFD_RELOC_16C_NUM16_C
5071 BFD_RELOC_16C_NUM32_C
5073 BFD_RELOC_16C_DISP04
5075 BFD_RELOC_16C_DISP04_C
5077 BFD_RELOC_16C_DISP08
5079 BFD_RELOC_16C_DISP08_C
5081 BFD_RELOC_16C_DISP16
5083 BFD_RELOC_16C_DISP16_C
5085 BFD_RELOC_16C_DISP24
5087 BFD_RELOC_16C_DISP24_C
5089 BFD_RELOC_16C_DISP24a
5091 BFD_RELOC_16C_DISP24a_C
5095 BFD_RELOC_16C_REG04_C
5097 BFD_RELOC_16C_REG04a
5099 BFD_RELOC_16C_REG04a_C
5103 BFD_RELOC_16C_REG14_C
5107 BFD_RELOC_16C_REG16_C
5111 BFD_RELOC_16C_REG20_C
5115 BFD_RELOC_16C_ABS20_C
5119 BFD_RELOC_16C_ABS24_C
5123 BFD_RELOC_16C_IMM04_C
5127 BFD_RELOC_16C_IMM16_C
5131 BFD_RELOC_16C_IMM20_C
5135 BFD_RELOC_16C_IMM24_C
5139 BFD_RELOC_16C_IMM32_C
5141 NS CR16C Relocations.
5146 BFD_RELOC_CR16_NUM16
5148 BFD_RELOC_CR16_NUM32
5150 BFD_RELOC_CR16_NUM32a
5152 BFD_RELOC_CR16_REGREL0
5154 BFD_RELOC_CR16_REGREL4
5156 BFD_RELOC_CR16_REGREL4a
5158 BFD_RELOC_CR16_REGREL14
5160 BFD_RELOC_CR16_REGREL14a
5162 BFD_RELOC_CR16_REGREL16
5164 BFD_RELOC_CR16_REGREL20
5166 BFD_RELOC_CR16_REGREL20a
5168 BFD_RELOC_CR16_ABS20
5170 BFD_RELOC_CR16_ABS24
5176 BFD_RELOC_CR16_IMM16
5178 BFD_RELOC_CR16_IMM20
5180 BFD_RELOC_CR16_IMM24
5182 BFD_RELOC_CR16_IMM32
5184 BFD_RELOC_CR16_IMM32a
5186 BFD_RELOC_CR16_DISP4
5188 BFD_RELOC_CR16_DISP8
5190 BFD_RELOC_CR16_DISP16
5192 BFD_RELOC_CR16_DISP20
5194 BFD_RELOC_CR16_DISP24
5196 BFD_RELOC_CR16_DISP24a
5198 BFD_RELOC_CR16_SWITCH8
5200 BFD_RELOC_CR16_SWITCH16
5202 BFD_RELOC_CR16_SWITCH32
5204 BFD_RELOC_CR16_GOT_REGREL20
5206 BFD_RELOC_CR16_GOTC_REGREL20
5208 BFD_RELOC_CR16_GLOB_DAT
5210 NS CR16 Relocations.
5217 BFD_RELOC_CRX_REL8_CMP
5225 BFD_RELOC_CRX_REGREL12
5227 BFD_RELOC_CRX_REGREL22
5229 BFD_RELOC_CRX_REGREL28
5231 BFD_RELOC_CRX_REGREL32
5247 BFD_RELOC_CRX_SWITCH8
5249 BFD_RELOC_CRX_SWITCH16
5251 BFD_RELOC_CRX_SWITCH32
5256 BFD_RELOC_CRIS_BDISP8
5258 BFD_RELOC_CRIS_UNSIGNED_5
5260 BFD_RELOC_CRIS_SIGNED_6
5262 BFD_RELOC_CRIS_UNSIGNED_6
5264 BFD_RELOC_CRIS_SIGNED_8
5266 BFD_RELOC_CRIS_UNSIGNED_8
5268 BFD_RELOC_CRIS_SIGNED_16
5270 BFD_RELOC_CRIS_UNSIGNED_16
5272 BFD_RELOC_CRIS_LAPCQ_OFFSET
5274 BFD_RELOC_CRIS_UNSIGNED_4
5276 These relocs are only used within the CRIS assembler. They are not
5277 (at present) written to any object files.
5281 BFD_RELOC_CRIS_GLOB_DAT
5283 BFD_RELOC_CRIS_JUMP_SLOT
5285 BFD_RELOC_CRIS_RELATIVE
5287 Relocs used in ELF shared libraries for CRIS.
5289 BFD_RELOC_CRIS_32_GOT
5291 32-bit offset to symbol-entry within GOT.
5293 BFD_RELOC_CRIS_16_GOT
5295 16-bit offset to symbol-entry within GOT.
5297 BFD_RELOC_CRIS_32_GOTPLT
5299 32-bit offset to symbol-entry within GOT, with PLT handling.
5301 BFD_RELOC_CRIS_16_GOTPLT
5303 16-bit offset to symbol-entry within GOT, with PLT handling.
5305 BFD_RELOC_CRIS_32_GOTREL
5307 32-bit offset to symbol, relative to GOT.
5309 BFD_RELOC_CRIS_32_PLT_GOTREL
5311 32-bit offset to symbol with PLT entry, relative to GOT.
5313 BFD_RELOC_CRIS_32_PLT_PCREL
5315 32-bit offset to symbol with PLT entry, relative to this relocation.
5318 BFD_RELOC_CRIS_32_GOT_GD
5320 BFD_RELOC_CRIS_16_GOT_GD
5322 BFD_RELOC_CRIS_32_GD
5326 BFD_RELOC_CRIS_32_DTPREL
5328 BFD_RELOC_CRIS_16_DTPREL
5330 BFD_RELOC_CRIS_32_GOT_TPREL
5332 BFD_RELOC_CRIS_16_GOT_TPREL
5334 BFD_RELOC_CRIS_32_TPREL
5336 BFD_RELOC_CRIS_16_TPREL
5338 BFD_RELOC_CRIS_DTPMOD
5340 BFD_RELOC_CRIS_32_IE
5342 Relocs used in TLS code for CRIS.
5347 BFD_RELOC_860_GLOB_DAT
5349 BFD_RELOC_860_JUMP_SLOT
5351 BFD_RELOC_860_RELATIVE
5361 BFD_RELOC_860_SPLIT0
5365 BFD_RELOC_860_SPLIT1
5369 BFD_RELOC_860_SPLIT2
5373 BFD_RELOC_860_LOGOT0
5375 BFD_RELOC_860_SPGOT0
5377 BFD_RELOC_860_LOGOT1
5379 BFD_RELOC_860_SPGOT1
5381 BFD_RELOC_860_LOGOTOFF0
5383 BFD_RELOC_860_SPGOTOFF0
5385 BFD_RELOC_860_LOGOTOFF1
5387 BFD_RELOC_860_SPGOTOFF1
5389 BFD_RELOC_860_LOGOTOFF2
5391 BFD_RELOC_860_LOGOTOFF3
5395 BFD_RELOC_860_HIGHADJ
5399 BFD_RELOC_860_HAGOTOFF
5407 BFD_RELOC_860_HIGOTOFF
5409 Intel i860 Relocations.
5412 BFD_RELOC_OPENRISC_ABS_26
5414 BFD_RELOC_OPENRISC_REL_26
5416 OpenRISC Relocations.
5419 BFD_RELOC_H8_DIR16A8
5421 BFD_RELOC_H8_DIR16R8
5423 BFD_RELOC_H8_DIR24A8
5425 BFD_RELOC_H8_DIR24R8
5427 BFD_RELOC_H8_DIR32A16
5432 BFD_RELOC_XSTORMY16_REL_12
5434 BFD_RELOC_XSTORMY16_12
5436 BFD_RELOC_XSTORMY16_24
5438 BFD_RELOC_XSTORMY16_FPTR16
5440 Sony Xstormy16 Relocations.
5445 Self-describing complex relocations.
5457 Infineon Relocations.
5460 BFD_RELOC_VAX_GLOB_DAT
5462 BFD_RELOC_VAX_JMP_SLOT
5464 BFD_RELOC_VAX_RELATIVE
5466 Relocations used by VAX ELF.
5471 Morpho MT - 16 bit immediate relocation.
5475 Morpho MT - Hi 16 bits of an address.
5479 Morpho MT - Low 16 bits of an address.
5481 BFD_RELOC_MT_GNU_VTINHERIT
5483 Morpho MT - Used to tell the linker which vtable entries are used.
5485 BFD_RELOC_MT_GNU_VTENTRY
5487 Morpho MT - Used to tell the linker which vtable entries are used.
5489 BFD_RELOC_MT_PCINSN8
5491 Morpho MT - 8 bit immediate relocation.
5494 BFD_RELOC_MSP430_10_PCREL
5496 BFD_RELOC_MSP430_16_PCREL
5500 BFD_RELOC_MSP430_16_PCREL_BYTE
5502 BFD_RELOC_MSP430_16_BYTE
5504 BFD_RELOC_MSP430_2X_PCREL
5506 BFD_RELOC_MSP430_RL_PCREL
5508 msp430 specific relocation codes
5511 BFD_RELOC_IQ2000_OFFSET_16
5513 BFD_RELOC_IQ2000_OFFSET_21
5515 BFD_RELOC_IQ2000_UHI16
5520 BFD_RELOC_XTENSA_RTLD
5522 Special Xtensa relocation used only by PLT entries in ELF shared
5523 objects to indicate that the runtime linker should set the value
5524 to one of its own internal functions or data structures.
5526 BFD_RELOC_XTENSA_GLOB_DAT
5528 BFD_RELOC_XTENSA_JMP_SLOT
5530 BFD_RELOC_XTENSA_RELATIVE
5532 Xtensa relocations for ELF shared objects.
5534 BFD_RELOC_XTENSA_PLT
5536 Xtensa relocation used in ELF object files for symbols that may require
5537 PLT entries. Otherwise, this is just a generic 32-bit relocation.
5539 BFD_RELOC_XTENSA_DIFF8
5541 BFD_RELOC_XTENSA_DIFF16
5543 BFD_RELOC_XTENSA_DIFF32
5545 Xtensa relocations to mark the difference of two local symbols.
5546 These are only needed to support linker relaxation and can be ignored
5547 when not relaxing. The field is set to the value of the difference
5548 assuming no relaxation. The relocation encodes the position of the
5549 first symbol so the linker can determine whether to adjust the field
5552 BFD_RELOC_XTENSA_SLOT0_OP
5554 BFD_RELOC_XTENSA_SLOT1_OP
5556 BFD_RELOC_XTENSA_SLOT2_OP
5558 BFD_RELOC_XTENSA_SLOT3_OP
5560 BFD_RELOC_XTENSA_SLOT4_OP
5562 BFD_RELOC_XTENSA_SLOT5_OP
5564 BFD_RELOC_XTENSA_SLOT6_OP
5566 BFD_RELOC_XTENSA_SLOT7_OP
5568 BFD_RELOC_XTENSA_SLOT8_OP
5570 BFD_RELOC_XTENSA_SLOT9_OP
5572 BFD_RELOC_XTENSA_SLOT10_OP
5574 BFD_RELOC_XTENSA_SLOT11_OP
5576 BFD_RELOC_XTENSA_SLOT12_OP
5578 BFD_RELOC_XTENSA_SLOT13_OP
5580 BFD_RELOC_XTENSA_SLOT14_OP
5582 Generic Xtensa relocations for instruction operands. Only the slot
5583 number is encoded in the relocation. The relocation applies to the
5584 last PC-relative immediate operand, or if there are no PC-relative
5585 immediates, to the last immediate operand.
5587 BFD_RELOC_XTENSA_SLOT0_ALT
5589 BFD_RELOC_XTENSA_SLOT1_ALT
5591 BFD_RELOC_XTENSA_SLOT2_ALT
5593 BFD_RELOC_XTENSA_SLOT3_ALT
5595 BFD_RELOC_XTENSA_SLOT4_ALT
5597 BFD_RELOC_XTENSA_SLOT5_ALT
5599 BFD_RELOC_XTENSA_SLOT6_ALT
5601 BFD_RELOC_XTENSA_SLOT7_ALT
5603 BFD_RELOC_XTENSA_SLOT8_ALT
5605 BFD_RELOC_XTENSA_SLOT9_ALT
5607 BFD_RELOC_XTENSA_SLOT10_ALT
5609 BFD_RELOC_XTENSA_SLOT11_ALT
5611 BFD_RELOC_XTENSA_SLOT12_ALT
5613 BFD_RELOC_XTENSA_SLOT13_ALT
5615 BFD_RELOC_XTENSA_SLOT14_ALT
5617 Alternate Xtensa relocations. Only the slot is encoded in the
5618 relocation. The meaning of these relocations is opcode-specific.
5620 BFD_RELOC_XTENSA_OP0
5622 BFD_RELOC_XTENSA_OP1
5624 BFD_RELOC_XTENSA_OP2
5626 Xtensa relocations for backward compatibility. These have all been
5627 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
5629 BFD_RELOC_XTENSA_ASM_EXPAND
5631 Xtensa relocation to mark that the assembler expanded the
5632 instructions from an original target. The expansion size is
5633 encoded in the reloc size.
5635 BFD_RELOC_XTENSA_ASM_SIMPLIFY
5637 Xtensa relocation to mark that the linker should simplify
5638 assembler-expanded instructions. This is commonly used
5639 internally by the linker after analysis of a
5640 BFD_RELOC_XTENSA_ASM_EXPAND.
5642 BFD_RELOC_XTENSA_TLSDESC_FN
5644 BFD_RELOC_XTENSA_TLSDESC_ARG
5646 BFD_RELOC_XTENSA_TLS_DTPOFF
5648 BFD_RELOC_XTENSA_TLS_TPOFF
5650 BFD_RELOC_XTENSA_TLS_FUNC
5652 BFD_RELOC_XTENSA_TLS_ARG
5654 BFD_RELOC_XTENSA_TLS_CALL
5656 Xtensa TLS relocations.
5661 8 bit signed offset in (ix+d) or (iy+d).
5679 BFD_RELOC_LM32_BRANCH
5681 BFD_RELOC_LM32_16_GOT
5683 BFD_RELOC_LM32_GOTOFF_HI16
5685 BFD_RELOC_LM32_GOTOFF_LO16
5689 BFD_RELOC_LM32_GLOB_DAT
5691 BFD_RELOC_LM32_JMP_SLOT
5693 BFD_RELOC_LM32_RELATIVE
5695 Lattice Mico32 relocations.
5698 BFD_RELOC_MACH_O_SECTDIFF
5700 Difference between two section addreses. Must be followed by a
5701 BFD_RELOC_MACH_O_PAIR.
5703 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
5705 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
5707 BFD_RELOC_MACH_O_PAIR
5709 Pair of relocation. Contains the first symbol.
5712 BFD_RELOC_MACH_O_X86_64_BRANCH32
5714 BFD_RELOC_MACH_O_X86_64_BRANCH8
5716 PCREL relocations. They are marked as branch to create PLT entry if
5719 BFD_RELOC_MACH_O_X86_64_GOT
5721 Used when referencing a GOT entry.
5723 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
5725 Used when loading a GOT entry with movq. It is specially marked so that
5726 the linker could optimize the movq to a leaq if possible.
5728 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
5730 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
5732 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
5734 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
5736 BFD_RELOC_MACH_O_X86_64_PCREL32_1
5738 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
5740 BFD_RELOC_MACH_O_X86_64_PCREL32_2
5742 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
5744 BFD_RELOC_MACH_O_X86_64_PCREL32_4
5746 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
5749 BFD_RELOC_MICROBLAZE_32_LO
5751 This is a 32 bit reloc for the microblaze that stores the
5752 low 16 bits of a value
5754 BFD_RELOC_MICROBLAZE_32_LO_PCREL
5756 This is a 32 bit pc-relative reloc for the microblaze that
5757 stores the low 16 bits of a value
5759 BFD_RELOC_MICROBLAZE_32_ROSDA
5761 This is a 32 bit reloc for the microblaze that stores a
5762 value relative to the read-only small data area anchor
5764 BFD_RELOC_MICROBLAZE_32_RWSDA
5766 This is a 32 bit reloc for the microblaze that stores a
5767 value relative to the read-write small data area anchor
5769 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
5771 This is a 32 bit reloc for the microblaze to handle
5772 expressions of the form "Symbol Op Symbol"
5774 BFD_RELOC_MICROBLAZE_64_NONE
5776 This is a 64 bit reloc that stores the 32 bit pc relative
5777 value in two words (with an imm instruction). No relocation is
5778 done here - only used for relaxing
5780 BFD_RELOC_MICROBLAZE_64_GOTPC
5782 This is a 64 bit reloc that stores the 32 bit pc relative
5783 value in two words (with an imm instruction). The relocation is
5784 PC-relative GOT offset
5786 BFD_RELOC_MICROBLAZE_64_GOT
5788 This is a 64 bit reloc that stores the 32 bit pc relative
5789 value in two words (with an imm instruction). The relocation is
5792 BFD_RELOC_MICROBLAZE_64_PLT
5794 This is a 64 bit reloc that stores the 32 bit pc relative
5795 value in two words (with an imm instruction). The relocation is
5796 PC-relative offset into PLT
5798 BFD_RELOC_MICROBLAZE_64_GOTOFF
5800 This is a 64 bit reloc that stores the 32 bit GOT relative
5801 value in two words (with an imm instruction). The relocation is
5802 relative offset from _GLOBAL_OFFSET_TABLE_
5804 BFD_RELOC_MICROBLAZE_32_GOTOFF
5806 This is a 32 bit reloc that stores the 32 bit GOT relative
5807 value in a word. The relocation is relative offset from
5808 _GLOBAL_OFFSET_TABLE_
5810 BFD_RELOC_MICROBLAZE_COPY
5812 This is used to tell the dynamic linker to copy the value out of
5813 the dynamic object into the runtime process image.
5816 BFD_RELOC_TILEPRO_COPY
5818 BFD_RELOC_TILEPRO_GLOB_DAT
5820 BFD_RELOC_TILEPRO_JMP_SLOT
5822 BFD_RELOC_TILEPRO_RELATIVE
5824 BFD_RELOC_TILEPRO_BROFF_X1
5826 BFD_RELOC_TILEPRO_JOFFLONG_X1
5828 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
5830 BFD_RELOC_TILEPRO_IMM8_X0
5832 BFD_RELOC_TILEPRO_IMM8_Y0
5834 BFD_RELOC_TILEPRO_IMM8_X1
5836 BFD_RELOC_TILEPRO_IMM8_Y1
5838 BFD_RELOC_TILEPRO_DEST_IMM8_X1
5840 BFD_RELOC_TILEPRO_MT_IMM15_X1
5842 BFD_RELOC_TILEPRO_MF_IMM15_X1
5844 BFD_RELOC_TILEPRO_IMM16_X0
5846 BFD_RELOC_TILEPRO_IMM16_X1
5848 BFD_RELOC_TILEPRO_IMM16_X0_LO
5850 BFD_RELOC_TILEPRO_IMM16_X1_LO
5852 BFD_RELOC_TILEPRO_IMM16_X0_HI
5854 BFD_RELOC_TILEPRO_IMM16_X1_HI
5856 BFD_RELOC_TILEPRO_IMM16_X0_HA
5858 BFD_RELOC_TILEPRO_IMM16_X1_HA
5860 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
5862 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
5864 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
5866 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
5868 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
5870 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
5872 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
5874 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
5876 BFD_RELOC_TILEPRO_IMM16_X0_GOT
5878 BFD_RELOC_TILEPRO_IMM16_X1_GOT
5880 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
5882 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
5884 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
5886 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
5888 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
5890 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
5892 BFD_RELOC_TILEPRO_MMSTART_X0
5894 BFD_RELOC_TILEPRO_MMEND_X0
5896 BFD_RELOC_TILEPRO_MMSTART_X1
5898 BFD_RELOC_TILEPRO_MMEND_X1
5900 BFD_RELOC_TILEPRO_SHAMT_X0
5902 BFD_RELOC_TILEPRO_SHAMT_X1
5904 BFD_RELOC_TILEPRO_SHAMT_Y0
5906 BFD_RELOC_TILEPRO_SHAMT_Y1
5908 BFD_RELOC_TILEPRO_TLS_GD_CALL
5910 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
5912 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
5914 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
5916 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
5918 BFD_RELOC_TILEPRO_TLS_IE_LOAD
5920 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
5922 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
5924 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
5926 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
5928 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
5930 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
5932 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
5934 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
5936 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
5938 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
5940 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
5942 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
5944 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
5946 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
5948 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
5950 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
5952 BFD_RELOC_TILEPRO_TLS_DTPMOD32
5954 BFD_RELOC_TILEPRO_TLS_DTPOFF32
5956 BFD_RELOC_TILEPRO_TLS_TPOFF32
5958 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
5960 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
5962 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
5964 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
5966 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
5968 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
5970 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
5972 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
5974 Tilera TILEPro Relocations.
5977 BFD_RELOC_TILEGX_HW0
5979 BFD_RELOC_TILEGX_HW1
5981 BFD_RELOC_TILEGX_HW2
5983 BFD_RELOC_TILEGX_HW3
5985 BFD_RELOC_TILEGX_HW0_LAST
5987 BFD_RELOC_TILEGX_HW1_LAST
5989 BFD_RELOC_TILEGX_HW2_LAST
5991 BFD_RELOC_TILEGX_COPY
5993 BFD_RELOC_TILEGX_GLOB_DAT
5995 BFD_RELOC_TILEGX_JMP_SLOT
5997 BFD_RELOC_TILEGX_RELATIVE
5999 BFD_RELOC_TILEGX_BROFF_X1
6001 BFD_RELOC_TILEGX_JUMPOFF_X1
6003 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
6005 BFD_RELOC_TILEGX_IMM8_X0
6007 BFD_RELOC_TILEGX_IMM8_Y0
6009 BFD_RELOC_TILEGX_IMM8_X1
6011 BFD_RELOC_TILEGX_IMM8_Y1
6013 BFD_RELOC_TILEGX_DEST_IMM8_X1
6015 BFD_RELOC_TILEGX_MT_IMM14_X1
6017 BFD_RELOC_TILEGX_MF_IMM14_X1
6019 BFD_RELOC_TILEGX_MMSTART_X0
6021 BFD_RELOC_TILEGX_MMEND_X0
6023 BFD_RELOC_TILEGX_SHAMT_X0
6025 BFD_RELOC_TILEGX_SHAMT_X1
6027 BFD_RELOC_TILEGX_SHAMT_Y0
6029 BFD_RELOC_TILEGX_SHAMT_Y1
6031 BFD_RELOC_TILEGX_IMM16_X0_HW0
6033 BFD_RELOC_TILEGX_IMM16_X1_HW0
6035 BFD_RELOC_TILEGX_IMM16_X0_HW1
6037 BFD_RELOC_TILEGX_IMM16_X1_HW1
6039 BFD_RELOC_TILEGX_IMM16_X0_HW2
6041 BFD_RELOC_TILEGX_IMM16_X1_HW2
6043 BFD_RELOC_TILEGX_IMM16_X0_HW3
6045 BFD_RELOC_TILEGX_IMM16_X1_HW3
6047 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
6049 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
6051 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
6053 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
6055 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
6057 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
6059 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
6061 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
6063 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
6065 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
6067 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
6069 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
6071 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
6073 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
6075 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
6077 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
6079 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
6081 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
6083 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
6085 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
6087 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
6089 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
6091 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
6093 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
6095 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
6097 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
6099 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
6101 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
6103 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
6105 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
6107 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
6109 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
6111 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
6113 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
6115 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
6117 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
6119 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
6121 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
6123 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
6125 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
6127 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
6129 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
6131 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
6133 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
6135 BFD_RELOC_TILEGX_TLS_DTPMOD64
6137 BFD_RELOC_TILEGX_TLS_DTPOFF64
6139 BFD_RELOC_TILEGX_TLS_TPOFF64
6141 BFD_RELOC_TILEGX_TLS_DTPMOD32
6143 BFD_RELOC_TILEGX_TLS_DTPOFF32
6145 BFD_RELOC_TILEGX_TLS_TPOFF32
6147 BFD_RELOC_TILEGX_TLS_GD_CALL
6149 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
6151 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
6153 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
6155 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
6157 BFD_RELOC_TILEGX_TLS_IE_LOAD
6159 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
6161 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
6163 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
6165 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
6167 Tilera TILE-Gx Relocations.
6170 BFD_RELOC_EPIPHANY_SIMM8
6172 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
6174 BFD_RELOC_EPIPHANY_SIMM24
6176 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
6178 BFD_RELOC_EPIPHANY_HIGH
6180 Adapteva EPIPHANY - 16 most-significant bits of absolute address
6182 BFD_RELOC_EPIPHANY_LOW
6184 Adapteva EPIPHANY - 16 least-significant bits of absolute address
6186 BFD_RELOC_EPIPHANY_SIMM11
6188 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
6190 BFD_RELOC_EPIPHANY_IMM11
6192 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
6194 BFD_RELOC_EPIPHANY_IMM8
6196 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
6203 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
6208 bfd_reloc_type_lookup
6209 bfd_reloc_name_lookup
6212 reloc_howto_type *bfd_reloc_type_lookup
6213 (bfd *abfd, bfd_reloc_code_real_type code);
6214 reloc_howto_type *bfd_reloc_name_lookup
6215 (bfd *abfd, const char *reloc_name);
6218 Return a pointer to a howto structure which, when
6219 invoked, will perform the relocation @var{code} on data from the
6225 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
6227 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
6231 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
6233 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
6236 static reloc_howto_type bfd_howto_32 =
6237 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
6241 bfd_default_reloc_type_lookup
6244 reloc_howto_type *bfd_default_reloc_type_lookup
6245 (bfd *abfd, bfd_reloc_code_real_type code);
6248 Provides a default relocation lookup routine for any architecture.
6253 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
6257 case BFD_RELOC_CTOR:
6258 /* The type of reloc used in a ctor, which will be as wide as the
6259 address - so either a 64, 32, or 16 bitter. */
6260 switch (bfd_arch_bits_per_address (abfd))
6265 return &bfd_howto_32;
6279 bfd_get_reloc_code_name
6282 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
6285 Provides a printable name for the supplied relocation code.
6286 Useful mainly for printing error messages.
6290 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
6292 if (code > BFD_RELOC_UNUSED)
6294 return bfd_reloc_code_real_names[code];
6299 bfd_generic_relax_section
6302 bfd_boolean bfd_generic_relax_section
6305 struct bfd_link_info *,
6309 Provides default handling for relaxing for back ends which
6314 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
6315 asection *section ATTRIBUTE_UNUSED,
6316 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
6319 if (link_info->relocatable)
6320 (*link_info->callbacks->einfo)
6321 (_("%P%F: --relax and -r may not be used together\n"));
6329 bfd_generic_gc_sections
6332 bfd_boolean bfd_generic_gc_sections
6333 (bfd *, struct bfd_link_info *);
6336 Provides default handling for relaxing for back ends which
6337 don't do section gc -- i.e., does nothing.
6341 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
6342 struct bfd_link_info *info ATTRIBUTE_UNUSED)
6349 bfd_generic_lookup_section_flags
6352 void bfd_generic_lookup_section_flags
6353 (struct bfd_link_info *, struct flag_info *);
6356 Provides default handling for section flags lookup
6357 -- i.e., does nothing.
6361 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
6362 struct flag_info *flaginfo)
6364 if (flaginfo != NULL)
6366 (*_bfd_error_handler) (_("INPUT_SECTION_FLAGS are not supported.\n"));
6373 bfd_generic_merge_sections
6376 bfd_boolean bfd_generic_merge_sections
6377 (bfd *, struct bfd_link_info *);
6380 Provides default handling for SEC_MERGE section merging for back ends
6381 which don't have SEC_MERGE support -- i.e., does nothing.
6385 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
6386 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
6393 bfd_generic_get_relocated_section_contents
6396 bfd_byte *bfd_generic_get_relocated_section_contents
6398 struct bfd_link_info *link_info,
6399 struct bfd_link_order *link_order,
6401 bfd_boolean relocatable,
6405 Provides default handling of relocation effort for back ends
6406 which can't be bothered to do it efficiently.
6411 bfd_generic_get_relocated_section_contents (bfd *abfd,
6412 struct bfd_link_info *link_info,
6413 struct bfd_link_order *link_order,
6415 bfd_boolean relocatable,
6418 bfd *input_bfd = link_order->u.indirect.section->owner;
6419 asection *input_section = link_order->u.indirect.section;
6421 arelent **reloc_vector;
6424 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
6428 /* Read in the section. */
6429 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
6432 if (reloc_size == 0)
6435 reloc_vector = (arelent **) bfd_malloc (reloc_size);
6436 if (reloc_vector == NULL)
6439 reloc_count = bfd_canonicalize_reloc (input_bfd,
6443 if (reloc_count < 0)
6446 if (reloc_count > 0)
6449 for (parent = reloc_vector; *parent != NULL; parent++)
6451 char *error_message = NULL;
6453 bfd_reloc_status_type r;
6455 symbol = *(*parent)->sym_ptr_ptr;
6456 if (symbol->section && discarded_section (symbol->section))
6459 static reloc_howto_type none_howto
6460 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
6461 "unused", FALSE, 0, 0, FALSE);
6463 p = data + (*parent)->address * bfd_octets_per_byte (input_bfd);
6464 _bfd_clear_contents ((*parent)->howto, input_bfd, input_section,
6466 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
6467 (*parent)->addend = 0;
6468 (*parent)->howto = &none_howto;
6472 r = bfd_perform_relocation (input_bfd,
6476 relocatable ? abfd : NULL,
6481 asection *os = input_section->output_section;
6483 /* A partial link, so keep the relocs. */
6484 os->orelocation[os->reloc_count] = *parent;
6488 if (r != bfd_reloc_ok)
6492 case bfd_reloc_undefined:
6493 if (!((*link_info->callbacks->undefined_symbol)
6494 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
6495 input_bfd, input_section, (*parent)->address,
6499 case bfd_reloc_dangerous:
6500 BFD_ASSERT (error_message != NULL);
6501 if (!((*link_info->callbacks->reloc_dangerous)
6502 (link_info, error_message, input_bfd, input_section,
6503 (*parent)->address)))
6506 case bfd_reloc_overflow:
6507 if (!((*link_info->callbacks->reloc_overflow)
6509 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
6510 (*parent)->howto->name, (*parent)->addend,
6511 input_bfd, input_section, (*parent)->address)))
6514 case bfd_reloc_outofrange:
6516 This error can result when processing some partially
6517 complete binaries. Do not abort, but issue an error
6519 link_info->callbacks->einfo
6520 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
6521 abfd, input_section, * parent);
6533 free (reloc_vector);
6537 free (reloc_vector);