1 /* MSP430-specific support for 32-bit ELF
2 Copyright (C) 2002-2017 Free Software Foundation, Inc.
3 Contributed by Dmitry Diky <diwil@mail.ru>
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
24 #include "libiberty.h"
27 #include "elf/msp430.h"
29 static bfd_reloc_status_type
30 rl78_sym_diff_handler (bfd * abfd,
32 asymbol * sym ATTRIBUTE_UNUSED,
33 void * addr ATTRIBUTE_UNUSED,
35 bfd * out_bfd ATTRIBUTE_UNUSED,
36 char ** error_message ATTRIBUTE_UNUSED)
39 octets = reloc->address * bfd_octets_per_byte (abfd);
41 /* Catch the case where bfd_install_relocation would return
42 bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very
43 small section. It does not actually matter if this happens because all
44 that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses
45 this value, and it is that reloc that must fit into the section.
47 This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */
48 if ((octets + bfd_get_reloc_size (reloc->howto))
49 > bfd_get_section_limit_octets (abfd, input_sec))
51 return bfd_reloc_continue;
54 static reloc_howto_type elf_msp430_howto_table[] =
56 HOWTO (R_MSP430_NONE, /* type */
58 3, /* size (0 = byte, 1 = short, 2 = long) */
60 FALSE, /* pc_relative */
62 complain_overflow_dont,/* complain_on_overflow */
63 bfd_elf_generic_reloc, /* special_function */
64 "R_MSP430_NONE", /* name */
65 FALSE, /* partial_inplace */
68 FALSE), /* pcrel_offset */
70 HOWTO (R_MSP430_32, /* type */
72 2, /* size (0 = byte, 1 = short, 2 = long) */
74 FALSE, /* pc_relative */
76 complain_overflow_bitfield,/* complain_on_overflow */
77 bfd_elf_generic_reloc, /* special_function */
78 "R_MSP430_32", /* name */
79 FALSE, /* partial_inplace */
80 0xffffffff, /* src_mask */
81 0xffffffff, /* dst_mask */
82 FALSE), /* pcrel_offset */
84 /* A 10 bit PC relative relocation. */
85 HOWTO (R_MSP430_10_PCREL, /* type */
87 1, /* size (0 = byte, 1 = short, 2 = long) */
89 TRUE, /* pc_relative */
91 complain_overflow_bitfield,/* complain_on_overflow */
92 bfd_elf_generic_reloc, /* special_function */
93 "R_MSP430_10_PCREL", /* name */
94 FALSE, /* partial_inplace */
97 TRUE), /* pcrel_offset */
99 /* A 16 bit absolute relocation. */
100 HOWTO (R_MSP430_16, /* type */
102 1, /* size (0 = byte, 1 = short, 2 = long) */
104 FALSE, /* pc_relative */
106 complain_overflow_dont,/* complain_on_overflow */
107 bfd_elf_generic_reloc, /* special_function */
108 "R_MSP430_16", /* name */
109 FALSE, /* partial_inplace */
111 0xffff, /* dst_mask */
112 FALSE), /* pcrel_offset */
114 /* A 16 bit PC relative relocation for command address. */
115 HOWTO (R_MSP430_16_PCREL, /* type */
117 1, /* size (0 = byte, 1 = short, 2 = long) */
119 TRUE, /* pc_relative */
121 complain_overflow_dont,/* complain_on_overflow */
122 bfd_elf_generic_reloc, /* special_function */
123 "R_MSP430_16_PCREL", /* name */
124 FALSE, /* partial_inplace */
126 0xffff, /* dst_mask */
127 TRUE), /* pcrel_offset */
129 /* A 16 bit absolute relocation, byte operations. */
130 HOWTO (R_MSP430_16_BYTE, /* type */
132 1, /* size (0 = byte, 1 = short, 2 = long) */
134 FALSE, /* pc_relative */
136 complain_overflow_dont,/* complain_on_overflow */
137 bfd_elf_generic_reloc, /* special_function */
138 "R_MSP430_16_BYTE", /* name */
139 FALSE, /* partial_inplace */
140 0xffff, /* src_mask */
141 0xffff, /* dst_mask */
142 FALSE), /* pcrel_offset */
144 /* A 16 bit absolute relocation for command address. */
145 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */
147 1, /* size (0 = byte, 1 = short, 2 = long) */
149 TRUE, /* pc_relative */
151 complain_overflow_dont,/* complain_on_overflow */
152 bfd_elf_generic_reloc, /* special_function */
153 "R_MSP430_16_PCREL_BYTE",/* name */
154 FALSE, /* partial_inplace */
155 0xffff, /* src_mask */
156 0xffff, /* dst_mask */
157 TRUE), /* pcrel_offset */
159 /* A 10 bit PC relative relocation for complicated polymorphs. */
160 HOWTO (R_MSP430_2X_PCREL, /* type */
162 2, /* size (0 = byte, 1 = short, 2 = long) */
164 TRUE, /* pc_relative */
166 complain_overflow_bitfield,/* complain_on_overflow */
167 bfd_elf_generic_reloc, /* special_function */
168 "R_MSP430_2X_PCREL", /* name */
169 FALSE, /* partial_inplace */
170 0x3ff, /* src_mask */
171 0x3ff, /* dst_mask */
172 TRUE), /* pcrel_offset */
174 /* A 16 bit relaxable relocation for command address. */
175 HOWTO (R_MSP430_RL_PCREL, /* type */
177 1, /* size (0 = byte, 1 = short, 2 = long) */
179 TRUE, /* pc_relative */
181 complain_overflow_dont,/* complain_on_overflow */
182 bfd_elf_generic_reloc, /* special_function */
183 "R_MSP430_RL_PCREL", /* name */
184 FALSE, /* partial_inplace */
186 0xffff, /* dst_mask */
187 TRUE) /* pcrel_offset */
189 /* A 8-bit absolute relocation. */
190 , HOWTO (R_MSP430_8, /* type */
192 0, /* size (0 = byte, 1 = short, 2 = long) */
194 FALSE, /* pc_relative */
196 complain_overflow_dont,/* complain_on_overflow */
197 bfd_elf_generic_reloc, /* special_function */
198 "R_MSP430_8", /* name */
199 FALSE, /* partial_inplace */
201 0xffff, /* dst_mask */
202 FALSE), /* pcrel_offset */
204 /* Together with a following reloc, allows for the difference
205 between two symbols to be the real addend of the second reloc. */
206 HOWTO (R_MSP430_SYM_DIFF, /* type */
208 2, /* size (0 = byte, 1 = short, 2 = long) */
210 FALSE, /* pc_relative */
212 complain_overflow_dont,/* complain_on_overflow */
213 rl78_sym_diff_handler, /* special handler. */
214 "R_MSP430_SYM_DIFF", /* name */
215 FALSE, /* partial_inplace */
216 0xffffffff, /* src_mask */
217 0xffffffff, /* dst_mask */
218 FALSE) /* pcrel_offset */
221 static reloc_howto_type elf_msp430x_howto_table[] =
223 HOWTO (R_MSP430_NONE, /* type */
225 3, /* size (0 = byte, 1 = short, 2 = long) */
227 FALSE, /* pc_relative */
229 complain_overflow_dont,/* complain_on_overflow */
230 bfd_elf_generic_reloc, /* special_function */
231 "R_MSP430_NONE", /* name */
232 FALSE, /* partial_inplace */
235 FALSE), /* pcrel_offset */
237 HOWTO (R_MSP430_ABS32, /* type */
239 2, /* size (0 = byte, 1 = short, 2 = long) */
241 FALSE, /* pc_relative */
243 complain_overflow_bitfield,/* complain_on_overflow */
244 bfd_elf_generic_reloc, /* special_function */
245 "R_MSP430_ABS32", /* name */
246 FALSE, /* partial_inplace */
247 0xffffffff, /* src_mask */
248 0xffffffff, /* dst_mask */
249 FALSE), /* pcrel_offset */
251 HOWTO (R_MSP430_ABS16, /* type */
253 1, /* size (0 = byte, 1 = short, 2 = long) */
255 FALSE, /* pc_relative */
257 complain_overflow_dont,/* complain_on_overflow */
258 bfd_elf_generic_reloc, /* special_function */
259 "R_MSP430_ABS16", /* name */
260 FALSE, /* partial_inplace */
262 0xffff, /* dst_mask */
263 FALSE), /* pcrel_offset */
265 HOWTO (R_MSP430_ABS8, /* type */
267 0, /* size (0 = byte, 1 = short, 2 = long) */
269 FALSE, /* pc_relative */
271 complain_overflow_bitfield,/* complain_on_overflow */
272 bfd_elf_generic_reloc, /* special_function */
273 "R_MSP430_ABS8", /* name */
274 FALSE, /* partial_inplace */
277 FALSE), /* pcrel_offset */
279 HOWTO (R_MSP430_PCR16, /* type */
281 1, /* size (0 = byte, 1 = short, 2 = long) */
283 TRUE, /* pc_relative */
285 complain_overflow_dont,/* complain_on_overflow */
286 bfd_elf_generic_reloc, /* special_function */
287 "R_MSP430_PCR16", /* name */
288 FALSE, /* partial_inplace */
290 0xffff, /* dst_mask */
291 TRUE), /* pcrel_offset */
293 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */
295 2, /* size (0 = byte, 1 = short, 2 = long) */
297 TRUE, /* pc_relative */
299 complain_overflow_dont,/* complain_on_overflow */
300 bfd_elf_generic_reloc, /* special_function */
301 "R_MSP430X_PCR20_EXT_SRC",/* name */
302 FALSE, /* partial_inplace */
304 0xffff, /* dst_mask */
305 TRUE), /* pcrel_offset */
307 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */
309 2, /* size (0 = byte, 1 = short, 2 = long) */
311 TRUE, /* pc_relative */
313 complain_overflow_dont,/* complain_on_overflow */
314 bfd_elf_generic_reloc, /* special_function */
315 "R_MSP430X_PCR20_EXT_DST",/* name */
316 FALSE, /* partial_inplace */
318 0xffff, /* dst_mask */
319 TRUE), /* pcrel_offset */
321 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */
323 2, /* size (0 = byte, 1 = short, 2 = long) */
325 TRUE, /* pc_relative */
327 complain_overflow_dont,/* complain_on_overflow */
328 bfd_elf_generic_reloc, /* special_function */
329 "R_MSP430X_PCR20_EXT_ODST",/* name */
330 FALSE, /* partial_inplace */
332 0xffff, /* dst_mask */
333 TRUE), /* pcrel_offset */
335 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */
337 2, /* size (0 = byte, 1 = short, 2 = long) */
339 TRUE, /* pc_relative */
341 complain_overflow_dont,/* complain_on_overflow */
342 bfd_elf_generic_reloc, /* special_function */
343 "R_MSP430X_ABS20_EXT_SRC",/* name */
344 FALSE, /* partial_inplace */
346 0xffff, /* dst_mask */
347 TRUE), /* pcrel_offset */
349 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */
351 2, /* size (0 = byte, 1 = short, 2 = long) */
353 TRUE, /* pc_relative */
355 complain_overflow_dont,/* complain_on_overflow */
356 bfd_elf_generic_reloc, /* special_function */
357 "R_MSP430X_ABS20_EXT_DST",/* name */
358 FALSE, /* partial_inplace */
360 0xffff, /* dst_mask */
361 TRUE), /* pcrel_offset */
363 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */
365 2, /* size (0 = byte, 1 = short, 2 = long) */
367 TRUE, /* pc_relative */
369 complain_overflow_dont,/* complain_on_overflow */
370 bfd_elf_generic_reloc, /* special_function */
371 "R_MSP430X_ABS20_EXT_ODST",/* name */
372 FALSE, /* partial_inplace */
374 0xffff, /* dst_mask */
375 TRUE), /* pcrel_offset */
377 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */
379 2, /* size (0 = byte, 1 = short, 2 = long) */
381 TRUE, /* pc_relative */
383 complain_overflow_dont,/* complain_on_overflow */
384 bfd_elf_generic_reloc, /* special_function */
385 "R_MSP430X_ABS20_ADR_SRC",/* name */
386 FALSE, /* partial_inplace */
388 0xffff, /* dst_mask */
389 TRUE), /* pcrel_offset */
391 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */
393 2, /* size (0 = byte, 1 = short, 2 = long) */
395 TRUE, /* pc_relative */
397 complain_overflow_dont,/* complain_on_overflow */
398 bfd_elf_generic_reloc, /* special_function */
399 "R_MSP430X_ABS20_ADR_DST",/* name */
400 FALSE, /* partial_inplace */
402 0xffff, /* dst_mask */
403 TRUE), /* pcrel_offset */
405 HOWTO (R_MSP430X_PCR16, /* type */
407 2, /* size (0 = byte, 1 = short, 2 = long) */
409 TRUE, /* pc_relative */
411 complain_overflow_dont,/* complain_on_overflow */
412 bfd_elf_generic_reloc, /* special_function */
413 "R_MSP430X_PCR16", /* name */
414 FALSE, /* partial_inplace */
416 0xffff, /* dst_mask */
417 TRUE), /* pcrel_offset */
419 HOWTO (R_MSP430X_PCR20_CALL, /* type */
421 2, /* size (0 = byte, 1 = short, 2 = long) */
423 TRUE, /* pc_relative */
425 complain_overflow_dont,/* complain_on_overflow */
426 bfd_elf_generic_reloc, /* special_function */
427 "R_MSP430X_PCR20_CALL",/* name */
428 FALSE, /* partial_inplace */
430 0xffff, /* dst_mask */
431 TRUE), /* pcrel_offset */
433 HOWTO (R_MSP430X_ABS16, /* type */
435 2, /* size (0 = byte, 1 = short, 2 = long) */
437 TRUE, /* pc_relative */
439 complain_overflow_dont,/* complain_on_overflow */
440 bfd_elf_generic_reloc, /* special_function */
441 "R_MSP430X_ABS16", /* name */
442 FALSE, /* partial_inplace */
444 0xffff, /* dst_mask */
445 TRUE), /* pcrel_offset */
447 HOWTO (R_MSP430_ABS_HI16, /* type */
449 2, /* size (0 = byte, 1 = short, 2 = long) */
451 TRUE, /* pc_relative */
453 complain_overflow_dont,/* complain_on_overflow */
454 bfd_elf_generic_reloc, /* special_function */
455 "R_MSP430_ABS_HI16", /* name */
456 FALSE, /* partial_inplace */
458 0xffff, /* dst_mask */
459 TRUE), /* pcrel_offset */
461 HOWTO (R_MSP430_PREL31, /* type */
463 2, /* size (0 = byte, 1 = short, 2 = long) */
465 TRUE, /* pc_relative */
467 complain_overflow_dont,/* complain_on_overflow */
468 bfd_elf_generic_reloc, /* special_function */
469 "R_MSP430_PREL31", /* name */
470 FALSE, /* partial_inplace */
472 0xffff, /* dst_mask */
473 TRUE), /* pcrel_offset */
475 EMPTY_HOWTO (R_MSP430_EHTYPE),
477 /* A 10 bit PC relative relocation. */
478 HOWTO (R_MSP430X_10_PCREL, /* type */
480 1, /* size (0 = byte, 1 = short, 2 = long) */
482 TRUE, /* pc_relative */
484 complain_overflow_bitfield,/* complain_on_overflow */
485 bfd_elf_generic_reloc, /* special_function */
486 "R_MSP430X_10_PCREL", /* name */
487 FALSE, /* partial_inplace */
488 0x3ff, /* src_mask */
489 0x3ff, /* dst_mask */
490 TRUE), /* pcrel_offset */
492 /* A 10 bit PC relative relocation for complicated polymorphs. */
493 HOWTO (R_MSP430X_2X_PCREL, /* type */
495 2, /* size (0 = byte, 1 = short, 2 = long) */
497 TRUE, /* pc_relative */
499 complain_overflow_bitfield,/* complain_on_overflow */
500 bfd_elf_generic_reloc, /* special_function */
501 "R_MSP430X_2X_PCREL", /* name */
502 FALSE, /* partial_inplace */
503 0x3ff, /* src_mask */
504 0x3ff, /* dst_mask */
505 TRUE), /* pcrel_offset */
507 /* Together with a following reloc, allows for the difference
508 between two symbols to be the real addend of the second reloc. */
509 HOWTO (R_MSP430X_SYM_DIFF, /* type */
511 2, /* size (0 = byte, 1 = short, 2 = long) */
513 FALSE, /* pc_relative */
515 complain_overflow_dont,/* complain_on_overflow */
516 rl78_sym_diff_handler, /* special handler. */
517 "R_MSP430X_SYM_DIFF", /* name */
518 FALSE, /* partial_inplace */
519 0xffffffff, /* src_mask */
520 0xffffffff, /* dst_mask */
521 FALSE) /* pcrel_offset */
524 /* Map BFD reloc types to MSP430 ELF reloc types. */
526 struct msp430_reloc_map
528 bfd_reloc_code_real_type bfd_reloc_val;
529 unsigned int elf_reloc_val;
532 static const struct msp430_reloc_map msp430_reloc_map[] =
534 {BFD_RELOC_NONE, R_MSP430_NONE},
535 {BFD_RELOC_32, R_MSP430_32},
536 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL},
537 {BFD_RELOC_16, R_MSP430_16_BYTE},
538 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL},
539 {BFD_RELOC_MSP430_16, R_MSP430_16},
540 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},
541 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},
542 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},
543 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},
544 {BFD_RELOC_8, R_MSP430_8},
545 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF}
548 static const struct msp430_reloc_map msp430x_reloc_map[] =
550 {BFD_RELOC_NONE, R_MSP430_NONE},
551 {BFD_RELOC_32, R_MSP430_ABS32},
552 {BFD_RELOC_16, R_MSP430_ABS16},
553 {BFD_RELOC_8, R_MSP430_ABS8},
554 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8},
555 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC},
556 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST},
557 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST},
558 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC},
559 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST},
560 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST},
561 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC},
562 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST},
563 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16},
564 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL},
565 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16},
566 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16},
567 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31},
568 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL},
569 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL},
570 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16},
571 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF}
574 static inline bfd_boolean
575 uses_msp430x_relocs (bfd * abfd)
577 extern const bfd_target msp430_elf32_ti_vec;
579 return bfd_get_mach (abfd) == bfd_mach_msp430x
580 || abfd->xvec == & msp430_elf32_ti_vec;
583 static reloc_howto_type *
584 bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
585 bfd_reloc_code_real_type code)
589 if (uses_msp430x_relocs (abfd))
591 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;)
592 if (msp430x_reloc_map[i].bfd_reloc_val == code)
593 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val;
597 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++)
598 if (msp430_reloc_map[i].bfd_reloc_val == code)
599 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val];
605 static reloc_howto_type *
606 bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
611 if (uses_msp430x_relocs (abfd))
613 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;)
614 if (elf_msp430x_howto_table[i].name != NULL
615 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0)
616 return elf_msp430x_howto_table + i;
621 i < (sizeof (elf_msp430_howto_table)
622 / sizeof (elf_msp430_howto_table[0]));
624 if (elf_msp430_howto_table[i].name != NULL
625 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)
626 return &elf_msp430_howto_table[i];
632 /* Set the howto pointer for an MSP430 ELF reloc. */
635 msp430_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
637 Elf_Internal_Rela * dst)
641 r_type = ELF32_R_TYPE (dst->r_info);
643 if (uses_msp430x_relocs (abfd))
645 if (r_type >= (unsigned int) R_MSP430x_max)
647 /* xgettext:c-format */
648 _bfd_error_handler (_("%B: invalid MSP430X reloc number: %d"), abfd, r_type);
651 cache_ptr->howto = elf_msp430x_howto_table + r_type;
655 if (r_type >= (unsigned int) R_MSP430_max)
657 /* xgettext:c-format */
658 _bfd_error_handler (_("%B: invalid MSP430 reloc number: %d"), abfd, r_type);
661 cache_ptr->howto = &elf_msp430_howto_table[r_type];
664 /* Look through the relocs for a section during the first phase.
665 Since we don't do .gots or .plts, we just need to consider the
666 virtual table relocs for gc. */
669 elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info,
670 asection * sec, const Elf_Internal_Rela * relocs)
672 Elf_Internal_Shdr *symtab_hdr;
673 struct elf_link_hash_entry **sym_hashes;
674 const Elf_Internal_Rela *rel;
675 const Elf_Internal_Rela *rel_end;
677 if (bfd_link_relocatable (info))
680 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
681 sym_hashes = elf_sym_hashes (abfd);
683 rel_end = relocs + sec->reloc_count;
684 for (rel = relocs; rel < rel_end; rel++)
686 struct elf_link_hash_entry *h;
687 unsigned long r_symndx;
689 r_symndx = ELF32_R_SYM (rel->r_info);
690 if (r_symndx < symtab_hdr->sh_info)
694 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
695 while (h->root.type == bfd_link_hash_indirect
696 || h->root.type == bfd_link_hash_warning)
697 h = (struct elf_link_hash_entry *) h->root.u.i.link;
704 /* Perform a single relocation. By default we use the standard BFD
705 routines, but a few relocs, we have to do them ourselves. */
707 static bfd_reloc_status_type
708 msp430_final_link_relocate (reloc_howto_type * howto,
710 asection * input_section,
712 Elf_Internal_Rela * rel,
714 struct bfd_link_info * info)
716 static asection * sym_diff_section;
717 static bfd_vma sym_diff_value;
719 struct bfd_elf_section_data * esd = elf_section_data (input_section);
720 bfd_reloc_status_type r = bfd_reloc_ok;
723 bfd_boolean is_rel_reloc = FALSE;
725 if (uses_msp430x_relocs (input_bfd))
727 /* See if we have a REL type relocation. */
728 is_rel_reloc = (esd->rel.hdr != NULL);
729 /* Sanity check - only one type of relocation per section.
730 FIXME: Theoretically it is possible to have both types,
731 but if that happens how can we distinguish between the two ? */
732 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr);
733 /* If we are using a REL relocation then the addend should be empty. */
734 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0);
737 if (sym_diff_section != NULL)
739 BFD_ASSERT (sym_diff_section == input_section);
741 if (uses_msp430x_relocs (input_bfd))
745 /* If we are computing a 32-bit value for the location lists
746 and the result is 0 then we add one to the value. A zero
747 value can result because of linker relaxation deleteing
748 prologue instructions and using a value of 1 (for the begin
749 and end offsets in the location list entry) results in a
750 nul entry which does not prevent the following entries from
752 if (relocation == sym_diff_value
753 && strcmp (input_section->name, ".debug_loc") == 0)
757 case R_MSP430X_ABS16:
759 BFD_ASSERT (! is_rel_reloc);
760 relocation -= sym_diff_value;
764 return bfd_reloc_dangerous;
771 case R_MSP430_16_BYTE:
773 relocation -= sym_diff_value;
777 return bfd_reloc_dangerous;
780 sym_diff_section = NULL;
783 if (uses_msp430x_relocs (input_bfd))
786 case R_MSP430X_SYM_DIFF:
787 /* Cache the input section and value.
788 The offset is unreliable, since relaxation may
789 have reduced the following reloc's offset. */
790 BFD_ASSERT (! is_rel_reloc);
791 sym_diff_section = input_section;
792 sym_diff_value = relocation;
796 contents += rel->r_offset;
797 srel = (bfd_signed_vma) relocation;
799 srel += bfd_get_16 (input_bfd, contents);
801 srel += rel->r_addend;
802 bfd_put_16 (input_bfd, srel & 0xffff, contents);
805 case R_MSP430X_10_PCREL:
806 contents += rel->r_offset;
807 srel = (bfd_signed_vma) relocation;
809 srel += bfd_get_16 (input_bfd, contents) & 0x3ff;
811 srel += rel->r_addend;
812 srel -= rel->r_offset;
813 srel -= 2; /* Branch instructions add 2 to the PC... */
814 srel -= (input_section->output_section->vma +
815 input_section->output_offset);
817 return bfd_reloc_outofrange;
819 /* MSP430 addresses commands as words. */
822 /* Check for an overflow. */
823 if (srel < -512 || srel > 511)
825 if (info->disable_target_specific_optimizations < 0)
827 static bfd_boolean warned = FALSE;
830 info->callbacks->warning
832 _("Try enabling relaxation to avoid relocation truncations"),
833 NULL, input_bfd, input_section, relocation);
837 return bfd_reloc_overflow;
840 x = bfd_get_16 (input_bfd, contents);
841 x = (x & 0xfc00) | (srel & 0x3ff);
842 bfd_put_16 (input_bfd, x, contents);
845 case R_MSP430X_PCR20_EXT_ODST:
846 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
847 contents += rel->r_offset;
848 srel = (bfd_signed_vma) relocation;
852 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
853 addend |= bfd_get_16 (input_bfd, contents + 6);
858 srel += rel->r_addend;
859 srel -= rel->r_offset;
860 srel -= (input_section->output_section->vma +
861 input_section->output_offset);
862 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
863 x = bfd_get_16 (input_bfd, contents);
864 x = (x & 0xfff0) | ((srel >> 16) & 0xf);
865 bfd_put_16 (input_bfd, x, contents);
868 case R_MSP430X_ABS20_EXT_SRC:
869 /* [7,4]+[32,16] = -78- ---- FFFF */
870 contents += rel->r_offset;
871 srel = (bfd_signed_vma) relocation;
875 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
876 addend |= bfd_get_16 (input_bfd, contents + 4);
880 srel += rel->r_addend;
881 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
883 x = bfd_get_16 (input_bfd, contents);
884 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
885 bfd_put_16 (input_bfd, x, contents);
888 case R_MSP430_16_PCREL:
889 contents += rel->r_offset;
890 srel = (bfd_signed_vma) relocation;
892 srel += bfd_get_16 (input_bfd, contents);
894 srel += rel->r_addend;
895 srel -= rel->r_offset;
896 /* Only branch instructions add 2 to the PC... */
897 srel -= (input_section->output_section->vma +
898 input_section->output_offset);
900 return bfd_reloc_outofrange;
901 bfd_put_16 (input_bfd, srel & 0xffff, contents);
904 case R_MSP430X_PCR20_EXT_DST:
905 /* [0,4]+[32,16] = ---F ---- FFFF */
906 contents += rel->r_offset;
907 srel = (bfd_signed_vma) relocation;
911 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
912 addend |= bfd_get_16 (input_bfd, contents + 4);
916 srel += rel->r_addend;
917 srel -= rel->r_offset;
918 srel -= (input_section->output_section->vma +
919 input_section->output_offset);
920 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
922 x = bfd_get_16 (input_bfd, contents);
923 x = (x & 0xfff0) | (srel & 0xf);
924 bfd_put_16 (input_bfd, x, contents);
927 case R_MSP430X_PCR20_EXT_SRC:
928 /* [7,4]+[32,16] = -78- ---- FFFF */
929 contents += rel->r_offset;
930 srel = (bfd_signed_vma) relocation;
934 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
935 addend |= bfd_get_16 (input_bfd, contents + 4);
939 srel += rel->r_addend;
940 srel -= rel->r_offset;
941 /* Only branch instructions add 2 to the PC... */
942 srel -= (input_section->output_section->vma +
943 input_section->output_offset);
944 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
946 x = bfd_get_16 (input_bfd, contents);
947 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
948 bfd_put_16 (input_bfd, x, contents);
952 contents += rel->r_offset;
953 srel = (bfd_signed_vma) relocation;
955 srel += bfd_get_8 (input_bfd, contents);
957 srel += rel->r_addend;
958 bfd_put_8 (input_bfd, srel & 0xff, contents);
961 case R_MSP430X_ABS20_EXT_DST:
962 /* [0,4]+[32,16] = ---F ---- FFFF */
963 contents += rel->r_offset;
964 srel = (bfd_signed_vma) relocation;
968 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
969 addend |= bfd_get_16 (input_bfd, contents + 4);
973 srel += rel->r_addend;
974 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
976 x = bfd_get_16 (input_bfd, contents);
977 x = (x & 0xfff0) | (srel & 0xf);
978 bfd_put_16 (input_bfd, x, contents);
981 case R_MSP430X_ABS20_EXT_ODST:
982 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
983 contents += rel->r_offset;
984 srel = (bfd_signed_vma) relocation;
988 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
989 addend |= bfd_get_16 (input_bfd, contents + 6);
993 srel += rel->r_addend;
994 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
996 x = bfd_get_16 (input_bfd, contents);
997 x = (x & 0xfff0) | (srel & 0xf);
998 bfd_put_16 (input_bfd, x, contents);
1001 case R_MSP430X_ABS20_ADR_SRC:
1002 /* [8,4]+[16,16] = -F-- FFFF */
1003 contents += rel->r_offset;
1004 srel = (bfd_signed_vma) relocation;
1009 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
1010 addend |= bfd_get_16 (input_bfd, contents + 2);
1014 srel += rel->r_addend;
1015 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1017 x = bfd_get_16 (input_bfd, contents);
1018 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00);
1019 bfd_put_16 (input_bfd, x, contents);
1022 case R_MSP430X_ABS20_ADR_DST:
1023 /* [0,4]+[16,16] = ---F FFFF */
1024 contents += rel->r_offset;
1025 srel = (bfd_signed_vma) relocation;
1029 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
1030 addend |= bfd_get_16 (input_bfd, contents + 2);
1034 srel += rel->r_addend;
1035 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1037 x = bfd_get_16 (input_bfd, contents);
1038 x = (x & 0xfff0) | (srel & 0xf);
1039 bfd_put_16 (input_bfd, x, contents);
1042 case R_MSP430X_ABS16:
1043 contents += rel->r_offset;
1044 srel = (bfd_signed_vma) relocation;
1046 srel += bfd_get_16 (input_bfd, contents);
1048 srel += rel->r_addend;
1051 return bfd_reloc_overflow;
1052 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1055 case R_MSP430_ABS_HI16:
1056 /* The EABI specifies that this must be a RELA reloc. */
1057 BFD_ASSERT (! is_rel_reloc);
1058 contents += rel->r_offset;
1059 srel = (bfd_signed_vma) relocation;
1060 srel += rel->r_addend;
1061 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
1064 case R_MSP430X_PCR20_CALL:
1065 /* [0,4]+[16,16] = ---F FFFF*/
1066 contents += rel->r_offset;
1067 srel = (bfd_signed_vma) relocation;
1071 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
1072 addend |= bfd_get_16 (input_bfd, contents + 2);
1076 srel += rel->r_addend;
1077 srel -= rel->r_offset;
1078 srel -= (input_section->output_section->vma +
1079 input_section->output_offset);
1080 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);
1082 x = bfd_get_16 (input_bfd, contents);
1083 x = (x & 0xfff0) | (srel & 0xf);
1084 bfd_put_16 (input_bfd, x, contents);
1087 case R_MSP430X_PCR16:
1088 contents += rel->r_offset;
1089 srel = (bfd_signed_vma) relocation;
1091 srel += bfd_get_16 (input_bfd, contents);
1093 srel += rel->r_addend;
1094 srel -= rel->r_offset;
1095 srel -= (input_section->output_section->vma +
1096 input_section->output_offset);
1097 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1100 case R_MSP430_PREL31:
1101 contents += rel->r_offset;
1102 srel = (bfd_signed_vma) relocation;
1104 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff);
1106 srel += rel->r_addend;
1107 srel += rel->r_addend;
1108 x = bfd_get_32 (input_bfd, contents);
1109 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
1110 bfd_put_32 (input_bfd, x, contents);
1114 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1115 contents, rel->r_offset,
1116 relocation, rel->r_addend);
1119 switch (howto->type)
1121 case R_MSP430_10_PCREL:
1122 contents += rel->r_offset;
1123 srel = (bfd_signed_vma) relocation;
1124 srel += rel->r_addend;
1125 srel -= rel->r_offset;
1126 srel -= 2; /* Branch instructions add 2 to the PC... */
1127 srel -= (input_section->output_section->vma +
1128 input_section->output_offset);
1131 return bfd_reloc_outofrange;
1133 /* MSP430 addresses commands as words. */
1136 /* Check for an overflow. */
1137 if (srel < -512 || srel > 511)
1139 if (info->disable_target_specific_optimizations < 0)
1141 static bfd_boolean warned = FALSE;
1144 info->callbacks->warning
1146 _("Try enabling relaxation to avoid relocation truncations"),
1147 NULL, input_bfd, input_section, relocation);
1151 return bfd_reloc_overflow;
1154 x = bfd_get_16 (input_bfd, contents);
1155 x = (x & 0xfc00) | (srel & 0x3ff);
1156 bfd_put_16 (input_bfd, x, contents);
1159 case R_MSP430_2X_PCREL:
1160 contents += rel->r_offset;
1161 srel = (bfd_signed_vma) relocation;
1162 srel += rel->r_addend;
1163 srel -= rel->r_offset;
1164 srel -= 2; /* Branch instructions add 2 to the PC... */
1165 srel -= (input_section->output_section->vma +
1166 input_section->output_offset);
1169 return bfd_reloc_outofrange;
1171 /* MSP430 addresses commands as words. */
1174 /* Check for an overflow. */
1175 if (srel < -512 || srel > 511)
1176 return bfd_reloc_overflow;
1178 x = bfd_get_16 (input_bfd, contents);
1179 x = (x & 0xfc00) | (srel & 0x3ff);
1180 bfd_put_16 (input_bfd, x, contents);
1181 /* Handle second jump instruction. */
1182 x = bfd_get_16 (input_bfd, contents - 2);
1184 x = (x & 0xfc00) | (srel & 0x3ff);
1185 bfd_put_16 (input_bfd, x, contents - 2);
1188 case R_MSP430_RL_PCREL:
1189 case R_MSP430_16_PCREL:
1190 contents += rel->r_offset;
1191 srel = (bfd_signed_vma) relocation;
1192 srel += rel->r_addend;
1193 srel -= rel->r_offset;
1194 /* Only branch instructions add 2 to the PC... */
1195 srel -= (input_section->output_section->vma +
1196 input_section->output_offset);
1199 return bfd_reloc_outofrange;
1201 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1204 case R_MSP430_16_PCREL_BYTE:
1205 contents += rel->r_offset;
1206 srel = (bfd_signed_vma) relocation;
1207 srel += rel->r_addend;
1208 srel -= rel->r_offset;
1209 /* Only branch instructions add 2 to the PC... */
1210 srel -= (input_section->output_section->vma +
1211 input_section->output_offset);
1213 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1216 case R_MSP430_16_BYTE:
1217 contents += rel->r_offset;
1218 srel = (bfd_signed_vma) relocation;
1219 srel += rel->r_addend;
1220 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1224 contents += rel->r_offset;
1225 srel = (bfd_signed_vma) relocation;
1226 srel += rel->r_addend;
1229 return bfd_reloc_notsupported;
1231 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1235 contents += rel->r_offset;
1236 srel = (bfd_signed_vma) relocation;
1237 srel += rel->r_addend;
1239 bfd_put_8 (input_bfd, srel & 0xff, contents);
1242 case R_MSP430_SYM_DIFF:
1243 /* Cache the input section and value.
1244 The offset is unreliable, since relaxation may
1245 have reduced the following reloc's offset. */
1246 sym_diff_section = input_section;
1247 sym_diff_value = relocation;
1248 return bfd_reloc_ok;
1251 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1252 contents, rel->r_offset,
1253 relocation, rel->r_addend);
1259 /* Relocate an MSP430 ELF section. */
1262 elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
1263 struct bfd_link_info * info,
1265 asection * input_section,
1266 bfd_byte * contents,
1267 Elf_Internal_Rela * relocs,
1268 Elf_Internal_Sym * local_syms,
1269 asection ** local_sections)
1271 Elf_Internal_Shdr *symtab_hdr;
1272 struct elf_link_hash_entry **sym_hashes;
1273 Elf_Internal_Rela *rel;
1274 Elf_Internal_Rela *relend;
1276 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1277 sym_hashes = elf_sym_hashes (input_bfd);
1278 relend = relocs + input_section->reloc_count;
1280 for (rel = relocs; rel < relend; rel++)
1282 reloc_howto_type *howto;
1283 unsigned long r_symndx;
1284 Elf_Internal_Sym *sym;
1286 struct elf_link_hash_entry *h;
1288 bfd_reloc_status_type r;
1289 const char *name = NULL;
1292 r_type = ELF32_R_TYPE (rel->r_info);
1293 r_symndx = ELF32_R_SYM (rel->r_info);
1295 if (uses_msp430x_relocs (input_bfd))
1296 howto = elf_msp430x_howto_table + r_type;
1298 howto = elf_msp430_howto_table + r_type;
1304 if (r_symndx < symtab_hdr->sh_info)
1306 sym = local_syms + r_symndx;
1307 sec = local_sections[r_symndx];
1308 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
1310 name = bfd_elf_string_from_elf_section
1311 (input_bfd, symtab_hdr->sh_link, sym->st_name);
1312 name = (name == NULL || * name == 0) ? bfd_section_name (input_bfd, sec) : name;
1316 bfd_boolean unresolved_reloc, warned, ignored;
1318 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
1319 r_symndx, symtab_hdr, sym_hashes,
1321 unresolved_reloc, warned, ignored);
1322 name = h->root.root.string;
1325 if (sec != NULL && discarded_section (sec))
1326 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
1327 rel, 1, relend, howto, 0, contents);
1329 if (bfd_link_relocatable (info))
1332 r = msp430_final_link_relocate (howto, input_bfd, input_section,
1333 contents, rel, relocation, info);
1335 if (r != bfd_reloc_ok)
1337 const char *msg = (const char *) NULL;
1341 case bfd_reloc_overflow:
1342 (*info->callbacks->reloc_overflow)
1343 (info, (h ? &h->root : NULL), name, howto->name,
1344 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
1347 case bfd_reloc_undefined:
1348 (*info->callbacks->undefined_symbol)
1349 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
1352 case bfd_reloc_outofrange:
1353 msg = _("internal error: branch/jump to an odd address detected");
1356 case bfd_reloc_notsupported:
1357 msg = _("internal error: unsupported relocation error");
1360 case bfd_reloc_dangerous:
1361 msg = _("internal error: dangerous relocation");
1365 msg = _("internal error: unknown error");
1370 (*info->callbacks->warning) (info, msg, name, input_bfd,
1371 input_section, rel->r_offset);
1379 /* The final processing done just before writing out a MSP430 ELF object
1380 file. This gets the MSP430 architecture right based on the machine
1384 bfd_elf_msp430_final_write_processing (bfd * abfd,
1385 bfd_boolean linker ATTRIBUTE_UNUSED)
1389 switch (bfd_get_mach (abfd))
1392 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break;
1393 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break;
1394 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break;
1395 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break;
1396 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break;
1397 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break;
1398 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break;
1399 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break;
1400 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break;
1401 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break;
1402 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break;
1403 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break;
1404 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break;
1405 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break;
1406 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break;
1407 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break;
1408 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break;
1409 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break;
1410 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break;
1411 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break;
1412 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break;
1413 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break;
1414 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break;
1417 elf_elfheader (abfd)->e_machine = EM_MSP430;
1418 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;
1419 elf_elfheader (abfd)->e_flags |= val;
1422 /* Set the right machine number. */
1425 elf32_msp430_object_p (bfd * abfd)
1427 int e_set = bfd_mach_msp14;
1429 if (elf_elfheader (abfd)->e_machine == EM_MSP430
1430 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)
1432 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;
1437 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break;
1438 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break;
1439 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break;
1440 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break;
1441 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break;
1442 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break;
1443 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break;
1444 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break;
1445 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break;
1446 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break;
1447 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break;
1448 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break;
1449 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break;
1450 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break;
1451 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break;
1452 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break;
1453 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break;
1454 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break;
1455 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break;
1456 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break;
1457 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break;
1458 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break;
1459 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
1463 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
1466 /* These functions handle relaxing for the msp430.
1467 Relaxation required only in two cases:
1468 - Bad hand coding like jumps from one section to another or
1470 - Sibling calls. This will affect only 'jump label' polymorph. Without
1471 relaxing this enlarges code by 2 bytes. Sibcalls implemented but
1472 do not work in gcc's port by the reason I do not know.
1473 - To convert out of range conditional jump instructions (found inside
1474 a function) into inverted jumps over an unconditional branch instruction.
1475 Anyway, if a relaxation required, user should pass -relax option to the
1478 There are quite a few relaxing opportunities available on the msp430:
1480 ================================================================
1482 1. 3 words -> 1 word
1484 eq == jeq label jne +4; br lab
1485 ne != jne label jeq +4; br lab
1486 lt < jl label jge +4; br lab
1487 ltu < jlo label lhs +4; br lab
1488 ge >= jge label jl +4; br lab
1489 geu >= jhs label jlo +4; br lab
1491 2. 4 words -> 1 word
1493 ltn < jn jn +2; jmp +4; br lab
1495 3. 4 words -> 2 words
1497 gt > jeq +2; jge label jeq +6; jl +4; br label
1498 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
1500 4. 4 words -> 2 words and 2 labels
1502 leu <= jeq label; jlo label jeq +2; jhs +4; br label
1503 le <= jeq label; jl label jeq +2; jge +4; br label
1504 =================================================================
1506 codemap for first cases is (labels masked ):
1507 eq: 0x2002,0x4010,0x0000 -> 0x2400
1508 ne: 0x2402,0x4010,0x0000 -> 0x2000
1509 lt: 0x3402,0x4010,0x0000 -> 0x3800
1510 ltu: 0x2c02,0x4010,0x0000 -> 0x2800
1511 ge: 0x3802,0x4010,0x0000 -> 0x3400
1512 geu: 0x2802,0x4010,0x0000 -> 0x2c00
1515 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000
1518 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400
1519 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00
1522 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800
1523 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800
1526 jump: 0x4010,0x0000 -> 0x3c00. */
1528 #define NUMB_RELAX_CODES 12
1529 static struct rcodes_s
1531 int f0, f1; /* From code. */
1532 int t0, t1; /* To code. */
1533 int labels; /* Position of labels: 1 - one label at first
1534 word, 2 - one at second word, 3 - two
1536 int cdx; /* Words to match. */
1537 int bs; /* Shrink bytes. */
1538 int off; /* Offset from old label for new code. */
1539 int ncl; /* New code length. */
1541 {/* lab,cdx,bs,off,ncl */
1542 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */
1543 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */
1544 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */
1545 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */
1546 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */
1547 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */
1548 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */
1549 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */
1550 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */
1551 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */
1552 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */
1553 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */
1554 { 0, 0, 0, 0, 0, 0, 0, 0, 0}
1557 /* Return TRUE if a symbol exists at the given address. */
1560 msp430_elf_symbol_address_p (bfd * abfd,
1562 Elf_Internal_Sym * isym,
1565 Elf_Internal_Shdr *symtab_hdr;
1566 unsigned int sec_shndx;
1567 Elf_Internal_Sym *isymend;
1568 struct elf_link_hash_entry **sym_hashes;
1569 struct elf_link_hash_entry **end_hashes;
1570 unsigned int symcount;
1572 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1574 /* Examine all the local symbols. */
1575 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1576 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1577 if (isym->st_shndx == sec_shndx && isym->st_value == addr)
1580 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1581 - symtab_hdr->sh_info);
1582 sym_hashes = elf_sym_hashes (abfd);
1583 end_hashes = sym_hashes + symcount;
1584 for (; sym_hashes < end_hashes; sym_hashes++)
1586 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1588 if ((sym_hash->root.type == bfd_link_hash_defined
1589 || sym_hash->root.type == bfd_link_hash_defweak)
1590 && sym_hash->root.u.def.section == sec
1591 && sym_hash->root.u.def.value == addr)
1598 /* Adjust all local symbols defined as '.section + 0xXXXX' (.section has
1599 sec_shndx) referenced from current and other sections. */
1602 msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr,
1603 int count, unsigned int sec_shndx,
1606 Elf_Internal_Shdr *symtab_hdr;
1607 Elf_Internal_Rela *irel;
1608 Elf_Internal_Rela *irelend;
1609 Elf_Internal_Sym *isym;
1611 irel = elf_section_data (sec)->relocs;
1615 irelend = irel + sec->reloc_count;
1616 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1617 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1619 for (;irel < irelend; irel++)
1621 unsigned int sidx = ELF32_R_SYM(irel->r_info);
1622 Elf_Internal_Sym *lsym = isym + sidx;
1624 /* Adjust symbols referenced by .sec+0xXX. */
1625 if (irel->r_addend > addr && irel->r_addend < toaddr
1626 && sidx < symtab_hdr->sh_info
1627 && lsym->st_shndx == sec_shndx)
1628 irel->r_addend -= count;
1634 /* Delete some bytes from a section while relaxing. */
1637 msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr,
1640 Elf_Internal_Shdr *symtab_hdr;
1641 unsigned int sec_shndx;
1643 Elf_Internal_Rela *irel;
1644 Elf_Internal_Rela *irelend;
1646 Elf_Internal_Sym *isym;
1647 Elf_Internal_Sym *isymend;
1648 struct elf_link_hash_entry **sym_hashes;
1649 struct elf_link_hash_entry **end_hashes;
1650 unsigned int symcount;
1653 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1655 contents = elf_section_data (sec)->this_hdr.contents;
1659 irel = elf_section_data (sec)->relocs;
1660 irelend = irel + sec->reloc_count;
1662 /* Actually delete the bytes. */
1663 memmove (contents + addr, contents + addr + count,
1664 (size_t) (toaddr - addr - count));
1667 /* Adjust all the relocs. */
1668 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1669 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1670 for (; irel < irelend; irel++)
1672 /* Get the new reloc address. */
1673 if ((irel->r_offset > addr && irel->r_offset < toaddr))
1674 irel->r_offset -= count;
1677 for (p = abfd->sections; p != NULL; p = p->next)
1678 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
1680 /* Adjust the local symbols defined in this section. */
1681 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1682 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1683 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1687 name = bfd_elf_string_from_elf_section
1688 (abfd, symtab_hdr->sh_link, isym->st_name);
1689 name = (name == NULL || * name == 0) ? bfd_section_name (abfd, sec) : name;
1691 if (isym->st_shndx != sec_shndx)
1694 if (isym->st_value > addr
1695 && (isym->st_value < toaddr
1696 /* We also adjust a symbol at the end of the section if its name is
1697 on the list below. These symbols are used for debug info
1698 generation and they refer to the end of the current section, not
1699 the start of the next section. */
1700 || (isym->st_value == toaddr
1702 && (CONST_STRNEQ (name, ".Letext")
1703 || CONST_STRNEQ (name, ".LFE")))))
1705 if (isym->st_value < addr + count)
1706 isym->st_value = addr;
1708 isym->st_value -= count;
1710 /* Adjust the function symbol's size as well. */
1711 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC
1712 && isym->st_value + isym->st_size > addr
1713 && isym->st_value + isym->st_size < toaddr)
1714 isym->st_size -= count;
1717 /* Now adjust the global symbols defined in this section. */
1718 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1719 - symtab_hdr->sh_info);
1720 sym_hashes = elf_sym_hashes (abfd);
1721 end_hashes = sym_hashes + symcount;
1722 for (; sym_hashes < end_hashes; sym_hashes++)
1724 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1726 if ((sym_hash->root.type == bfd_link_hash_defined
1727 || sym_hash->root.type == bfd_link_hash_defweak)
1728 && sym_hash->root.u.def.section == sec
1729 && sym_hash->root.u.def.value > addr
1730 && sym_hash->root.u.def.value < toaddr)
1732 if (sym_hash->root.u.def.value < addr + count)
1733 sym_hash->root.u.def.value = addr;
1735 sym_hash->root.u.def.value -= count;
1737 /* Adjust the function symbol's size as well. */
1738 else if (sym_hash->root.type == bfd_link_hash_defined
1739 && sym_hash->root.u.def.section == sec
1740 && sym_hash->type == STT_FUNC
1741 && sym_hash->root.u.def.value + sym_hash->size > addr
1742 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1743 sym_hash->size -= count;
1749 /* Insert two words into a section whilst relaxing. */
1752 msp430_elf_relax_add_two_words (bfd * abfd, asection * sec, bfd_vma addr,
1753 int word1, int word2)
1755 Elf_Internal_Shdr *symtab_hdr;
1756 unsigned int sec_shndx;
1758 Elf_Internal_Rela *irel;
1759 Elf_Internal_Rela *irelend;
1760 Elf_Internal_Sym *isym;
1761 Elf_Internal_Sym *isymend;
1762 struct elf_link_hash_entry **sym_hashes;
1763 struct elf_link_hash_entry **end_hashes;
1764 unsigned int symcount;
1768 contents = elf_section_data (sec)->this_hdr.contents;
1769 sec_end = sec->size;
1771 /* Make space for the new words. */
1772 contents = bfd_realloc (contents, sec_end + 4);
1773 memmove (contents + addr + 4, contents + addr, sec_end - addr);
1775 /* Insert the new words. */
1776 bfd_put_16 (abfd, word1, contents + addr);
1777 bfd_put_16 (abfd, word2, contents + addr + 2);
1779 /* Update the section information. */
1781 elf_section_data (sec)->this_hdr.contents = contents;
1783 /* Adjust all the relocs. */
1784 irel = elf_section_data (sec)->relocs;
1785 irelend = irel + sec->reloc_count;
1787 for (; irel < irelend; irel++)
1788 if ((irel->r_offset >= addr && irel->r_offset < sec_end))
1789 irel->r_offset += 4;
1791 /* Adjust the local symbols defined in this section. */
1792 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1793 for (p = abfd->sections; p != NULL; p = p->next)
1794 msp430_elf_relax_adjust_locals (abfd, p, addr, -4,
1795 sec_shndx, sec_end);
1797 /* Adjust the global symbols affected by the move. */
1798 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1799 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1800 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1801 if (isym->st_shndx == sec_shndx
1802 && isym->st_value >= addr && isym->st_value < sec_end)
1803 isym->st_value += 4;
1805 /* Now adjust the global symbols defined in this section. */
1806 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1807 - symtab_hdr->sh_info);
1808 sym_hashes = elf_sym_hashes (abfd);
1809 end_hashes = sym_hashes + symcount;
1810 for (; sym_hashes < end_hashes; sym_hashes++)
1812 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1814 if ((sym_hash->root.type == bfd_link_hash_defined
1815 || sym_hash->root.type == bfd_link_hash_defweak)
1816 && sym_hash->root.u.def.section == sec
1817 && sym_hash->root.u.def.value >= addr
1818 && sym_hash->root.u.def.value < sec_end)
1819 sym_hash->root.u.def.value += 4;
1826 msp430_elf_relax_section (bfd * abfd, asection * sec,
1827 struct bfd_link_info * link_info,
1828 bfd_boolean * again)
1830 Elf_Internal_Shdr * symtab_hdr;
1831 Elf_Internal_Rela * internal_relocs;
1832 Elf_Internal_Rela * irel;
1833 Elf_Internal_Rela * irelend;
1834 bfd_byte * contents = NULL;
1835 Elf_Internal_Sym * isymbuf = NULL;
1837 /* Assume nothing changes. */
1840 /* We don't have to do anything for a relocatable link, if
1841 this section does not have relocs, or if this is not a
1843 if (bfd_link_relocatable (link_info)
1844 || (sec->flags & SEC_RELOC) == 0
1845 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0)
1848 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1850 /* Get a copy of the native relocations. */
1852 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
1853 if (internal_relocs == NULL)
1856 /* Walk through them looking for relaxing opportunities. */
1857 irelend = internal_relocs + sec->reloc_count;
1859 /* Do code size growing relocs first. */
1860 for (irel = internal_relocs; irel < irelend; irel++)
1864 /* If this isn't something that can be relaxed, then ignore
1866 if (uses_msp430x_relocs (abfd)
1867 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL)
1869 else if (! uses_msp430x_relocs (abfd)
1870 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL)
1875 /* Get the section contents if we haven't done so already. */
1876 if (contents == NULL)
1878 /* Get cached copy if it exists. */
1879 if (elf_section_data (sec)->this_hdr.contents != NULL)
1880 contents = elf_section_data (sec)->this_hdr.contents;
1881 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
1885 /* Read this BFD's local symbols if we haven't done so already. */
1886 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1888 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1889 if (isymbuf == NULL)
1890 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
1891 symtab_hdr->sh_info, 0,
1893 if (isymbuf == NULL)
1897 /* Get the value of the symbol referred to by the reloc. */
1898 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1900 /* A local symbol. */
1901 Elf_Internal_Sym *isym;
1904 isym = isymbuf + ELF32_R_SYM (irel->r_info);
1905 if (isym->st_shndx == SHN_UNDEF)
1906 sym_sec = bfd_und_section_ptr;
1907 else if (isym->st_shndx == SHN_ABS)
1908 sym_sec = bfd_abs_section_ptr;
1909 else if (isym->st_shndx == SHN_COMMON)
1910 sym_sec = bfd_com_section_ptr;
1912 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1913 symval = (isym->st_value
1914 + sym_sec->output_section->vma + sym_sec->output_offset);
1919 struct elf_link_hash_entry *h;
1921 /* An external symbol. */
1922 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
1923 h = elf_sym_hashes (abfd)[indx];
1924 BFD_ASSERT (h != NULL);
1926 if (h->root.type != bfd_link_hash_defined
1927 && h->root.type != bfd_link_hash_defweak)
1928 /* This appears to be a reference to an undefined
1929 symbol. Just ignore it--it will be caught by the
1930 regular reloc processing. */
1933 symval = (h->root.u.def.value
1934 + h->root.u.def.section->output_section->vma
1935 + h->root.u.def.section->output_offset);
1938 /* For simplicity of coding, we are going to modify the section
1939 contents, the section relocs, and the BFD symbol table. We
1940 must tell the rest of the code not to free up this
1941 information. It would be possible to instead create a table
1942 of changes which have to be made, as is done in coff-mips.c;
1943 that would be more work, but would require less memory when
1944 the linker is run. */
1946 bfd_signed_vma value = symval;
1949 /* Compute the value that will be relocated. */
1950 value += irel->r_addend;
1951 /* Convert to PC relative. */
1952 value -= (sec->output_section->vma + sec->output_offset);
1953 value -= irel->r_offset;
1958 /* If it is in range then no modifications are needed. */
1959 if (value >= -512 && value <= 511)
1962 /* Get the opcode. */
1963 opcode = bfd_get_16 (abfd, contents + irel->r_offset);
1965 /* Compute the new opcode. We are going to convert:
1971 switch (opcode & 0xfc00)
1973 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
1974 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
1975 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
1976 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
1977 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */
1978 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */
1979 case 0x3000: /* jn */
1980 /* There is no direct inverse of the Jn insn.
1981 FIXME: we could do this as:
1988 /* Not a conditional branch instruction. */
1989 /* fprintf (stderr, "unrecog: %x\n", opcode); */
1993 /* Note that we've changed the relocs, section contents, etc. */
1994 elf_section_data (sec)->relocs = internal_relocs;
1995 elf_section_data (sec)->this_hdr.contents = contents;
1996 symtab_hdr->contents = (unsigned char *) isymbuf;
1998 /* Install the new opcode. */
1999 bfd_put_16 (abfd, opcode, contents + irel->r_offset);
2001 /* Insert the new branch instruction. */
2002 if (uses_msp430x_relocs (abfd))
2004 /* Insert an absolute branch (aka MOVA) instruction. */
2005 contents = msp430_elf_relax_add_two_words
2006 (abfd, sec, irel->r_offset + 2, 0x0080, 0x0000);
2008 /* Update the relocation to point to the inserted branch
2009 instruction. Note - we are changing a PC-relative reloc
2010 into an absolute reloc, but this is OK because we have
2011 arranged with the assembler to have the reloc's value be
2012 a (local) symbol, not a section+offset value. */
2013 irel->r_offset += 2;
2014 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2015 R_MSP430X_ABS20_ADR_SRC);
2019 contents = msp430_elf_relax_add_two_words
2020 (abfd, sec, irel->r_offset + 2, 0x4030, 0x0000);
2022 /* See comment above about converting a 10-bit PC-rel
2023 relocation into a 16-bit absolute relocation. */
2024 irel->r_offset += 4;
2025 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2029 /* Growing the section may mean that other
2030 conditional branches need to be fixed. */
2034 for (irel = internal_relocs; irel < irelend; irel++)
2038 /* Get the section contents if we haven't done so already. */
2039 if (contents == NULL)
2041 /* Get cached copy if it exists. */
2042 if (elf_section_data (sec)->this_hdr.contents != NULL)
2043 contents = elf_section_data (sec)->this_hdr.contents;
2044 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2048 /* Read this BFD's local symbols if we haven't done so already. */
2049 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2051 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2052 if (isymbuf == NULL)
2053 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2054 symtab_hdr->sh_info, 0,
2056 if (isymbuf == NULL)
2060 /* Get the value of the symbol referred to by the reloc. */
2061 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
2063 /* A local symbol. */
2064 Elf_Internal_Sym *isym;
2067 isym = isymbuf + ELF32_R_SYM (irel->r_info);
2068 if (isym->st_shndx == SHN_UNDEF)
2069 sym_sec = bfd_und_section_ptr;
2070 else if (isym->st_shndx == SHN_ABS)
2071 sym_sec = bfd_abs_section_ptr;
2072 else if (isym->st_shndx == SHN_COMMON)
2073 sym_sec = bfd_com_section_ptr;
2075 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2076 symval = (isym->st_value
2077 + sym_sec->output_section->vma + sym_sec->output_offset);
2082 struct elf_link_hash_entry *h;
2084 /* An external symbol. */
2085 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2086 h = elf_sym_hashes (abfd)[indx];
2087 BFD_ASSERT (h != NULL);
2089 if (h->root.type != bfd_link_hash_defined
2090 && h->root.type != bfd_link_hash_defweak)
2091 /* This appears to be a reference to an undefined
2092 symbol. Just ignore it--it will be caught by the
2093 regular reloc processing. */
2096 symval = (h->root.u.def.value
2097 + h->root.u.def.section->output_section->vma
2098 + h->root.u.def.section->output_offset);
2101 /* For simplicity of coding, we are going to modify the section
2102 contents, the section relocs, and the BFD symbol table. We
2103 must tell the rest of the code not to free up this
2104 information. It would be possible to instead create a table
2105 of changes which have to be made, as is done in coff-mips.c;
2106 that would be more work, but would require less memory when
2107 the linker is run. */
2109 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
2111 /* Paranoia? paranoia... */
2112 if (! uses_msp430x_relocs (abfd)
2113 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
2115 bfd_vma value = symval;
2117 /* Deal with pc-relative gunk. */
2118 value -= (sec->output_section->vma + sec->output_offset);
2119 value -= irel->r_offset;
2120 value += irel->r_addend;
2122 /* See if the value will fit in 10 bits, note the high value is
2123 1016 as the target will be two bytes closer if we are
2125 if ((long) value < 1016 && (long) value > -1016)
2127 int code0 = 0, code1 = 0, code2 = 0;
2129 struct rcodes_s *rx;
2131 /* Get the opcode. */
2132 if (irel->r_offset >= 6)
2133 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6);
2135 if (irel->r_offset >= 4)
2136 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2138 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2140 if (code2 != 0x4010)
2143 /* Check r4 and r3. */
2144 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--)
2147 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1)
2149 else if (rx->cdx == 1 && rx->f1 == code1)
2151 else if (rx->cdx == 0) /* This is an unconditional jump. */
2156 .Label0: ; we do not care about this label
2158 .Label1: ; make sure there is no label here
2160 .Label2: ; make sure there is no label here
2163 So, if there is .Label1 or .Label2 we cannot relax this code.
2164 This actually should not happen, cause for relaxable
2165 instructions we use RL_PCREL reloc instead of 16_PCREL.
2166 Will change this in the future. */
2169 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2170 irel->r_offset - 2))
2173 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2174 irel->r_offset - 4))
2177 /* Note that we've changed the relocs, section contents, etc. */
2178 elf_section_data (sec)->relocs = internal_relocs;
2179 elf_section_data (sec)->this_hdr.contents = contents;
2180 symtab_hdr->contents = (unsigned char *) isymbuf;
2182 /* Fix the relocation's type. */
2183 if (uses_msp430x_relocs (abfd))
2185 if (rx->labels == 3) /* Handle special cases. */
2186 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2187 R_MSP430X_2X_PCREL);
2189 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2190 R_MSP430X_10_PCREL);
2194 if (rx->labels == 3) /* Handle special cases. */
2195 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2198 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2202 /* Fix the opcode right way. */
2203 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off);
2205 bfd_put_16 (abfd, rx->t1,
2206 contents + irel->r_offset - rx->off + 2);
2209 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2210 irel->r_offset - rx->off +
2214 /* Handle unconditional jumps. */
2216 irel->r_offset -= 2;
2218 /* That will change things, so, we should relax again.
2219 Note that this is not required, and it may be slow. */
2224 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative
2226 if ((uses_msp430x_relocs (abfd)
2227 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16)
2228 || (! uses_msp430x_relocs (abfd)
2229 && ELF32_R_TYPE (irel->r_info) == R_MSP430_16))
2231 bfd_vma value = symval;
2233 value -= (sec->output_section->vma + sec->output_offset);
2234 value -= irel->r_offset;
2235 value += irel->r_addend;
2237 /* See if the value will fit in 10 bits, note the high value is
2238 1016 as the target will be two bytes closer if we are
2240 if ((long) value < 1016 && (long) value > -1016)
2244 /* Get the opcode. */
2245 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2246 if (code2 != 0x4030)
2248 /* FIXME: check r4 and r3 ? */
2249 /* FIXME: Handle 0x4010 as well ? */
2251 /* Note that we've changed the relocs, section contents, etc. */
2252 elf_section_data (sec)->relocs = internal_relocs;
2253 elf_section_data (sec)->this_hdr.contents = contents;
2254 symtab_hdr->contents = (unsigned char *) isymbuf;
2256 /* Fix the relocation's type. */
2257 if (uses_msp430x_relocs (abfd))
2259 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2260 R_MSP430X_10_PCREL);
2264 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2268 /* Fix the opcode right way. */
2269 bfd_put_16 (abfd, 0x3c00, contents + irel->r_offset - 2);
2270 irel->r_offset -= 2;
2273 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2274 irel->r_offset + 2, 2))
2277 /* That will change things, so, we should relax again.
2278 Note that this is not required, and it may be slow. */
2284 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2286 if (!link_info->keep_memory)
2290 /* Cache the symbols for elf_link_input_bfd. */
2291 symtab_hdr->contents = (unsigned char *) isymbuf;
2295 if (contents != NULL
2296 && elf_section_data (sec)->this_hdr.contents != contents)
2298 if (!link_info->keep_memory)
2302 /* Cache the section contents for elf_link_input_bfd. */
2303 elf_section_data (sec)->this_hdr.contents = contents;
2307 if (internal_relocs != NULL
2308 && elf_section_data (sec)->relocs != internal_relocs)
2309 free (internal_relocs);
2314 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2316 if (contents != NULL
2317 && elf_section_data (sec)->this_hdr.contents != contents)
2319 if (internal_relocs != NULL
2320 && elf_section_data (sec)->relocs != internal_relocs)
2321 free (internal_relocs);
2326 /* Handle an MSP430 specific section when reading an object file.
2327 This is called when bfd_section_from_shdr finds a section with
2331 elf32_msp430_section_from_shdr (bfd *abfd,
2332 Elf_Internal_Shdr * hdr,
2336 switch (hdr->sh_type)
2338 case SHT_MSP430_SEC_FLAGS:
2339 case SHT_MSP430_SYM_ALIASES:
2340 case SHT_MSP430_ATTRIBUTES:
2341 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex);
2348 elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag)
2351 /* xgettext:c-format */
2352 (_("Warning: %B: Unknown MSPABI object attribute %d"),
2357 /* Determine whether an object attribute tag takes an integer, a
2361 elf32_msp430_obj_attrs_arg_type (int tag)
2363 if (tag == Tag_compatibility)
2364 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2367 return ATTR_TYPE_FLAG_INT_VAL;
2369 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
2372 static inline const char *
2377 case 1: return "MSP430";
2378 case 2: return "MSP430X";
2379 default: return "unknown";
2383 static inline const char *
2384 code_model (int model)
2388 case 1: return "small";
2389 case 2: return "large";
2390 default: return "unknown";
2394 static inline const char *
2395 data_model (int model)
2399 case 1: return "small";
2400 case 2: return "large";
2401 case 3: return "restricted large";
2402 default: return "unknown";
2406 /* Merge MSPABI object attributes from IBFD into OBFD.
2407 Raise an error if there are conflicting attributes. */
2410 elf32_msp430_merge_mspabi_attributes (bfd *ibfd, struct bfd_link_info *info)
2412 bfd *obfd = info->output_bfd;
2413 obj_attribute *in_attr;
2414 obj_attribute *out_attr;
2415 bfd_boolean result = TRUE;
2416 static bfd * first_input_bfd = NULL;
2418 /* Skip linker created files. */
2419 if (ibfd->flags & BFD_LINKER_CREATED)
2422 /* If this is the first real object just copy the attributes. */
2423 if (!elf_known_obj_attributes_proc (obfd)[0].i)
2425 _bfd_elf_copy_obj_attributes (ibfd, obfd);
2427 out_attr = elf_known_obj_attributes_proc (obfd);
2429 /* Use the Tag_null value to indicate that
2430 the attributes have been initialized. */
2433 first_input_bfd = ibfd;
2437 in_attr = elf_known_obj_attributes_proc (ibfd);
2438 out_attr = elf_known_obj_attributes_proc (obfd);
2440 /* The ISAs must be the same. */
2441 if (in_attr[OFBA_MSPABI_Tag_ISA].i != out_attr[OFBA_MSPABI_Tag_ISA].i)
2444 /* xgettext:c-format */
2445 (_("error: %B uses %s instructions but %B uses %s"),
2446 ibfd, isa_type (in_attr[OFBA_MSPABI_Tag_ISA].i),
2447 first_input_bfd, isa_type (out_attr[OFBA_MSPABI_Tag_ISA].i));
2451 /* The code models must be the same. */
2452 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i !=
2453 out_attr[OFBA_MSPABI_Tag_Code_Model].i)
2456 /* xgettext:c-format */
2457 (_("error: %B uses the %s code model whereas %B uses the %s code model"),
2458 ibfd, code_model (in_attr[OFBA_MSPABI_Tag_Code_Model].i),
2459 first_input_bfd, code_model (out_attr[OFBA_MSPABI_Tag_Code_Model].i));
2463 /* The large code model is only supported by the MSP430X. */
2464 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 2
2465 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2468 /* xgettext:c-format */
2469 (_("error: %B uses the large code model but %B uses MSP430 instructions"),
2470 ibfd, first_input_bfd);
2474 /* The data models must be the same. */
2475 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i !=
2476 out_attr[OFBA_MSPABI_Tag_Data_Model].i)
2479 /* xgettext:c-format */
2480 (_("error: %B uses the %s data model whereas %B uses the %s data model"),
2481 ibfd, data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i),
2482 first_input_bfd, data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2486 /* The small code model requires the use of the small data model. */
2487 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 1
2488 && out_attr[OFBA_MSPABI_Tag_Data_Model].i != 1)
2491 /* xgettext:c-format */
2492 (_("error: %B uses the small code model but %B uses the %s data model"),
2493 ibfd, first_input_bfd,
2494 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2498 /* The large data models are only supported by the MSP430X. */
2499 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i > 1
2500 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2503 /* xgettext:c-format */
2504 (_("error: %B uses the %s data model but %B only uses MSP430 instructions"),
2505 ibfd, data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i),
2513 /* Merge backend specific data from an object file to the output
2514 object file when linking. */
2517 elf32_msp430_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
2519 bfd *obfd = info->output_bfd;
2520 /* Make sure that the machine number reflects the most
2521 advanced version of the MSP architecture required. */
2522 #define max(a,b) ((a) > (b) ? (a) : (b))
2523 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd))
2524 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd),
2525 max (bfd_get_mach (ibfd), bfd_get_mach (obfd)));
2528 return elf32_msp430_merge_mspabi_attributes (ibfd, info);
2532 msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
2534 return _bfd_elf_is_local_label_name (abfd, sym->name);
2538 uses_large_model (bfd *abfd)
2540 obj_attribute * attr;
2542 if (abfd->flags & BFD_LINKER_CREATED)
2545 attr = elf_known_obj_attributes_proc (abfd);
2549 return attr[OFBA_MSPABI_Tag_Code_Model].i == 2;
2553 elf32_msp430_eh_frame_address_size (bfd *abfd,
2554 const asection *sec ATTRIBUTE_UNUSED)
2556 return uses_large_model (abfd) ? 4 : 2;
2559 /* This is gross. The MSP430 EABI says that (sec 11.5):
2561 "An implementation may choose to use Rel or Rela
2562 type relocations for other relocations."
2564 But it also says that:
2566 "Certain relocations are identified as Rela only. [snip]
2567 Where Rela is specified, an implementation must honor
2570 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but
2571 to keep things simple we choose to use RELA relocations throughout. The
2572 problem is that the TI compiler generates REL relocations, so we have to
2573 be able to accept those as well. */
2575 #define elf_backend_may_use_rel_p 1
2576 #define elf_backend_may_use_rela_p 1
2577 #define elf_backend_default_use_rela_p 1
2579 #undef elf_backend_obj_attrs_vendor
2580 #define elf_backend_obj_attrs_vendor "mspabi"
2581 #undef elf_backend_obj_attrs_section
2582 #define elf_backend_obj_attrs_section ".MSP430.attributes"
2583 #undef elf_backend_obj_attrs_section_type
2584 #define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES
2585 #define elf_backend_section_from_shdr elf32_msp430_section_from_shdr
2586 #define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown
2587 #undef elf_backend_obj_attrs_arg_type
2588 #define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
2589 #define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
2590 #define elf_backend_eh_frame_address_size elf32_msp430_eh_frame_address_size
2592 #define ELF_ARCH bfd_arch_msp430
2593 #define ELF_MACHINE_CODE EM_MSP430
2594 #define ELF_MACHINE_ALT1 EM_MSP430_OLD
2595 #define ELF_MAXPAGESIZE 4
2596 #define ELF_OSABI ELFOSABI_STANDALONE
2598 #define TARGET_LITTLE_SYM msp430_elf32_vec
2599 #define TARGET_LITTLE_NAME "elf32-msp430"
2601 #define elf_info_to_howto msp430_info_to_howto_rela
2602 #define elf_info_to_howto_rel NULL
2603 #define elf_backend_relocate_section elf32_msp430_relocate_section
2604 #define elf_backend_check_relocs elf32_msp430_check_relocs
2605 #define elf_backend_can_gc_sections 1
2606 #define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing
2607 #define elf_backend_object_p elf32_msp430_object_p
2608 #define bfd_elf32_bfd_relax_section msp430_elf_relax_section
2609 #define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol
2612 #define elf32_bed elf32_msp430_bed
2614 #include "elf32-target.h"
2616 /* The TI compiler sets the OSABI field to ELFOSABI_NONE. */
2617 #undef TARGET_LITTLE_SYM
2618 #define TARGET_LITTLE_SYM msp430_elf32_ti_vec
2621 #define elf32_bed elf32_msp430_ti_bed
2624 #define ELF_OSABI ELFOSABI_NONE
2626 static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
2628 /* prefix, prefix_length, suffix_len, type, attributes. */
2629 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 },
2630 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 },
2631 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 },
2632 { NULL, 0, 0, 0, 0 }
2635 #undef elf_backend_special_sections
2636 #define elf_backend_special_sections msp430_ti_elf_special_sections
2638 #include "elf32-target.h"