2 BFD keeps one atom in a BFD describing the
3 architecture of the data attached to the BFD: a pointer to a
4 @code{bfd_arch_info_type}.
6 Pointers to structures can be requested independently of a BFD
7 so that an architecture's information can be interrogated
8 without access to an open BFD.
10 The architecture information is provided by each architecture package.
11 The set of default architectures is selected by the macro
12 @code{SELECT_ARCHITECTURES}. This is normally set up in the
13 @file{config/@var{target}.mt} file of your choice. If the name is not
14 defined, then all the architectures supported are included.
16 When BFD starts up, all the architectures are called with an
17 initialize method. It is up to the architecture back end to
18 insert as many items into the list of architectures as it wants to;
19 generally this would be one for each machine and one for the
20 default case (an item with a machine field of 0).
22 BFD's idea of an architecture is implemented in @file{archures.c}.
24 @subsection bfd_architecture
27 @strong{Description}@*
28 This enum gives the object file's CPU architecture, in a
29 global sense---i.e., what processor family does it belong to?
30 Another field indicates which processor within
31 the family is in use. The machine gives a number which
32 distinguishes different versions of the architecture,
33 containing, for example, 2 and 3 for Intel i960 KA and i960 KB,
34 and 68020 and 68030 for Motorola 68020 and 68030.
38 bfd_arch_unknown, /* File arch not known. */
39 bfd_arch_obscure, /* Arch known, not one of these. */
40 bfd_arch_m68k, /* Motorola 68xxx */
41 #define bfd_mach_m68000 1
42 #define bfd_mach_m68008 2
43 #define bfd_mach_m68010 3
44 #define bfd_mach_m68020 4
45 #define bfd_mach_m68030 5
46 #define bfd_mach_m68040 6
47 #define bfd_mach_m68060 7
48 #define bfd_mach_cpu32 8
49 #define bfd_mach_fido 9
50 #define bfd_mach_mcf_isa_a_nodiv 10
51 #define bfd_mach_mcf_isa_a 11
52 #define bfd_mach_mcf_isa_a_mac 12
53 #define bfd_mach_mcf_isa_a_emac 13
54 #define bfd_mach_mcf_isa_aplus 14
55 #define bfd_mach_mcf_isa_aplus_mac 15
56 #define bfd_mach_mcf_isa_aplus_emac 16
57 #define bfd_mach_mcf_isa_b_nousp 17
58 #define bfd_mach_mcf_isa_b_nousp_mac 18
59 #define bfd_mach_mcf_isa_b_nousp_emac 19
60 #define bfd_mach_mcf_isa_b 20
61 #define bfd_mach_mcf_isa_b_mac 21
62 #define bfd_mach_mcf_isa_b_emac 22
63 #define bfd_mach_mcf_isa_b_float 23
64 #define bfd_mach_mcf_isa_b_float_mac 24
65 #define bfd_mach_mcf_isa_b_float_emac 25
66 #define bfd_mach_mcf_isa_c 26
67 #define bfd_mach_mcf_isa_c_mac 27
68 #define bfd_mach_mcf_isa_c_emac 28
69 #define bfd_mach_mcf_isa_c_nodiv 29
70 #define bfd_mach_mcf_isa_c_nodiv_mac 30
71 #define bfd_mach_mcf_isa_c_nodiv_emac 31
72 bfd_arch_vax, /* DEC Vax */
73 bfd_arch_i960, /* Intel 960 */
74 /* The order of the following is important.
75 lower number indicates a machine type that
76 only accepts a subset of the instructions
77 available to machines with higher numbers.
78 The exception is the "ca", which is
79 incompatible with all other machines except
82 #define bfd_mach_i960_core 1
83 #define bfd_mach_i960_ka_sa 2
84 #define bfd_mach_i960_kb_sb 3
85 #define bfd_mach_i960_mc 4
86 #define bfd_mach_i960_xa 5
87 #define bfd_mach_i960_ca 6
88 #define bfd_mach_i960_jx 7
89 #define bfd_mach_i960_hx 8
91 bfd_arch_or32, /* OpenRISC 32 */
93 bfd_arch_sparc, /* SPARC */
94 #define bfd_mach_sparc 1
95 /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
96 #define bfd_mach_sparc_sparclet 2
97 #define bfd_mach_sparc_sparclite 3
98 #define bfd_mach_sparc_v8plus 4
99 #define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
100 #define bfd_mach_sparc_sparclite_le 6
101 #define bfd_mach_sparc_v9 7
102 #define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
103 #define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
104 #define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
105 /* Nonzero if MACH has the v9 instruction set. */
106 #define bfd_mach_sparc_v9_p(mach) \
107 ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
108 && (mach) != bfd_mach_sparc_sparclite_le)
109 /* Nonzero if MACH is a 64 bit sparc architecture. */
110 #define bfd_mach_sparc_64bit_p(mach) \
111 ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
112 bfd_arch_spu, /* PowerPC SPU */
113 #define bfd_mach_spu 256
114 bfd_arch_mips, /* MIPS Rxxxx */
115 #define bfd_mach_mips3000 3000
116 #define bfd_mach_mips3900 3900
117 #define bfd_mach_mips4000 4000
118 #define bfd_mach_mips4010 4010
119 #define bfd_mach_mips4100 4100
120 #define bfd_mach_mips4111 4111
121 #define bfd_mach_mips4120 4120
122 #define bfd_mach_mips4300 4300
123 #define bfd_mach_mips4400 4400
124 #define bfd_mach_mips4600 4600
125 #define bfd_mach_mips4650 4650
126 #define bfd_mach_mips5000 5000
127 #define bfd_mach_mips5400 5400
128 #define bfd_mach_mips5500 5500
129 #define bfd_mach_mips6000 6000
130 #define bfd_mach_mips7000 7000
131 #define bfd_mach_mips8000 8000
132 #define bfd_mach_mips9000 9000
133 #define bfd_mach_mips10000 10000
134 #define bfd_mach_mips12000 12000
135 #define bfd_mach_mips14000 14000
136 #define bfd_mach_mips16000 16000
137 #define bfd_mach_mips16 16
138 #define bfd_mach_mips5 5
139 #define bfd_mach_mips_loongson_2e 3001
140 #define bfd_mach_mips_loongson_2f 3002
141 #define bfd_mach_mips_loongson_3a 3003
142 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
143 #define bfd_mach_mips_octeon 6501
144 #define bfd_mach_mips_octeonp 6601
145 #define bfd_mach_mips_octeon2 6502
146 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
147 #define bfd_mach_mipsisa32 32
148 #define bfd_mach_mipsisa32r2 33
149 #define bfd_mach_mipsisa64 64
150 #define bfd_mach_mipsisa64r2 65
151 #define bfd_mach_mips_micromips 96
152 bfd_arch_i386, /* Intel 386 */
153 #define bfd_mach_i386_intel_syntax (1 << 0)
154 #define bfd_mach_i386_i8086 (1 << 1)
155 #define bfd_mach_i386_i386 (1 << 2)
156 #define bfd_mach_x86_64 (1 << 3)
157 #define bfd_mach_x64_32 (1 << 4)
158 #define bfd_mach_i386_i386_intel_syntax (bfd_mach_i386_i386 | bfd_mach_i386_intel_syntax)
159 #define bfd_mach_x86_64_intel_syntax (bfd_mach_x86_64 | bfd_mach_i386_intel_syntax)
160 #define bfd_mach_x64_32_intel_syntax (bfd_mach_x64_32 | bfd_mach_i386_intel_syntax)
161 bfd_arch_l1om, /* Intel L1OM */
162 #define bfd_mach_l1om (1 << 5)
163 #define bfd_mach_l1om_intel_syntax (bfd_mach_l1om | bfd_mach_i386_intel_syntax)
164 bfd_arch_k1om, /* Intel K1OM */
165 #define bfd_mach_k1om (1 << 6)
166 #define bfd_mach_k1om_intel_syntax (bfd_mach_k1om | bfd_mach_i386_intel_syntax)
167 bfd_arch_we32k, /* AT&T WE32xxx */
168 bfd_arch_tahoe, /* CCI/Harris Tahoe */
169 bfd_arch_i860, /* Intel 860 */
170 bfd_arch_i370, /* IBM 360/370 Mainframes */
171 bfd_arch_romp, /* IBM ROMP PC/RT */
172 bfd_arch_convex, /* Convex */
173 bfd_arch_m88k, /* Motorola 88xxx */
174 bfd_arch_m98k, /* Motorola 98xxx */
175 bfd_arch_pyramid, /* Pyramid Technology */
176 bfd_arch_h8300, /* Renesas H8/300 (formerly Hitachi H8/300) */
177 #define bfd_mach_h8300 1
178 #define bfd_mach_h8300h 2
179 #define bfd_mach_h8300s 3
180 #define bfd_mach_h8300hn 4
181 #define bfd_mach_h8300sn 5
182 #define bfd_mach_h8300sx 6
183 #define bfd_mach_h8300sxn 7
184 bfd_arch_pdp11, /* DEC PDP-11 */
186 bfd_arch_powerpc, /* PowerPC */
187 #define bfd_mach_ppc 32
188 #define bfd_mach_ppc64 64
189 #define bfd_mach_ppc_403 403
190 #define bfd_mach_ppc_403gc 4030
191 #define bfd_mach_ppc_405 405
192 #define bfd_mach_ppc_505 505
193 #define bfd_mach_ppc_601 601
194 #define bfd_mach_ppc_602 602
195 #define bfd_mach_ppc_603 603
196 #define bfd_mach_ppc_ec603e 6031
197 #define bfd_mach_ppc_604 604
198 #define bfd_mach_ppc_620 620
199 #define bfd_mach_ppc_630 630
200 #define bfd_mach_ppc_750 750
201 #define bfd_mach_ppc_860 860
202 #define bfd_mach_ppc_a35 35
203 #define bfd_mach_ppc_rs64ii 642
204 #define bfd_mach_ppc_rs64iii 643
205 #define bfd_mach_ppc_7400 7400
206 #define bfd_mach_ppc_e500 500
207 #define bfd_mach_ppc_e500mc 5001
208 #define bfd_mach_ppc_e500mc64 5005
209 #define bfd_mach_ppc_e5500 5006
210 #define bfd_mach_ppc_e6500 5007
211 #define bfd_mach_ppc_titan 83
212 #define bfd_mach_ppc_vle 84
213 bfd_arch_rs6000, /* IBM RS/6000 */
214 #define bfd_mach_rs6k 6000
215 #define bfd_mach_rs6k_rs1 6001
216 #define bfd_mach_rs6k_rsc 6003
217 #define bfd_mach_rs6k_rs2 6002
218 bfd_arch_hppa, /* HP PA RISC */
219 #define bfd_mach_hppa10 10
220 #define bfd_mach_hppa11 11
221 #define bfd_mach_hppa20 20
222 #define bfd_mach_hppa20w 25
223 bfd_arch_d10v, /* Mitsubishi D10V */
224 #define bfd_mach_d10v 1
225 #define bfd_mach_d10v_ts2 2
226 #define bfd_mach_d10v_ts3 3
227 bfd_arch_d30v, /* Mitsubishi D30V */
228 bfd_arch_dlx, /* DLX */
229 bfd_arch_m68hc11, /* Motorola 68HC11 */
230 bfd_arch_m68hc12, /* Motorola 68HC12 */
231 #define bfd_mach_m6812_default 0
232 #define bfd_mach_m6812 1
233 #define bfd_mach_m6812s 2
234 bfd_arch_m9s12x, /* Freescale S12X */
235 bfd_arch_m9s12xg, /* Freescale XGATE */
236 bfd_arch_z8k, /* Zilog Z8000 */
237 #define bfd_mach_z8001 1
238 #define bfd_mach_z8002 2
239 bfd_arch_h8500, /* Renesas H8/500 (formerly Hitachi H8/500) */
240 bfd_arch_sh, /* Renesas / SuperH SH (formerly Hitachi SH) */
241 #define bfd_mach_sh 1
242 #define bfd_mach_sh2 0x20
243 #define bfd_mach_sh_dsp 0x2d
244 #define bfd_mach_sh2a 0x2a
245 #define bfd_mach_sh2a_nofpu 0x2b
246 #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
247 #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
248 #define bfd_mach_sh2a_or_sh4 0x2a3
249 #define bfd_mach_sh2a_or_sh3e 0x2a4
250 #define bfd_mach_sh2e 0x2e
251 #define bfd_mach_sh3 0x30
252 #define bfd_mach_sh3_nommu 0x31
253 #define bfd_mach_sh3_dsp 0x3d
254 #define bfd_mach_sh3e 0x3e
255 #define bfd_mach_sh4 0x40
256 #define bfd_mach_sh4_nofpu 0x41
257 #define bfd_mach_sh4_nommu_nofpu 0x42
258 #define bfd_mach_sh4a 0x4a
259 #define bfd_mach_sh4a_nofpu 0x4b
260 #define bfd_mach_sh4al_dsp 0x4d
261 #define bfd_mach_sh5 0x50
262 bfd_arch_alpha, /* Dec Alpha */
263 #define bfd_mach_alpha_ev4 0x10
264 #define bfd_mach_alpha_ev5 0x20
265 #define bfd_mach_alpha_ev6 0x30
266 bfd_arch_arm, /* Advanced Risc Machines ARM. */
267 #define bfd_mach_arm_unknown 0
268 #define bfd_mach_arm_2 1
269 #define bfd_mach_arm_2a 2
270 #define bfd_mach_arm_3 3
271 #define bfd_mach_arm_3M 4
272 #define bfd_mach_arm_4 5
273 #define bfd_mach_arm_4T 6
274 #define bfd_mach_arm_5 7
275 #define bfd_mach_arm_5T 8
276 #define bfd_mach_arm_5TE 9
277 #define bfd_mach_arm_XScale 10
278 #define bfd_mach_arm_ep9312 11
279 #define bfd_mach_arm_iWMMXt 12
280 #define bfd_mach_arm_iWMMXt2 13
281 bfd_arch_ns32k, /* National Semiconductors ns32000 */
282 bfd_arch_w65, /* WDC 65816 */
283 bfd_arch_tic30, /* Texas Instruments TMS320C30 */
284 bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */
285 #define bfd_mach_tic3x 30
286 #define bfd_mach_tic4x 40
287 bfd_arch_tic54x, /* Texas Instruments TMS320C54X */
288 bfd_arch_tic6x, /* Texas Instruments TMS320C6X */
289 bfd_arch_tic80, /* TI TMS320c80 (MVP) */
290 bfd_arch_v850, /* NEC V850 */
291 #define bfd_mach_v850 1
292 #define bfd_mach_v850e 'E'
293 #define bfd_mach_v850e1 '1'
294 #define bfd_mach_v850e2 0x4532
295 #define bfd_mach_v850e2v3 0x45325633
296 bfd_arch_arc, /* ARC Cores */
297 #define bfd_mach_arc_5 5
298 #define bfd_mach_arc_6 6
299 #define bfd_mach_arc_7 7
300 #define bfd_mach_arc_8 8
301 bfd_arch_m32c, /* Renesas M16C/M32C. */
302 #define bfd_mach_m16c 0x75
303 #define bfd_mach_m32c 0x78
304 bfd_arch_m32r, /* Renesas M32R (formerly Mitsubishi M32R/D) */
305 #define bfd_mach_m32r 1 /* For backwards compatibility. */
306 #define bfd_mach_m32rx 'x'
307 #define bfd_mach_m32r2 '2'
308 bfd_arch_mn10200, /* Matsushita MN10200 */
309 bfd_arch_mn10300, /* Matsushita MN10300 */
310 #define bfd_mach_mn10300 300
311 #define bfd_mach_am33 330
312 #define bfd_mach_am33_2 332
314 #define bfd_mach_fr30 0x46523330
316 #define bfd_mach_frv 1
317 #define bfd_mach_frvsimple 2
318 #define bfd_mach_fr300 300
319 #define bfd_mach_fr400 400
320 #define bfd_mach_fr450 450
321 #define bfd_mach_frvtomcat 499 /* fr500 prototype */
322 #define bfd_mach_fr500 500
323 #define bfd_mach_fr550 550
324 bfd_arch_moxie, /* The moxie processor */
325 #define bfd_mach_moxie 1
328 #define bfd_mach_mep 1
329 #define bfd_mach_mep_h1 0x6831
330 #define bfd_mach_mep_c5 0x6335
331 bfd_arch_ia64, /* HP/Intel ia64 */
332 #define bfd_mach_ia64_elf64 64
333 #define bfd_mach_ia64_elf32 32
334 bfd_arch_ip2k, /* Ubicom IP2K microcontrollers. */
335 #define bfd_mach_ip2022 1
336 #define bfd_mach_ip2022ext 2
337 bfd_arch_iq2000, /* Vitesse IQ2000. */
338 #define bfd_mach_iq2000 1
339 #define bfd_mach_iq10 2
340 bfd_arch_epiphany, /* Adapteva EPIPHANY */
341 #define bfd_mach_epiphany16 1
342 #define bfd_mach_epiphany32 2
344 #define bfd_mach_ms1 1
345 #define bfd_mach_mrisc2 2
346 #define bfd_mach_ms2 3
348 bfd_arch_avr, /* Atmel AVR microcontrollers. */
349 #define bfd_mach_avr1 1
350 #define bfd_mach_avr2 2
351 #define bfd_mach_avr25 25
352 #define bfd_mach_avr3 3
353 #define bfd_mach_avr31 31
354 #define bfd_mach_avr35 35
355 #define bfd_mach_avr4 4
356 #define bfd_mach_avr5 5
357 #define bfd_mach_avr51 51
358 #define bfd_mach_avr6 6
359 #define bfd_mach_avrxmega1 101
360 #define bfd_mach_avrxmega2 102
361 #define bfd_mach_avrxmega3 103
362 #define bfd_mach_avrxmega4 104
363 #define bfd_mach_avrxmega5 105
364 #define bfd_mach_avrxmega6 106
365 #define bfd_mach_avrxmega7 107
366 bfd_arch_bfin, /* ADI Blackfin */
367 #define bfd_mach_bfin 1
368 bfd_arch_cr16, /* National Semiconductor CompactRISC (ie CR16). */
369 #define bfd_mach_cr16 1
370 bfd_arch_cr16c, /* National Semiconductor CompactRISC. */
371 #define bfd_mach_cr16c 1
372 bfd_arch_crx, /* National Semiconductor CRX. */
373 #define bfd_mach_crx 1
374 bfd_arch_cris, /* Axis CRIS */
375 #define bfd_mach_cris_v0_v10 255
376 #define bfd_mach_cris_v32 32
377 #define bfd_mach_cris_v10_v32 1032
379 #define bfd_mach_rl78 0x75
380 bfd_arch_rx, /* Renesas RX. */
381 #define bfd_mach_rx 0x75
382 bfd_arch_s390, /* IBM s390 */
383 #define bfd_mach_s390_31 31
384 #define bfd_mach_s390_64 64
385 bfd_arch_score, /* Sunplus score */
386 #define bfd_mach_score3 3
387 #define bfd_mach_score7 7
388 bfd_arch_openrisc, /* OpenRISC */
389 bfd_arch_mmix, /* Donald Knuth's educational processor. */
391 #define bfd_mach_xstormy16 1
392 bfd_arch_msp430, /* Texas Instruments MSP430 architecture. */
393 #define bfd_mach_msp11 11
394 #define bfd_mach_msp110 110
395 #define bfd_mach_msp12 12
396 #define bfd_mach_msp13 13
397 #define bfd_mach_msp14 14
398 #define bfd_mach_msp15 15
399 #define bfd_mach_msp16 16
400 #define bfd_mach_msp21 21
401 #define bfd_mach_msp31 31
402 #define bfd_mach_msp32 32
403 #define bfd_mach_msp33 33
404 #define bfd_mach_msp41 41
405 #define bfd_mach_msp42 42
406 #define bfd_mach_msp43 43
407 #define bfd_mach_msp44 44
408 bfd_arch_xc16x, /* Infineon's XC16X Series. */
409 #define bfd_mach_xc16x 1
410 #define bfd_mach_xc16xl 2
411 #define bfd_mach_xc16xs 3
412 bfd_arch_xgate, /* Freescale XGATE */
413 #define bfd_mach_xgate 1
414 bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
415 #define bfd_mach_xtensa 1
417 #define bfd_mach_z80strict 1 /* No undocumented opcodes. */
418 #define bfd_mach_z80 3 /* With ixl, ixh, iyl, and iyh. */
419 #define bfd_mach_z80full 7 /* All undocumented instructions. */
420 #define bfd_mach_r800 11 /* R800: successor with multiplication. */
421 bfd_arch_lm32, /* Lattice Mico32 */
422 #define bfd_mach_lm32 1
423 bfd_arch_microblaze,/* Xilinx MicroBlaze. */
424 bfd_arch_tilepro, /* Tilera TILEPro */
425 bfd_arch_tilegx, /* Tilera TILE-Gx */
426 #define bfd_mach_tilepro 1
427 #define bfd_mach_tilegx 1
428 #define bfd_mach_tilegx32 2
433 @subsection bfd_arch_info
436 @strong{Description}@*
437 This structure contains information on architectures for use
441 typedef struct bfd_arch_info
444 int bits_per_address;
446 enum bfd_architecture arch;
448 const char *arch_name;
449 const char *printable_name;
450 unsigned int section_align_power;
451 /* TRUE if this is the default machine for the architecture.
452 The default arch should be the first entry for an arch so that
453 all the entries for that arch can be accessed via @code{next}. */
454 bfd_boolean the_default;
455 const struct bfd_arch_info * (*compatible)
456 (const struct bfd_arch_info *a, const struct bfd_arch_info *b);
458 bfd_boolean (*scan) (const struct bfd_arch_info *, const char *);
460 /* Allocate via bfd_malloc and return a fill buffer of size COUNT. If
461 IS_BIGENDIAN is TRUE, the order of bytes is big endian. If CODE is
462 TRUE, the buffer contains code. */
463 void *(*fill) (bfd_size_type count, bfd_boolean is_bigendian,
466 const struct bfd_arch_info *next;
472 @findex bfd_printable_name
473 @subsubsection @code{bfd_printable_name}
476 const char *bfd_printable_name (bfd *abfd);
478 @strong{Description}@*
479 Return a printable string representing the architecture and machine
480 from the pointer to the architecture info structure.
482 @findex bfd_scan_arch
483 @subsubsection @code{bfd_scan_arch}
486 const bfd_arch_info_type *bfd_scan_arch (const char *string);
488 @strong{Description}@*
489 Figure out if BFD supports any cpu which could be described with
490 the name @var{string}. Return a pointer to an @code{arch_info}
491 structure if a machine is found, otherwise NULL.
493 @findex bfd_arch_list
494 @subsubsection @code{bfd_arch_list}
497 const char **bfd_arch_list (void);
499 @strong{Description}@*
500 Return a freshly malloced NULL-terminated vector of the names
501 of all the valid BFD architectures. Do not modify the names.
503 @findex bfd_arch_get_compatible
504 @subsubsection @code{bfd_arch_get_compatible}
507 const bfd_arch_info_type *bfd_arch_get_compatible
508 (const bfd *abfd, const bfd *bbfd, bfd_boolean accept_unknowns);
510 @strong{Description}@*
511 Determine whether two BFDs' architectures and machine types
512 are compatible. Calculates the lowest common denominator
513 between the two architectures and machine types implied by
514 the BFDs and returns a pointer to an @code{arch_info} structure
515 describing the compatible machine.
517 @findex bfd_default_arch_struct
518 @subsubsection @code{bfd_default_arch_struct}
519 @strong{Description}@*
520 The @code{bfd_default_arch_struct} is an item of
521 @code{bfd_arch_info_type} which has been initialized to a fairly
522 generic state. A BFD starts life by pointing to this
523 structure, until the correct back end has determined the real
524 architecture of the file.
526 extern const bfd_arch_info_type bfd_default_arch_struct;
529 @findex bfd_set_arch_info
530 @subsubsection @code{bfd_set_arch_info}
533 void bfd_set_arch_info (bfd *abfd, const bfd_arch_info_type *arg);
535 @strong{Description}@*
536 Set the architecture info of @var{abfd} to @var{arg}.
538 @findex bfd_default_set_arch_mach
539 @subsubsection @code{bfd_default_set_arch_mach}
542 bfd_boolean bfd_default_set_arch_mach
543 (bfd *abfd, enum bfd_architecture arch, unsigned long mach);
545 @strong{Description}@*
546 Set the architecture and machine type in BFD @var{abfd}
547 to @var{arch} and @var{mach}. Find the correct
548 pointer to a structure and insert it into the @code{arch_info}
552 @subsubsection @code{bfd_get_arch}
555 enum bfd_architecture bfd_get_arch (bfd *abfd);
557 @strong{Description}@*
558 Return the enumerated type which describes the BFD @var{abfd}'s
562 @subsubsection @code{bfd_get_mach}
565 unsigned long bfd_get_mach (bfd *abfd);
567 @strong{Description}@*
568 Return the long type which describes the BFD @var{abfd}'s
571 @findex bfd_arch_bits_per_byte
572 @subsubsection @code{bfd_arch_bits_per_byte}
575 unsigned int bfd_arch_bits_per_byte (bfd *abfd);
577 @strong{Description}@*
578 Return the number of bits in one of the BFD @var{abfd}'s
579 architecture's bytes.
581 @findex bfd_arch_bits_per_address
582 @subsubsection @code{bfd_arch_bits_per_address}
585 unsigned int bfd_arch_bits_per_address (bfd *abfd);
587 @strong{Description}@*
588 Return the number of bits in one of the BFD @var{abfd}'s
589 architecture's addresses.
591 @findex bfd_default_compatible
592 @subsubsection @code{bfd_default_compatible}
595 const bfd_arch_info_type *bfd_default_compatible
596 (const bfd_arch_info_type *a, const bfd_arch_info_type *b);
598 @strong{Description}@*
599 The default function for testing for compatibility.
601 @findex bfd_default_scan
602 @subsubsection @code{bfd_default_scan}
605 bfd_boolean bfd_default_scan
606 (const struct bfd_arch_info *info, const char *string);
608 @strong{Description}@*
609 The default function for working out whether this is an
610 architecture hit and a machine hit.
612 @findex bfd_get_arch_info
613 @subsubsection @code{bfd_get_arch_info}
616 const bfd_arch_info_type *bfd_get_arch_info (bfd *abfd);
618 @strong{Description}@*
619 Return the architecture info struct in @var{abfd}.
621 @findex bfd_lookup_arch
622 @subsubsection @code{bfd_lookup_arch}
625 const bfd_arch_info_type *bfd_lookup_arch
626 (enum bfd_architecture arch, unsigned long machine);
628 @strong{Description}@*
629 Look for the architecture info structure which matches the
630 arguments @var{arch} and @var{machine}. A machine of 0 matches the
631 machine/architecture structure which marks itself as the
634 @findex bfd_printable_arch_mach
635 @subsubsection @code{bfd_printable_arch_mach}
638 const char *bfd_printable_arch_mach
639 (enum bfd_architecture arch, unsigned long machine);
641 @strong{Description}@*
642 Return a printable string representing the architecture and
645 This routine is depreciated.
647 @findex bfd_octets_per_byte
648 @subsubsection @code{bfd_octets_per_byte}
651 unsigned int bfd_octets_per_byte (bfd *abfd);
653 @strong{Description}@*
654 Return the number of octets (8-bit quantities) per target byte
655 (minimum addressable unit). In most cases, this will be one, but some
656 DSP targets have 16, 32, or even 48 bits per byte.
658 @findex bfd_arch_mach_octets_per_byte
659 @subsubsection @code{bfd_arch_mach_octets_per_byte}
662 unsigned int bfd_arch_mach_octets_per_byte
663 (enum bfd_architecture arch, unsigned long machine);
665 @strong{Description}@*
666 See bfd_octets_per_byte.
668 This routine is provided for those cases where a bfd * is not
671 @findex bfd_arch_default_fill
672 @subsubsection @code{bfd_arch_default_fill}
675 void *bfd_arch_default_fill (bfd_size_type count,
676 bfd_boolean is_bigendian,
679 @strong{Description}@*
680 Allocate via bfd_malloc and return a fill buffer of size COUNT.
681 If IS_BIGENDIAN is TRUE, the order of bytes is big endian. If
682 CODE is TRUE, the buffer contains code.