2 BFD keeps one atom in a BFD describing the
3 architecture of the data attached to the BFD: a pointer to a
4 @code{bfd_arch_info_type}.
6 Pointers to structures can be requested independently of a BFD
7 so that an architecture's information can be interrogated
8 without access to an open BFD.
10 The architecture information is provided by each architecture package.
11 The set of default architectures is selected by the macro
12 @code{SELECT_ARCHITECTURES}. This is normally set up in the
13 @file{config/@var{target}.mt} file of your choice. If the name is not
14 defined, then all the architectures supported are included.
16 When BFD starts up, all the architectures are called with an
17 initialize method. It is up to the architecture back end to
18 insert as many items into the list of architectures as it wants to;
19 generally this would be one for each machine and one for the
20 default case (an item with a machine field of 0).
22 BFD's idea of an architecture is implemented in @file{archures.c}.
24 @subsection bfd_architecture
27 @strong{Description}@*
28 This enum gives the object file's CPU architecture, in a
29 global sense---i.e., what processor family does it belong to?
30 Another field indicates which processor within
31 the family is in use. The machine gives a number which
32 distinguishes different versions of the architecture,
33 containing, for example, 2 and 3 for Intel i960 KA and i960 KB,
34 and 68020 and 68030 for Motorola 68020 and 68030.
38 bfd_arch_unknown, /* File arch not known. */
39 bfd_arch_obscure, /* Arch known, not one of these. */
40 bfd_arch_m68k, /* Motorola 68xxx */
41 #define bfd_mach_m68000 1
42 #define bfd_mach_m68008 2
43 #define bfd_mach_m68010 3
44 #define bfd_mach_m68020 4
45 #define bfd_mach_m68030 5
46 #define bfd_mach_m68040 6
47 #define bfd_mach_m68060 7
48 #define bfd_mach_cpu32 8
49 #define bfd_mach_fido 9
50 #define bfd_mach_mcf_isa_a_nodiv 10
51 #define bfd_mach_mcf_isa_a 11
52 #define bfd_mach_mcf_isa_a_mac 12
53 #define bfd_mach_mcf_isa_a_emac 13
54 #define bfd_mach_mcf_isa_aplus 14
55 #define bfd_mach_mcf_isa_aplus_mac 15
56 #define bfd_mach_mcf_isa_aplus_emac 16
57 #define bfd_mach_mcf_isa_b_nousp 17
58 #define bfd_mach_mcf_isa_b_nousp_mac 18
59 #define bfd_mach_mcf_isa_b_nousp_emac 19
60 #define bfd_mach_mcf_isa_b 20
61 #define bfd_mach_mcf_isa_b_mac 21
62 #define bfd_mach_mcf_isa_b_emac 22
63 #define bfd_mach_mcf_isa_b_float 23
64 #define bfd_mach_mcf_isa_b_float_mac 24
65 #define bfd_mach_mcf_isa_b_float_emac 25
66 #define bfd_mach_mcf_isa_c 26
67 #define bfd_mach_mcf_isa_c_mac 27
68 #define bfd_mach_mcf_isa_c_emac 28
69 #define bfd_mach_mcf_isa_c_nodiv 29
70 #define bfd_mach_mcf_isa_c_nodiv_mac 30
71 #define bfd_mach_mcf_isa_c_nodiv_emac 31
72 bfd_arch_vax, /* DEC Vax */
73 bfd_arch_i960, /* Intel 960 */
74 /* The order of the following is important.
75 lower number indicates a machine type that
76 only accepts a subset of the instructions
77 available to machines with higher numbers.
78 The exception is the "ca", which is
79 incompatible with all other machines except
82 #define bfd_mach_i960_core 1
83 #define bfd_mach_i960_ka_sa 2
84 #define bfd_mach_i960_kb_sb 3
85 #define bfd_mach_i960_mc 4
86 #define bfd_mach_i960_xa 5
87 #define bfd_mach_i960_ca 6
88 #define bfd_mach_i960_jx 7
89 #define bfd_mach_i960_hx 8
91 bfd_arch_or1k, /* OpenRISC 1000 */
92 #define bfd_mach_or1k 1
93 #define bfd_mach_or1knd 2
95 bfd_arch_sparc, /* SPARC */
96 #define bfd_mach_sparc 1
97 /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
98 #define bfd_mach_sparc_sparclet 2
99 #define bfd_mach_sparc_sparclite 3
100 #define bfd_mach_sparc_v8plus 4
101 #define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
102 #define bfd_mach_sparc_sparclite_le 6
103 #define bfd_mach_sparc_v9 7
104 #define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
105 #define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
106 #define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
107 /* Nonzero if MACH has the v9 instruction set. */
108 #define bfd_mach_sparc_v9_p(mach) \
109 ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
110 && (mach) != bfd_mach_sparc_sparclite_le)
111 /* Nonzero if MACH is a 64 bit sparc architecture. */
112 #define bfd_mach_sparc_64bit_p(mach) \
113 ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
114 bfd_arch_spu, /* PowerPC SPU */
115 #define bfd_mach_spu 256
116 bfd_arch_mips, /* MIPS Rxxxx */
117 #define bfd_mach_mips3000 3000
118 #define bfd_mach_mips3900 3900
119 #define bfd_mach_mips4000 4000
120 #define bfd_mach_mips4010 4010
121 #define bfd_mach_mips4100 4100
122 #define bfd_mach_mips4111 4111
123 #define bfd_mach_mips4120 4120
124 #define bfd_mach_mips4300 4300
125 #define bfd_mach_mips4400 4400
126 #define bfd_mach_mips4600 4600
127 #define bfd_mach_mips4650 4650
128 #define bfd_mach_mips5000 5000
129 #define bfd_mach_mips5400 5400
130 #define bfd_mach_mips5500 5500
131 #define bfd_mach_mips5900 5900
132 #define bfd_mach_mips6000 6000
133 #define bfd_mach_mips7000 7000
134 #define bfd_mach_mips8000 8000
135 #define bfd_mach_mips9000 9000
136 #define bfd_mach_mips10000 10000
137 #define bfd_mach_mips12000 12000
138 #define bfd_mach_mips14000 14000
139 #define bfd_mach_mips16000 16000
140 #define bfd_mach_mips16 16
141 #define bfd_mach_mips5 5
142 #define bfd_mach_mips_loongson_2e 3001
143 #define bfd_mach_mips_loongson_2f 3002
144 #define bfd_mach_mips_loongson_3a 3003
145 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
146 #define bfd_mach_mips_octeon 6501
147 #define bfd_mach_mips_octeonp 6601
148 #define bfd_mach_mips_octeon2 6502
149 #define bfd_mach_mips_octeon3 6503
150 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
151 #define bfd_mach_mipsisa32 32
152 #define bfd_mach_mipsisa32r2 33
153 #define bfd_mach_mipsisa32r3 34
154 #define bfd_mach_mipsisa32r5 36
155 #define bfd_mach_mipsisa32r6 37
156 #define bfd_mach_mipsisa64 64
157 #define bfd_mach_mipsisa64r2 65
158 #define bfd_mach_mipsisa64r3 66
159 #define bfd_mach_mipsisa64r5 68
160 #define bfd_mach_mipsisa64r6 69
161 #define bfd_mach_mips_micromips 96
162 bfd_arch_i386, /* Intel 386 */
163 #define bfd_mach_i386_intel_syntax (1 << 0)
164 #define bfd_mach_i386_i8086 (1 << 1)
165 #define bfd_mach_i386_i386 (1 << 2)
166 #define bfd_mach_x86_64 (1 << 3)
167 #define bfd_mach_x64_32 (1 << 4)
168 #define bfd_mach_i386_i386_intel_syntax (bfd_mach_i386_i386 | bfd_mach_i386_intel_syntax)
169 #define bfd_mach_x86_64_intel_syntax (bfd_mach_x86_64 | bfd_mach_i386_intel_syntax)
170 #define bfd_mach_x64_32_intel_syntax (bfd_mach_x64_32 | bfd_mach_i386_intel_syntax)
171 bfd_arch_l1om, /* Intel L1OM */
172 #define bfd_mach_l1om (1 << 5)
173 #define bfd_mach_l1om_intel_syntax (bfd_mach_l1om | bfd_mach_i386_intel_syntax)
174 bfd_arch_k1om, /* Intel K1OM */
175 #define bfd_mach_k1om (1 << 6)
176 #define bfd_mach_k1om_intel_syntax (bfd_mach_k1om | bfd_mach_i386_intel_syntax)
177 #define bfd_mach_i386_nacl (1 << 7)
178 #define bfd_mach_i386_i386_nacl (bfd_mach_i386_i386 | bfd_mach_i386_nacl)
179 #define bfd_mach_x86_64_nacl (bfd_mach_x86_64 | bfd_mach_i386_nacl)
180 #define bfd_mach_x64_32_nacl (bfd_mach_x64_32 | bfd_mach_i386_nacl)
181 bfd_arch_we32k, /* AT&T WE32xxx */
182 bfd_arch_tahoe, /* CCI/Harris Tahoe */
183 bfd_arch_i860, /* Intel 860 */
184 bfd_arch_i370, /* IBM 360/370 Mainframes */
185 bfd_arch_romp, /* IBM ROMP PC/RT */
186 bfd_arch_convex, /* Convex */
187 bfd_arch_m88k, /* Motorola 88xxx */
188 bfd_arch_m98k, /* Motorola 98xxx */
189 bfd_arch_pyramid, /* Pyramid Technology */
190 bfd_arch_h8300, /* Renesas H8/300 (formerly Hitachi H8/300) */
191 #define bfd_mach_h8300 1
192 #define bfd_mach_h8300h 2
193 #define bfd_mach_h8300s 3
194 #define bfd_mach_h8300hn 4
195 #define bfd_mach_h8300sn 5
196 #define bfd_mach_h8300sx 6
197 #define bfd_mach_h8300sxn 7
198 bfd_arch_pdp11, /* DEC PDP-11 */
200 bfd_arch_powerpc, /* PowerPC */
201 #define bfd_mach_ppc 32
202 #define bfd_mach_ppc64 64
203 #define bfd_mach_ppc_403 403
204 #define bfd_mach_ppc_403gc 4030
205 #define bfd_mach_ppc_405 405
206 #define bfd_mach_ppc_505 505
207 #define bfd_mach_ppc_601 601
208 #define bfd_mach_ppc_602 602
209 #define bfd_mach_ppc_603 603
210 #define bfd_mach_ppc_ec603e 6031
211 #define bfd_mach_ppc_604 604
212 #define bfd_mach_ppc_620 620
213 #define bfd_mach_ppc_630 630
214 #define bfd_mach_ppc_750 750
215 #define bfd_mach_ppc_860 860
216 #define bfd_mach_ppc_a35 35
217 #define bfd_mach_ppc_rs64ii 642
218 #define bfd_mach_ppc_rs64iii 643
219 #define bfd_mach_ppc_7400 7400
220 #define bfd_mach_ppc_e500 500
221 #define bfd_mach_ppc_e500mc 5001
222 #define bfd_mach_ppc_e500mc64 5005
223 #define bfd_mach_ppc_e5500 5006
224 #define bfd_mach_ppc_e6500 5007
225 #define bfd_mach_ppc_titan 83
226 #define bfd_mach_ppc_vle 84
227 bfd_arch_rs6000, /* IBM RS/6000 */
228 #define bfd_mach_rs6k 6000
229 #define bfd_mach_rs6k_rs1 6001
230 #define bfd_mach_rs6k_rsc 6003
231 #define bfd_mach_rs6k_rs2 6002
232 bfd_arch_hppa, /* HP PA RISC */
233 #define bfd_mach_hppa10 10
234 #define bfd_mach_hppa11 11
235 #define bfd_mach_hppa20 20
236 #define bfd_mach_hppa20w 25
237 bfd_arch_d10v, /* Mitsubishi D10V */
238 #define bfd_mach_d10v 1
239 #define bfd_mach_d10v_ts2 2
240 #define bfd_mach_d10v_ts3 3
241 bfd_arch_d30v, /* Mitsubishi D30V */
242 bfd_arch_dlx, /* DLX */
243 bfd_arch_m68hc11, /* Motorola 68HC11 */
244 bfd_arch_m68hc12, /* Motorola 68HC12 */
245 #define bfd_mach_m6812_default 0
246 #define bfd_mach_m6812 1
247 #define bfd_mach_m6812s 2
248 bfd_arch_m9s12x, /* Freescale S12X */
249 bfd_arch_m9s12xg, /* Freescale XGATE */
250 bfd_arch_z8k, /* Zilog Z8000 */
251 #define bfd_mach_z8001 1
252 #define bfd_mach_z8002 2
253 bfd_arch_h8500, /* Renesas H8/500 (formerly Hitachi H8/500) */
254 bfd_arch_sh, /* Renesas / SuperH SH (formerly Hitachi SH) */
255 #define bfd_mach_sh 1
256 #define bfd_mach_sh2 0x20
257 #define bfd_mach_sh_dsp 0x2d
258 #define bfd_mach_sh2a 0x2a
259 #define bfd_mach_sh2a_nofpu 0x2b
260 #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
261 #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
262 #define bfd_mach_sh2a_or_sh4 0x2a3
263 #define bfd_mach_sh2a_or_sh3e 0x2a4
264 #define bfd_mach_sh2e 0x2e
265 #define bfd_mach_sh3 0x30
266 #define bfd_mach_sh3_nommu 0x31
267 #define bfd_mach_sh3_dsp 0x3d
268 #define bfd_mach_sh3e 0x3e
269 #define bfd_mach_sh4 0x40
270 #define bfd_mach_sh4_nofpu 0x41
271 #define bfd_mach_sh4_nommu_nofpu 0x42
272 #define bfd_mach_sh4a 0x4a
273 #define bfd_mach_sh4a_nofpu 0x4b
274 #define bfd_mach_sh4al_dsp 0x4d
275 #define bfd_mach_sh5 0x50
276 bfd_arch_alpha, /* Dec Alpha */
277 #define bfd_mach_alpha_ev4 0x10
278 #define bfd_mach_alpha_ev5 0x20
279 #define bfd_mach_alpha_ev6 0x30
280 bfd_arch_arm, /* Advanced Risc Machines ARM. */
281 #define bfd_mach_arm_unknown 0
282 #define bfd_mach_arm_2 1
283 #define bfd_mach_arm_2a 2
284 #define bfd_mach_arm_3 3
285 #define bfd_mach_arm_3M 4
286 #define bfd_mach_arm_4 5
287 #define bfd_mach_arm_4T 6
288 #define bfd_mach_arm_5 7
289 #define bfd_mach_arm_5T 8
290 #define bfd_mach_arm_5TE 9
291 #define bfd_mach_arm_XScale 10
292 #define bfd_mach_arm_ep9312 11
293 #define bfd_mach_arm_iWMMXt 12
294 #define bfd_mach_arm_iWMMXt2 13
295 bfd_arch_nds32, /* Andes NDS32 */
296 #define bfd_mach_n1 1
297 #define bfd_mach_n1h 2
298 #define bfd_mach_n1h_v2 3
299 #define bfd_mach_n1h_v3 4
300 #define bfd_mach_n1h_v3m 5
301 bfd_arch_ns32k, /* National Semiconductors ns32000 */
302 bfd_arch_w65, /* WDC 65816 */
303 bfd_arch_tic30, /* Texas Instruments TMS320C30 */
304 bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */
305 #define bfd_mach_tic3x 30
306 #define bfd_mach_tic4x 40
307 bfd_arch_tic54x, /* Texas Instruments TMS320C54X */
308 bfd_arch_tic6x, /* Texas Instruments TMS320C6X */
309 bfd_arch_tic80, /* TI TMS320c80 (MVP) */
310 bfd_arch_v850, /* NEC V850 */
311 bfd_arch_v850_rh850,/* NEC V850 (using RH850 ABI) */
312 #define bfd_mach_v850 1
313 #define bfd_mach_v850e 'E'
314 #define bfd_mach_v850e1 '1'
315 #define bfd_mach_v850e2 0x4532
316 #define bfd_mach_v850e2v3 0x45325633
317 #define bfd_mach_v850e3v5 0x45335635 /* ('E'|'3'|'V'|'5') */
318 bfd_arch_arc, /* ARC Cores */
319 #define bfd_mach_arc_5 5
320 #define bfd_mach_arc_6 6
321 #define bfd_mach_arc_7 7
322 #define bfd_mach_arc_8 8
323 bfd_arch_m32c, /* Renesas M16C/M32C. */
324 #define bfd_mach_m16c 0x75
325 #define bfd_mach_m32c 0x78
326 bfd_arch_m32r, /* Renesas M32R (formerly Mitsubishi M32R/D) */
327 #define bfd_mach_m32r 1 /* For backwards compatibility. */
328 #define bfd_mach_m32rx 'x'
329 #define bfd_mach_m32r2 '2'
330 bfd_arch_mn10200, /* Matsushita MN10200 */
331 bfd_arch_mn10300, /* Matsushita MN10300 */
332 #define bfd_mach_mn10300 300
333 #define bfd_mach_am33 330
334 #define bfd_mach_am33_2 332
336 #define bfd_mach_fr30 0x46523330
338 #define bfd_mach_frv 1
339 #define bfd_mach_frvsimple 2
340 #define bfd_mach_fr300 300
341 #define bfd_mach_fr400 400
342 #define bfd_mach_fr450 450
343 #define bfd_mach_frvtomcat 499 /* fr500 prototype */
344 #define bfd_mach_fr500 500
345 #define bfd_mach_fr550 550
346 bfd_arch_moxie, /* The moxie processor */
347 #define bfd_mach_moxie 1
350 #define bfd_mach_mep 1
351 #define bfd_mach_mep_h1 0x6831
352 #define bfd_mach_mep_c5 0x6335
354 #define bfd_mach_metag 1
355 bfd_arch_ia64, /* HP/Intel ia64 */
356 #define bfd_mach_ia64_elf64 64
357 #define bfd_mach_ia64_elf32 32
358 bfd_arch_ip2k, /* Ubicom IP2K microcontrollers. */
359 #define bfd_mach_ip2022 1
360 #define bfd_mach_ip2022ext 2
361 bfd_arch_iq2000, /* Vitesse IQ2000. */
362 #define bfd_mach_iq2000 1
363 #define bfd_mach_iq10 2
364 bfd_arch_epiphany, /* Adapteva EPIPHANY */
365 #define bfd_mach_epiphany16 1
366 #define bfd_mach_epiphany32 2
368 #define bfd_mach_ms1 1
369 #define bfd_mach_mrisc2 2
370 #define bfd_mach_ms2 3
372 bfd_arch_avr, /* Atmel AVR microcontrollers. */
373 #define bfd_mach_avr1 1
374 #define bfd_mach_avr2 2
375 #define bfd_mach_avr25 25
376 #define bfd_mach_avr3 3
377 #define bfd_mach_avr31 31
378 #define bfd_mach_avr35 35
379 #define bfd_mach_avr4 4
380 #define bfd_mach_avr5 5
381 #define bfd_mach_avr51 51
382 #define bfd_mach_avr6 6
383 #define bfd_mach_avrtiny 100
384 #define bfd_mach_avrxmega1 101
385 #define bfd_mach_avrxmega2 102
386 #define bfd_mach_avrxmega3 103
387 #define bfd_mach_avrxmega4 104
388 #define bfd_mach_avrxmega5 105
389 #define bfd_mach_avrxmega6 106
390 #define bfd_mach_avrxmega7 107
391 bfd_arch_bfin, /* ADI Blackfin */
392 #define bfd_mach_bfin 1
393 bfd_arch_cr16, /* National Semiconductor CompactRISC (ie CR16). */
394 #define bfd_mach_cr16 1
395 bfd_arch_cr16c, /* National Semiconductor CompactRISC. */
396 #define bfd_mach_cr16c 1
397 bfd_arch_crx, /* National Semiconductor CRX. */
398 #define bfd_mach_crx 1
399 bfd_arch_cris, /* Axis CRIS */
400 #define bfd_mach_cris_v0_v10 255
401 #define bfd_mach_cris_v32 32
402 #define bfd_mach_cris_v10_v32 1032
404 #define bfd_mach_rl78 0x75
405 bfd_arch_rx, /* Renesas RX. */
406 #define bfd_mach_rx 0x75
407 bfd_arch_s390, /* IBM s390 */
408 #define bfd_mach_s390_31 31
409 #define bfd_mach_s390_64 64
410 bfd_arch_score, /* Sunplus score */
411 #define bfd_mach_score3 3
412 #define bfd_mach_score7 7
413 bfd_arch_mmix, /* Donald Knuth's educational processor. */
415 #define bfd_mach_xstormy16 1
416 bfd_arch_msp430, /* Texas Instruments MSP430 architecture. */
417 #define bfd_mach_msp11 11
418 #define bfd_mach_msp110 110
419 #define bfd_mach_msp12 12
420 #define bfd_mach_msp13 13
421 #define bfd_mach_msp14 14
422 #define bfd_mach_msp15 15
423 #define bfd_mach_msp16 16
424 #define bfd_mach_msp20 20
425 #define bfd_mach_msp21 21
426 #define bfd_mach_msp22 22
427 #define bfd_mach_msp23 23
428 #define bfd_mach_msp24 24
429 #define bfd_mach_msp26 26
430 #define bfd_mach_msp31 31
431 #define bfd_mach_msp32 32
432 #define bfd_mach_msp33 33
433 #define bfd_mach_msp41 41
434 #define bfd_mach_msp42 42
435 #define bfd_mach_msp43 43
436 #define bfd_mach_msp44 44
437 #define bfd_mach_msp430x 45
438 #define bfd_mach_msp46 46
439 #define bfd_mach_msp47 47
440 #define bfd_mach_msp54 54
441 bfd_arch_xc16x, /* Infineon's XC16X Series. */
442 #define bfd_mach_xc16x 1
443 #define bfd_mach_xc16xl 2
444 #define bfd_mach_xc16xs 3
445 bfd_arch_xgate, /* Freescale XGATE */
446 #define bfd_mach_xgate 1
447 bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
448 #define bfd_mach_xtensa 1
450 #define bfd_mach_z80strict 1 /* No undocumented opcodes. */
451 #define bfd_mach_z80 3 /* With ixl, ixh, iyl, and iyh. */
452 #define bfd_mach_z80full 7 /* All undocumented instructions. */
453 #define bfd_mach_r800 11 /* R800: successor with multiplication. */
454 bfd_arch_lm32, /* Lattice Mico32 */
455 #define bfd_mach_lm32 1
456 bfd_arch_microblaze,/* Xilinx MicroBlaze. */
457 bfd_arch_tilepro, /* Tilera TILEPro */
458 bfd_arch_tilegx, /* Tilera TILE-Gx */
459 #define bfd_mach_tilepro 1
460 #define bfd_mach_tilegx 1
461 #define bfd_mach_tilegx32 2
462 bfd_arch_aarch64, /* AArch64 */
463 #define bfd_mach_aarch64 0
464 #define bfd_mach_aarch64_ilp32 32
466 #define bfd_mach_nios2 0
467 bfd_arch_visium, /* Visium */
468 #define bfd_mach_visium 1
473 @subsection bfd_arch_info
476 @strong{Description}@*
477 This structure contains information on architectures for use
481 typedef struct bfd_arch_info
484 int bits_per_address;
486 enum bfd_architecture arch;
488 const char *arch_name;
489 const char *printable_name;
490 unsigned int section_align_power;
491 /* TRUE if this is the default machine for the architecture.
492 The default arch should be the first entry for an arch so that
493 all the entries for that arch can be accessed via @code{next}. */
494 bfd_boolean the_default;
495 const struct bfd_arch_info * (*compatible)
496 (const struct bfd_arch_info *a, const struct bfd_arch_info *b);
498 bfd_boolean (*scan) (const struct bfd_arch_info *, const char *);
500 /* Allocate via bfd_malloc and return a fill buffer of size COUNT. If
501 IS_BIGENDIAN is TRUE, the order of bytes is big endian. If CODE is
502 TRUE, the buffer contains code. */
503 void *(*fill) (bfd_size_type count, bfd_boolean is_bigendian,
506 const struct bfd_arch_info *next;
512 @findex bfd_printable_name
513 @subsubsection @code{bfd_printable_name}
516 const char *bfd_printable_name (bfd *abfd);
518 @strong{Description}@*
519 Return a printable string representing the architecture and machine
520 from the pointer to the architecture info structure.
522 @findex bfd_scan_arch
523 @subsubsection @code{bfd_scan_arch}
526 const bfd_arch_info_type *bfd_scan_arch (const char *string);
528 @strong{Description}@*
529 Figure out if BFD supports any cpu which could be described with
530 the name @var{string}. Return a pointer to an @code{arch_info}
531 structure if a machine is found, otherwise NULL.
533 @findex bfd_arch_list
534 @subsubsection @code{bfd_arch_list}
537 const char **bfd_arch_list (void);
539 @strong{Description}@*
540 Return a freshly malloced NULL-terminated vector of the names
541 of all the valid BFD architectures. Do not modify the names.
543 @findex bfd_arch_get_compatible
544 @subsubsection @code{bfd_arch_get_compatible}
547 const bfd_arch_info_type *bfd_arch_get_compatible
548 (const bfd *abfd, const bfd *bbfd, bfd_boolean accept_unknowns);
550 @strong{Description}@*
551 Determine whether two BFDs' architectures and machine types
552 are compatible. Calculates the lowest common denominator
553 between the two architectures and machine types implied by
554 the BFDs and returns a pointer to an @code{arch_info} structure
555 describing the compatible machine.
557 @findex bfd_default_arch_struct
558 @subsubsection @code{bfd_default_arch_struct}
559 @strong{Description}@*
560 The @code{bfd_default_arch_struct} is an item of
561 @code{bfd_arch_info_type} which has been initialized to a fairly
562 generic state. A BFD starts life by pointing to this
563 structure, until the correct back end has determined the real
564 architecture of the file.
566 extern const bfd_arch_info_type bfd_default_arch_struct;
569 @findex bfd_set_arch_info
570 @subsubsection @code{bfd_set_arch_info}
573 void bfd_set_arch_info (bfd *abfd, const bfd_arch_info_type *arg);
575 @strong{Description}@*
576 Set the architecture info of @var{abfd} to @var{arg}.
578 @findex bfd_default_set_arch_mach
579 @subsubsection @code{bfd_default_set_arch_mach}
582 bfd_boolean bfd_default_set_arch_mach
583 (bfd *abfd, enum bfd_architecture arch, unsigned long mach);
585 @strong{Description}@*
586 Set the architecture and machine type in BFD @var{abfd}
587 to @var{arch} and @var{mach}. Find the correct
588 pointer to a structure and insert it into the @code{arch_info}
592 @subsubsection @code{bfd_get_arch}
595 enum bfd_architecture bfd_get_arch (bfd *abfd);
597 @strong{Description}@*
598 Return the enumerated type which describes the BFD @var{abfd}'s
602 @subsubsection @code{bfd_get_mach}
605 unsigned long bfd_get_mach (bfd *abfd);
607 @strong{Description}@*
608 Return the long type which describes the BFD @var{abfd}'s
611 @findex bfd_arch_bits_per_byte
612 @subsubsection @code{bfd_arch_bits_per_byte}
615 unsigned int bfd_arch_bits_per_byte (bfd *abfd);
617 @strong{Description}@*
618 Return the number of bits in one of the BFD @var{abfd}'s
619 architecture's bytes.
621 @findex bfd_arch_bits_per_address
622 @subsubsection @code{bfd_arch_bits_per_address}
625 unsigned int bfd_arch_bits_per_address (bfd *abfd);
627 @strong{Description}@*
628 Return the number of bits in one of the BFD @var{abfd}'s
629 architecture's addresses.
631 @findex bfd_default_compatible
632 @subsubsection @code{bfd_default_compatible}
635 const bfd_arch_info_type *bfd_default_compatible
636 (const bfd_arch_info_type *a, const bfd_arch_info_type *b);
638 @strong{Description}@*
639 The default function for testing for compatibility.
641 @findex bfd_default_scan
642 @subsubsection @code{bfd_default_scan}
645 bfd_boolean bfd_default_scan
646 (const struct bfd_arch_info *info, const char *string);
648 @strong{Description}@*
649 The default function for working out whether this is an
650 architecture hit and a machine hit.
652 @findex bfd_get_arch_info
653 @subsubsection @code{bfd_get_arch_info}
656 const bfd_arch_info_type *bfd_get_arch_info (bfd *abfd);
658 @strong{Description}@*
659 Return the architecture info struct in @var{abfd}.
661 @findex bfd_lookup_arch
662 @subsubsection @code{bfd_lookup_arch}
665 const bfd_arch_info_type *bfd_lookup_arch
666 (enum bfd_architecture arch, unsigned long machine);
668 @strong{Description}@*
669 Look for the architecture info structure which matches the
670 arguments @var{arch} and @var{machine}. A machine of 0 matches the
671 machine/architecture structure which marks itself as the
674 @findex bfd_printable_arch_mach
675 @subsubsection @code{bfd_printable_arch_mach}
678 const char *bfd_printable_arch_mach
679 (enum bfd_architecture arch, unsigned long machine);
681 @strong{Description}@*
682 Return a printable string representing the architecture and
685 This routine is depreciated.
687 @findex bfd_octets_per_byte
688 @subsubsection @code{bfd_octets_per_byte}
691 unsigned int bfd_octets_per_byte (bfd *abfd);
693 @strong{Description}@*
694 Return the number of octets (8-bit quantities) per target byte
695 (minimum addressable unit). In most cases, this will be one, but some
696 DSP targets have 16, 32, or even 48 bits per byte.
698 @findex bfd_arch_mach_octets_per_byte
699 @subsubsection @code{bfd_arch_mach_octets_per_byte}
702 unsigned int bfd_arch_mach_octets_per_byte
703 (enum bfd_architecture arch, unsigned long machine);
705 @strong{Description}@*
706 See bfd_octets_per_byte.
708 This routine is provided for those cases where a bfd * is not
711 @findex bfd_arch_default_fill
712 @subsubsection @code{bfd_arch_default_fill}
715 void *bfd_arch_default_fill (bfd_size_type count,
716 bfd_boolean is_bigendian,
719 @strong{Description}@*
720 Allocate via bfd_malloc and return a fill buffer of size COUNT.
721 If IS_BIGENDIAN is TRUE, the order of bytes is big endian. If
722 CODE is TRUE, the buffer contains code.