1 // Copyright 2012 The Chromium Authors
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
6 #include "base/containers/contains.h"
7 #include "base/logging.h"
8 #include "base/strings/string_util.h"
9 #include "build/build_config.h"
10 #include "testing/gtest/include/gtest/gtest.h"
12 // Tests whether we can run extended instructions represented by the CPU
13 // information. This test actually executes some extended instructions (such as
14 // MMX, SSE, etc.) supported by the CPU and sees we can run them without
15 // "undefined instruction" exceptions. That is, this test succeeds when this
16 // test finishes without a crash.
17 TEST(CPU, RunExtendedInstructions) {
18 // Retrieve the CPU information.
20 #if defined(ARCH_CPU_X86_FAMILY)
22 ASSERT_TRUE(cpu.has_mmx());
23 ASSERT_TRUE(cpu.has_sse());
24 ASSERT_TRUE(cpu.has_sse2());
25 ASSERT_TRUE(cpu.has_sse3());
27 // GCC and clang instruction test.
28 #if defined(COMPILER_GCC)
29 // Execute an MMX instruction.
30 __asm__ __volatile__("emms\n" : : : "mm0");
32 // Execute an SSE instruction.
33 __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0");
35 // Execute an SSE 2 instruction.
36 __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
38 // Execute an SSE 3 instruction.
39 __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
41 if (cpu.has_ssse3()) {
42 // Execute a Supplimental SSE 3 instruction.
43 __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0");
46 if (cpu.has_sse41()) {
47 // Execute an SSE 4.1 instruction.
48 __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0");
51 if (cpu.has_sse42()) {
52 // Execute an SSE 4.2 instruction.
53 __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax");
56 if (cpu.has_popcnt()) {
57 // Execute a POPCNT instruction.
58 __asm__ __volatile__("popcnt %%eax, %%eax\n" : : : "eax");
62 // Execute an AVX instruction.
63 __asm__ __volatile__("vzeroupper\n" : : : "xmm0");
67 // Execute a FMA3 instruction.
68 __asm__ __volatile__("vfmadd132ps %%xmm0, %%xmm0, %%xmm0\n" : : : "xmm0");
72 // Execute an AVX 2 instruction.
73 __asm__ __volatile__("vpunpcklbw %%ymm0, %%ymm0, %%ymm0\n" : : : "xmm0");
79 __asm__ __volatile__(".byte 0x0f,0x01,0xee\n"
83 // Visual C 32 bit and ClangCL 32/64 bit test.
84 #elif defined(COMPILER_MSVC) && (defined(ARCH_CPU_32_BITS) || \
85 (defined(ARCH_CPU_64_BITS) && defined(__clang__)))
87 // Execute an MMX instruction.
90 // Execute an SSE instruction.
91 __asm xorps xmm0, xmm0;
93 // Execute an SSE 2 instruction.
96 // Execute an SSE 3 instruction.
97 __asm addsubpd xmm0, xmm0;
99 if (cpu.has_ssse3()) {
100 // Execute a Supplimental SSE 3 instruction.
101 __asm psignb xmm0, xmm0;
104 if (cpu.has_sse41()) {
105 // Execute an SSE 4.1 instruction.
106 __asm pmuldq xmm0, xmm0;
109 if (cpu.has_sse42()) {
110 // Execute an SSE 4.2 instruction.
111 __asm crc32 eax, eax;
114 if (cpu.has_popcnt()) {
115 // Execute a POPCNT instruction.
116 __asm popcnt eax, eax;
120 // Execute an AVX instruction.
124 if (cpu.has_fma3()) {
125 // Execute an AVX instruction.
126 __asm vfmadd132ps xmm0, xmm0, xmm0;
129 if (cpu.has_avx2()) {
130 // Execute an AVX 2 instruction.
131 __asm vpunpcklbw ymm0, ymm0, ymm0
133 #endif // defined(COMPILER_GCC)
134 #endif // defined(ARCH_CPU_X86_FAMILY)
136 #if defined(ARCH_CPU_ARM64)
137 // Check that the CPU is correctly reporting support for the Armv8.5-A memory
138 // tagging extension. The new MTE instructions aren't encoded in NOP space
139 // like BTI/Pointer Authentication and will crash older cores with a SIGILL if
140 // used incorrectly. This test demonstrates how it should be done and that
141 // this approach works.
143 #if !defined(__ARM_FEATURE_MEMORY_TAGGING)
144 // In this section, we're running on an MTE-compatible core, but we're
145 // building this file without MTE support. Fail this test to indicate that
146 // there's a problem with the base/ build configuration.
148 << "MTE support detected (but base/ built without MTE support)";
152 // Execute a trivial MTE instruction. Normally, MTE should be used via the
153 // intrinsics documented at
154 // https://developer.arm.com/documentation/101028/0012/10--Memory-tagging-intrinsics,
155 // this test uses the irg (Insert Random Tag) instruction directly to make
156 // sure that it's not optimized out by the compiler.
157 __asm__ __volatile__("irg %0, %1" : "=r"(val) : "r"(ptr));
158 #endif // __ARM_FEATURE_MEMORY_TAGGING
160 #endif // ARCH_CPU_ARM64
163 // For https://crbug.com/249713
164 TEST(CPU, BrandAndVendorContainsNoNUL) {
166 EXPECT_FALSE(base::Contains(cpu.cpu_brand(), '\0'));
167 EXPECT_FALSE(base::Contains(cpu.vendor_name(), '\0'));
170 #if defined(ARCH_CPU_X86_FAMILY)
171 // Tests that we compute the correct CPU family and model based on the vendor
172 // and CPUID signature.
173 TEST(CPU, X86FamilyAndModel) {
174 base::internal::X86ModelInfo info;
176 // Check with an Intel Skylake signature.
177 info = base::internal::ComputeX86FamilyAndModel("GenuineIntel", 0x000406e3);
178 EXPECT_EQ(info.family, 6);
179 EXPECT_EQ(info.model, 78);
180 EXPECT_EQ(info.ext_family, 0);
181 EXPECT_EQ(info.ext_model, 4);
183 // Check with an Intel Airmont signature.
184 info = base::internal::ComputeX86FamilyAndModel("GenuineIntel", 0x000406c2);
185 EXPECT_EQ(info.family, 6);
186 EXPECT_EQ(info.model, 76);
187 EXPECT_EQ(info.ext_family, 0);
188 EXPECT_EQ(info.ext_model, 4);
190 // Check with an Intel Prescott signature.
191 info = base::internal::ComputeX86FamilyAndModel("GenuineIntel", 0x00000f31);
192 EXPECT_EQ(info.family, 15);
193 EXPECT_EQ(info.model, 3);
194 EXPECT_EQ(info.ext_family, 0);
195 EXPECT_EQ(info.ext_model, 0);
197 // Check with an AMD Excavator signature.
198 info = base::internal::ComputeX86FamilyAndModel("AuthenticAMD", 0x00670f00);
199 EXPECT_EQ(info.family, 21);
200 EXPECT_EQ(info.model, 112);
201 EXPECT_EQ(info.ext_family, 6);
202 EXPECT_EQ(info.ext_model, 7);
204 #endif // defined(ARCH_CPU_X86_FAMILY)
206 #if defined(ARCH_CPU_ARM_FAMILY) && \
207 (BUILDFLAG(IS_LINUX) || BUILDFLAG(IS_ANDROID) || BUILDFLAG(IS_CHROMEOS))
208 TEST(CPU, ARMImplementerAndPartNumber) {
211 const std::string& cpu_brand = cpu.cpu_brand();
213 // Some devices, including on the CQ, do not report a cpu_brand
214 // https://crbug.com/1166533 and https://crbug.com/1167123.
215 EXPECT_EQ(cpu_brand, base::TrimWhitespaceASCII(cpu_brand, base::TRIM_ALL));
216 EXPECT_GT(cpu.implementer(), 0u);
217 EXPECT_GT(cpu.part_number(), 0u);
219 #endif // defined(ARCH_CPU_ARM_FAMILY) && (BUILDFLAG(IS_LINUX) ||
220 // BUILDFLAG(IS_ANDROID) || BUILDFLAG(IS_CHROMEOS))