1 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
15 #include "base/stl_util.h"
16 #include "build/build_config.h"
18 #if defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) || defined(OS_LINUX))
19 #include "base/files/file_util.h"
22 #if defined(ARCH_CPU_X86_FAMILY)
23 #if defined(COMPILER_MSVC)
25 #include <immintrin.h> // For _xgetbv()
50 has_non_stop_time_stamp_counter_(false),
51 cpu_vendor_("unknown") {
57 #if defined(ARCH_CPU_X86_FAMILY)
58 #if !defined(COMPILER_MSVC)
60 #if defined(__pic__) && defined(__i386__)
62 void __cpuid(int cpu_info[4], int info_type) {
67 : "=a"(cpu_info[0]), "=D"(cpu_info[1]), "=c"(cpu_info[2]),
69 : "a"(info_type), "c"(0));
74 void __cpuid(int cpu_info[4], int info_type) {
75 __asm__ volatile("cpuid\n"
76 : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]),
78 : "a"(info_type), "c"(0));
82 #endif // !defined(COMPILER_MSVC)
84 // xgetbv returns the value of an Intel Extended Control Register (XCR).
85 // Currently only XCR0 is defined by Intel so |xcr| should always be zero.
86 uint64_t xgetbv(uint32_t xcr) {
87 #if defined(COMPILER_MSVC)
93 "xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
94 return (static_cast<uint64_t>(edx) << 32) | eax;
95 #endif // defined(COMPILER_MSVC)
98 #endif // ARCH_CPU_X86_FAMILY
100 #if defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) || defined(OS_LINUX))
101 std::string* CpuInfoBrand() {
102 static std::string* brand = []() {
103 // This function finds the value from /proc/cpuinfo under the key "model
104 // name" or "Processor". "model name" is used in Linux 3.8 and later (3.7
105 // and later for arm64) and is shown once per CPU. "Processor" is used in
106 // earler versions and is shown only once at the top of /proc/cpuinfo
107 // regardless of the number CPUs.
108 const char kModelNamePrefix[] = "model name\t: ";
109 const char kProcessorPrefix[] = "Processor\t: ";
111 std::string contents;
112 ReadFileToString(FilePath("/proc/cpuinfo"), &contents);
113 DCHECK(!contents.empty());
115 std::istringstream iss(contents);
117 while (std::getline(iss, line)) {
118 if (line.compare(0, strlen(kModelNamePrefix), kModelNamePrefix) == 0)
119 return new std::string(line.substr(strlen(kModelNamePrefix)));
120 if (line.compare(0, strlen(kProcessorPrefix), kProcessorPrefix) == 0)
121 return new std::string(line.substr(strlen(kProcessorPrefix)));
124 return new std::string();
129 #endif // defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) ||
130 // defined(OS_LINUX))
134 void CPU::Initialize() {
135 #if defined(ARCH_CPU_X86_FAMILY)
136 int cpu_info[4] = {-1};
137 // This array is used to temporarily hold the vendor name and then the brand
138 // name. Thus it has to be big enough for both use cases. There are
139 // static_asserts below for each of the use cases to make sure this array is
141 char cpu_string[sizeof(cpu_info) * 3 + 1];
143 // __cpuid with an InfoType argument of 0 returns the number of
144 // valid Ids in CPUInfo[0] and the CPU identification string in
145 // the other three array elements. The CPU identification string is
146 // not in linear order. The code below arranges the information
147 // in a human readable form. The human readable order is CPUInfo[1] |
148 // CPUInfo[3] | CPUInfo[2]. CPUInfo[2] and CPUInfo[3] are swapped
149 // before using memcpy() to copy these three array elements to |cpu_string|.
150 __cpuid(cpu_info, 0);
151 int num_ids = cpu_info[0];
152 std::swap(cpu_info[2], cpu_info[3]);
153 static constexpr size_t kVendorNameSize = 3 * sizeof(cpu_info[1]);
154 static_assert(kVendorNameSize < base::size(cpu_string),
155 "cpu_string too small");
156 memcpy(cpu_string, &cpu_info[1], kVendorNameSize);
157 cpu_string[kVendorNameSize] = '\0';
158 cpu_vendor_ = cpu_string;
159 bool hypervisor = false;
161 // Interpret CPU feature information.
163 int cpu_info7[4] = {0};
164 __cpuid(cpu_info, 1);
166 __cpuid(cpu_info7, 7);
168 signature_ = cpu_info[0];
169 stepping_ = cpu_info[0] & 0xf;
170 model_ = ((cpu_info[0] >> 4) & 0xf) + ((cpu_info[0] >> 12) & 0xf0);
171 family_ = (cpu_info[0] >> 8) & 0xf;
172 type_ = (cpu_info[0] >> 12) & 0x3;
173 ext_model_ = (cpu_info[0] >> 16) & 0xf;
174 ext_family_ = (cpu_info[0] >> 20) & 0xff;
175 has_mmx_ = (cpu_info[3] & 0x00800000) != 0;
176 has_sse_ = (cpu_info[3] & 0x02000000) != 0;
177 has_sse2_ = (cpu_info[3] & 0x04000000) != 0;
178 has_sse3_ = (cpu_info[2] & 0x00000001) != 0;
179 has_ssse3_ = (cpu_info[2] & 0x00000200) != 0;
180 has_sse41_ = (cpu_info[2] & 0x00080000) != 0;
181 has_sse42_ = (cpu_info[2] & 0x00100000) != 0;
182 has_popcnt_ = (cpu_info[2] & 0x00800000) != 0;
184 // "Hypervisor Present Bit: Bit 31 of ECX of CPUID leaf 0x1."
185 // See https://lwn.net/Articles/301888/
186 // This is checking for any hypervisor. Hypervisors may choose not to
187 // announce themselves. Hypervisors trap CPUID and sometimes return
188 // different results to underlying hardware.
189 hypervisor = (cpu_info[2] & 0x80000000) != 0;
191 // AVX instructions will generate an illegal instruction exception unless
192 // a) they are supported by the CPU,
193 // b) XSAVE is supported by the CPU and
194 // c) XSAVE is enabled by the kernel.
195 // See http://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
197 // In addition, we have observed some crashes with the xgetbv instruction
198 // even after following Intel's example code. (See crbug.com/375968.)
199 // Because of that, we also test the XSAVE bit because its description in
200 // the CPUID documentation suggests that it signals xgetbv support.
202 (cpu_info[2] & 0x10000000) != 0 &&
203 (cpu_info[2] & 0x04000000) != 0 /* XSAVE */ &&
204 (cpu_info[2] & 0x08000000) != 0 /* OSXSAVE */ &&
205 (xgetbv(0) & 6) == 6 /* XSAVE enabled by kernel */;
206 has_aesni_ = (cpu_info[2] & 0x02000000) != 0;
207 has_avx2_ = has_avx_ && (cpu_info7[1] & 0x00000020) != 0;
210 // Get the brand string of the cpu.
211 __cpuid(cpu_info, 0x80000000);
212 const int max_parameter = cpu_info[0];
214 static constexpr int kParameterStart = 0x80000002;
215 static constexpr int kParameterEnd = 0x80000004;
216 static constexpr int kParameterSize = kParameterEnd - kParameterStart + 1;
217 static_assert(kParameterSize * sizeof(cpu_info) + 1 == base::size(cpu_string),
218 "cpu_string has wrong size");
220 if (max_parameter >= kParameterEnd) {
222 for (int parameter = kParameterStart; parameter <= kParameterEnd;
224 __cpuid(cpu_info, parameter);
225 memcpy(&cpu_string[i], cpu_info, sizeof(cpu_info));
226 i += sizeof(cpu_info);
228 cpu_string[i] = '\0';
229 cpu_brand_ = cpu_string;
232 static constexpr int kParameterContainingNonStopTimeStampCounter = 0x80000007;
233 if (max_parameter >= kParameterContainingNonStopTimeStampCounter) {
234 __cpuid(cpu_info, kParameterContainingNonStopTimeStampCounter);
235 has_non_stop_time_stamp_counter_ = (cpu_info[3] & (1 << 8)) != 0;
238 if (!has_non_stop_time_stamp_counter_ && hypervisor) {
239 int cpu_info_hv[4] = {};
240 __cpuid(cpu_info_hv, 0x40000000);
241 if (cpu_info_hv[1] == 0x7263694D && // Micr
242 cpu_info_hv[2] == 0x666F736F && // osof
243 cpu_info_hv[3] == 0x76482074) { // t Hv
244 // If CPUID says we have a variant TSC and a hypervisor has identified
245 // itself and the hypervisor says it is Microsoft Hyper-V, then treat
248 // Microsoft Hyper-V hypervisor reports variant TSC as there are some
249 // scenarios (eg. VM live migration) where the TSC is variant, but for
250 // our purposes we can treat it as invariant.
251 has_non_stop_time_stamp_counter_ = true;
254 #elif defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) || defined(OS_LINUX))
255 cpu_brand_ = *CpuInfoBrand();
259 CPU::IntelMicroArchitecture CPU::GetIntelMicroArchitecture() const {
260 if (has_avx2()) return AVX2;
261 if (has_avx()) return AVX;
262 if (has_sse42()) return SSE42;
263 if (has_sse41()) return SSE41;
264 if (has_ssse3()) return SSSE3;
265 if (has_sse3()) return SSE3;
266 if (has_sse2()) return SSE2;
267 if (has_sse()) return SSE;