1 // Copyright (c) 2014 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 // This file is an internal atomic implementation, use atomicops.h instead.
7 // This implementation uses C++11 atomics' member functions. The code base is
8 // currently written assuming atomicity revolves around accesses instead of
9 // C++11's memory locations. The burden is on the programmer to ensure that all
10 // memory locations accessed atomically are never accessed non-atomically (tsan
11 // should help with this).
13 // TODO(jfb) Modify the atomicops.h API and user code to declare atomic
14 // locations as truly atomic. See the static_assert below.
16 // Of note in this implementation:
17 // * All NoBarrier variants are implemented as relaxed.
18 // * All Barrier variants are implemented as sequentially-consistent.
19 // * Compare exchange's failure ordering is always the same as the success one
20 // (except for release, which fails as relaxed): using a weaker ordering is
21 // only valid under certain uses of compare exchange.
22 // * Acquire store doesn't exist in the C11 memory model, it is instead
23 // implemented as a relaxed store followed by a sequentially consistent
25 // * Release load doesn't exist in the C11 memory model, it is instead
26 // implemented as sequentially consistent fence followed by a relaxed load.
27 // * Atomic increment is expected to return the post-incremented value, whereas
28 // C11 fetch add returns the previous value. The implementation therefore
29 // needs to increment twice (which the compiler should be able to detect and
32 #ifndef BASE_ATOMICOPS_INTERNALS_PORTABLE_H_
33 #define BASE_ATOMICOPS_INTERNALS_PORTABLE_H_
37 #include "build/build_config.h"
42 // This implementation is transitional and maintains the original API for
43 // atomicops.h. This requires casting memory locations to the atomic types, and
44 // assumes that the API and the C++11 implementation are layout-compatible,
45 // which isn't true for all implementations or hardware platforms. The static
46 // assertion should detect this issue, were it to fire then this header
49 // TODO(jfb) If this header manages to stay committed then the API should be
50 // modified, and all call sites updated.
51 typedef volatile std::atomic<Atomic32>* AtomicLocation32;
52 static_assert(sizeof(*(AtomicLocation32) nullptr) == sizeof(Atomic32),
53 "incompatible 32-bit atomic layout");
55 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
58 ((AtomicLocation32)ptr)
59 ->compare_exchange_strong(old_value,
61 std::memory_order_relaxed,
62 std::memory_order_relaxed);
66 inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
68 return ((AtomicLocation32)ptr)
69 ->exchange(new_value, std::memory_order_relaxed);
72 inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
75 ((AtomicLocation32)ptr)
76 ->fetch_add(increment, std::memory_order_relaxed);
79 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
81 return increment + ((AtomicLocation32)ptr)->fetch_add(increment);
84 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
87 ((AtomicLocation32)ptr)
88 ->compare_exchange_strong(old_value,
90 std::memory_order_acquire,
91 std::memory_order_acquire);
95 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
98 ((AtomicLocation32)ptr)
99 ->compare_exchange_strong(old_value,
101 std::memory_order_release,
102 std::memory_order_relaxed);
106 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
107 ((AtomicLocation32)ptr)->store(value, std::memory_order_relaxed);
110 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
111 ((AtomicLocation32)ptr)->store(value, std::memory_order_relaxed);
112 std::atomic_thread_fence(std::memory_order_seq_cst);
115 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
116 ((AtomicLocation32)ptr)->store(value, std::memory_order_release);
119 inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
120 return ((AtomicLocation32)ptr)->load(std::memory_order_relaxed);
123 inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
124 return ((AtomicLocation32)ptr)->load(std::memory_order_acquire);
127 inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
128 std::atomic_thread_fence(std::memory_order_seq_cst);
129 return ((AtomicLocation32)ptr)->load(std::memory_order_relaxed);
132 #if defined(ARCH_CPU_64_BITS)
134 typedef volatile std::atomic<Atomic64>* AtomicLocation64;
135 static_assert(sizeof(*(AtomicLocation64) nullptr) == sizeof(Atomic64),
136 "incompatible 64-bit atomic layout");
138 inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
140 Atomic64 new_value) {
141 ((AtomicLocation64)ptr)
142 ->compare_exchange_strong(old_value,
144 std::memory_order_relaxed,
145 std::memory_order_relaxed);
149 inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
150 Atomic64 new_value) {
151 return ((AtomicLocation64)ptr)
152 ->exchange(new_value, std::memory_order_relaxed);
155 inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
156 Atomic64 increment) {
158 ((AtomicLocation64)ptr)
159 ->fetch_add(increment, std::memory_order_relaxed);
162 inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
163 Atomic64 increment) {
164 return increment + ((AtomicLocation64)ptr)->fetch_add(increment);
167 inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
169 Atomic64 new_value) {
170 ((AtomicLocation64)ptr)
171 ->compare_exchange_strong(old_value,
173 std::memory_order_acquire,
174 std::memory_order_acquire);
178 inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
180 Atomic64 new_value) {
181 ((AtomicLocation64)ptr)
182 ->compare_exchange_strong(old_value,
184 std::memory_order_release,
185 std::memory_order_relaxed);
189 inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
190 ((AtomicLocation64)ptr)->store(value, std::memory_order_relaxed);
193 inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
194 ((AtomicLocation64)ptr)->store(value, std::memory_order_relaxed);
195 std::atomic_thread_fence(std::memory_order_seq_cst);
198 inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
199 ((AtomicLocation64)ptr)->store(value, std::memory_order_release);
202 inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
203 return ((AtomicLocation64)ptr)->load(std::memory_order_relaxed);
206 inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
207 return ((AtomicLocation64)ptr)->load(std::memory_order_acquire);
210 inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
211 std::atomic_thread_fence(std::memory_order_seq_cst);
212 return ((AtomicLocation64)ptr)->load(std::memory_order_relaxed);
215 #endif // defined(ARCH_CPU_64_BITS)
216 } // namespace subtle
219 #endif // BASE_ATOMICOPS_INTERNALS_PORTABLE_H_