1 // Copyright (c) 2011 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 // For atomic operations on reference counts, see atomic_refcount.h.
6 // For atomic operations on sequence numbers, see atomic_sequence_num.h.
8 // The routines exported by this module are subtle. If you use them, even if
9 // you get the code right, it will depend on careful reasoning about atomicity
10 // and memory ordering; it will be less readable, and harder to maintain. If
11 // you plan to use these routines, you should have a good reason, such as solid
12 // evidence that performance would otherwise suffer, or there being no
13 // alternative. You should assume only properties explicitly guaranteed by the
14 // specifications in this file. You are almost certainly _not_ writing code
15 // just for the x86; if you assume x86 semantics, x86 hardware bugs and
16 // implementations on other archtectures will cause your code to break. If you
17 // do not know what you are doing, avoid these routines, and use a Mutex.
19 // It is incorrect to make direct assignments to/from an atomic variable.
20 // You should use one of the Load or Store routines. The NoBarrier
21 // versions are provided when no barriers are needed:
24 // Although there are currently no compiler enforcement, you are encouraged
28 #ifndef BASE_ATOMICOPS_H_
29 #define BASE_ATOMICOPS_H_
32 #include "base/basictypes.h"
33 #include "build/build_config.h"
38 typedef int32 Atomic32;
39 #ifdef ARCH_CPU_64_BITS
40 // We need to be able to go between Atomic64 and AtomicWord implicitly. This
41 // means Atomic64 and AtomicWord should be the same type on 64-bit.
43 // NaCl's intptr_t is not actually 64-bits on 64-bit!
44 // http://code.google.com/p/nativeclient/issues/detail?id=1162
45 typedef int64_t Atomic64;
47 typedef intptr_t Atomic64;
51 // Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or
52 // Atomic64 routines below, depending on your architecture.
53 typedef intptr_t AtomicWord;
55 // Atomically execute:
57 // if (*ptr == old_value)
61 // I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value".
62 // Always return the old value of "*ptr"
64 // This routine implies no memory barriers.
65 Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
69 // Atomically store new_value into *ptr, returning the previous value held in
70 // *ptr. This routine implies no memory barriers.
71 Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, Atomic32 new_value);
73 // Atomically increment *ptr by "increment". Returns the new value of
74 // *ptr with the increment applied. This routine implies no memory barriers.
75 Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, Atomic32 increment);
77 Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
80 // These following lower-level operations are typically useful only to people
81 // implementing higher-level synchronization operations like spinlocks,
82 // mutexes, and condition-variables. They combine CompareAndSwap(), a load, or
83 // a store with appropriate memory-ordering instructions. "Acquire" operations
84 // ensure that no later memory access can be reordered ahead of the operation.
85 // "Release" operations ensure that no previous memory access can be reordered
86 // after the operation. "Barrier" operations have both "Acquire" and "Release"
87 // semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory
89 Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
92 Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
97 void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value);
98 void Acquire_Store(volatile Atomic32* ptr, Atomic32 value);
99 void Release_Store(volatile Atomic32* ptr, Atomic32 value);
101 Atomic32 NoBarrier_Load(volatile const Atomic32* ptr);
102 Atomic32 Acquire_Load(volatile const Atomic32* ptr);
103 Atomic32 Release_Load(volatile const Atomic32* ptr);
105 // 64-bit atomic operations (only available on 64-bit processors).
106 #ifdef ARCH_CPU_64_BITS
107 Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
110 Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, Atomic64 new_value);
111 Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment);
112 Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment);
114 Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
117 Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
120 void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value);
121 void Acquire_Store(volatile Atomic64* ptr, Atomic64 value);
122 void Release_Store(volatile Atomic64* ptr, Atomic64 value);
123 Atomic64 NoBarrier_Load(volatile const Atomic64* ptr);
124 Atomic64 Acquire_Load(volatile const Atomic64* ptr);
125 Atomic64 Release_Load(volatile const Atomic64* ptr);
126 #endif // ARCH_CPU_64_BITS
128 } // namespace base::subtle
131 // Include our platform specific implementation.
132 #if defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY)
133 #include "base/atomicops_internals_x86_msvc.h"
134 #elif defined(OS_MACOSX) && defined(ARCH_CPU_X86_FAMILY)
135 #include "base/atomicops_internals_x86_macosx.h"
136 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_X86_FAMILY)
137 #include "base/atomicops_internals_x86_gcc.h"
138 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY)
139 #include "base/atomicops_internals_arm_gcc.h"
141 #error "Atomic operations are not supported on your platform"
144 // On some platforms we need additional declarations to make
145 // AtomicWord compatible with our other Atomic* types.
146 #if defined(OS_MACOSX) || defined(OS_OPENBSD)
147 #include "base/atomicops_internals_atomicword_compat.h"
150 #endif // BASE_ATOMICOPS_H_