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24 /** @file gen8_instruction.h
26 * A representation of a Gen8+ EU instruction, with helper methods to get
27 * and set various fields. This is the actual hardware format.
30 #ifndef GEN8_INSTRUCTION_H
31 #define GEN8_INSTRUCTION_H
36 #include "brw_compat.h"
39 struct gen8_instruction {
43 static inline unsigned gen8_bits(struct gen8_instruction *insn,
46 static inline void gen8_set_bits(struct gen8_instruction *insn,
51 #define F(name, high, low) \
52 static inline void gen8_set_##name(struct gen8_instruction *insn, unsigned v) \
54 gen8_set_bits(insn, high, low, v); \
56 static inline unsigned gen8_##name(struct gen8_instruction *insn) \
58 return gen8_bits(insn, high, low); \
62 * Direct addressing only:
65 F(src1_da_reg_nr, 108, 101);
66 F(src0_da_reg_nr, 76, 69);
67 F(dst_da1_hstride, 62, 61);
68 F(dst_da_reg_nr, 60, 53);
69 F(dst_da16_subreg_nr, 52, 52);
70 F(dst_da1_subreg_nr, 52, 48);
71 F(da16_writemask, 51, 48); /* Dst.ChanEn */
74 F(src1_vert_stride, 120, 117)
75 F(src1_da1_width, 116, 114)
76 F(src1_da16_swiz_w, 115, 114)
77 F(src1_da16_swiz_z, 113, 112)
78 F(src1_da1_hstride, 113, 112)
79 F(src1_address_mode, 111, 111)
81 F(src1_negate, 110, 110)
84 F(src1_da16_subreg_nr, 100, 100)
85 F(src1_da1_subreg_nr, 100, 96)
86 F(src1_da16_swiz_y, 99, 98)
87 F(src1_da16_swiz_x, 97, 96)
88 F(src1_reg_type, 94, 91)
89 F(src1_reg_file, 90, 89)
90 F(src0_vert_stride, 88, 85)
91 F(src0_da1_width, 84, 82)
92 F(src0_da16_swiz_w, 83, 82)
93 F(src0_da16_swiz_z, 81, 80)
94 F(src0_da1_hstride, 81, 80)
95 F(src0_address_mode, 79, 79)
97 F(src0_negate, 78, 78)
100 F(src0_da16_subreg_nr, 68, 68)
101 F(src0_da1_subreg_nr, 68, 64)
102 F(src0_da16_swiz_y, 67, 66)
103 F(src0_da16_swiz_x, 65, 64)
104 F(dst_address_mode, 63, 63)
105 F(src0_reg_type, 46, 43)
106 F(src0_reg_file, 42, 41)
107 F(dst_reg_type, 40, 37)
108 F(dst_reg_file, 36, 35)
109 F(mask_control, 34, 34)
110 F(flag_reg_nr, 33, 33)
111 F(flag_subreg_nr, 32, 32)
113 F(branch_control, 30, 30)
114 F(debug_control, 30, 30)
115 F(cmpt_control, 29, 29)
116 F(acc_wr_control, 28, 28)
117 F(cond_modifier, 27, 24)
120 F(pred_control, 19, 16)
121 F(thread_control, 15, 14)
122 F(qtr_control, 13, 12)
123 F(nib_control, 11, 11)
124 F(dep_control, 10, 9)
126 /* Bit 7 is Reserve d (for future Opcode expansion) */
130 * Three-source instructions:
133 F(src2_3src_reg_nr, 125, 118)
134 F(src2_3src_subreg_nr, 117, 115)
135 F(src2_3src_swizzle, 114, 107)
136 F(src2_3src_rep_ctrl, 106, 106)
137 F(src1_3src_reg_nr, 104, 97)
138 F(src1_3src_subreg_hi, 96, 96)
139 F(src1_3src_subreg_lo, 95, 94)
140 F(src1_3src_swizzle, 93, 86)
141 F(src1_3src_rep_ctrl, 85, 85)
142 F(src0_3src_reg_nr, 83, 76)
143 F(src0_3src_subreg_nr, 75, 73)
144 F(src0_3src_swizzle, 72, 65)
145 F(src0_3src_rep_ctrl, 64, 64)
146 F(dst_3src_reg_nr, 63, 56)
147 F(dst_3src_subreg_nr, 55, 53)
148 F(dst_3src_writemask, 52, 49)
149 F(dst_3src_type, 48, 46)
150 F(src_3src_type, 45, 43)
151 F(src2_3src_negate, 42, 42)
152 F(src2_3src_abs, 41, 41)
153 F(src1_3src_negate, 40, 40)
154 F(src1_3src_abs, 39, 39)
155 F(src0_3src_negate, 38, 38)
156 F(src0_3src_abs, 37, 37)
160 * Fields for SEND messages:
166 F(header_present, 115, 115)
167 F(function_control, 114, 96)
169 F(math_function, 27, 24)
173 * URB message function control bits:
176 F(urb_per_slot_offset, 113, 113)
177 F(urb_interleave, 111, 111)
178 F(urb_global_offset, 110, 100)
179 F(urb_opcode, 99, 96)
183 * Sampler message function control bits:
186 F(sampler_simd_mode, 114, 113)
187 F(sampler_msg_type, 112, 108)
189 F(binding_table_index, 103, 96)
193 * Data port message function control bits:
196 F(dp_category, 114, 114)
197 F(dp_message_type, 113, 110)
198 F(dp_message_control, 109, 104)
199 F(dp_binding_table_index, 103, 96)
203 * Thread Spawn message function control bits:
206 F(ts_resource_select, 100, 100)
207 F(ts_request_type, 97, 97)
212 * Video Motion Estimation message function control bits:
215 F(vme_message_type, 110, 109)
216 F(vme_binding_table_index, 103, 96)
220 * Check & Refinement Engine message function control bits:
223 F(cre_message_type, 110, 109)
224 F(cre_binding_table_index, 103, 96)
229 F(dst_addr_mode, 63, 63)
230 F(src0_addr_mode, 79, 79)
231 F(src1_addr_mode, 111, 111)
233 /* Indirect access mode for Align1. */
234 F(dst_ida1_sub_nr, 60, 57)
235 F(src0_ida1_sub_nr, 76, 73)
236 F(src1_ida1_sub_nr, 108, 105)
238 /* Imm[8:0] of Immediate addr offset under Indirect mode */
239 F(dst_ida1_imm8, 56, 48)
240 F(src0_ida1_imm8, 72, 64)
241 F(src1_ida1_imm8, 104, 96)
243 /* Imm Bit9 of Immediate addr offset under Indirect mode */
244 F(dst_ida1_imm9, 47, 47)
245 F(src0_ida1_imm9, 95, 95)
246 F(src1_ida1_imm9, 121, 121)
250 #define IMM8_MASK 0x1FF
251 #define IMM9_MASK 0x200
254 * Flow control instruction bits:
257 static inline unsigned gen8_uip(struct gen8_instruction *insn)
259 return insn->data[2];
261 static inline void gen8_set_uip(struct gen8_instruction *insn, unsigned uip)
265 static inline unsigned gen8_jip(struct gen8_instruction *insn)
267 return insn->data[3];
269 static inline void gen8_set_jip(struct gen8_instruction *insn, unsigned jip)
275 static inline int gen8_src1_imm_d(struct gen8_instruction *insn)
277 return insn->data[3];
279 static inline unsigned gen8_src1_imm_ud(struct gen8_instruction *insn)
281 return insn->data[3];
283 static inline float gen8_src1_imm_f(struct gen8_instruction *insn)
287 ft.u = insn->data[3];
291 void gen8_set_dst(struct gen8_instruction *insn, struct brw_reg reg);
292 void gen8_set_src0(struct gen8_instruction *insn, struct brw_reg reg);
293 void gen8_set_src1(struct gen8_instruction *insn, struct brw_reg reg);
295 void gen8_set_urb_message(struct gen8_instruction *insn,
296 unsigned opcode, unsigned mlen, unsigned rlen,
297 bool eot, unsigned offset, bool interleave);
299 void gen8_set_sampler_message(struct gen8_instruction *insn,
300 unsigned binding_table_index, unsigned sampler,
301 unsigned msg_type, unsigned rlen, unsigned mlen,
302 bool header_present, unsigned simd_mode);
304 void gen8_set_dp_message(struct gen8_instruction *insn,
305 enum brw_message_target sfid,
306 unsigned binding_table_index,
308 unsigned msg_control,
310 unsigned response_length,
314 /** Disassemble the instruction. */
315 int gen8_disassemble(FILE *file, struct gen8_instruction *insn, int gen);
319 * Fetch a set of contiguous bits from the instruction.
321 * Bits indexes range from 0..127; fields may not cross 32-bit boundaries.
323 static inline unsigned
324 gen8_bits(struct gen8_instruction *insn, unsigned high, unsigned low)
326 /* We assume the field doesn't cross 32-bit boundaries. */
327 const unsigned word = high / 32;
328 assert(word == low / 32);
333 const unsigned mask = (((1 << (high - low + 1)) - 1) << low);
335 return (insn->data[word] & mask) >> low;
339 * Set bits in the instruction, with proper shifting and masking.
341 * Bits indexes range from 0..127; fields may not cross 32-bit boundaries.
344 gen8_set_bits(struct gen8_instruction *insn,
349 const unsigned word = high / 32;
350 assert(word == low / 32);
355 const unsigned mask = (((1 << (high - low + 1)) - 1) << low);
357 insn->data[word] = (insn->data[word] & ~mask) | ((value << low) & mask);