2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 * This file defines struct brw_reg, which is our representation for EU
35 * registers. They're not a hardware specific format, just an abstraction
36 * that intends to capture the full flexibility of the hardware registers.
38 * The brw_eu_emit.c layer's brw_set_dest/brw_set_src[01] functions encode
39 * the abstract brw_reg type into the actual hardware instruction encoding.
47 #include "brw_defines.h"
53 /** Number of general purpose registers (VS, WM, etc) */
54 #define BRW_MAX_GRF 128
57 * First GRF used for the MRF hack.
59 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We
60 * haven't converted our compiler to be aware of this, so it asks for MRFs and
61 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The
62 * register allocators have to be careful of this to avoid corrupting the "MRF"s
63 * with actual GRF allocations.
65 #define GEN7_MRF_HACK_START 112
67 /** Number of message register file registers */
68 #define BRW_MAX_MRF 16
70 #define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
71 #define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)
73 #define BRW_SWIZZLE_NOOP BRW_SWIZZLE4(0,1,2,3)
74 #define BRW_SWIZZLE_XYZW BRW_SWIZZLE4(0,1,2,3)
75 #define BRW_SWIZZLE_XXXX BRW_SWIZZLE4(0,0,0,0)
76 #define BRW_SWIZZLE_YYYY BRW_SWIZZLE4(1,1,1,1)
77 #define BRW_SWIZZLE_ZZZZ BRW_SWIZZLE4(2,2,2,2)
78 #define BRW_SWIZZLE_WWWW BRW_SWIZZLE4(3,3,3,3)
79 #define BRW_SWIZZLE_XYXY BRW_SWIZZLE4(0,1,0,1)
82 brw_is_single_value_swizzle(int swiz)
84 return (swiz == BRW_SWIZZLE_XXXX ||
85 swiz == BRW_SWIZZLE_YYYY ||
86 swiz == BRW_SWIZZLE_ZZZZ ||
87 swiz == BRW_SWIZZLE_WWWW);
90 #define BRW_WRITEMASK_X 0x1
91 #define BRW_WRITEMASK_Y 0x2
92 #define BRW_WRITEMASK_Z 0x4
93 #define BRW_WRITEMASK_W 0x8
95 #define BRW_WRITEMASK_XY (BRW_WRITEMASK_X | BRW_WRITEMASK_Y)
96 #define BRW_WRITEMASK_XZ (BRW_WRITEMASK_X | BRW_WRITEMASK_Z)
97 #define BRW_WRITEMASK_XW (BRW_WRITEMASK_X | BRW_WRITEMASK_W)
98 #define BRW_WRITEMASK_YW (BRW_WRITEMASK_Y | BRW_WRITEMASK_W)
99 #define BRW_WRITEMASK_ZW (BRW_WRITEMASK_Z | BRW_WRITEMASK_W)
100 #define BRW_WRITEMASK_XYZ (BRW_WRITEMASK_X | BRW_WRITEMASK_Y | BRW_WRITEMASK_Z)
101 #define BRW_WRITEMASK_XYZW (BRW_WRITEMASK_X | BRW_WRITEMASK_Y | \
102 BRW_WRITEMASK_Z | BRW_WRITEMASK_W)
104 #define REG_SIZE (8*4)
106 /* These aren't hardware structs, just something useful for us to pass around:
108 * Align1 operation has a lot of control over input ranges. Used in
109 * WM programs to implement shaders decomposed into "channel serial"
110 * or "structure of array" form:
116 unsigned subnr:5; /* :1 in align16 */
117 unsigned negate:1; /* source only */
118 unsigned abs:1; /* source only */
119 unsigned vstride:4; /* source only */
120 unsigned width:3; /* src only, align1 only */
121 unsigned hstride:2; /* align1 only */
122 unsigned address_mode:1; /* relative addressing, hopefully! */
127 unsigned swizzle:8; /* src only, align16 only */
128 unsigned writemask:4; /* dest only, align16 only */
129 int indirect_offset:10; /* relative addressing offset */
130 unsigned pad1:10; /* two dwords total */
140 struct brw_indirect {
141 unsigned addr_subnr:4;
148 type_sz(unsigned type)
151 case BRW_REGISTER_TYPE_UD:
152 case BRW_REGISTER_TYPE_D:
153 case BRW_REGISTER_TYPE_F:
155 case BRW_REGISTER_TYPE_HF:
156 case BRW_REGISTER_TYPE_UW:
157 case BRW_REGISTER_TYPE_W:
159 case BRW_REGISTER_TYPE_UB:
160 case BRW_REGISTER_TYPE_B:
168 * Construct a brw_reg.
169 * \param file one of the BRW_x_REGISTER_FILE values
170 * \param nr register number/index
171 * \param subnr register sub number
172 * \param type one of BRW_REGISTER_TYPE_x
173 * \param vstride one of BRW_VERTICAL_STRIDE_x
174 * \param width one of BRW_WIDTH_x
175 * \param hstride one of BRW_HORIZONTAL_STRIDE_x
176 * \param swizzle one of BRW_SWIZZLE_x
177 * \param writemask BRW_WRITEMASK_X/Y/Z/W bitfield
179 static inline struct brw_reg
180 brw_reg(unsigned file,
191 if (file == BRW_GENERAL_REGISTER_FILE)
192 assert(nr < BRW_MAX_GRF);
193 else if (file == BRW_MESSAGE_REGISTER_FILE)
194 assert((nr & ~(1 << 7)) < BRW_MAX_MRF);
195 else if (file == BRW_ARCHITECTURE_REGISTER_FILE)
196 assert(nr <= BRW_ARF_TIMESTAMP);
201 reg.subnr = subnr * type_sz(type);
204 reg.vstride = vstride;
206 reg.hstride = hstride;
207 reg.address_mode = BRW_ADDRESS_DIRECT;
210 /* Could do better: If the reg is r5.3<0;1,0>, we probably want to
211 * set swizzle and writemask to W, as the lower bits of subnr will
212 * be lost when converted to align16. This is probably too much to
213 * keep track of as you'd want it adjusted by suboffset(), etc.
214 * Perhaps fix up when converting to align16?
216 reg.dw1.bits.swizzle = swizzle;
217 reg.dw1.bits.writemask = writemask;
218 reg.dw1.bits.indirect_offset = 0;
219 reg.dw1.bits.pad1 = 0;
223 /** Construct float[16] register */
224 static inline struct brw_reg
225 brw_vec16_reg(unsigned file, unsigned nr, unsigned subnr)
231 BRW_VERTICAL_STRIDE_16,
233 BRW_HORIZONTAL_STRIDE_1,
238 /** Construct float[8] register */
239 static inline struct brw_reg
240 brw_vec8_reg(unsigned file, unsigned nr, unsigned subnr)
246 BRW_VERTICAL_STRIDE_8,
248 BRW_HORIZONTAL_STRIDE_1,
253 /** Construct float[4] register */
254 static inline struct brw_reg
255 brw_vec4_reg(unsigned file, unsigned nr, unsigned subnr)
261 BRW_VERTICAL_STRIDE_4,
263 BRW_HORIZONTAL_STRIDE_1,
268 /** Construct float[2] register */
269 static inline struct brw_reg
270 brw_vec2_reg(unsigned file, unsigned nr, unsigned subnr)
276 BRW_VERTICAL_STRIDE_2,
278 BRW_HORIZONTAL_STRIDE_1,
283 /** Construct float[1] register */
284 static inline struct brw_reg
285 brw_vec1_reg(unsigned file, unsigned nr, unsigned subnr)
291 BRW_VERTICAL_STRIDE_0,
293 BRW_HORIZONTAL_STRIDE_0,
299 static inline struct brw_reg
300 retype(struct brw_reg reg, unsigned type)
306 static inline struct brw_reg
307 sechalf(struct brw_reg reg)
314 static inline struct brw_reg
315 suboffset(struct brw_reg reg, unsigned delta)
317 reg.subnr += delta * type_sz(reg.type);
322 static inline struct brw_reg
323 offset(struct brw_reg reg, unsigned delta)
330 static inline struct brw_reg
331 byte_offset(struct brw_reg reg, unsigned bytes)
333 unsigned newoffset = reg.nr * REG_SIZE + reg.subnr + bytes;
334 reg.nr = newoffset / REG_SIZE;
335 reg.subnr = newoffset % REG_SIZE;
340 /** Construct unsigned word[16] register */
341 static inline struct brw_reg
342 brw_uw16_reg(unsigned file, unsigned nr, unsigned subnr)
344 return suboffset(retype(brw_vec16_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
347 /** Construct unsigned word[8] register */
348 static inline struct brw_reg
349 brw_uw8_reg(unsigned file, unsigned nr, unsigned subnr)
351 return suboffset(retype(brw_vec8_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
354 /** Construct unsigned word[1] register */
355 static inline struct brw_reg
356 brw_uw1_reg(unsigned file, unsigned nr, unsigned subnr)
358 return suboffset(retype(brw_vec1_reg(file, nr, 0), BRW_REGISTER_TYPE_UW), subnr);
361 static inline struct brw_reg
362 brw_imm_reg(unsigned type)
364 return brw_reg(BRW_IMMEDIATE_VALUE,
368 BRW_VERTICAL_STRIDE_0,
370 BRW_HORIZONTAL_STRIDE_0,
375 /** Construct float immediate register */
376 static inline struct brw_reg
379 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
384 /** Construct integer immediate register */
385 static inline struct brw_reg
388 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
393 /** Construct uint immediate register */
394 static inline struct brw_reg
395 brw_imm_ud(unsigned ud)
397 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
402 /** Construct ushort immediate register */
403 static inline struct brw_reg
404 brw_imm_uw(uint16_t uw)
406 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
407 imm.dw1.ud = uw | (uw << 16);
411 /** Construct short immediate register */
412 static inline struct brw_reg
415 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
416 imm.dw1.d = w | (w << 16);
420 /* brw_imm_b and brw_imm_ub aren't supported by hardware - the type
421 * numbers alias with _V and _VF below:
424 /** Construct vector of eight signed half-byte values */
425 static inline struct brw_reg
426 brw_imm_v(unsigned v)
428 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_V);
429 imm.vstride = BRW_VERTICAL_STRIDE_0;
430 imm.width = BRW_WIDTH_8;
431 imm.hstride = BRW_HORIZONTAL_STRIDE_1;
436 /** Construct vector of four 8-bit float values */
437 static inline struct brw_reg
438 brw_imm_vf(unsigned v)
440 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
441 imm.vstride = BRW_VERTICAL_STRIDE_0;
442 imm.width = BRW_WIDTH_4;
443 imm.hstride = BRW_HORIZONTAL_STRIDE_1;
450 #define VF_NEG (1<<7)
452 static inline struct brw_reg
453 brw_imm_vf4(unsigned v0, unsigned v1, unsigned v2, unsigned v3)
455 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_VF);
456 imm.vstride = BRW_VERTICAL_STRIDE_0;
457 imm.width = BRW_WIDTH_4;
458 imm.hstride = BRW_HORIZONTAL_STRIDE_1;
459 imm.dw1.ud = ((v0 << 0) | (v1 << 8) | (v2 << 16) | (v3 << 24));
464 static inline struct brw_reg
465 brw_address(struct brw_reg reg)
467 return brw_imm_uw(reg.nr * REG_SIZE + reg.subnr);
470 /** Construct float[1] general-purpose register */
471 static inline struct brw_reg
472 brw_vec1_grf(unsigned nr, unsigned subnr)
474 return brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
477 /** Construct float[2] general-purpose register */
478 static inline struct brw_reg
479 brw_vec2_grf(unsigned nr, unsigned subnr)
481 return brw_vec2_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
484 /** Construct float[4] general-purpose register */
485 static inline struct brw_reg
486 brw_vec4_grf(unsigned nr, unsigned subnr)
488 return brw_vec4_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
491 /** Construct float[8] general-purpose register */
492 static inline struct brw_reg
493 brw_vec8_grf(unsigned nr, unsigned subnr)
495 return brw_vec8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
499 static inline struct brw_reg
500 brw_uw8_grf(unsigned nr, unsigned subnr)
502 return brw_uw8_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
505 static inline struct brw_reg
506 brw_uw16_grf(unsigned nr, unsigned subnr)
508 return brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
512 /** Construct null register (usually used for setting condition codes) */
513 static inline struct brw_reg
516 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_NULL, 0);
519 static inline struct brw_reg
520 brw_address_reg(unsigned subnr)
522 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ADDRESS, subnr);
525 /* If/else instructions break in align16 mode if writemask & swizzle
526 * aren't xyzw. This goes against the convention for other scalar
529 static inline struct brw_reg
532 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
535 BRW_REGISTER_TYPE_UD,
536 BRW_VERTICAL_STRIDE_4, /* ? */
538 BRW_HORIZONTAL_STRIDE_0,
539 BRW_SWIZZLE_XYZW, /* NOTE! */
540 BRW_WRITEMASK_XYZW); /* NOTE! */
543 static inline struct brw_reg
546 return brw_vec8_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_ACCUMULATOR, 0);
549 static inline struct brw_reg
550 brw_notification_1_reg(void)
553 return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
554 BRW_ARF_NOTIFICATION_COUNT,
556 BRW_REGISTER_TYPE_UD,
557 BRW_VERTICAL_STRIDE_0,
559 BRW_HORIZONTAL_STRIDE_0,
565 static inline struct brw_reg
566 brw_flag_reg(int reg, int subreg)
568 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
569 BRW_ARF_FLAG + reg, subreg);
573 static inline struct brw_reg
574 brw_mask_reg(unsigned subnr)
576 return brw_uw1_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_MASK, subnr);
579 static inline struct brw_reg
580 brw_message_reg(unsigned nr)
582 assert((nr & ~(1 << 7)) < BRW_MAX_MRF);
583 return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, nr, 0);
587 /* This is almost always called with a numeric constant argument, so
588 * make things easy to evaluate at compile time:
590 static inline unsigned cvt(unsigned val)
604 static inline struct brw_reg
605 stride(struct brw_reg reg, unsigned vstride, unsigned width, unsigned hstride)
607 reg.vstride = cvt(vstride);
608 reg.width = cvt(width) - 1;
609 reg.hstride = cvt(hstride);
614 static inline struct brw_reg
615 vec16(struct brw_reg reg)
617 return stride(reg, 16,16,1);
620 static inline struct brw_reg
621 vec8(struct brw_reg reg)
623 return stride(reg, 8,8,1);
626 static inline struct brw_reg
627 vec4(struct brw_reg reg)
629 return stride(reg, 4,4,1);
632 static inline struct brw_reg
633 vec2(struct brw_reg reg)
635 return stride(reg, 2,2,1);
638 static inline struct brw_reg
639 vec1(struct brw_reg reg)
641 return stride(reg, 0,1,0);
645 static inline struct brw_reg
646 get_element(struct brw_reg reg, unsigned elt)
648 return vec1(suboffset(reg, elt));
651 static inline struct brw_reg
652 get_element_ud(struct brw_reg reg, unsigned elt)
654 return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_UD), elt));
657 static inline struct brw_reg
658 get_element_d(struct brw_reg reg, unsigned elt)
660 return vec1(suboffset(retype(reg, BRW_REGISTER_TYPE_D), elt));
664 static inline struct brw_reg
665 brw_swizzle(struct brw_reg reg, unsigned x, unsigned y, unsigned z, unsigned w)
667 assert(reg.file != BRW_IMMEDIATE_VALUE);
669 reg.dw1.bits.swizzle = BRW_SWIZZLE4(BRW_GET_SWZ(reg.dw1.bits.swizzle, x),
670 BRW_GET_SWZ(reg.dw1.bits.swizzle, y),
671 BRW_GET_SWZ(reg.dw1.bits.swizzle, z),
672 BRW_GET_SWZ(reg.dw1.bits.swizzle, w));
677 static inline struct brw_reg
678 brw_swizzle1(struct brw_reg reg, unsigned x)
680 return brw_swizzle(reg, x, x, x, x);
683 static inline struct brw_reg
684 brw_writemask(struct brw_reg reg, unsigned mask)
686 assert(reg.file != BRW_IMMEDIATE_VALUE);
687 reg.dw1.bits.writemask &= mask;
691 static inline struct brw_reg
692 brw_set_writemask(struct brw_reg reg, unsigned mask)
694 assert(reg.file != BRW_IMMEDIATE_VALUE);
695 reg.dw1.bits.writemask = mask;
699 static inline struct brw_reg
700 negate(struct brw_reg reg)
706 static inline struct brw_reg
707 brw_abs(struct brw_reg reg)
714 /************************************************************************/
716 static inline struct brw_reg
717 brw_vec4_indirect(unsigned subnr, int offset)
719 struct brw_reg reg = brw_vec4_grf(0, 0);
721 reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
722 reg.dw1.bits.indirect_offset = offset;
726 static inline struct brw_reg
727 brw_vec1_indirect(unsigned subnr, int offset)
729 struct brw_reg reg = brw_vec1_grf(0, 0);
731 reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
732 reg.dw1.bits.indirect_offset = offset;
736 static inline struct brw_reg
737 deref_4f(struct brw_indirect ptr, int offset)
739 return brw_vec4_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
742 static inline struct brw_reg
743 deref_1f(struct brw_indirect ptr, int offset)
745 return brw_vec1_indirect(ptr.addr_subnr, ptr.addr_offset + offset);
748 static inline struct brw_reg
749 deref_4b(struct brw_indirect ptr, int offset)
751 return retype(deref_4f(ptr, offset), BRW_REGISTER_TYPE_B);
754 static inline struct brw_reg
755 deref_1uw(struct brw_indirect ptr, int offset)
757 return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UW);
760 static inline struct brw_reg
761 deref_1d(struct brw_indirect ptr, int offset)
763 return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_D);
766 static inline struct brw_reg
767 deref_1ud(struct brw_indirect ptr, int offset)
769 return retype(deref_1f(ptr, offset), BRW_REGISTER_TYPE_UD);
772 static inline struct brw_reg
773 get_addr_reg(struct brw_indirect ptr)
775 return brw_address_reg(ptr.addr_subnr);
778 static inline struct brw_indirect
779 brw_indirect_offset(struct brw_indirect ptr, int offset)
781 ptr.addr_offset += offset;
785 static inline struct brw_indirect
786 brw_indirect(unsigned addr_subnr, int offset)
788 struct brw_indirect ptr;
789 ptr.addr_subnr = addr_subnr;
790 ptr.addr_offset = offset;
795 /** Do two brw_regs refer to the same register? */
797 brw_same_reg(struct brw_reg r1, struct brw_reg r2)
799 return r1.file == r2.file && r1.nr == r2.nr;
802 void brw_print_reg(struct brw_reg reg);