1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2011 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \172\ab - the register number from operand a in bits 7..4, with
70 * the 4-bit immediate from operand b in bits 3..0.
71 * \173\xab - the register number from operand a in bits 7..4, with
72 * the value b in bits 3..0.
73 * \174\a - the register number from operand a in bits 7..4, and
74 * an arbitrary value in bits 3..0 (assembled as zero.)
75 * \2ab - a ModRM, calculated on EA in operand a, with the spare
76 * field equal to digit b.
77 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
78 * is not equal to the truncated and sign-extended 32-bit
79 * operand; used for 32-bit immediates in 64-bit mode.
80 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
81 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
82 * V field taken from operand 0..3.
83 * \270 - this instruction uses VEX/XOP rather than REX, with the
84 * V field set to 1111b.
86 * VEX/XOP prefixes are followed by the sequence:
87 * \tmm\wlp where mm is the M field; and wlp is:
89 * [l0] ll = 0 for L = 0 (.128, .lz)
90 * [l1] ll = 1 for L = 1 (.256)
91 * [lig] ll = 2 for L don't care (always assembled as 0)
93 * [w0] ww = 0 for W = 0
94 * [w1 ] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
98 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
100 * \274..\277 - a signed byte immediate operand, from operand 0..3,
101 * which is to be extended to the operand size.
102 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
103 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
104 * \312 - (disassembler only) invalid with non-default address size.
105 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
106 * \314 - (disassembler only) invalid with REX.B
107 * \315 - (disassembler only) invalid with REX.X
108 * \316 - (disassembler only) invalid with REX.R
109 * \317 - (disassembler only) invalid with REX.W
110 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
111 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
112 * \322 - indicates that this instruction is only valid when the
113 * operand size is the default (instruction to disassembler,
114 * generates no code in the assembler)
115 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
116 * \324 - indicates 64-bit operand size requiring REX prefix.
117 * \325 - instruction which always uses spl/bpl/sil/dil
118 * \330 - a literal byte follows in the code stream, to be added
119 * to the condition code value of the instruction.
120 * \331 - instruction not valid with REP prefix. Hint for
121 * disassembler only; for SSE instructions.
122 * \332 - REP prefix (0xF2 byte) used as opcode extension.
123 * \333 - REP prefix (0xF3 byte) used as opcode extension.
124 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
125 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
126 * \336 - force a REP(E) prefix (0xF2) even if not specified.
127 * \337 - force a REPNE prefix (0xF3) even if not specified.
128 * \336-\337 are still listed as prefixes in the disassembler.
129 * \340 - reserve <operand 0> bytes of uninitialized storage.
130 * Operand 0 had better be a segmentless constant.
131 * \341 - this instruction needs a WAIT "prefix"
132 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
133 * (POP is never used for CS) depending on operand 0
134 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
136 * \360 - no SSE prefix (== \364\331)
137 * \361 - 66 SSE prefix (== \366\331)
138 * \362 - F2 SSE prefix (== \364\332)
139 * \363 - F3 SSE prefix (== \364\333)
140 * \364 - operand-size prefix (0x66) not permitted
141 * \365 - address-size prefix (0x67) not permitted
142 * \366 - operand-size prefix (0x66) used as opcode extension
143 * \367 - address-size prefix (0x67) used as opcode extension
144 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
145 * 370 is used for Jcc, 371 is used for JMP.
146 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
147 * used for conditional jump over longer jump
148 * \374 - this instruction takes an XMM VSIB memory EA
149 * \375 - this instruction takes an YMM VSIB memory EA
152 #include "compiler.h"
156 #include <inttypes.h>
160 #include "assemble.h"
166 * Matching errors. These should be sorted so that more specific
167 * errors come later in the sequence.
175 * Matching success; the conditional ones first
177 MOK_JUMP, /* Matching OK but needs jmp_match() */
178 MOK_GOOD /* Matching unconditionally OK */
182 enum ea_type type; /* what kind of EA is this? */
183 int sib_present; /* is a SIB byte necessary? */
184 int bytes; /* # of bytes of offset needed */
185 int size; /* lazy - this is sib+bytes+1 */
186 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
189 static uint32_t cpu; /* cpu level received from nasm.c */
190 static efunc errfunc;
191 static struct ofmt *outfmt;
192 static ListGen *list;
194 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
195 static void gencode(int32_t segment, int64_t offset, int bits,
196 insn * ins, const struct itemplate *temp,
198 static enum match_result find_match(const struct itemplate **tempp,
200 int32_t segment, int64_t offset, int bits);
201 static enum match_result matches(const struct itemplate *, insn *, int bits);
202 static opflags_t regflag(const operand *);
203 static int32_t regval(const operand *);
204 static int rexflags(int, opflags_t, int);
205 static int op_rexflags(const operand *, int);
206 static void add_asp(insn *, int);
208 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
210 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
212 return ins->prefixes[pos] == prefix;
215 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
217 if (ins->prefixes[pos])
218 errfunc(ERR_NONFATAL, "invalid %s prefix",
219 prefix_name(ins->prefixes[pos]));
222 static const char *size_name(int size)
244 static void warn_overflow(int pass, int size)
246 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
247 "%s data exceeds bounds", size_name(size));
250 static void warn_overflow_const(int64_t data, int size)
252 if (overflow_general(data, size))
253 warn_overflow(ERR_PASS1, size);
256 static void warn_overflow_opd(const struct operand *o, int size)
258 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
259 if (overflow_general(o->offset, size))
260 warn_overflow(ERR_PASS2, size);
265 * This routine wrappers the real output format's output routine,
266 * in order to pass a copy of the data off to the listing file
267 * generator at the same time.
269 static void out(int64_t offset, int32_t segto, const void *data,
270 enum out_type type, uint64_t size,
271 int32_t segment, int32_t wrt)
273 static int32_t lineno = 0; /* static!!! */
274 static char *lnfname = NULL;
277 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
279 * This is a non-relocated address, and we're going to
280 * convert it into RAWDATA format.
285 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
289 WRITEADDR(q, *(int64_t *)data, size);
294 list->output(offset, data, type, size);
297 * this call to src_get determines when we call the
298 * debug-format-specific "linenum" function
299 * it updates lineno and lnfname to the current values
300 * returning 0 if "same as last time", -2 if lnfname
301 * changed, and the amount by which lineno changed,
302 * if it did. thus, these variables must be static
305 if (src_get(&lineno, &lnfname))
306 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
308 outfmt->output(segto, data, type, size, segment, wrt);
311 static bool jmp_match(int32_t segment, int64_t offset, int bits,
312 insn * ins, const uint8_t *code)
317 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
321 if (optimizing < 0 && c == 0371)
324 isize = calcsize(segment, offset, bits, ins, code);
326 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
327 /* Be optimistic in pass 1 */
330 if (ins->oprs[0].segment != segment)
333 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
334 return (isize >= -128 && isize <= 127); /* is it byte size? */
337 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
338 insn * instruction, struct ofmt *output, efunc error,
341 const struct itemplate *temp;
346 int64_t start = offset;
347 int64_t wsize; /* size for DB etc. */
349 errfunc = error; /* to pass to other functions */
351 outfmt = output; /* likewise */
352 list = listgen; /* and again */
354 wsize = idata_bytes(instruction->opcode);
360 int32_t t = instruction->times;
363 "instruction->times < 0 (%ld) in assemble()", t);
365 while (t--) { /* repeat TIMES times */
366 list_for_each(e, instruction->eops) {
367 if (e->type == EOT_DB_NUMBER) {
369 errfunc(ERR_NONFATAL,
370 "integer supplied to a DT, DO or DY"
373 out(offset, segment, &e->offset,
374 OUT_ADDRESS, wsize, e->segment, e->wrt);
377 } else if (e->type == EOT_DB_STRING ||
378 e->type == EOT_DB_STRING_FREE) {
381 out(offset, segment, e->stringval,
382 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
383 align = e->stringlen % wsize;
386 align = wsize - align;
387 out(offset, segment, zero_buffer,
388 OUT_RAWDATA, align, NO_SEG, NO_SEG);
390 offset += e->stringlen + align;
393 if (t > 0 && t == instruction->times - 1) {
395 * Dummy call to list->output to give the offset to the
398 list->output(offset, NULL, OUT_RAWDATA, 0);
399 list->uplevel(LIST_TIMES);
402 if (instruction->times > 1)
403 list->downlevel(LIST_TIMES);
404 return offset - start;
407 if (instruction->opcode == I_INCBIN) {
408 const char *fname = instruction->eops->stringval;
411 fp = fopen(fname, "rb");
413 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
415 } else if (fseek(fp, 0L, SEEK_END) < 0) {
416 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
419 static char buf[4096];
420 size_t t = instruction->times;
425 if (instruction->eops->next) {
426 base = instruction->eops->next->offset;
428 if (instruction->eops->next->next &&
429 len > (size_t)instruction->eops->next->next->offset)
430 len = (size_t)instruction->eops->next->next->offset;
433 * Dummy call to list->output to give the offset to the
436 list->output(offset, NULL, OUT_RAWDATA, 0);
437 list->uplevel(LIST_INCBIN);
441 fseek(fp, base, SEEK_SET);
445 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
448 * This shouldn't happen unless the file
449 * actually changes while we are reading
453 "`incbin': unexpected EOF while"
454 " reading file `%s'", fname);
455 t = 0; /* Try to exit cleanly */
458 out(offset, segment, buf, OUT_RAWDATA, m,
463 list->downlevel(LIST_INCBIN);
464 if (instruction->times > 1) {
466 * Dummy call to list->output to give the offset to the
469 list->output(offset, NULL, OUT_RAWDATA, 0);
470 list->uplevel(LIST_TIMES);
471 list->downlevel(LIST_TIMES);
474 return instruction->times * len;
476 return 0; /* if we're here, there's an error */
479 /* Check to see if we need an address-size prefix */
480 add_asp(instruction, bits);
482 m = find_match(&temp, instruction, segment, offset, bits);
486 int64_t insn_size = calcsize(segment, offset, bits,
487 instruction, temp->code);
488 itimes = instruction->times;
489 if (insn_size < 0) /* shouldn't be, on pass two */
490 error(ERR_PANIC, "errors made it through from pass one");
493 for (j = 0; j < MAXPREFIX; j++) {
495 switch (instruction->prefixes[j]) {
513 error(ERR_WARNING | ERR_PASS2,
514 "cs segment base generated, but will be ignored in 64-bit mode");
520 error(ERR_WARNING | ERR_PASS2,
521 "ds segment base generated, but will be ignored in 64-bit mode");
527 error(ERR_WARNING | ERR_PASS2,
528 "es segment base generated, but will be ignored in 64-bit mode");
540 error(ERR_WARNING | ERR_PASS2,
541 "ss segment base generated, but will be ignored in 64-bit mode");
548 "segr6 and segr7 cannot be used as prefixes");
553 "16-bit addressing is not supported "
555 } else if (bits != 16)
565 "64-bit addressing is only supported "
589 error(ERR_PANIC, "invalid instruction prefix");
592 out(offset, segment, &c, OUT_RAWDATA, 1,
597 insn_end = offset + insn_size;
598 gencode(segment, offset, bits, instruction,
601 if (itimes > 0 && itimes == instruction->times - 1) {
603 * Dummy call to list->output to give the offset to the
606 list->output(offset, NULL, OUT_RAWDATA, 0);
607 list->uplevel(LIST_TIMES);
610 if (instruction->times > 1)
611 list->downlevel(LIST_TIMES);
612 return offset - start;
616 case MERR_OPSIZEMISSING:
617 error(ERR_NONFATAL, "operation size not specified");
619 case MERR_OPSIZEMISMATCH:
620 error(ERR_NONFATAL, "mismatch in operand sizes");
623 error(ERR_NONFATAL, "no instruction for this cpu level");
626 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
631 "invalid combination of opcode and operands");
638 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
639 insn * instruction, efunc error)
641 const struct itemplate *temp;
644 errfunc = error; /* to pass to other functions */
647 if (instruction->opcode == I_none)
650 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
651 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
652 instruction->opcode == I_DT || instruction->opcode == I_DO ||
653 instruction->opcode == I_DY) {
655 int32_t isize, osize, wsize;
658 wsize = idata_bytes(instruction->opcode);
660 list_for_each(e, instruction->eops) {
664 if (e->type == EOT_DB_NUMBER) {
666 warn_overflow_const(e->offset, wsize);
667 } else if (e->type == EOT_DB_STRING ||
668 e->type == EOT_DB_STRING_FREE)
669 osize = e->stringlen;
671 align = (-osize) % wsize;
674 isize += osize + align;
676 return isize * instruction->times;
679 if (instruction->opcode == I_INCBIN) {
680 const char *fname = instruction->eops->stringval;
685 fp = fopen(fname, "rb");
687 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
689 else if (fseek(fp, 0L, SEEK_END) < 0)
690 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
694 if (instruction->eops->next) {
695 len -= instruction->eops->next->offset;
696 if (instruction->eops->next->next &&
697 len > (size_t)instruction->eops->next->next->offset) {
698 len = (size_t)instruction->eops->next->next->offset;
701 val = instruction->times * len;
708 /* Check to see if we need an address-size prefix */
709 add_asp(instruction, bits);
711 m = find_match(&temp, instruction, segment, offset, bits);
713 /* we've matched an instruction. */
715 const uint8_t *codes = temp->code;
718 isize = calcsize(segment, offset, bits, instruction, codes);
721 for (j = 0; j < MAXPREFIX; j++) {
722 switch (instruction->prefixes[j]) {
748 return isize * instruction->times;
750 return -1; /* didn't match any instruction */
754 static bool possible_sbyte(operand *o)
756 return o->wrt == NO_SEG && o->segment == NO_SEG &&
757 !(o->opflags & OPFLAG_UNKNOWN) &&
758 optimizing >= 0 && !(o->type & STRICT);
761 /* check that opn[op] is a signed byte of size 16 or 32 */
762 static bool is_sbyte16(operand *o)
766 if (!possible_sbyte(o))
770 return v >= -128 && v <= 127;
773 static bool is_sbyte32(operand *o)
777 if (!possible_sbyte(o))
781 return v >= -128 && v <= 127;
784 /* Common construct */
785 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
787 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
788 insn * ins, const uint8_t *codes)
798 ins->rex = 0; /* Ensure REX is reset */
799 eat = EA_SCALAR; /* Expect a scalar EA */
801 if (ins->prefixes[PPS_OSIZE] == P_O64)
804 (void)segment; /* Don't warn that this parameter is unused */
805 (void)offset; /* Don't warn that this parameter is unused */
809 op1 = (c & 3) + ((opex & 1) << 2);
810 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
811 opx = &ins->oprs[op1];
812 opex = 0; /* For the next iteration */
819 codes += c, length += c;
830 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
845 if (opx->type & (BITS16 | BITS32 | BITS64))
846 length += (opx->type & BITS16) ? 2 : 4;
848 length += (bits == 16) ? 2 : 4;
856 length += ins->addr_size >> 3;
864 length += 8; /* MOV reg64/imm */
872 if (opx->type & (BITS16 | BITS32 | BITS64))
873 length += (opx->type & BITS16) ? 2 : 4;
875 length += (bits == 16) ? 2 : 4;
887 length += is_sbyte16(opx) ? 1 : 2;
896 length += is_sbyte32(opx) ? 1 : 4;
912 length += is_sbyte32(opx) ? 1 : 4;
921 ins->vexreg = regval(opx);
922 ins->vex_cm = *codes++;
923 ins->vex_wlp = *codes++;
929 ins->vex_cm = *codes++;
930 ins->vex_wlp = *codes++;
943 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
947 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
954 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
955 has_prefix(ins, PPS_ASIZE, P_A32))
964 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
968 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
970 ins->prefixes[PPS_OSIZE] = P_O16;
976 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
980 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
982 ins->prefixes[PPS_OSIZE] = P_O32;
1021 if (!ins->prefixes[PPS_LREP])
1022 ins->prefixes[PPS_LREP] = P_REP;
1026 if (!ins->prefixes[PPS_LREP])
1027 ins->prefixes[PPS_LREP] = P_REPNE;
1031 if (ins->oprs[0].segment != NO_SEG)
1032 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1033 " quantity of BSS space");
1035 length += ins->oprs[0].offset;
1039 if (!ins->prefixes[PPS_WAIT])
1040 ins->prefixes[PPS_WAIT] = P_WAIT;
1098 struct operand *opy = &ins->oprs[op2];
1100 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1103 /* pick rfield from operand b (opx) */
1104 rflags = regflag(opx);
1105 rfield = nasm_regvals[opx->basereg];
1110 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1111 rfield, rflags) != eat) {
1112 errfunc(ERR_NONFATAL, "invalid effective address");
1115 ins->rex |= ea_data.rex;
1116 length += ea_data.size;
1122 errfunc(ERR_PANIC, "internal instruction table corrupt"
1123 ": instruction code \\%o (0x%02X) given", c, c);
1128 ins->rex &= rex_mask;
1130 if (ins->rex & REX_NH) {
1131 if (ins->rex & REX_H) {
1132 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1135 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1138 if (ins->rex & REX_V) {
1139 int bad32 = REX_R|REX_W|REX_X|REX_B;
1141 if (ins->rex & REX_H) {
1142 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1145 switch (ins->vex_wlp & 060) {
1159 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1160 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1163 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1167 } else if (ins->rex & REX_REAL) {
1168 if (ins->rex & REX_H) {
1169 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1171 } else if (bits == 64) {
1173 } else if ((ins->rex & REX_L) &&
1174 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1177 assert_no_prefix(ins, PPS_LREP);
1180 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1188 #define EMIT_REX() \
1189 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1190 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1191 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1196 static void gencode(int32_t segment, int64_t offset, int bits,
1197 insn * ins, const struct itemplate *temp,
1200 static const char condval[] = { /* conditional opcodes */
1201 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1202 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1203 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1210 struct operand *opx;
1211 const uint8_t *codes = temp->code;
1213 enum ea_type eat = EA_SCALAR;
1217 op1 = (c & 3) + ((opex & 1) << 2);
1218 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1219 opx = &ins->oprs[op1];
1220 opex = 0; /* For the next iteration */
1228 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1241 bytes[0] = *codes++ + (regval(opx) & 7);
1242 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1248 * The test for BITS8 and SBYTE here is intended to avoid
1249 * warning on optimizer actions due to SBYTE, while still
1250 * warn on explicit BYTE directives. Also warn, obviously,
1251 * if the optimizer isn't enabled.
1253 if (((opx->type & BITS8) ||
1254 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1255 (opx->offset < -128 || opx->offset > 127)) {
1256 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1257 "signed byte value exceeds bounds");
1259 if (opx->segment != NO_SEG) {
1261 out(offset, segment, &data, OUT_ADDRESS, 1,
1262 opx->segment, opx->wrt);
1264 bytes[0] = opx->offset;
1265 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1272 if (opx->offset < -256 || opx->offset > 255) {
1273 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1274 "byte value exceeds bounds");
1276 if (opx->segment != NO_SEG) {
1278 out(offset, segment, &data, OUT_ADDRESS, 1,
1279 opx->segment, opx->wrt);
1281 bytes[0] = opx->offset;
1282 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1289 if (opx->offset < 0 || opx->offset > 255)
1290 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1291 "unsigned byte value exceeds bounds");
1292 if (opx->segment != NO_SEG) {
1294 out(offset, segment, &data, OUT_ADDRESS, 1,
1295 opx->segment, opx->wrt);
1297 bytes[0] = opx->offset;
1298 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1305 warn_overflow_opd(opx, 2);
1307 out(offset, segment, &data, OUT_ADDRESS, 2,
1308 opx->segment, opx->wrt);
1313 if (opx->type & (BITS16 | BITS32))
1314 size = (opx->type & BITS16) ? 2 : 4;
1316 size = (bits == 16) ? 2 : 4;
1317 warn_overflow_opd(opx, size);
1319 out(offset, segment, &data, OUT_ADDRESS, size,
1320 opx->segment, opx->wrt);
1325 warn_overflow_opd(opx, 4);
1327 out(offset, segment, &data, OUT_ADDRESS, 4,
1328 opx->segment, opx->wrt);
1334 size = ins->addr_size >> 3;
1335 warn_overflow_opd(opx, size);
1336 out(offset, segment, &data, OUT_ADDRESS, size,
1337 opx->segment, opx->wrt);
1342 if (opx->segment != segment) {
1344 out(offset, segment, &data,
1345 OUT_REL1ADR, insn_end - offset,
1346 opx->segment, opx->wrt);
1348 data = opx->offset - insn_end;
1349 if (data > 127 || data < -128)
1350 errfunc(ERR_NONFATAL, "short jump is out of range");
1351 out(offset, segment, &data,
1352 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1358 data = (int64_t)opx->offset;
1359 out(offset, segment, &data, OUT_ADDRESS, 8,
1360 opx->segment, opx->wrt);
1365 if (opx->segment != segment) {
1367 out(offset, segment, &data,
1368 OUT_REL2ADR, insn_end - offset,
1369 opx->segment, opx->wrt);
1371 data = opx->offset - insn_end;
1372 out(offset, segment, &data,
1373 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1379 if (opx->type & (BITS16 | BITS32 | BITS64))
1380 size = (opx->type & BITS16) ? 2 : 4;
1382 size = (bits == 16) ? 2 : 4;
1383 if (opx->segment != segment) {
1385 out(offset, segment, &data,
1386 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1387 insn_end - offset, opx->segment, opx->wrt);
1389 data = opx->offset - insn_end;
1390 out(offset, segment, &data,
1391 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1397 if (opx->segment != segment) {
1399 out(offset, segment, &data,
1400 OUT_REL4ADR, insn_end - offset,
1401 opx->segment, opx->wrt);
1403 data = opx->offset - insn_end;
1404 out(offset, segment, &data,
1405 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1411 if (opx->segment == NO_SEG)
1412 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1415 out(offset, segment, &data, OUT_ADDRESS, 2,
1416 outfmt->segbase(1 + opx->segment),
1423 warn_overflow_opd(opx, 2);
1424 if (is_sbyte16(opx)) {
1426 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1430 out(offset, segment, &data, OUT_ADDRESS, 2,
1431 opx->segment, opx->wrt);
1438 bytes[0] = *codes++;
1439 if (is_sbyte16(opx))
1440 bytes[0] |= 2; /* s-bit */
1441 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1447 warn_overflow_opd(opx, 4);
1448 if (is_sbyte32(opx)) {
1450 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1454 out(offset, segment, &data, OUT_ADDRESS, 4,
1455 opx->segment, opx->wrt);
1462 bytes[0] = *codes++;
1463 if (is_sbyte32(opx))
1464 bytes[0] |= 2; /* s-bit */
1465 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1471 opx = &ins->oprs[c >> 3];
1472 bytes[0] = nasm_regvals[opx->basereg] << 4;
1473 opx = &ins->oprs[c & 7];
1474 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1475 errfunc(ERR_NONFATAL,
1476 "non-absolute expression not permitted as argument %d",
1479 if (opx->offset & ~15) {
1480 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1481 "four-bit argument exceeds bounds");
1483 bytes[0] |= opx->offset & 15;
1485 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1491 opx = &ins->oprs[c >> 4];
1492 bytes[0] = nasm_regvals[opx->basereg] << 4;
1494 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1500 opx = &ins->oprs[c];
1501 bytes[0] = nasm_regvals[opx->basereg] << 4;
1502 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1508 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1509 (int32_t)data != (int64_t)data) {
1510 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1511 "signed dword immediate exceeds bounds");
1513 if (is_sbyte32(opx)) {
1515 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1519 out(offset, segment, &data, OUT_ADDRESS, 4,
1520 opx->segment, opx->wrt);
1527 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1528 (int32_t)data != (int64_t)data) {
1529 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1530 "signed dword immediate exceeds bounds");
1532 out(offset, segment, &data, OUT_ADDRESS, 4,
1533 opx->segment, opx->wrt);
1540 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1541 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1542 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1543 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1544 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1545 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1549 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1550 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1551 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1561 if (ins->rex & REX_W)
1563 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1565 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1570 um = (uint64_t)2 << (s-1);
1573 if (uv > 127 && uv < (uint64_t)-128 &&
1574 (uv < um-128 || uv > um-1)) {
1575 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1576 "signed byte value exceeds bounds");
1578 if (opx->segment != NO_SEG) {
1580 out(offset, segment, &data, OUT_ADDRESS, 1,
1581 opx->segment, opx->wrt);
1584 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1595 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1597 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1604 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1606 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1638 *bytes = *codes++ ^ condval[ins->condition];
1639 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1648 *bytes = c - 0332 + 0xF2;
1649 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1654 if (ins->rex & REX_R) {
1656 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1659 ins->rex &= ~(REX_L|REX_R);
1670 if (ins->oprs[0].segment != NO_SEG)
1671 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1673 int64_t size = ins->oprs[0].offset;
1675 out(offset, segment, NULL,
1676 OUT_RESERVE, size, NO_SEG, NO_SEG);
1687 switch (ins->oprs[0].basereg) {
1702 "bizarre 8086 segment register received");
1704 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1711 switch (ins->oprs[0].basereg) {
1720 "bizarre 386 segment register received");
1722 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1731 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1737 bytes[0] = c - 0362 + 0xf2;
1738 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1748 *bytes = c - 0366 + 0x66;
1749 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1759 *bytes = bits == 16 ? 3 : 5;
1760 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1791 struct operand *opy = &ins->oprs[op2];
1794 /* pick rfield from operand b (opx) */
1795 rflags = regflag(opx);
1796 rfield = nasm_regvals[opx->basereg];
1798 /* rfield is constant */
1803 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1804 rfield, rflags) != eat) {
1805 errfunc(ERR_NONFATAL, "invalid effective address");
1810 *p++ = ea_data.modrm;
1811 if (ea_data.sib_present)
1815 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1818 * Make sure the address gets the right offset in case
1819 * the line breaks in the .lst file (BR 1197827)
1824 switch (ea_data.bytes) {
1834 if (opy->segment == segment) {
1836 if (overflow_signed(data, ea_data.bytes))
1837 warn_overflow(ERR_PASS2, ea_data.bytes);
1838 out(offset, segment, &data, OUT_ADDRESS,
1839 ea_data.bytes, NO_SEG, NO_SEG);
1841 /* overflow check in output/linker? */
1842 out(offset, segment, &data, OUT_REL4ADR,
1843 insn_end - offset, opy->segment, opy->wrt);
1846 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1847 signed_bits(opy->offset, ins->addr_size) !=
1848 signed_bits(opy->offset, ea_data.bytes * 8))
1849 warn_overflow(ERR_PASS2, ea_data.bytes);
1852 out(offset, segment, &data, OUT_ADDRESS,
1853 ea_data.bytes, opy->segment, opy->wrt);
1859 "Invalid amount of bytes (%d) for offset?!",
1868 errfunc(ERR_PANIC, "internal instruction table corrupt"
1869 ": instruction code \\%o (0x%02X) given", c, c);
1875 static opflags_t regflag(const operand * o)
1877 if (!is_register(o->basereg))
1878 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1879 return nasm_reg_flags[o->basereg];
1882 static int32_t regval(const operand * o)
1884 if (!is_register(o->basereg))
1885 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1886 return nasm_regvals[o->basereg];
1889 static int op_rexflags(const operand * o, int mask)
1894 if (!is_register(o->basereg))
1895 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1897 flags = nasm_reg_flags[o->basereg];
1898 val = nasm_regvals[o->basereg];
1900 return rexflags(val, flags, mask);
1903 static int rexflags(int val, opflags_t flags, int mask)
1908 rex |= REX_B|REX_X|REX_R;
1911 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1913 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1919 static enum match_result find_match(const struct itemplate **tempp,
1921 int32_t segment, int64_t offset, int bits)
1923 const struct itemplate *temp;
1924 enum match_result m, merr;
1925 opflags_t xsizeflags[MAX_OPERANDS];
1926 bool opsizemissing = false;
1929 for (i = 0; i < instruction->operands; i++)
1930 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1932 merr = MERR_INVALOP;
1934 for (temp = nasm_instructions[instruction->opcode];
1935 temp->opcode != I_none; temp++) {
1936 m = matches(temp, instruction, bits);
1937 if (m == MOK_JUMP) {
1938 if (jmp_match(segment, offset, bits, instruction, temp->code))
1942 } else if (m == MERR_OPSIZEMISSING &&
1943 (temp->flags & IF_SMASK) != IF_SX) {
1945 * Missing operand size and a candidate for fuzzy matching...
1947 for (i = 0; i < temp->operands; i++) {
1948 if ((temp->opd[i] & SAME_AS) == 0)
1949 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1951 opsizemissing = true;
1955 if (merr == MOK_GOOD)
1959 /* No match, but see if we can get a fuzzy operand size match... */
1963 for (i = 0; i < instruction->operands; i++) {
1965 * We ignore extrinsic operand sizes on registers, so we should
1966 * never try to fuzzy-match on them. This also resolves the case
1967 * when we have e.g. "xmmrm128" in two different positions.
1969 if (is_class(REGISTER, instruction->oprs[i].type))
1972 /* This tests if xsizeflags[i] has more than one bit set */
1973 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1974 goto done; /* No luck */
1976 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1979 /* Try matching again... */
1980 for (temp = nasm_instructions[instruction->opcode];
1981 temp->opcode != I_none; temp++) {
1982 m = matches(temp, instruction, bits);
1983 if (m == MOK_JUMP) {
1984 if (jmp_match(segment, offset, bits, instruction, temp->code))
1991 if (merr == MOK_GOOD)
2000 static enum match_result matches(const struct itemplate *itemp,
2001 insn *instruction, int bits)
2003 int i, size[MAX_OPERANDS], asize, oprs;
2004 bool opsizemissing = false;
2009 if (itemp->opcode != instruction->opcode)
2010 return MERR_INVALOP;
2013 * Count the operands
2015 if (itemp->operands != instruction->operands)
2016 return MERR_INVALOP;
2021 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2022 return MERR_INVALOP;
2025 * Check that no spurious colons or TOs are present
2027 for (i = 0; i < itemp->operands; i++)
2028 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2029 return MERR_INVALOP;
2032 * Process size flags
2034 switch (itemp->flags & IF_SMASK) {
2074 if (itemp->flags & IF_ARMASK) {
2075 /* S- flags only apply to a specific operand */
2076 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2077 memset(size, 0, sizeof size);
2080 /* S- flags apply to all operands */
2081 for (i = 0; i < MAX_OPERANDS; i++)
2086 * Check that the operand flags all match up,
2087 * it's a bit tricky so lets be verbose:
2089 * 1) Find out the size of operand. If instruction
2090 * doesn't have one specified -- we're trying to
2091 * guess it either from template (IF_S* flag) or
2094 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2095 * (ie the same operand as was specified somewhere in template, and
2096 * this referred operand index is being achieved via ~SAME_AS)
2097 * we are to be sure that both registers (in template and instruction)
2100 * 3) If template operand do not match the instruction OR
2101 * template has an operand size specified AND this size differ
2102 * from which instruction has (perhaps we got it from code bits)
2104 * a) Check that only size of instruction and operand is differ
2105 * other characteristics do match
2106 * b) Perhaps it's a register specified in instruction so
2107 * for such a case we just mark that operand as "size
2108 * missing" and this will turn on fuzzy operand size
2109 * logic facility (handled by a caller)
2111 for (i = 0; i < itemp->operands; i++) {
2112 opflags_t type = instruction->oprs[i].type;
2113 if (!(type & SIZE_MASK))
2116 if (itemp->opd[i] & SAME_AS) {
2117 int j = itemp->opd[i] & ~SAME_AS;
2118 if (type != instruction->oprs[j].type ||
2119 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2120 return MERR_INVALOP;
2121 } else if (itemp->opd[i] & ~type ||
2122 ((itemp->opd[i] & SIZE_MASK) &&
2123 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2124 if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
2125 return MERR_INVALOP;
2126 } else if (!is_class(REGISTER, type)) {
2128 * Note: we don't honor extrinsic operand sizes for registers,
2129 * so "missing operand size" for a register should be
2130 * considered a wildcard match rather than an error.
2132 opsizemissing = true;
2138 return MERR_OPSIZEMISSING;
2141 * Check operand sizes
2143 if (itemp->flags & (IF_SM | IF_SM2)) {
2144 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2145 for (i = 0; i < oprs; i++) {
2146 asize = itemp->opd[i] & SIZE_MASK;
2148 for (i = 0; i < oprs; i++)
2154 oprs = itemp->operands;
2157 for (i = 0; i < itemp->operands; i++) {
2158 if (!(itemp->opd[i] & SIZE_MASK) &&
2159 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2160 return MERR_OPSIZEMISMATCH;
2164 * Check template is okay at the set cpu level
2166 if (((itemp->flags & IF_PLEVEL) > cpu))
2170 * Verify the appropriate long mode flag.
2172 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2173 return MERR_BADMODE;
2176 * Check if special handling needed for Jumps
2178 if ((itemp->code[0] & 0374) == 0370)
2184 static enum ea_type process_ea(operand * input, ea * output, int bits,
2185 int addrbits, int rfield, opflags_t rflags)
2187 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2189 output->type = EA_SCALAR;
2190 output->rip = false;
2192 /* REX flags for the rfield operand */
2193 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2195 if (is_class(REGISTER, input->type)) { /* register direct */
2199 if (!is_register(input->basereg))
2202 i = nasm_regvals[input->basereg];
2207 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2209 output->sib_present = false; /* no SIB necessary */
2210 output->bytes = 0; /* no offset necessary either */
2211 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2212 } else { /* it's a memory reference */
2213 if (input->basereg == -1 &&
2214 (input->indexreg == -1 || input->scale == 0)) {
2215 /* it's a pure offset */
2217 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2218 input->segment == NO_SEG) {
2219 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2220 input->type &= ~IP_REL;
2221 input->type |= MEMORY;
2224 if (input->eaflags & EAF_BYTEOFFS ||
2225 (input->eaflags & EAF_WORDOFFS &&
2226 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2227 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2230 if (bits == 64 && (~input->type & IP_REL)) {
2231 int scale, index, base;
2232 output->sib_present = true;
2236 output->sib = (scale << 6) | (index << 3) | base;
2238 output->modrm = 4 | ((rfield & 7) << 3);
2239 output->rip = false;
2241 output->sib_present = false;
2242 output->bytes = (addrbits != 16 ? 4 : 2);
2243 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2244 output->rip = bits == 64;
2246 } else { /* it's an indirection */
2247 int i = input->indexreg, b = input->basereg, s = input->scale;
2248 int32_t seg = input->segment;
2249 int hb = input->hintbase, ht = input->hinttype;
2250 int t, it, bt; /* register numbers */
2251 opflags_t x, ix, bx; /* register flags */
2254 i = -1; /* make this easy, at least */
2256 if (is_register(i)) {
2257 it = nasm_regvals[i];
2258 ix = nasm_reg_flags[i];
2264 if (is_register(b)) {
2265 bt = nasm_regvals[b];
2266 bx = nasm_reg_flags[b];
2272 /* if either one are a vector register... */
2273 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2274 int32_t sok = BITS32 | BITS64;
2275 int32_t o = input->offset;
2276 int mod, scale, index, base;
2278 printf("bt = %x, bx = %x, it = %x, ix = %x, s = %d\n",
2282 * For a vector SIB, one has to be a vector and the other,
2283 * if present, a GPR. The vector must be the index operand.
2285 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2291 t = bt, bt = it, it = t;
2292 x = bx, bx = ix, ix = x;
2298 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2305 * While we're here, ensure the user didn't specify
2308 if (input->disp_size == 16 || input->disp_size == 64)
2311 if (addrbits == 16 ||
2312 (addrbits == 32 && !(sok & BITS32)) ||
2313 (addrbits == 64 && !(sok & BITS64)))
2316 output->type = (ix & YMMREG & ~REG_EA)
2317 ? EA_YMMVSIB : EA_XMMVSIB;
2319 output->rex |= rexflags(it, ix, REX_X);
2320 output->rex |= rexflags(bt, bx, REX_B);
2322 index = it & 7; /* it is known to be != -1 */
2337 default: /* then what the smeg is it? */
2338 goto err; /* panic */
2346 if (base != REG_NUM_EBP && o == 0 &&
2347 seg == NO_SEG && !forw_ref &&
2348 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2350 else if (input->eaflags & EAF_BYTEOFFS ||
2351 (o >= -128 && o <= 127 &&
2352 seg == NO_SEG && !forw_ref &&
2353 !(input->eaflags & EAF_WORDOFFS)))
2359 output->sib_present = true;
2360 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2361 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2362 output->sib = (scale << 6) | (index << 3) | base;
2363 } else if ((ix|bx) & (BITS32|BITS64)) {
2365 * it must be a 32/64-bit memory reference. Firstly we have
2366 * to check that all registers involved are type E/Rxx.
2368 int32_t sok = BITS32 | BITS64;
2369 int32_t o = input->offset;
2372 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2380 goto err; /* Invalid register */
2381 if (~sok & bx & SIZE_MASK)
2382 goto err; /* Invalid size */
2387 * While we're here, ensure the user didn't specify
2390 if (input->disp_size == 16 || input->disp_size == 64)
2393 if (addrbits == 16 ||
2394 (addrbits == 32 && !(sok & BITS32)) ||
2395 (addrbits == 64 && !(sok & BITS64)))
2398 /* now reorganize base/index */
2399 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2400 ((hb == b && ht == EAH_NOTBASE) ||
2401 (hb == i && ht == EAH_MAKEBASE))) {
2402 /* swap if hints say so */
2403 t = bt, bt = it, it = t;
2404 x = bx, bx = ix, ix = x;
2406 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2407 bt = -1, bx = 0, s++;
2408 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2409 /* make single reg base, unless hint */
2410 bt = it, bx = ix, it = -1, ix = 0;
2412 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2413 s == 3 || s == 5 || s == 9) && bt == -1)
2414 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2415 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2416 (input->eaflags & EAF_TIMESTWO))
2417 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2418 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2419 if (s == 1 && it == REG_NUM_ESP) {
2420 /* swap ESP into base if scale is 1 */
2421 t = it, it = bt, bt = t;
2422 x = ix, ix = bx, bx = x;
2424 if (it == REG_NUM_ESP ||
2425 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2426 goto err; /* wrong, for various reasons */
2428 output->rex |= rexflags(it, ix, REX_X);
2429 output->rex |= rexflags(bt, bx, REX_B);
2431 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2440 if (rm != REG_NUM_EBP && o == 0 &&
2441 seg == NO_SEG && !forw_ref &&
2442 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2444 else if (input->eaflags & EAF_BYTEOFFS ||
2445 (o >= -128 && o <= 127 &&
2446 seg == NO_SEG && !forw_ref &&
2447 !(input->eaflags & EAF_WORDOFFS)))
2453 output->sib_present = false;
2454 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2455 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2458 int mod, scale, index, base;
2478 default: /* then what the smeg is it? */
2479 goto err; /* panic */
2487 if (base != REG_NUM_EBP && o == 0 &&
2488 seg == NO_SEG && !forw_ref &&
2489 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2491 else if (input->eaflags & EAF_BYTEOFFS ||
2492 (o >= -128 && o <= 127 &&
2493 seg == NO_SEG && !forw_ref &&
2494 !(input->eaflags & EAF_WORDOFFS)))
2500 output->sib_present = true;
2501 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2502 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2503 output->sib = (scale << 6) | (index << 3) | base;
2505 } else { /* it's 16-bit */
2507 int16_t o = input->offset;
2509 /* check for 64-bit long mode */
2513 /* check all registers are BX, BP, SI or DI */
2514 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2515 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2518 /* ensure the user didn't specify DWORD/QWORD */
2519 if (input->disp_size == 32 || input->disp_size == 64)
2522 if (s != 1 && i != -1)
2523 goto err; /* no can do, in 16-bit EA */
2524 if (b == -1 && i != -1) {
2529 if ((b == R_SI || b == R_DI) && i != -1) {
2534 /* have BX/BP as base, SI/DI index */
2536 goto err; /* shouldn't ever happen, in theory */
2537 if (i != -1 && b != -1 &&
2538 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2539 goto err; /* invalid combinations */
2540 if (b == -1) /* pure offset: handled above */
2541 goto err; /* so if it gets to here, panic! */
2545 switch (i * 256 + b) {
2546 case R_SI * 256 + R_BX:
2549 case R_DI * 256 + R_BX:
2552 case R_SI * 256 + R_BP:
2555 case R_DI * 256 + R_BP:
2573 if (rm == -1) /* can't happen, in theory */
2574 goto err; /* so panic if it does */
2576 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2577 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2579 else if (input->eaflags & EAF_BYTEOFFS ||
2580 (o >= -128 && o <= 127 && seg == NO_SEG &&
2581 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2586 output->sib_present = false; /* no SIB - it's 16-bit */
2587 output->bytes = mod; /* bytes of offset needed */
2588 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2593 output->size = 1 + output->sib_present + output->bytes;
2594 return output->type;
2597 return output->type = EA_INVALID;
2600 static void add_asp(insn *ins, int addrbits)
2605 valid = (addrbits == 64) ? 64|32 : 32|16;
2607 switch (ins->prefixes[PPS_ASIZE]) {
2618 valid &= (addrbits == 32) ? 16 : 32;
2624 for (j = 0; j < ins->operands; j++) {
2625 if (is_class(MEMORY, ins->oprs[j].type)) {
2628 /* Verify as Register */
2629 if (!is_register(ins->oprs[j].indexreg))
2632 i = nasm_reg_flags[ins->oprs[j].indexreg];
2634 /* Verify as Register */
2635 if (!is_register(ins->oprs[j].basereg))
2638 b = nasm_reg_flags[ins->oprs[j].basereg];
2640 if (ins->oprs[j].scale == 0)
2644 int ds = ins->oprs[j].disp_size;
2645 if ((addrbits != 64 && ds > 8) ||
2646 (addrbits == 64 && ds == 16))
2666 if (valid & addrbits) {
2667 ins->addr_size = addrbits;
2668 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2669 /* Add an address size prefix */
2670 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2671 ins->prefixes[PPS_ASIZE] = pref;
2672 ins->addr_size = (addrbits == 32) ? 16 : 32;
2675 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2676 ins->addr_size = addrbits; /* Error recovery */
2679 defdisp = ins->addr_size == 16 ? 16 : 32;
2681 for (j = 0; j < ins->operands; j++) {
2682 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2683 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2685 * mem_offs sizes must match the address size; if not,
2686 * strip the MEM_OFFS bit and match only EA instructions
2688 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);